Commit | Line | Data |
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8bd22949 KH |
1 | /* |
2 | * OMAP3 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2006-2008 Nokia Corporation | |
5 | * Tony Lindgren <tony@atomide.com> | |
6 | * Jouni Hogander | |
7 | * | |
2f5939c3 RN |
8 | * Copyright (C) 2007 Texas Instruments, Inc. |
9 | * Rajendra Nayak <rnayak@ti.com> | |
10 | * | |
8bd22949 KH |
11 | * Copyright (C) 2005 Texas Instruments, Inc. |
12 | * Richard Woodruff <r-woodruff2@ti.com> | |
13 | * | |
14 | * Based on pm.c for omap1 | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/pm.h> | |
22 | #include <linux/suspend.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/gpio.h> | |
c40552bc | 28 | #include <linux/clk.h> |
dccaad89 | 29 | #include <linux/delay.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
0d8e2d0d | 31 | #include <linux/console.h> |
5e7c58dc | 32 | #include <trace/events/power.h> |
8bd22949 | 33 | |
2c74a0ce RK |
34 | #include <asm/suspend.h> |
35 | ||
ce491cf8 | 36 | #include <plat/sram.h> |
1540f214 | 37 | #include "clockdomain.h" |
72e06d08 | 38 | #include "powerdomain.h" |
ce491cf8 | 39 | #include <plat/serial.h> |
61255ab9 | 40 | #include <plat/sdrc.h> |
2f5939c3 RN |
41 | #include <plat/prcm.h> |
42 | #include <plat/gpmc.h> | |
f2d11858 | 43 | #include <plat/dma.h> |
8bd22949 | 44 | |
59fb659b | 45 | #include "cm2xxx_3xxx.h" |
8bd22949 KH |
46 | #include "cm-regbits-34xx.h" |
47 | #include "prm-regbits-34xx.h" | |
48 | ||
59fb659b | 49 | #include "prm2xxx_3xxx.h" |
8bd22949 | 50 | #include "pm.h" |
13a6fe0f | 51 | #include "sdrc.h" |
4814ced5 | 52 | #include "control.h" |
13a6fe0f | 53 | |
e83df17f KH |
54 | #ifdef CONFIG_SUSPEND |
55 | static suspend_state_t suspend_state = PM_SUSPEND_ON; | |
56 | static inline bool is_suspending(void) | |
57 | { | |
dca2d0eb | 58 | return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled; |
e83df17f KH |
59 | } |
60 | #else | |
61 | static inline bool is_suspending(void) | |
62 | { | |
63 | return false; | |
64 | } | |
65 | #endif | |
66 | ||
8cdfd834 NM |
67 | /* pm34xx errata defined in pm.h */ |
68 | u16 pm34xx_errata; | |
69 | ||
8bd22949 KH |
70 | struct power_state { |
71 | struct powerdomain *pwrdm; | |
72 | u32 next_state; | |
10f90ed2 | 73 | #ifdef CONFIG_SUSPEND |
8bd22949 | 74 | u32 saved_state; |
10f90ed2 | 75 | #endif |
8bd22949 KH |
76 | struct list_head node; |
77 | }; | |
78 | ||
79 | static LIST_HEAD(pwrst_list); | |
80 | ||
27d59a4a | 81 | static int (*_omap_save_secure_sram)(u32 *addr); |
46e130d2 | 82 | void (*omap3_do_wfi_sram)(void); |
27d59a4a | 83 | |
fa3c2a4f RN |
84 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
85 | static struct powerdomain *core_pwrdm, *per_pwrdm; | |
c16c3f67 | 86 | static struct powerdomain *cam_pwrdm; |
fa3c2a4f | 87 | |
2f5939c3 RN |
88 | static inline void omap3_per_save_context(void) |
89 | { | |
90 | omap_gpio_save_context(); | |
91 | } | |
92 | ||
93 | static inline void omap3_per_restore_context(void) | |
94 | { | |
95 | omap_gpio_restore_context(); | |
96 | } | |
97 | ||
3a7ec26b KJ |
98 | static void omap3_enable_io_chain(void) |
99 | { | |
100 | int timeout = 0; | |
101 | ||
b02b9172 PW |
102 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
103 | PM_WKEN); | |
104 | /* Do a readback to assure write has been done */ | |
105 | omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); | |
106 | ||
107 | while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & | |
108 | OMAP3430_ST_IO_CHAIN_MASK)) { | |
109 | timeout++; | |
110 | if (timeout > 1000) { | |
111 | pr_err("Wake up daisy chain activation failed.\n"); | |
112 | return; | |
3a7ec26b | 113 | } |
b02b9172 PW |
114 | omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, |
115 | WKUP_MOD, PM_WKEN); | |
3a7ec26b KJ |
116 | } |
117 | } | |
118 | ||
119 | static void omap3_disable_io_chain(void) | |
120 | { | |
b02b9172 PW |
121 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
122 | PM_WKEN); | |
3a7ec26b KJ |
123 | } |
124 | ||
2f5939c3 RN |
125 | static void omap3_core_save_context(void) |
126 | { | |
596efe47 | 127 | omap3_ctrl_save_padconf(); |
dccaad89 TK |
128 | |
129 | /* | |
130 | * Force write last pad into memory, as this can fail in some | |
83521291 | 131 | * cases according to errata 1.157, 1.185 |
dccaad89 TK |
132 | */ |
133 | omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), | |
134 | OMAP343X_CONTROL_MEM_WKUP + 0x2a0); | |
135 | ||
2f5939c3 RN |
136 | /* Save the Interrupt controller context */ |
137 | omap_intc_save_context(); | |
138 | /* Save the GPMC context */ | |
139 | omap3_gpmc_save_context(); | |
140 | /* Save the system control module context, padconf already save above*/ | |
141 | omap3_control_save_context(); | |
f2d11858 | 142 | omap_dma_global_context_save(); |
2f5939c3 RN |
143 | } |
144 | ||
145 | static void omap3_core_restore_context(void) | |
146 | { | |
147 | /* Restore the control module context, padconf restored by h/w */ | |
148 | omap3_control_restore_context(); | |
149 | /* Restore the GPMC context */ | |
150 | omap3_gpmc_restore_context(); | |
151 | /* Restore the interrupt controller context */ | |
152 | omap_intc_restore_context(); | |
f2d11858 | 153 | omap_dma_global_context_restore(); |
2f5939c3 RN |
154 | } |
155 | ||
9d97140b TK |
156 | /* |
157 | * FIXME: This function should be called before entering off-mode after | |
158 | * OMAP3 secure services have been accessed. Currently it is only called | |
159 | * once during boot sequence, but this works as we are not using secure | |
160 | * services. | |
161 | */ | |
617fcc98 | 162 | static void omap3_save_secure_ram_context(void) |
27d59a4a TK |
163 | { |
164 | u32 ret; | |
617fcc98 | 165 | int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
27d59a4a TK |
166 | |
167 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | |
27d59a4a TK |
168 | /* |
169 | * MPU next state must be set to POWER_ON temporarily, | |
170 | * otherwise the WFI executed inside the ROM code | |
171 | * will hang the system. | |
172 | */ | |
173 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | |
174 | ret = _omap_save_secure_sram((u32 *) | |
175 | __pa(omap3_secure_ram_storage)); | |
617fcc98 | 176 | pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); |
27d59a4a TK |
177 | /* Following is for error tracking, it should not happen */ |
178 | if (ret) { | |
179 | printk(KERN_ERR "save_secure_sram() returns %08x\n", | |
180 | ret); | |
181 | while (1) | |
182 | ; | |
183 | } | |
184 | } | |
185 | } | |
186 | ||
77da2d91 JH |
187 | /* |
188 | * PRCM Interrupt Handler Helper Function | |
189 | * | |
190 | * The purpose of this function is to clear any wake-up events latched | |
191 | * in the PRCM PM_WKST_x registers. It is possible that a wake-up event | |
192 | * may occur whilst attempting to clear a PM_WKST_x register and thus | |
193 | * set another bit in this register. A while loop is used to ensure | |
194 | * that any peripheral wake-up events occurring while attempting to | |
195 | * clear the PM_WKST_x are detected and cleared. | |
196 | */ | |
8cb0ac99 | 197 | static int prcm_clear_mod_irqs(s16 module, u8 regs) |
8bd22949 | 198 | { |
71a80775 | 199 | u32 wkst, fclk, iclk, clken; |
77da2d91 JH |
200 | u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; |
201 | u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; | |
202 | u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; | |
5d805978 PW |
203 | u16 grpsel_off = (regs == 3) ? |
204 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; | |
8cb0ac99 | 205 | int c = 0; |
8bd22949 | 206 | |
c4d7e58f PW |
207 | wkst = omap2_prm_read_mod_reg(module, wkst_off); |
208 | wkst &= omap2_prm_read_mod_reg(module, grpsel_off); | |
8bd22949 | 209 | if (wkst) { |
c4d7e58f PW |
210 | iclk = omap2_cm_read_mod_reg(module, iclk_off); |
211 | fclk = omap2_cm_read_mod_reg(module, fclk_off); | |
77da2d91 | 212 | while (wkst) { |
71a80775 | 213 | clken = wkst; |
c4d7e58f | 214 | omap2_cm_set_mod_reg_bits(clken, module, iclk_off); |
71a80775 VP |
215 | /* |
216 | * For USBHOST, we don't know whether HOST1 or | |
217 | * HOST2 woke us up, so enable both f-clocks | |
218 | */ | |
219 | if (module == OMAP3430ES2_USBHOST_MOD) | |
220 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; | |
c4d7e58f PW |
221 | omap2_cm_set_mod_reg_bits(clken, module, fclk_off); |
222 | omap2_prm_write_mod_reg(wkst, module, wkst_off); | |
223 | wkst = omap2_prm_read_mod_reg(module, wkst_off); | |
8cb0ac99 | 224 | c++; |
77da2d91 | 225 | } |
c4d7e58f PW |
226 | omap2_cm_write_mod_reg(iclk, module, iclk_off); |
227 | omap2_cm_write_mod_reg(fclk, module, fclk_off); | |
8bd22949 | 228 | } |
8cb0ac99 PW |
229 | |
230 | return c; | |
231 | } | |
232 | ||
233 | static int _prcm_int_handle_wakeup(void) | |
234 | { | |
235 | int c; | |
236 | ||
237 | c = prcm_clear_mod_irqs(WKUP_MOD, 1); | |
238 | c += prcm_clear_mod_irqs(CORE_MOD, 1); | |
239 | c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); | |
240 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
241 | c += prcm_clear_mod_irqs(CORE_MOD, 3); | |
242 | c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); | |
243 | } | |
244 | ||
245 | return c; | |
77da2d91 | 246 | } |
8bd22949 | 247 | |
77da2d91 JH |
248 | /* |
249 | * PRCM Interrupt Handler | |
250 | * | |
251 | * The PRM_IRQSTATUS_MPU register indicates if there are any pending | |
252 | * interrupts from the PRCM for the MPU. These bits must be cleared in | |
253 | * order to clear the PRCM interrupt. The PRCM interrupt handler is | |
254 | * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear | |
255 | * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU | |
256 | * register indicates that a wake-up event is pending for the MPU and | |
257 | * this bit can only be cleared if the all the wake-up events latched | |
258 | * in the various PM_WKST_x registers have been cleared. The interrupt | |
259 | * handler is implemented using a do-while loop so that if a wake-up | |
260 | * event occurred during the processing of the prcm interrupt handler | |
261 | * (setting a bit in the corresponding PM_WKST_x register and thus | |
262 | * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) | |
263 | * this would be handled. | |
264 | */ | |
265 | static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) | |
266 | { | |
d6290a3e | 267 | u32 irqenable_mpu, irqstatus_mpu; |
8cb0ac99 | 268 | int c = 0; |
77da2d91 | 269 | |
c4d7e58f | 270 | irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, |
d6290a3e | 271 | OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
c4d7e58f | 272 | irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, |
d6290a3e KH |
273 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
274 | irqstatus_mpu &= irqenable_mpu; | |
8cb0ac99 | 275 | |
d6290a3e | 276 | do { |
2bc4ef71 PW |
277 | if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK | |
278 | OMAP3430_IO_ST_MASK)) { | |
8cb0ac99 PW |
279 | c = _prcm_int_handle_wakeup(); |
280 | ||
281 | /* | |
282 | * Is the MPU PRCM interrupt handler racing with the | |
283 | * IVA2 PRCM interrupt handler ? | |
284 | */ | |
285 | WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " | |
286 | "but no wakeup sources are marked\n"); | |
287 | } else { | |
288 | /* XXX we need to expand our PRCM interrupt handler */ | |
289 | WARN(1, "prcm: WARNING: PRCM interrupt received, but " | |
290 | "no code to handle it (%08x)\n", irqstatus_mpu); | |
291 | } | |
292 | ||
c4d7e58f | 293 | omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, |
77da2d91 | 294 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
8bd22949 | 295 | |
c4d7e58f | 296 | irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, |
d6290a3e KH |
297 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
298 | irqstatus_mpu &= irqenable_mpu; | |
299 | ||
300 | } while (irqstatus_mpu); | |
8bd22949 KH |
301 | |
302 | return IRQ_HANDLED; | |
303 | } | |
304 | ||
cbe26349 RK |
305 | static void omap34xx_save_context(u32 *save) |
306 | { | |
307 | u32 val; | |
308 | ||
309 | /* Read Auxiliary Control Register */ | |
310 | asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); | |
311 | *save++ = 1; | |
312 | *save++ = val; | |
313 | ||
314 | /* Read L2 AUX ctrl register */ | |
315 | asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); | |
316 | *save++ = 1; | |
317 | *save++ = val; | |
318 | } | |
319 | ||
29cb3cd2 | 320 | static int omap34xx_do_sram_idle(unsigned long save_state) |
57f277b0 | 321 | { |
cbe26349 | 322 | omap34xx_cpu_suspend(save_state); |
29cb3cd2 | 323 | return 0; |
57f277b0 RN |
324 | } |
325 | ||
99e6a4d2 | 326 | void omap_sram_idle(void) |
8bd22949 KH |
327 | { |
328 | /* Variable to tell what needs to be saved and restored | |
329 | * in omap_sram_idle*/ | |
330 | /* save_state = 0 => Nothing to save and restored */ | |
331 | /* save_state = 1 => Only L1 and logic lost */ | |
332 | /* save_state = 2 => Only L2 lost */ | |
333 | /* save_state = 3 => L1, L2 and logic lost */ | |
fa3c2a4f RN |
334 | int save_state = 0; |
335 | int mpu_next_state = PWRDM_POWER_ON; | |
336 | int per_next_state = PWRDM_POWER_ON; | |
337 | int core_next_state = PWRDM_POWER_ON; | |
72e06d08 | 338 | int per_going_off; |
2f5939c3 | 339 | int core_prev_state, per_prev_state; |
13a6fe0f | 340 | u32 sdrc_pwr = 0; |
8bd22949 | 341 | |
fa3c2a4f RN |
342 | pwrdm_clear_all_prev_pwrst(mpu_pwrdm); |
343 | pwrdm_clear_all_prev_pwrst(neon_pwrdm); | |
344 | pwrdm_clear_all_prev_pwrst(core_pwrdm); | |
345 | pwrdm_clear_all_prev_pwrst(per_pwrdm); | |
346 | ||
8bd22949 KH |
347 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
348 | switch (mpu_next_state) { | |
fa3c2a4f | 349 | case PWRDM_POWER_ON: |
8bd22949 KH |
350 | case PWRDM_POWER_RET: |
351 | /* No need to save context */ | |
352 | save_state = 0; | |
353 | break; | |
61255ab9 RN |
354 | case PWRDM_POWER_OFF: |
355 | save_state = 3; | |
356 | break; | |
8bd22949 KH |
357 | default: |
358 | /* Invalid state */ | |
359 | printk(KERN_ERR "Invalid mpu state in sram_idle\n"); | |
360 | return; | |
361 | } | |
fe617af7 | 362 | |
fa3c2a4f RN |
363 | /* NEON control */ |
364 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) | |
7139178e | 365 | pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
fa3c2a4f | 366 | |
40742fa8 | 367 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
658ce97e | 368 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
ecf157d0 | 369 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
d5c47d7e KH |
370 | if (omap3_has_io_wakeup() && |
371 | (per_next_state < PWRDM_POWER_ON || | |
372 | core_next_state < PWRDM_POWER_ON)) { | |
c4d7e58f | 373 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); |
b02b9172 PW |
374 | if (omap3_has_io_chain_ctrl()) |
375 | omap3_enable_io_chain(); | |
40742fa8 MC |
376 | } |
377 | ||
0d8e2d0d | 378 | /* Block console output in case it is on one of the OMAP UARTs */ |
e83df17f KH |
379 | if (!is_suspending()) |
380 | if (per_next_state < PWRDM_POWER_ON || | |
381 | core_next_state < PWRDM_POWER_ON) | |
ac751efa | 382 | if (!console_trylock()) |
e83df17f | 383 | goto console_still_active; |
0d8e2d0d | 384 | |
ff2f8e5f C |
385 | pwrdm_pre_transition(); |
386 | ||
40742fa8 | 387 | /* PER */ |
658ce97e | 388 | if (per_next_state < PWRDM_POWER_ON) { |
72e06d08 | 389 | per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; |
658ce97e | 390 | omap_uart_prepare_idle(2); |
cd4f1fae | 391 | omap_uart_prepare_idle(3); |
72e06d08 | 392 | omap2_gpio_prepare_for_idle(per_going_off); |
e7410cf7 | 393 | if (per_next_state == PWRDM_POWER_OFF) |
ecf157d0 | 394 | omap3_per_save_context(); |
658ce97e KH |
395 | } |
396 | ||
397 | /* CORE */ | |
fa3c2a4f | 398 | if (core_next_state < PWRDM_POWER_ON) { |
fa3c2a4f RN |
399 | omap_uart_prepare_idle(0); |
400 | omap_uart_prepare_idle(1); | |
2f5939c3 RN |
401 | if (core_next_state == PWRDM_POWER_OFF) { |
402 | omap3_core_save_context(); | |
f0611a5c | 403 | omap3_cm_save_context(); |
2f5939c3 | 404 | } |
fa3c2a4f | 405 | } |
40742fa8 | 406 | |
f18cc2ff | 407 | omap3_intc_prepare_idle(); |
8bd22949 | 408 | |
13a6fe0f | 409 | /* |
30474544 PW |
410 | * On EMU/HS devices ROM code restores a SRDC value |
411 | * from scratchpad which has automatic self refresh on timeout | |
412 | * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. | |
413 | * Hence store/restore the SDRC_POWER register here. | |
414 | */ | |
415 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && | |
416 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || | |
417 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && | |
f265dc4c | 418 | core_next_state == PWRDM_POWER_OFF) |
13a6fe0f | 419 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); |
13a6fe0f | 420 | |
61255ab9 | 421 | /* |
076f2cc4 RK |
422 | * omap3_arm_context is the location where some ARM context |
423 | * get saved. The rest is placed on the stack, and restored | |
424 | * from there before resuming. | |
61255ab9 | 425 | */ |
cbe26349 RK |
426 | if (save_state) |
427 | omap34xx_save_context(omap3_arm_context); | |
076f2cc4 | 428 | if (save_state == 1 || save_state == 3) |
2c74a0ce | 429 | cpu_suspend(save_state, omap34xx_do_sram_idle); |
076f2cc4 RK |
430 | else |
431 | omap34xx_do_sram_idle(save_state); | |
8bd22949 | 432 | |
f265dc4c | 433 | /* Restore normal SDRC POWER settings */ |
30474544 PW |
434 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && |
435 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || | |
436 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && | |
13a6fe0f TK |
437 | core_next_state == PWRDM_POWER_OFF) |
438 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); | |
439 | ||
658ce97e | 440 | /* CORE */ |
fa3c2a4f | 441 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
442 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); |
443 | if (core_prev_state == PWRDM_POWER_OFF) { | |
444 | omap3_core_restore_context(); | |
f0611a5c | 445 | omap3_cm_restore_context(); |
2f5939c3 | 446 | omap3_sram_restore_context(); |
8a917d2f | 447 | omap2_sms_restore_context(); |
2f5939c3 | 448 | } |
658ce97e KH |
449 | omap_uart_resume_idle(0); |
450 | omap_uart_resume_idle(1); | |
451 | if (core_next_state == PWRDM_POWER_OFF) | |
c4d7e58f | 452 | omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, |
658ce97e KH |
453 | OMAP3430_GR_MOD, |
454 | OMAP3_PRM_VOLTCTRL_OFFSET); | |
455 | } | |
f18cc2ff | 456 | omap3_intc_resume_idle(); |
658ce97e | 457 | |
ff2f8e5f C |
458 | pwrdm_post_transition(); |
459 | ||
658ce97e KH |
460 | /* PER */ |
461 | if (per_next_state < PWRDM_POWER_ON) { | |
462 | per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); | |
43ffcd9a KH |
463 | omap2_gpio_resume_after_idle(); |
464 | if (per_prev_state == PWRDM_POWER_OFF) | |
658ce97e | 465 | omap3_per_restore_context(); |
ecf157d0 | 466 | omap_uart_resume_idle(2); |
cd4f1fae | 467 | omap_uart_resume_idle(3); |
fa3c2a4f | 468 | } |
fe617af7 | 469 | |
e83df17f | 470 | if (!is_suspending()) |
ac751efa | 471 | console_unlock(); |
0d8e2d0d PW |
472 | |
473 | console_still_active: | |
3a7ec26b | 474 | /* Disable IO-PAD and IO-CHAIN wakeup */ |
58a5559e KH |
475 | if (omap3_has_io_wakeup() && |
476 | (per_next_state < PWRDM_POWER_ON || | |
477 | core_next_state < PWRDM_POWER_ON)) { | |
c4d7e58f PW |
478 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, |
479 | PM_WKEN); | |
b02b9172 PW |
480 | if (omap3_has_io_chain_ctrl()) |
481 | omap3_disable_io_chain(); | |
3a7ec26b | 482 | } |
658ce97e | 483 | |
5cd1937b | 484 | clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); |
8bd22949 KH |
485 | } |
486 | ||
20b01669 | 487 | int omap3_can_sleep(void) |
8bd22949 | 488 | { |
4af4016c KH |
489 | if (!omap_uart_can_sleep()) |
490 | return 0; | |
8bd22949 KH |
491 | return 1; |
492 | } | |
493 | ||
8bd22949 KH |
494 | static void omap3_pm_idle(void) |
495 | { | |
496 | local_irq_disable(); | |
497 | local_fiq_disable(); | |
498 | ||
499 | if (!omap3_can_sleep()) | |
500 | goto out; | |
501 | ||
cf22854c | 502 | if (omap_irq_pending() || need_resched()) |
8bd22949 KH |
503 | goto out; |
504 | ||
5e7c58dc JP |
505 | trace_power_start(POWER_CSTATE, 1, smp_processor_id()); |
506 | trace_cpu_idle(1, smp_processor_id()); | |
507 | ||
8bd22949 KH |
508 | omap_sram_idle(); |
509 | ||
5e7c58dc JP |
510 | trace_power_end(smp_processor_id()); |
511 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); | |
512 | ||
8bd22949 KH |
513 | out: |
514 | local_fiq_enable(); | |
515 | local_irq_enable(); | |
516 | } | |
517 | ||
10f90ed2 | 518 | #ifdef CONFIG_SUSPEND |
8bd22949 KH |
519 | static int omap3_pm_suspend(void) |
520 | { | |
521 | struct power_state *pwrst; | |
522 | int state, ret = 0; | |
523 | ||
524 | /* Read current next_pwrsts */ | |
525 | list_for_each_entry(pwrst, &pwrst_list, node) | |
526 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | |
527 | /* Set ones wanted by suspend */ | |
528 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
eb6a2c75 | 529 | if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) |
8bd22949 KH |
530 | goto restore; |
531 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) | |
532 | goto restore; | |
533 | } | |
534 | ||
4af4016c | 535 | omap_uart_prepare_suspend(); |
2bbe3af3 TK |
536 | omap3_intc_suspend(); |
537 | ||
8bd22949 KH |
538 | omap_sram_idle(); |
539 | ||
540 | restore: | |
541 | /* Restore next_pwrsts */ | |
542 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
8bd22949 KH |
543 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
544 | if (state > pwrst->next_state) { | |
545 | printk(KERN_INFO "Powerdomain (%s) didn't enter " | |
546 | "target state %d\n", | |
547 | pwrst->pwrdm->name, pwrst->next_state); | |
548 | ret = -1; | |
549 | } | |
eb6a2c75 | 550 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
8bd22949 KH |
551 | } |
552 | if (ret) | |
553 | printk(KERN_ERR "Could not enter target state in pm_suspend\n"); | |
554 | else | |
555 | printk(KERN_INFO "Successfully put all powerdomains " | |
556 | "to target state\n"); | |
557 | ||
558 | return ret; | |
559 | } | |
560 | ||
2466211e | 561 | static int omap3_pm_enter(suspend_state_t unused) |
8bd22949 KH |
562 | { |
563 | int ret = 0; | |
564 | ||
2466211e | 565 | switch (suspend_state) { |
8bd22949 KH |
566 | case PM_SUSPEND_STANDBY: |
567 | case PM_SUSPEND_MEM: | |
568 | ret = omap3_pm_suspend(); | |
569 | break; | |
570 | default: | |
571 | ret = -EINVAL; | |
572 | } | |
573 | ||
574 | return ret; | |
575 | } | |
576 | ||
2466211e TK |
577 | /* Hooks to enable / disable UART interrupts during suspend */ |
578 | static int omap3_pm_begin(suspend_state_t state) | |
579 | { | |
c166381d | 580 | disable_hlt(); |
2466211e TK |
581 | suspend_state = state; |
582 | omap_uart_enable_irqs(0); | |
583 | return 0; | |
584 | } | |
585 | ||
586 | static void omap3_pm_end(void) | |
587 | { | |
588 | suspend_state = PM_SUSPEND_ON; | |
589 | omap_uart_enable_irqs(1); | |
c166381d | 590 | enable_hlt(); |
2466211e TK |
591 | return; |
592 | } | |
593 | ||
2f55ac07 | 594 | static const struct platform_suspend_ops omap_pm_ops = { |
2466211e TK |
595 | .begin = omap3_pm_begin, |
596 | .end = omap3_pm_end, | |
8bd22949 | 597 | .enter = omap3_pm_enter, |
8bd22949 KH |
598 | .valid = suspend_valid_only_mem, |
599 | }; | |
10f90ed2 | 600 | #endif /* CONFIG_SUSPEND */ |
8bd22949 | 601 | |
1155e426 KH |
602 | |
603 | /** | |
604 | * omap3_iva_idle(): ensure IVA is in idle so it can be put into | |
605 | * retention | |
606 | * | |
607 | * In cases where IVA2 is activated by bootcode, it may prevent | |
608 | * full-chip retention or off-mode because it is not idle. This | |
609 | * function forces the IVA2 into idle state so it can go | |
610 | * into retention/off and thus allow full-chip retention/off. | |
611 | * | |
612 | **/ | |
613 | static void __init omap3_iva_idle(void) | |
614 | { | |
615 | /* ensure IVA2 clock is disabled */ | |
c4d7e58f | 616 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
1155e426 KH |
617 | |
618 | /* if no clock activity, nothing else to do */ | |
c4d7e58f | 619 | if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & |
1155e426 KH |
620 | OMAP3430_CLKACTIVITY_IVA2_MASK)) |
621 | return; | |
622 | ||
623 | /* Reset IVA2 */ | |
c4d7e58f | 624 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
2bc4ef71 PW |
625 | OMAP3430_RST2_IVA2_MASK | |
626 | OMAP3430_RST3_IVA2_MASK, | |
37903009 | 627 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
628 | |
629 | /* Enable IVA2 clock */ | |
c4d7e58f | 630 | omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, |
1155e426 KH |
631 | OMAP3430_IVA2_MOD, CM_FCLKEN); |
632 | ||
633 | /* Set IVA2 boot mode to 'idle' */ | |
634 | omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, | |
635 | OMAP343X_CONTROL_IVA2_BOOTMOD); | |
636 | ||
637 | /* Un-reset IVA2 */ | |
c4d7e58f | 638 | omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
639 | |
640 | /* Disable IVA2 clock */ | |
c4d7e58f | 641 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
1155e426 KH |
642 | |
643 | /* Reset IVA2 */ | |
c4d7e58f | 644 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
2bc4ef71 PW |
645 | OMAP3430_RST2_IVA2_MASK | |
646 | OMAP3430_RST3_IVA2_MASK, | |
37903009 | 647 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
648 | } |
649 | ||
8111b221 | 650 | static void __init omap3_d2d_idle(void) |
8bd22949 | 651 | { |
8111b221 KH |
652 | u16 mask, padconf; |
653 | ||
654 | /* In a stand alone OMAP3430 where there is not a stacked | |
655 | * modem for the D2D Idle Ack and D2D MStandby must be pulled | |
656 | * high. S CONTROL_PADCONF_SAD2D_IDLEACK and | |
657 | * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ | |
658 | mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ | |
659 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); | |
660 | padconf |= mask; | |
661 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); | |
662 | ||
663 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); | |
664 | padconf |= mask; | |
665 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); | |
666 | ||
8bd22949 | 667 | /* reset modem */ |
c4d7e58f | 668 | omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | |
2bc4ef71 | 669 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, |
37903009 | 670 | CORE_MOD, OMAP2_RM_RSTCTRL); |
c4d7e58f | 671 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); |
8111b221 | 672 | } |
8bd22949 | 673 | |
8111b221 KH |
674 | static void __init prcm_setup_regs(void) |
675 | { | |
e5863689 G |
676 | u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? |
677 | OMAP3630_EN_UART4_MASK : 0; | |
678 | u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? | |
679 | OMAP3630_GRPSEL_UART4_MASK : 0; | |
680 | ||
4ef70c06 | 681 | /* XXX This should be handled by hwmod code or SCM init code */ |
2fd0f75c | 682 | omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); |
b296c811 | 683 | |
8bd22949 KH |
684 | /* |
685 | * Enable control of expternal oscillator through | |
686 | * sys_clkreq. In the long run clock framework should | |
687 | * take care of this. | |
688 | */ | |
c4d7e58f | 689 | omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, |
8bd22949 KH |
690 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, |
691 | OMAP3430_GR_MOD, | |
692 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | |
693 | ||
694 | /* setup wakup source */ | |
c4d7e58f | 695 | omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | |
2fd0f75c | 696 | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, |
8bd22949 KH |
697 | WKUP_MOD, PM_WKEN); |
698 | /* No need to write EN_IO, that is always enabled */ | |
c4d7e58f | 699 | omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | |
275f675c PW |
700 | OMAP3430_GRPSEL_GPT1_MASK | |
701 | OMAP3430_GRPSEL_GPT12_MASK, | |
8bd22949 KH |
702 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); |
703 | /* For some reason IO doesn't generate wakeup event even if | |
704 | * it is selected to mpu wakeup goup */ | |
c4d7e58f | 705 | omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, |
8bd22949 | 706 | OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); |
1155e426 | 707 | |
b92c5721 | 708 | /* Enable PM_WKEN to support DSS LPR */ |
c4d7e58f | 709 | omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, |
b92c5721 SV |
710 | OMAP3430_DSS_MOD, PM_WKEN); |
711 | ||
b427f92f | 712 | /* Enable wakeups in PER */ |
c4d7e58f | 713 | omap2_prm_write_mod_reg(omap3630_en_uart4_mask | |
e5863689 | 714 | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | |
2fd0f75c PW |
715 | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | |
716 | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | | |
717 | OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | | |
718 | OMAP3430_EN_MCBSP4_MASK, | |
b427f92f | 719 | OMAP3430_PER_MOD, PM_WKEN); |
eb350f74 | 720 | /* and allow them to wake up MPU */ |
c4d7e58f | 721 | omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | |
e5863689 | 722 | OMAP3430_GRPSEL_GPIO2_MASK | |
275f675c PW |
723 | OMAP3430_GRPSEL_GPIO3_MASK | |
724 | OMAP3430_GRPSEL_GPIO4_MASK | | |
725 | OMAP3430_GRPSEL_GPIO5_MASK | | |
726 | OMAP3430_GRPSEL_GPIO6_MASK | | |
727 | OMAP3430_GRPSEL_UART3_MASK | | |
728 | OMAP3430_GRPSEL_MCBSP2_MASK | | |
729 | OMAP3430_GRPSEL_MCBSP3_MASK | | |
730 | OMAP3430_GRPSEL_MCBSP4_MASK, | |
eb350f74 KH |
731 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
732 | ||
d3fd3290 | 733 | /* Don't attach IVA interrupts */ |
c4d7e58f PW |
734 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); |
735 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | |
736 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | |
737 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | |
d3fd3290 | 738 | |
b1340d17 | 739 | /* Clear any pending 'reset' flags */ |
c4d7e58f PW |
740 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); |
741 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); | |
742 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); | |
743 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); | |
744 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); | |
745 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); | |
746 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); | |
b1340d17 | 747 | |
014c46db | 748 | /* Clear any pending PRCM interrupts */ |
c4d7e58f | 749 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
014c46db | 750 | |
1155e426 | 751 | omap3_iva_idle(); |
8111b221 | 752 | omap3_d2d_idle(); |
8bd22949 KH |
753 | } |
754 | ||
c40552bc KH |
755 | void omap3_pm_off_mode_enable(int enable) |
756 | { | |
757 | struct power_state *pwrst; | |
758 | u32 state; | |
759 | ||
760 | if (enable) | |
761 | state = PWRDM_POWER_OFF; | |
762 | else | |
763 | state = PWRDM_POWER_RET; | |
764 | ||
765 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
cc1b6028 EV |
766 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && |
767 | pwrst->pwrdm == core_pwrdm && | |
768 | state == PWRDM_POWER_OFF) { | |
769 | pwrst->next_state = PWRDM_POWER_RET; | |
e16b41bf | 770 | pr_warn("%s: Core OFF disabled due to errata i583\n", |
cc1b6028 EV |
771 | __func__); |
772 | } else { | |
773 | pwrst->next_state = state; | |
774 | } | |
775 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | |
c40552bc KH |
776 | } |
777 | } | |
778 | ||
68d4778c TK |
779 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
780 | { | |
781 | struct power_state *pwrst; | |
782 | ||
783 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
784 | if (pwrst->pwrdm == pwrdm) | |
785 | return pwrst->next_state; | |
786 | } | |
787 | return -EINVAL; | |
788 | } | |
789 | ||
790 | int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) | |
791 | { | |
792 | struct power_state *pwrst; | |
793 | ||
794 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
795 | if (pwrst->pwrdm == pwrdm) { | |
796 | pwrst->next_state = state; | |
797 | return 0; | |
798 | } | |
799 | } | |
800 | return -EINVAL; | |
801 | } | |
802 | ||
a23456e9 | 803 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
8bd22949 KH |
804 | { |
805 | struct power_state *pwrst; | |
806 | ||
807 | if (!pwrdm->pwrsts) | |
808 | return 0; | |
809 | ||
d3d381c6 | 810 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
8bd22949 KH |
811 | if (!pwrst) |
812 | return -ENOMEM; | |
813 | pwrst->pwrdm = pwrdm; | |
814 | pwrst->next_state = PWRDM_POWER_RET; | |
815 | list_add(&pwrst->node, &pwrst_list); | |
816 | ||
817 | if (pwrdm_has_hdwr_sar(pwrdm)) | |
818 | pwrdm_enable_hdwr_sar(pwrdm); | |
819 | ||
eb6a2c75 | 820 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
8bd22949 KH |
821 | } |
822 | ||
823 | /* | |
824 | * Enable hw supervised mode for all clockdomains if it's | |
825 | * supported. Initiate sleep transition for other clockdomains, if | |
826 | * they are not used | |
827 | */ | |
a23456e9 | 828 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
8bd22949 KH |
829 | { |
830 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | |
5cd1937b | 831 | clkdm_allow_idle(clkdm); |
8bd22949 KH |
832 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && |
833 | atomic_read(&clkdm->usecount) == 0) | |
68b921ad | 834 | clkdm_sleep(clkdm); |
8bd22949 KH |
835 | return 0; |
836 | } | |
837 | ||
46e130d2 JP |
838 | /* |
839 | * Push functions to SRAM | |
840 | * | |
841 | * The minimum set of functions is pushed to SRAM for execution: | |
842 | * - omap3_do_wfi for erratum i581 WA, | |
843 | * - save_secure_ram_context for security extensions. | |
844 | */ | |
3231fc88 RN |
845 | void omap_push_sram_idle(void) |
846 | { | |
46e130d2 JP |
847 | omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); |
848 | ||
27d59a4a TK |
849 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
850 | _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, | |
851 | save_secure_ram_context_sz); | |
3231fc88 RN |
852 | } |
853 | ||
8cdfd834 NM |
854 | static void __init pm_errata_configure(void) |
855 | { | |
c4236d2e | 856 | if (cpu_is_omap3630()) { |
458e999e | 857 | pm34xx_errata |= PM_RTA_ERRATUM_i608; |
c4236d2e PDS |
858 | /* Enable the l2 cache toggling in sleep logic */ |
859 | enable_omap3630_toggle_l2_on_restore(); | |
cc1b6028 EV |
860 | if (omap_rev() < OMAP3630_REV_ES1_2) |
861 | pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; | |
c4236d2e | 862 | } |
8cdfd834 NM |
863 | } |
864 | ||
7cc515f7 | 865 | static int __init omap3_pm_init(void) |
8bd22949 KH |
866 | { |
867 | struct power_state *pwrst, *tmp; | |
55ed9694 | 868 | struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; |
8bd22949 KH |
869 | int ret; |
870 | ||
871 | if (!cpu_is_omap34xx()) | |
872 | return -ENODEV; | |
873 | ||
b02b9172 PW |
874 | if (!omap3_has_io_chain_ctrl()) |
875 | pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); | |
876 | ||
8cdfd834 NM |
877 | pm_errata_configure(); |
878 | ||
8bd22949 KH |
879 | /* XXX prcm_setup_regs needs to be before enabling hw |
880 | * supervised mode for powerdomains */ | |
881 | prcm_setup_regs(); | |
882 | ||
883 | ret = request_irq(INT_34XX_PRCM_MPU_IRQ, | |
884 | (irq_handler_t)prcm_interrupt_handler, | |
885 | IRQF_DISABLED, "prcm", NULL); | |
886 | if (ret) { | |
887 | printk(KERN_ERR "request_irq failed to register for 0x%x\n", | |
888 | INT_34XX_PRCM_MPU_IRQ); | |
889 | goto err1; | |
890 | } | |
891 | ||
a23456e9 | 892 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
8bd22949 KH |
893 | if (ret) { |
894 | printk(KERN_ERR "Failed to setup powerdomains\n"); | |
895 | goto err2; | |
896 | } | |
897 | ||
a23456e9 | 898 | (void) clkdm_for_each(clkdms_setup, NULL); |
8bd22949 KH |
899 | |
900 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
901 | if (mpu_pwrdm == NULL) { | |
902 | printk(KERN_ERR "Failed to get mpu_pwrdm\n"); | |
903 | goto err2; | |
904 | } | |
905 | ||
fa3c2a4f RN |
906 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
907 | per_pwrdm = pwrdm_lookup("per_pwrdm"); | |
908 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
c16c3f67 | 909 | cam_pwrdm = pwrdm_lookup("cam_pwrdm"); |
fa3c2a4f | 910 | |
55ed9694 PW |
911 | neon_clkdm = clkdm_lookup("neon_clkdm"); |
912 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | |
913 | per_clkdm = clkdm_lookup("per_clkdm"); | |
914 | core_clkdm = clkdm_lookup("core_clkdm"); | |
915 | ||
10f90ed2 | 916 | #ifdef CONFIG_SUSPEND |
8bd22949 | 917 | suspend_set_ops(&omap_pm_ops); |
10f90ed2 | 918 | #endif /* CONFIG_SUSPEND */ |
8bd22949 KH |
919 | |
920 | pm_idle = omap3_pm_idle; | |
0343371e | 921 | omap3_idle_init(); |
8bd22949 | 922 | |
458e999e NM |
923 | /* |
924 | * RTA is disabled during initialization as per erratum i608 | |
925 | * it is safer to disable RTA by the bootloader, but we would like | |
926 | * to be doubly sure here and prevent any mishaps. | |
927 | */ | |
928 | if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) | |
929 | omap3630_ctrl_disable_rta(); | |
930 | ||
55ed9694 | 931 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
27d59a4a TK |
932 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
933 | omap3_secure_ram_storage = | |
934 | kmalloc(0x803F, GFP_KERNEL); | |
935 | if (!omap3_secure_ram_storage) | |
936 | printk(KERN_ERR "Memory allocation failed when" | |
937 | "allocating for secure sram context\n"); | |
9d97140b TK |
938 | |
939 | local_irq_disable(); | |
940 | local_fiq_disable(); | |
941 | ||
942 | omap_dma_global_context_save(); | |
617fcc98 | 943 | omap3_save_secure_ram_context(); |
9d97140b TK |
944 | omap_dma_global_context_restore(); |
945 | ||
946 | local_irq_enable(); | |
947 | local_fiq_enable(); | |
27d59a4a | 948 | } |
27d59a4a | 949 | |
9d97140b | 950 | omap3_save_scratchpad_contents(); |
8bd22949 KH |
951 | err1: |
952 | return ret; | |
953 | err2: | |
954 | free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); | |
955 | list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { | |
956 | list_del(&pwrst->node); | |
957 | kfree(pwrst); | |
958 | } | |
959 | return ret; | |
960 | } | |
961 | ||
962 | late_initcall(omap3_pm_init); |