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OMAP3: PM: Enable IO-CHAIN wakeup
[linux-2.6-block.git] / arch / arm / mach-omap2 / pm34xx.c
CommitLineData
8bd22949
KH		 1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
2f5939c3
RN		 8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
8bd22949
KH		 11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
c40552bc 28#include <linux/clk.h>
8bd22949 29
ce491cf8
TL		 30#include <plat/sram.h>
31#include <plat/clockdomain.h>
32#include <plat/powerdomain.h>
33#include <plat/control.h>
34#include <plat/serial.h>
61255ab9 35#include <plat/sdrc.h>
2f5939c3
RN		 36#include <plat/prcm.h>
37#include <plat/gpmc.h>
f2d11858 38#include <plat/dma.h>
d7814e4d 39#include <plat/dmtimer.h>
8bd22949 40
57f277b0
RN		 41#include <asm/tlbflush.h>
42
8bd22949
KH		 43#include "cm.h"
44#include "cm-regbits-34xx.h"
45#include "prm-regbits-34xx.h"
46
47#include "prm.h"
48#include "pm.h"
13a6fe0f
TK		 49#include "sdrc.h"
50
51#define SDRC_POWER_AUTOCOUNT_SHIFT 8
52#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
53#define SDRC_POWER_CLKCTRL_SHIFT 4
54#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
55#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
8bd22949 56
2f5939c3
RN		 57/* Scratchpad offsets */
58#define OMAP343X_TABLE_ADDRESS_OFFSET 0x31
59#define OMAP343X_TABLE_VALUE_OFFSET 0x30
60#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32
61
c40552bc
KH		 62u32 enable_off_mode;
63u32 sleep_while_idle;
d7814e4d 64u32 wakeup_timer_seconds;
c40552bc 65
8bd22949
KH		 66struct power_state {
67 struct powerdomain *pwrdm;
68 u32 next_state;
10f90ed2 69#ifdef CONFIG_SUSPEND
8bd22949 70 u32 saved_state;
10f90ed2 71#endif
8bd22949
KH		 72 struct list_head node;
73};
74
75static LIST_HEAD(pwrst_list);
76
77static void (*_omap_sram_idle)(u32 *addr, int save_state);
78
27d59a4a
TK		 79static int (*_omap_save_secure_sram)(u32 *addr);
80
fa3c2a4f
RN		 81static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
82static struct powerdomain *core_pwrdm, *per_pwrdm;
c16c3f67 83static struct powerdomain *cam_pwrdm;
fa3c2a4f
RN		 84
85static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
8bd22949 86
2f5939c3
RN		 87static inline void omap3_per_save_context(void)
88{
89 omap_gpio_save_context();
90}
91
92static inline void omap3_per_restore_context(void)
93{
94 omap_gpio_restore_context();
95}
96
3a7ec26b
KJ		 97static void omap3_enable_io_chain(void)
98{
99 int timeout = 0;
100
101 if (omap_rev() >= OMAP3430_REV_ES3_1) {
102 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
103 /* Do a readback to assure write has been done */
104 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
105
106 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
107 OMAP3430_ST_IO_CHAIN)) {
108 timeout++;
109 if (timeout > 1000) {
110 printk(KERN_ERR "Wake up daisy chain "
111 "activation failed.\n");
112 return;
113 }
114 prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN,
115 WKUP_MOD, PM_WKST);
116 }
117 }
118}
119
120static void omap3_disable_io_chain(void)
121{
122 if (omap_rev() >= OMAP3430_REV_ES3_1)
123 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN, WKUP_MOD, PM_WKEN);
124}
125
2f5939c3
RN		 126static void omap3_core_save_context(void)
127{
128 u32 control_padconf_off;
129
130 /* Save the padconf registers */
131 control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
132 control_padconf_off |= START_PADCONF_SAVE;
133 omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
134 /* wait for the save to complete */
135 while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
136 & PADCONF_SAVE_DONE)
137 ;
138 /* Save the Interrupt controller context */
139 omap_intc_save_context();
140 /* Save the GPMC context */
141 omap3_gpmc_save_context();
142 /* Save the system control module context, padconf already save above*/
143 omap3_control_save_context();
f2d11858 144 omap_dma_global_context_save();
2f5939c3
RN		 145}
146
147static void omap3_core_restore_context(void)
148{
149 /* Restore the control module context, padconf restored by h/w */
150 omap3_control_restore_context();
151 /* Restore the GPMC context */
152 omap3_gpmc_restore_context();
153 /* Restore the interrupt controller context */
154 omap_intc_restore_context();
f2d11858 155 omap_dma_global_context_restore();
2f5939c3
RN		 156}
157
9d97140b
TK		 158/*
159 * FIXME: This function should be called before entering off-mode after
160 * OMAP3 secure services have been accessed. Currently it is only called
161 * once during boot sequence, but this works as we are not using secure
162 * services.
163 */
27d59a4a
TK		 164static void omap3_save_secure_ram_context(u32 target_mpu_state)
165{
166 u32 ret;
167
168 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
27d59a4a
TK		 169 /*
170 * MPU next state must be set to POWER_ON temporarily,
171 * otherwise the WFI executed inside the ROM code
172 * will hang the system.
173 */
174 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
175 ret = _omap_save_secure_sram((u32 *)
176 __pa(omap3_secure_ram_storage));
177 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
178 /* Following is for error tracking, it should not happen */
179 if (ret) {
180 printk(KERN_ERR "save_secure_sram() returns %08x\n",
181 ret);
182 while (1)
183 ;
184 }
185 }
186}
187
77da2d91
JH		 188/*
189 * PRCM Interrupt Handler Helper Function
190 *
191 * The purpose of this function is to clear any wake-up events latched
192 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
193 * may occur whilst attempting to clear a PM_WKST_x register and thus
194 * set another bit in this register. A while loop is used to ensure
195 * that any peripheral wake-up events occurring while attempting to
196 * clear the PM_WKST_x are detected and cleared.
197 */
8cb0ac99 198static int prcm_clear_mod_irqs(s16 module, u8 regs)
8bd22949 199{
71a80775 200 u32 wkst, fclk, iclk, clken;
77da2d91
JH		 201 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
202 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
203 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
5d805978
PW		 204 u16 grpsel_off = (regs == 3) ?
205 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
8cb0ac99 206 int c = 0;
8bd22949 207
77da2d91 208 wkst = prm_read_mod_reg(module, wkst_off);
5d805978 209 wkst &= prm_read_mod_reg(module, grpsel_off);
8bd22949 210 if (wkst) {
77da2d91
JH		 211 iclk = cm_read_mod_reg(module, iclk_off);
212 fclk = cm_read_mod_reg(module, fclk_off);
213 while (wkst) {
71a80775
VP		 214 clken = wkst;
215 cm_set_mod_reg_bits(clken, module, iclk_off);
216 /*
217 * For USBHOST, we don't know whether HOST1 or
218 * HOST2 woke us up, so enable both f-clocks
219 */
220 if (module == OMAP3430ES2_USBHOST_MOD)
221 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
222 cm_set_mod_reg_bits(clken, module, fclk_off);
77da2d91
JH		 223 prm_write_mod_reg(wkst, module, wkst_off);
224 wkst = prm_read_mod_reg(module, wkst_off);
8cb0ac99 225 c++;
77da2d91
JH		 226 }
227 cm_write_mod_reg(iclk, module, iclk_off);
228 cm_write_mod_reg(fclk, module, fclk_off);
8bd22949 229 }
8cb0ac99
PW		 230
231 return c;
232}
233
234static int _prcm_int_handle_wakeup(void)
235{
236 int c;
237
238 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
239 c += prcm_clear_mod_irqs(CORE_MOD, 1);
240 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
241 if (omap_rev() > OMAP3430_REV_ES1_0) {
242 c += prcm_clear_mod_irqs(CORE_MOD, 3);
243 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
244 }
245
246 return c;
77da2d91 247}
8bd22949 248
77da2d91
JH		 249/*
250 * PRCM Interrupt Handler
251 *
252 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
253 * interrupts from the PRCM for the MPU. These bits must be cleared in
254 * order to clear the PRCM interrupt. The PRCM interrupt handler is
255 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
256 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
257 * register indicates that a wake-up event is pending for the MPU and
258 * this bit can only be cleared if the all the wake-up events latched
259 * in the various PM_WKST_x registers have been cleared. The interrupt
260 * handler is implemented using a do-while loop so that if a wake-up
261 * event occurred during the processing of the prcm interrupt handler
262 * (setting a bit in the corresponding PM_WKST_x register and thus
263 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
264 * this would be handled.
265 */
266static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
267{
268 u32 irqstatus_mpu;
8cb0ac99 269 int c = 0;
77da2d91
JH		 270
271 do {
77da2d91
JH		 272 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
273 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
8cb0ac99
PW		 274
275 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
276 c = _prcm_int_handle_wakeup();
277
278 /*
279 * Is the MPU PRCM interrupt handler racing with the
280 * IVA2 PRCM interrupt handler ?
281 */
282 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
283 "but no wakeup sources are marked\n");
284 } else {
285 /* XXX we need to expand our PRCM interrupt handler */
286 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
287 "no code to handle it (%08x)\n", irqstatus_mpu);
288 }
289
77da2d91
JH		 290 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
291 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
8bd22949 292
77da2d91 293 } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
8bd22949
KH		 294
295 return IRQ_HANDLED;
296}
297
57f277b0
RN		 298static void restore_control_register(u32 val)
299{
300 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
301}
302
303/* Function to restore the table entry that was modified for enabling MMU */
304static void restore_table_entry(void)
305{
306 u32 *scratchpad_address;
307 u32 previous_value, control_reg_value;
308 u32 *address;
309
310 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
311
312 /* Get address of entry that was modified */
313 address = (u32 *)__raw_readl(scratchpad_address +
314 OMAP343X_TABLE_ADDRESS_OFFSET);
315 /* Get the previous value which needs to be restored */
316 previous_value = __raw_readl(scratchpad_address +
317 OMAP343X_TABLE_VALUE_OFFSET);
318 address = __va(address);
319 *address = previous_value;
320 flush_tlb_all();
321 control_reg_value = __raw_readl(scratchpad_address
322 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
323 /* This will enable caches and prediction */
324 restore_control_register(control_reg_value);
325}
326
8bd22949
KH		 327static void omap_sram_idle(void)
328{
329 /* Variable to tell what needs to be saved and restored
330 * in omap_sram_idle*/
331 /* save_state = 0 => Nothing to save and restored */
332 /* save_state = 1 => Only L1 and logic lost */
333 /* save_state = 2 => Only L2 lost */
334 /* save_state = 3 => L1, L2 and logic lost */
fa3c2a4f
RN		 335 int save_state = 0;
336 int mpu_next_state = PWRDM_POWER_ON;
337 int per_next_state = PWRDM_POWER_ON;
338 int core_next_state = PWRDM_POWER_ON;
2f5939c3 339 int core_prev_state, per_prev_state;
13a6fe0f 340 u32 sdrc_pwr = 0;
ecf157d0 341 int per_state_modified = 0;
8bd22949
KH		 342
343 if (!_omap_sram_idle)
344 return;
345
fa3c2a4f
RN		 346 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
347 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
348 pwrdm_clear_all_prev_pwrst(core_pwrdm);
349 pwrdm_clear_all_prev_pwrst(per_pwrdm);
350
8bd22949
KH		 351 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
352 switch (mpu_next_state) {
fa3c2a4f 353 case PWRDM_POWER_ON:
8bd22949
KH		 354 case PWRDM_POWER_RET:
355 /* No need to save context */
356 save_state = 0;
357 break;
61255ab9
RN		 358 case PWRDM_POWER_OFF:
359 save_state = 3;
360 break;
8bd22949
KH		 361 default:
362 /* Invalid state */
363 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
364 return;
365 }
fe617af7
PDS		 366 pwrdm_pre_transition();
367
fa3c2a4f
RN		 368 /* NEON control */
369 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
370 set_pwrdm_state(neon_pwrdm, mpu_next_state);
371
658ce97e
KH		 372 /* PER */
373 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
ecf157d0 374 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
658ce97e 375 if (per_next_state < PWRDM_POWER_ON) {
658ce97e 376 omap_uart_prepare_idle(2);
ecf157d0
TK		 377 omap2_gpio_prepare_for_retention();
378 if (per_next_state == PWRDM_POWER_OFF) {
379 if (core_next_state == PWRDM_POWER_ON) {
380 per_next_state = PWRDM_POWER_RET;
381 pwrdm_set_next_pwrst(per_pwrdm, per_next_state);
382 per_state_modified = 1;
383 } else
384 omap3_per_save_context();
385 }
658ce97e
KH		 386 }
387
c16c3f67
TK		 388 if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON)
389 omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]);
390
658ce97e 391 /* CORE */
fa3c2a4f 392 if (core_next_state < PWRDM_POWER_ON) {
fa3c2a4f
RN		 393 omap_uart_prepare_idle(0);
394 omap_uart_prepare_idle(1);
2f5939c3
RN		 395 if (core_next_state == PWRDM_POWER_OFF) {
396 omap3_core_save_context();
397 omap3_prcm_save_context();
398 }
3a7ec26b 399 /* Enable IO-PAD and IO-CHAIN wakeups */
fa3c2a4f 400 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
3a7ec26b 401 omap3_enable_io_chain();
fa3c2a4f 402 }
8bd22949 403
13a6fe0f
TK		 404 /*
405 * Force SDRAM controller to self-refresh mode after timeout on
406 * autocount. This is needed on ES3.0 to avoid SDRAM controller
407 * hang-ups.
408 */
409 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
410 omap_type() != OMAP2_DEVICE_TYPE_GP &&
411 core_next_state == PWRDM_POWER_OFF) {
412 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
413 sdrc_write_reg((sdrc_pwr &
414 ~(SDRC_POWER_AUTOCOUNT_MASK|SDRC_POWER_CLKCTRL_MASK)) |
415 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
416 SDRC_SELF_REFRESH_ON_AUTOCOUNT, SDRC_POWER);
417 }
418
61255ab9
RN		 419 /*
420 * omap3_arm_context is the location where ARM registers
421 * get saved. The restore path then reads from this
422 * location and restores them back.
423 */
424 _omap_sram_idle(omap3_arm_context, save_state);
8bd22949
KH		 425 cpu_init();
426
13a6fe0f
TK		 427 /* Restore normal SDRAM settings */
428 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
429 omap_type() != OMAP2_DEVICE_TYPE_GP &&
430 core_next_state == PWRDM_POWER_OFF)
431 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
432
57f277b0
RN		 433 /* Restore table entry modified during MMU restoration */
434 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
435 restore_table_entry();
436
658ce97e 437 /* CORE */
fa3c2a4f 438 if (core_next_state < PWRDM_POWER_ON) {
2f5939c3
RN		 439 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
440 if (core_prev_state == PWRDM_POWER_OFF) {
441 omap3_core_restore_context();
442 omap3_prcm_restore_context();
443 omap3_sram_restore_context();
8a917d2f 444 omap2_sms_restore_context();
2f5939c3 445 }
658ce97e
KH		 446 omap_uart_resume_idle(0);
447 omap_uart_resume_idle(1);
448 if (core_next_state == PWRDM_POWER_OFF)
449 prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF,
450 OMAP3430_GR_MOD,
451 OMAP3_PRM_VOLTCTRL_OFFSET);
452 }
453
454 /* PER */
455 if (per_next_state < PWRDM_POWER_ON) {
456 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
658ce97e
KH		 457 if (per_prev_state == PWRDM_POWER_OFF)
458 omap3_per_restore_context();
fa3c2a4f 459 omap2_gpio_resume_after_retention();
ecf157d0
TK		 460 omap_uart_resume_idle(2);
461 if (per_state_modified)
462 pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF);
fa3c2a4f 463 }
fe617af7 464
3a7ec26b
KJ		 465 /* Disable IO-PAD and IO-CHAIN wakeup */
466 if (core_next_state < PWRDM_POWER_ON) {
658ce97e 467 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
3a7ec26b
KJ		 468 omap3_disable_io_chain();
469 }
658ce97e 470
fe617af7
PDS		 471 pwrdm_post_transition();
472
c16c3f67 473 omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
8bd22949
KH		 474}
475
476/*
477 * Check if functional clocks are enabled before entering
478 * sleep. This function could be behind CONFIG_PM_DEBUG
479 * when all drivers are configuring their sysconfig registers
480 * properly and using their clocks properly.
481 */
482static int omap3_fclks_active(void)
483{
484 u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
485 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
486
487 fck_core1 = cm_read_mod_reg(CORE_MOD,
488 CM_FCLKEN1);
489 if (omap_rev() > OMAP3430_REV_ES1_0) {
490 fck_core3 = cm_read_mod_reg(CORE_MOD,
491 OMAP3430ES2_CM_FCLKEN3);
492 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
493 CM_FCLKEN);
494 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
495 CM_FCLKEN);
496 } else
497 fck_sgx = cm_read_mod_reg(GFX_MOD,
498 OMAP3430ES2_CM_FCLKEN3);
499 fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
500 CM_FCLKEN);
501 fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
502 CM_FCLKEN);
503 fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
504 CM_FCLKEN);
4af4016c
KH		 505
506 /* Ignore UART clocks. These are handled by UART core (serial.c) */
507 fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
508 fck_per &= ~OMAP3430_EN_UART3;
509
8bd22949
KH		 510 if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
511 fck_cam | fck_per | fck_usbhost)
512 return 1;
513 return 0;
514}
515
516static int omap3_can_sleep(void)
517{
c40552bc
KH		 518 if (!sleep_while_idle)
519 return 0;
4af4016c
KH		 520 if (!omap_uart_can_sleep())
521 return 0;
8bd22949
KH		 522 if (omap3_fclks_active())
523 return 0;
524 return 1;
525}
526
527/* This sets pwrdm state (other than mpu & core. Currently only ON &
528 * RET are supported. Function is assuming that clkdm doesn't have
529 * hw_sup mode enabled. */
530static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
531{
532 u32 cur_state;
533 int sleep_switch = 0;
534 int ret = 0;
535
536 if (pwrdm == NULL || IS_ERR(pwrdm))
537 return -EINVAL;
538
539 while (!(pwrdm->pwrsts & (1 << state))) {
540 if (state == PWRDM_POWER_OFF)
541 return ret;
542 state--;
543 }
544
545 cur_state = pwrdm_read_next_pwrst(pwrdm);
546 if (cur_state == state)
547 return ret;
548
549 if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
550 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
551 sleep_switch = 1;
552 pwrdm_wait_transition(pwrdm);
553 }
554
555 ret = pwrdm_set_next_pwrst(pwrdm, state);
556 if (ret) {
557 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
558 pwrdm->name);
559 goto err;
560 }
561
562 if (sleep_switch) {
563 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
564 pwrdm_wait_transition(pwrdm);
fe617af7 565 pwrdm_state_switch(pwrdm);
8bd22949
KH		 566 }
567
568err:
569 return ret;
570}
571
572static void omap3_pm_idle(void)
573{
574 local_irq_disable();
575 local_fiq_disable();
576
577 if (!omap3_can_sleep())
578 goto out;
579
580 if (omap_irq_pending())
581 goto out;
582
583 omap_sram_idle();
584
585out:
586 local_fiq_enable();
587 local_irq_enable();
588}
589
10f90ed2 590#ifdef CONFIG_SUSPEND
2466211e
TK		 591static suspend_state_t suspend_state;
592
d7814e4d
KH		 593static void omap2_pm_wakeup_on_timer(u32 seconds)
594{
595 u32 tick_rate, cycles;
596
597 if (!seconds)
598 return;
599
600 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
601 cycles = tick_rate * seconds;
602 omap_dm_timer_stop(gptimer_wakeup);
603 omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
604
605 pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n",
606 seconds, cycles, tick_rate);
607}
608
8bd22949
KH		 609static int omap3_pm_prepare(void)
610{
611 disable_hlt();
612 return 0;
613}
614
615static int omap3_pm_suspend(void)
616{
617 struct power_state *pwrst;
618 int state, ret = 0;
619
d7814e4d
KH		 620 if (wakeup_timer_seconds)
621 omap2_pm_wakeup_on_timer(wakeup_timer_seconds);
622
8bd22949
KH		 623 /* Read current next_pwrsts */
624 list_for_each_entry(pwrst, &pwrst_list, node)
625 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
626 /* Set ones wanted by suspend */
627 list_for_each_entry(pwrst, &pwrst_list, node) {
628 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
629 goto restore;
630 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
631 goto restore;
632 }
633
4af4016c 634 omap_uart_prepare_suspend();
8bd22949
KH		 635 omap_sram_idle();
636
637restore:
638 /* Restore next_pwrsts */
639 list_for_each_entry(pwrst, &pwrst_list, node) {
8bd22949
KH		 640 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
641 if (state > pwrst->next_state) {
642 printk(KERN_INFO "Powerdomain (%s) didn't enter "
643 "target state %d\n",
644 pwrst->pwrdm->name, pwrst->next_state);
645 ret = -1;
646 }
6c5f8039 647 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
8bd22949
KH		 648 }
649 if (ret)
650 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
651 else
652 printk(KERN_INFO "Successfully put all powerdomains "
653 "to target state\n");
654
655 return ret;
656}
657
2466211e 658static int omap3_pm_enter(suspend_state_t unused)
8bd22949
KH		 659{
660 int ret = 0;
661
2466211e 662 switch (suspend_state) {
8bd22949
KH		 663 case PM_SUSPEND_STANDBY:
664 case PM_SUSPEND_MEM:
665 ret = omap3_pm_suspend();
666 break;
667 default:
668 ret = -EINVAL;
669 }
670
671 return ret;
672}
673
674static void omap3_pm_finish(void)
675{
676 enable_hlt();
677}
678
2466211e
TK		 679/* Hooks to enable / disable UART interrupts during suspend */
680static int omap3_pm_begin(suspend_state_t state)
681{
682 suspend_state = state;
683 omap_uart_enable_irqs(0);
684 return 0;
685}
686
687static void omap3_pm_end(void)
688{
689 suspend_state = PM_SUSPEND_ON;
690 omap_uart_enable_irqs(1);
691 return;
692}
693
8bd22949 694static struct platform_suspend_ops omap_pm_ops = {
2466211e
TK		 695 .begin = omap3_pm_begin,
696 .end = omap3_pm_end,
8bd22949
KH		 697 .prepare = omap3_pm_prepare,
698 .enter = omap3_pm_enter,
699 .finish = omap3_pm_finish,
700 .valid = suspend_valid_only_mem,
701};
10f90ed2 702#endif /* CONFIG_SUSPEND */
8bd22949 703
1155e426
KH		 704
705/**
706 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
707 * retention
708 *
709 * In cases where IVA2 is activated by bootcode, it may prevent
710 * full-chip retention or off-mode because it is not idle. This
711 * function forces the IVA2 into idle state so it can go
712 * into retention/off and thus allow full-chip retention/off.
713 *
714 **/
715static void __init omap3_iva_idle(void)
716{
717 /* ensure IVA2 clock is disabled */
718 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
719
720 /* if no clock activity, nothing else to do */
721 if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
722 OMAP3430_CLKACTIVITY_IVA2_MASK))
723 return;
724
725 /* Reset IVA2 */
726 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
727 OMAP3430_RST2_IVA2 |
728 OMAP3430_RST3_IVA2,
729 OMAP3430_IVA2_MOD, RM_RSTCTRL);
730
731 /* Enable IVA2 clock */
732 cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
733 OMAP3430_IVA2_MOD, CM_FCLKEN);
734
735 /* Set IVA2 boot mode to 'idle' */
736 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
737 OMAP343X_CONTROL_IVA2_BOOTMOD);
738
739 /* Un-reset IVA2 */
740 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
741
742 /* Disable IVA2 clock */
743 cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
744
745 /* Reset IVA2 */
746 prm_write_mod_reg(OMAP3430_RST1_IVA2 |
747 OMAP3430_RST2_IVA2 |
748 OMAP3430_RST3_IVA2,
749 OMAP3430_IVA2_MOD, RM_RSTCTRL);
750}
751
8111b221 752static void __init omap3_d2d_idle(void)
8bd22949 753{
8111b221
KH		 754 u16 mask, padconf;
755
756 /* In a stand alone OMAP3430 where there is not a stacked
757 * modem for the D2D Idle Ack and D2D MStandby must be pulled
758 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
759 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
760 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
761 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
762 padconf |= mask;
763 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
764
765 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
766 padconf |= mask;
767 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
768
8bd22949
KH		 769 /* reset modem */
770 prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
771 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
772 CORE_MOD, RM_RSTCTRL);
773 prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
8111b221 774}
8bd22949 775
8111b221
KH		 776static void __init prcm_setup_regs(void)
777{
8bd22949
KH		 778 /* XXX Reset all wkdeps. This should be done when initializing
779 * powerdomains */
780 prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
781 prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
782 prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
783 prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
784 prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
785 prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
786 if (omap_rev() > OMAP3430_REV_ES1_0) {
787 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
788 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
789 } else
790 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
791
792 /*
793 * Enable interface clock autoidle for all modules.
794 * Note that in the long run this should be done by clockfw
795 */
796 cm_write_mod_reg(
8111b221 797 OMAP3430_AUTO_MODEM |
8bd22949
KH		 798 OMAP3430ES2_AUTO_MMC3 |
799 OMAP3430ES2_AUTO_ICR |
800 OMAP3430_AUTO_AES2 |
801 OMAP3430_AUTO_SHA12 |
802 OMAP3430_AUTO_DES2 |
803 OMAP3430_AUTO_MMC2 |
804 OMAP3430_AUTO_MMC1 |
805 OMAP3430_AUTO_MSPRO |
806 OMAP3430_AUTO_HDQ |
807 OMAP3430_AUTO_MCSPI4 |
808 OMAP3430_AUTO_MCSPI3 |
809 OMAP3430_AUTO_MCSPI2 |
810 OMAP3430_AUTO_MCSPI1 |
811 OMAP3430_AUTO_I2C3 |
812 OMAP3430_AUTO_I2C2 |
813 OMAP3430_AUTO_I2C1 |
814 OMAP3430_AUTO_UART2 |
815 OMAP3430_AUTO_UART1 |
816 OMAP3430_AUTO_GPT11 |
817 OMAP3430_AUTO_GPT10 |
818 OMAP3430_AUTO_MCBSP5 |
819 OMAP3430_AUTO_MCBSP1 |
820 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
821 OMAP3430_AUTO_MAILBOXES |
822 OMAP3430_AUTO_OMAPCTRL |
823 OMAP3430ES1_AUTO_FSHOSTUSB |
824 OMAP3430_AUTO_HSOTGUSB |
8111b221 825 OMAP3430_AUTO_SAD2D |
8bd22949
KH		 826 OMAP3430_AUTO_SSI,
827 CORE_MOD, CM_AUTOIDLE1);
828
829 cm_write_mod_reg(
830 OMAP3430_AUTO_PKA |
831 OMAP3430_AUTO_AES1 |
832 OMAP3430_AUTO_RNG |
833 OMAP3430_AUTO_SHA11 |
834 OMAP3430_AUTO_DES1,
835 CORE_MOD, CM_AUTOIDLE2);
836
837 if (omap_rev() > OMAP3430_REV_ES1_0) {
838 cm_write_mod_reg(
8111b221 839 OMAP3430_AUTO_MAD2D |
8bd22949
KH		 840 OMAP3430ES2_AUTO_USBTLL,
841 CORE_MOD, CM_AUTOIDLE3);
842 }
843
844 cm_write_mod_reg(
845 OMAP3430_AUTO_WDT2 |
846 OMAP3430_AUTO_WDT1 |
847 OMAP3430_AUTO_GPIO1 |
848 OMAP3430_AUTO_32KSYNC |
849 OMAP3430_AUTO_GPT12 |
850 OMAP3430_AUTO_GPT1 ,
851 WKUP_MOD, CM_AUTOIDLE);
852
853 cm_write_mod_reg(
854 OMAP3430_AUTO_DSS,
855 OMAP3430_DSS_MOD,
856 CM_AUTOIDLE);
857
858 cm_write_mod_reg(
859 OMAP3430_AUTO_CAM,
860 OMAP3430_CAM_MOD,
861 CM_AUTOIDLE);
862
863 cm_write_mod_reg(
864 OMAP3430_AUTO_GPIO6 |
865 OMAP3430_AUTO_GPIO5 |
866 OMAP3430_AUTO_GPIO4 |
867 OMAP3430_AUTO_GPIO3 |
868 OMAP3430_AUTO_GPIO2 |
869 OMAP3430_AUTO_WDT3 |
870 OMAP3430_AUTO_UART3 |
871 OMAP3430_AUTO_GPT9 |
872 OMAP3430_AUTO_GPT8 |
873 OMAP3430_AUTO_GPT7 |
874 OMAP3430_AUTO_GPT6 |
875 OMAP3430_AUTO_GPT5 |
876 OMAP3430_AUTO_GPT4 |
877 OMAP3430_AUTO_GPT3 |
878 OMAP3430_AUTO_GPT2 |
879 OMAP3430_AUTO_MCBSP4 |
880 OMAP3430_AUTO_MCBSP3 |
881 OMAP3430_AUTO_MCBSP2,
882 OMAP3430_PER_MOD,
883 CM_AUTOIDLE);
884
885 if (omap_rev() > OMAP3430_REV_ES1_0) {
886 cm_write_mod_reg(
887 OMAP3430ES2_AUTO_USBHOST,
888 OMAP3430ES2_USBHOST_MOD,
889 CM_AUTOIDLE);
890 }
891
892 /*
893 * Set all plls to autoidle. This is needed until autoidle is
894 * enabled by clockfw
895 */
896 cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
897 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
898 cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
899 MPU_MOD,
900 CM_AUTOIDLE2);
901 cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
902 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
903 PLL_MOD,
904 CM_AUTOIDLE);
905 cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
906 PLL_MOD,
907 CM_AUTOIDLE2);
908
909 /*
910 * Enable control of expternal oscillator through
911 * sys_clkreq. In the long run clock framework should
912 * take care of this.
913 */
914 prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
915 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
916 OMAP3430_GR_MOD,
917 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
918
919 /* setup wakup source */
920 prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
921 OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
922 WKUP_MOD, PM_WKEN);
923 /* No need to write EN_IO, that is always enabled */
924 prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
925 OMAP3430_EN_GPT12,
926 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
927 /* For some reason IO doesn't generate wakeup event even if
928 * it is selected to mpu wakeup goup */
929 prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
930 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
1155e426 931
b427f92f 932 /* Enable wakeups in PER */
eb350f74
KH		 933 prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
934 OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
b427f92f
KH		 935 OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
936 OMAP3430_PER_MOD, PM_WKEN);
eb350f74
KH		 937 /* and allow them to wake up MPU */
938 prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
939 OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
b427f92f 940 OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
eb350f74
KH		 941 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
942
d3fd3290
KH		 943 /* Don't attach IVA interrupts */
944 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
945 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
946 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
947 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
948
b1340d17
KH		 949 /* Clear any pending 'reset' flags */
950 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
951 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
952 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
953 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
954 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
955 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
956 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
957
014c46db
KH		 958 /* Clear any pending PRCM interrupts */
959 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
960
040fed05
KH		 961 /* Don't attach IVA interrupts */
962 prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
963 prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
964 prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
965 prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
966
3a07ae30
KH		 967 /* Clear any pending 'reset' flags */
968 prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
969 prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
970 prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
971 prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
972 prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
973 prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
974 prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
975
3a6667ac
KH		 976 /* Clear any pending PRCM interrupts */
977 prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
978
1155e426 979 omap3_iva_idle();
8111b221 980 omap3_d2d_idle();
8bd22949
KH		 981}
982
c40552bc
KH		 983void omap3_pm_off_mode_enable(int enable)
984{
985 struct power_state *pwrst;
986 u32 state;
987
988 if (enable)
989 state = PWRDM_POWER_OFF;
990 else
991 state = PWRDM_POWER_RET;
992
993 list_for_each_entry(pwrst, &pwrst_list, node) {
994 pwrst->next_state = state;
995 set_pwrdm_state(pwrst->pwrdm, state);
996 }
997}
998
68d4778c
TK		 999int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
1000{
1001 struct power_state *pwrst;
1002
1003 list_for_each_entry(pwrst, &pwrst_list, node) {
1004 if (pwrst->pwrdm == pwrdm)
1005 return pwrst->next_state;
1006 }
1007 return -EINVAL;
1008}
1009
1010int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
1011{
1012 struct power_state *pwrst;
1013
1014 list_for_each_entry(pwrst, &pwrst_list, node) {
1015 if (pwrst->pwrdm == pwrdm) {
1016 pwrst->next_state = state;
1017 return 0;
1018 }
1019 }
1020 return -EINVAL;
1021}
1022
a23456e9 1023static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
8bd22949
KH		 1024{
1025 struct power_state *pwrst;
1026
1027 if (!pwrdm->pwrsts)
1028 return 0;
1029
d3d381c6 1030 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
8bd22949
KH		 1031 if (!pwrst)
1032 return -ENOMEM;
1033 pwrst->pwrdm = pwrdm;
1034 pwrst->next_state = PWRDM_POWER_RET;
1035 list_add(&pwrst->node, &pwrst_list);
1036
1037 if (pwrdm_has_hdwr_sar(pwrdm))
1038 pwrdm_enable_hdwr_sar(pwrdm);
1039
1040 return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
1041}
1042
1043/*
1044 * Enable hw supervised mode for all clockdomains if it's
1045 * supported. Initiate sleep transition for other clockdomains, if
1046 * they are not used
1047 */
a23456e9 1048static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
8bd22949
KH		 1049{
1050 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
1051 omap2_clkdm_allow_idle(clkdm);
1052 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
1053 atomic_read(&clkdm->usecount) == 0)
1054 omap2_clkdm_sleep(clkdm);
1055 return 0;
1056}
1057
3231fc88
RN		 1058void omap_push_sram_idle(void)
1059{
1060 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
1061 omap34xx_cpu_suspend_sz);
27d59a4a
TK		 1062 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
1063 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
1064 save_secure_ram_context_sz);
3231fc88
RN		 1065}
1066
7cc515f7 1067static int __init omap3_pm_init(void)
8bd22949
KH		 1068{
1069 struct power_state *pwrst, *tmp;
1070 int ret;
1071
1072 if (!cpu_is_omap34xx())
1073 return -ENODEV;
1074
1075 printk(KERN_ERR "Power Management for TI OMAP3.\n");
1076
1077 /* XXX prcm_setup_regs needs to be before enabling hw
1078 * supervised mode for powerdomains */
1079 prcm_setup_regs();
1080
1081 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
1082 (irq_handler_t)prcm_interrupt_handler,
1083 IRQF_DISABLED, "prcm", NULL);
1084 if (ret) {
1085 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
1086 INT_34XX_PRCM_MPU_IRQ);
1087 goto err1;
1088 }
1089
a23456e9 1090 ret = pwrdm_for_each(pwrdms_setup, NULL);
8bd22949
KH		 1091 if (ret) {
1092 printk(KERN_ERR "Failed to setup powerdomains\n");
1093 goto err2;
1094 }
1095
a23456e9 1096 (void) clkdm_for_each(clkdms_setup, NULL);
8bd22949
KH		 1097
1098 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1099 if (mpu_pwrdm == NULL) {
1100 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1101 goto err2;
1102 }
1103
fa3c2a4f
RN		 1104 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1105 per_pwrdm = pwrdm_lookup("per_pwrdm");
1106 core_pwrdm = pwrdm_lookup("core_pwrdm");
c16c3f67 1107 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
fa3c2a4f 1108
3231fc88 1109 omap_push_sram_idle();
10f90ed2 1110#ifdef CONFIG_SUSPEND
8bd22949 1111 suspend_set_ops(&omap_pm_ops);
10f90ed2 1112#endif /* CONFIG_SUSPEND */
8bd22949
KH		 1113
1114 pm_idle = omap3_pm_idle;
1115
fa3c2a4f
RN		 1116 pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
1117 /*
1118 * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
1119 * IO-pad wakeup. Otherwise it will unnecessarily waste power
1120 * waking up PER with every CORE wakeup - see
1121 * http://marc.info/?l=linux-omap&m=121852150710062&w=2
1122 */
1123 pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
1124
27d59a4a
TK		 1125 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1126 omap3_secure_ram_storage =
1127 kmalloc(0x803F, GFP_KERNEL);
1128 if (!omap3_secure_ram_storage)
1129 printk(KERN_ERR "Memory allocation failed when"
1130 "allocating for secure sram context\n");
9d97140b
TK		 1131
1132 local_irq_disable();
1133 local_fiq_disable();
1134
1135 omap_dma_global_context_save();
1136 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1137 omap_dma_global_context_restore();
1138
1139 local_irq_enable();
1140 local_fiq_enable();
27d59a4a 1141 }
27d59a4a 1142
9d97140b 1143 omap3_save_scratchpad_contents();
8bd22949
KH		 1144err1:
1145 return ret;
1146err2:
1147 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1148 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1149 list_del(&pwrst->node);
1150 kfree(pwrst);
1151 }
1152 return ret;
1153}
1154
1155late_initcall(omap3_pm_init);
Linux 6.x block layer and io_uring tree(s)