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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, Benoît Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
75 | * | (__raw_{read,write}l, clk*) | | |
76 | * +-------------------------------+ | |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
133 | #include <linux/clk.h> | |
134 | #include <linux/delay.h> | |
135 | #include <linux/err.h> | |
136 | #include <linux/list.h> | |
137 | #include <linux/mutex.h> | |
dc6d1cda | 138 | #include <linux/spinlock.h> |
abc2d545 | 139 | #include <linux/slab.h> |
2221b5cd | 140 | #include <linux/bootmem.h> |
63c85238 | 141 | |
a135eaae | 142 | #include "clock.h" |
2a296c8f | 143 | #include "omap_hwmod.h" |
5365efbe | 144 | #include <plat/prcm.h> |
63c85238 | 145 | |
dbc04161 TL |
146 | #include "soc.h" |
147 | #include "common.h" | |
148 | #include "clockdomain.h" | |
149 | #include "powerdomain.h" | |
ff4ae5d9 PW |
150 | #include "cm2xxx.h" |
151 | #include "cm3xxx.h" | |
d0f0631d | 152 | #include "cminst44xx.h" |
1688bf19 | 153 | #include "cm33xx.h" |
139563ad | 154 | #include "prm3xxx.h" |
d198b514 | 155 | #include "prm44xx.h" |
1688bf19 | 156 | #include "prm33xx.h" |
eaac329d | 157 | #include "prminst44xx.h" |
8d9af88f | 158 | #include "mux.h" |
5165882a | 159 | #include "pm.h" |
63c85238 | 160 | |
5365efbe BC |
161 | /* Maximum microseconds to wait for OMAP module to softreset */ |
162 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | |
63c85238 PW |
163 | |
164 | /* Name of the OMAP hwmod for the MPU */ | |
5c2c0296 | 165 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 | 166 | |
2221b5cd PW |
167 | /* |
168 | * Number of struct omap_hwmod_link records per struct | |
169 | * omap_hwmod_ocp_if record (master->slave and slave->master) | |
170 | */ | |
171 | #define LINKS_PER_OCP_IF 2 | |
172 | ||
9ebfd285 KH |
173 | /** |
174 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | |
175 | * @enable_module: function to enable a module (via MODULEMODE) | |
176 | * @disable_module: function to disable a module (via MODULEMODE) | |
177 | * | |
178 | * XXX Eventually this functionality will be hidden inside the PRM/CM | |
179 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | |
180 | * conditionals in this code. | |
181 | */ | |
182 | struct omap_hwmod_soc_ops { | |
183 | void (*enable_module)(struct omap_hwmod *oh); | |
184 | int (*disable_module)(struct omap_hwmod *oh); | |
8f6aa8ee | 185 | int (*wait_target_ready)(struct omap_hwmod *oh); |
b8249cf2 KH |
186 | int (*assert_hardreset)(struct omap_hwmod *oh, |
187 | struct omap_hwmod_rst_info *ohri); | |
188 | int (*deassert_hardreset)(struct omap_hwmod *oh, | |
189 | struct omap_hwmod_rst_info *ohri); | |
190 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | |
191 | struct omap_hwmod_rst_info *ohri); | |
0a179eaa | 192 | int (*init_clkdm)(struct omap_hwmod *oh); |
9ebfd285 KH |
193 | }; |
194 | ||
195 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | |
196 | static struct omap_hwmod_soc_ops soc_ops; | |
197 | ||
63c85238 PW |
198 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
199 | static LIST_HEAD(omap_hwmod_list); | |
200 | ||
63c85238 PW |
201 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
202 | static struct omap_hwmod *mpu_oh; | |
203 | ||
5165882a VB |
204 | /* io_chain_lock: used to serialize reconfigurations of the I/O chain */ |
205 | static DEFINE_SPINLOCK(io_chain_lock); | |
206 | ||
2221b5cd PW |
207 | /* |
208 | * linkspace: ptr to a buffer that struct omap_hwmod_link records are | |
209 | * allocated from - used to reduce the number of small memory | |
210 | * allocations, which has a significant impact on performance | |
211 | */ | |
212 | static struct omap_hwmod_link *linkspace; | |
213 | ||
214 | /* | |
215 | * free_ls, max_ls: array indexes into linkspace; representing the | |
216 | * next free struct omap_hwmod_link index, and the maximum number of | |
217 | * struct omap_hwmod_link records allocated (respectively) | |
218 | */ | |
219 | static unsigned short free_ls, max_ls, ls_supp; | |
63c85238 | 220 | |
9ebfd285 KH |
221 | /* inited: set to true once the hwmod code is initialized */ |
222 | static bool inited; | |
223 | ||
63c85238 PW |
224 | /* Private functions */ |
225 | ||
5d95dde7 | 226 | /** |
11cd4b94 | 227 | * _fetch_next_ocp_if - return the next OCP interface in a list |
2221b5cd | 228 | * @p: ptr to a ptr to the list_head inside the ocp_if to return |
11cd4b94 PW |
229 | * @i: pointer to the index of the element pointed to by @p in the list |
230 | * | |
231 | * Return a pointer to the struct omap_hwmod_ocp_if record | |
232 | * containing the struct list_head pointed to by @p, and increment | |
233 | * @p such that a future call to this routine will return the next | |
234 | * record. | |
5d95dde7 PW |
235 | */ |
236 | static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p, | |
5d95dde7 PW |
237 | int *i) |
238 | { | |
239 | struct omap_hwmod_ocp_if *oi; | |
240 | ||
11cd4b94 PW |
241 | oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if; |
242 | *p = (*p)->next; | |
2221b5cd | 243 | |
5d95dde7 PW |
244 | *i = *i + 1; |
245 | ||
246 | return oi; | |
247 | } | |
248 | ||
63c85238 PW |
249 | /** |
250 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
251 | * @oh: struct omap_hwmod * | |
252 | * | |
253 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
254 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
255 | * OCP_SYSCONFIG register or 0 upon success. | |
256 | */ | |
257 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
258 | { | |
43b40992 PW |
259 | if (!oh->class->sysc) { |
260 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
261 | return -EINVAL; |
262 | } | |
263 | ||
264 | /* XXX ensure module interface clock is up */ | |
265 | ||
cc7a1d2a | 266 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 267 | |
43b40992 | 268 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 269 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
270 | |
271 | return 0; | |
272 | } | |
273 | ||
274 | /** | |
275 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
276 | * @v: OCP_SYSCONFIG value to write | |
277 | * @oh: struct omap_hwmod * | |
278 | * | |
43b40992 PW |
279 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
280 | * one. No return value. | |
63c85238 PW |
281 | */ |
282 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
283 | { | |
43b40992 PW |
284 | if (!oh->class->sysc) { |
285 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
286 | return; |
287 | } | |
288 | ||
289 | /* XXX ensure module interface clock is up */ | |
290 | ||
233cbe5b RN |
291 | /* Module might have lost context, always update cache and register */ |
292 | oh->_sysc_cache = v; | |
293 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); | |
63c85238 PW |
294 | } |
295 | ||
296 | /** | |
297 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
298 | * @oh: struct omap_hwmod * | |
299 | * @standbymode: MIDLEMODE field bits | |
300 | * @v: pointer to register contents to modify | |
301 | * | |
302 | * Update the master standby mode bits in @v to be @standbymode for | |
303 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
304 | * upon error or 0 upon success. | |
305 | */ | |
306 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
307 | u32 *v) | |
308 | { | |
358f0e63 TG |
309 | u32 mstandby_mask; |
310 | u8 mstandby_shift; | |
311 | ||
43b40992 PW |
312 | if (!oh->class->sysc || |
313 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
314 | return -EINVAL; |
315 | ||
43b40992 PW |
316 | if (!oh->class->sysc->sysc_fields) { |
317 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
318 | return -EINVAL; |
319 | } | |
320 | ||
43b40992 | 321 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
322 | mstandby_mask = (0x3 << mstandby_shift); |
323 | ||
324 | *v &= ~mstandby_mask; | |
325 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
326 | |
327 | return 0; | |
328 | } | |
329 | ||
330 | /** | |
331 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
332 | * @oh: struct omap_hwmod * | |
333 | * @idlemode: SIDLEMODE field bits | |
334 | * @v: pointer to register contents to modify | |
335 | * | |
336 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
337 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
338 | * or 0 upon success. | |
339 | */ | |
340 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
341 | { | |
358f0e63 TG |
342 | u32 sidle_mask; |
343 | u8 sidle_shift; | |
344 | ||
43b40992 PW |
345 | if (!oh->class->sysc || |
346 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
347 | return -EINVAL; |
348 | ||
43b40992 PW |
349 | if (!oh->class->sysc->sysc_fields) { |
350 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
351 | return -EINVAL; |
352 | } | |
353 | ||
43b40992 | 354 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
355 | sidle_mask = (0x3 << sidle_shift); |
356 | ||
357 | *v &= ~sidle_mask; | |
358 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
359 | |
360 | return 0; | |
361 | } | |
362 | ||
363 | /** | |
364 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
365 | * @oh: struct omap_hwmod * | |
366 | * @clockact: CLOCKACTIVITY field bits | |
367 | * @v: pointer to register contents to modify | |
368 | * | |
369 | * Update the clockactivity mode bits in @v to be @clockact for the | |
370 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
371 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
372 | * success. | |
373 | */ | |
374 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
375 | { | |
358f0e63 TG |
376 | u32 clkact_mask; |
377 | u8 clkact_shift; | |
378 | ||
43b40992 PW |
379 | if (!oh->class->sysc || |
380 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
381 | return -EINVAL; |
382 | ||
43b40992 PW |
383 | if (!oh->class->sysc->sysc_fields) { |
384 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
385 | return -EINVAL; |
386 | } | |
387 | ||
43b40992 | 388 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
389 | clkact_mask = (0x3 << clkact_shift); |
390 | ||
391 | *v &= ~clkact_mask; | |
392 | *v |= clockact << clkact_shift; | |
63c85238 PW |
393 | |
394 | return 0; | |
395 | } | |
396 | ||
397 | /** | |
398 | * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
399 | * @oh: struct omap_hwmod * | |
400 | * @v: pointer to register contents to modify | |
401 | * | |
402 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
403 | * error or 0 upon success. | |
404 | */ | |
405 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
406 | { | |
358f0e63 TG |
407 | u32 softrst_mask; |
408 | ||
43b40992 PW |
409 | if (!oh->class->sysc || |
410 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
411 | return -EINVAL; |
412 | ||
43b40992 PW |
413 | if (!oh->class->sysc->sysc_fields) { |
414 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
415 | return -EINVAL; |
416 | } | |
417 | ||
43b40992 | 418 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
419 | |
420 | *v |= softrst_mask; | |
63c85238 PW |
421 | |
422 | return 0; | |
423 | } | |
424 | ||
6668546f KVA |
425 | /** |
426 | * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v | |
427 | * @oh: struct omap_hwmod * | |
428 | * | |
429 | * The DMADISABLE bit is a semi-automatic bit present in sysconfig register | |
430 | * of some modules. When the DMA must perform read/write accesses, the | |
431 | * DMADISABLE bit is cleared by the hardware. But when the DMA must stop | |
432 | * for power management, software must set the DMADISABLE bit back to 1. | |
433 | * | |
434 | * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon | |
435 | * error or 0 upon success. | |
436 | */ | |
437 | static int _set_dmadisable(struct omap_hwmod *oh) | |
438 | { | |
439 | u32 v; | |
440 | u32 dmadisable_mask; | |
441 | ||
442 | if (!oh->class->sysc || | |
443 | !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE)) | |
444 | return -EINVAL; | |
445 | ||
446 | if (!oh->class->sysc->sysc_fields) { | |
447 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
448 | return -EINVAL; | |
449 | } | |
450 | ||
451 | /* clocks must be on for this operation */ | |
452 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
453 | pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name); | |
454 | return -EINVAL; | |
455 | } | |
456 | ||
457 | pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name); | |
458 | ||
459 | v = oh->_sysc_cache; | |
460 | dmadisable_mask = | |
461 | (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift); | |
462 | v |= dmadisable_mask; | |
463 | _write_sysconfig(v, oh); | |
464 | ||
465 | return 0; | |
466 | } | |
467 | ||
726072e5 PW |
468 | /** |
469 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
470 | * @oh: struct omap_hwmod * | |
471 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
472 | * @v: pointer to register contents to modify | |
473 | * | |
474 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
475 | * hwmod. The autoidle bit controls whether the module can gate | |
476 | * internal clocks automatically when it isn't doing anything; the | |
477 | * exact function of this bit varies on a per-module basis. This | |
478 | * function does not write to the hardware. Returns -EINVAL upon | |
479 | * error or 0 upon success. | |
480 | */ | |
481 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
482 | u32 *v) | |
483 | { | |
358f0e63 TG |
484 | u32 autoidle_mask; |
485 | u8 autoidle_shift; | |
486 | ||
43b40992 PW |
487 | if (!oh->class->sysc || |
488 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
489 | return -EINVAL; |
490 | ||
43b40992 PW |
491 | if (!oh->class->sysc->sysc_fields) { |
492 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
493 | return -EINVAL; |
494 | } | |
495 | ||
43b40992 | 496 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 497 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
498 | |
499 | *v &= ~autoidle_mask; | |
500 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
501 | |
502 | return 0; | |
503 | } | |
504 | ||
eceec009 G |
505 | /** |
506 | * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux | |
507 | * @oh: struct omap_hwmod * | |
508 | * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable | |
509 | * | |
510 | * Set or clear the I/O pad wakeup flag in the mux entries for the | |
511 | * hwmod @oh. This function changes the @oh->mux->pads_dynamic array | |
512 | * in memory. If the hwmod is currently idled, and the new idle | |
513 | * values don't match the previous ones, this function will also | |
514 | * update the SCM PADCTRL registers. Otherwise, if the hwmod is not | |
515 | * currently idled, this function won't touch the hardware: the new | |
516 | * mux settings are written to the SCM PADCTRL registers when the | |
517 | * hwmod is idled. No return value. | |
518 | */ | |
519 | static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake) | |
520 | { | |
521 | struct omap_device_pad *pad; | |
522 | bool change = false; | |
523 | u16 prev_idle; | |
524 | int j; | |
525 | ||
526 | if (!oh->mux || !oh->mux->enabled) | |
527 | return; | |
528 | ||
529 | for (j = 0; j < oh->mux->nr_pads_dynamic; j++) { | |
530 | pad = oh->mux->pads_dynamic[j]; | |
531 | ||
532 | if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP)) | |
533 | continue; | |
534 | ||
535 | prev_idle = pad->idle; | |
536 | ||
537 | if (set_wake) | |
538 | pad->idle |= OMAP_WAKEUP_EN; | |
539 | else | |
540 | pad->idle &= ~OMAP_WAKEUP_EN; | |
541 | ||
542 | if (prev_idle != pad->idle) | |
543 | change = true; | |
544 | } | |
545 | ||
546 | if (change && oh->_state == _HWMOD_STATE_IDLE) | |
547 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); | |
548 | } | |
549 | ||
63c85238 PW |
550 | /** |
551 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
552 | * @oh: struct omap_hwmod * | |
553 | * | |
554 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
555 | * upon error or 0 upon success. | |
556 | */ | |
5a7ddcbd | 557 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 558 | { |
43b40992 | 559 | if (!oh->class->sysc || |
86009eb3 | 560 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
561 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
562 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
563 | return -EINVAL; |
564 | ||
43b40992 PW |
565 | if (!oh->class->sysc->sysc_fields) { |
566 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
567 | return -EINVAL; |
568 | } | |
569 | ||
1fe74113 BC |
570 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
571 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 572 | |
86009eb3 BC |
573 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
574 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
575 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
576 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 577 | |
63c85238 PW |
578 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
579 | ||
580 | oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
585 | /** | |
586 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
587 | * @oh: struct omap_hwmod * | |
588 | * | |
589 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
590 | * upon error or 0 upon success. | |
591 | */ | |
5a7ddcbd | 592 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 593 | { |
43b40992 | 594 | if (!oh->class->sysc || |
86009eb3 | 595 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
596 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
597 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
598 | return -EINVAL; |
599 | ||
43b40992 PW |
600 | if (!oh->class->sysc->sysc_fields) { |
601 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
602 | return -EINVAL; |
603 | } | |
604 | ||
1fe74113 BC |
605 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
606 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 607 | |
86009eb3 BC |
608 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
609 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 | 610 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
561038f0 | 611 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v); |
86009eb3 | 612 | |
63c85238 PW |
613 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
614 | ||
615 | oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
620 | /** | |
621 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
622 | * @oh: struct omap_hwmod * | |
623 | * | |
624 | * Prevent the hardware module @oh from entering idle while the | |
625 | * hardare module initiator @init_oh is active. Useful when a module | |
626 | * will be accessed by a particular initiator (e.g., if a module will | |
627 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
628 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
629 | * mode. If the clockdomain is marked as not needing autodeps, return |
630 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
631 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
632 | */ |
633 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
634 | { | |
635 | if (!oh->_clk) | |
636 | return -EINVAL; | |
637 | ||
570b54c7 PW |
638 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
639 | return 0; | |
640 | ||
55ed9694 | 641 | return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
642 | } |
643 | ||
644 | /** | |
645 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
646 | * @oh: struct omap_hwmod * | |
647 | * | |
648 | * Allow the hardware module @oh to enter idle while the hardare | |
649 | * module initiator @init_oh is active. Useful when a module will not | |
650 | * be accessed by a particular initiator (e.g., if a module will not | |
651 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
652 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
653 | * mode. If the clockdomain is marked as not needing autodeps, return |
654 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
655 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
656 | */ |
657 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
658 | { | |
659 | if (!oh->_clk) | |
660 | return -EINVAL; | |
661 | ||
570b54c7 PW |
662 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
663 | return 0; | |
664 | ||
55ed9694 | 665 | return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
666 | } |
667 | ||
668 | /** | |
669 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
670 | * @oh: struct omap_hwmod * | |
671 | * | |
672 | * Called from _init_clocks(). Populates the @oh _clk (main | |
673 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
674 | * success or -EINVAL on error. | |
675 | */ | |
676 | static int _init_main_clk(struct omap_hwmod *oh) | |
677 | { | |
63c85238 PW |
678 | int ret = 0; |
679 | ||
50ebdac2 | 680 | if (!oh->main_clk) |
63c85238 PW |
681 | return 0; |
682 | ||
6ea74cb9 RN |
683 | oh->_clk = clk_get(NULL, oh->main_clk); |
684 | if (IS_ERR(oh->_clk)) { | |
20383d82 BC |
685 | pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
686 | oh->name, oh->main_clk); | |
63403384 | 687 | return -EINVAL; |
dc75925d | 688 | } |
4d7cb45e RN |
689 | /* |
690 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
691 | * to do something meaningful. Today its just a no-op. | |
692 | * If clk_prepare() is used at some point to do things like | |
693 | * voltage scaling etc, then this would have to be moved to | |
694 | * some point where subsystems like i2c and pmic become | |
695 | * available. | |
696 | */ | |
697 | clk_prepare(oh->_clk); | |
63c85238 | 698 | |
63403384 | 699 | if (!oh->_clk->clkdm) |
3bb05dbf | 700 | pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", |
5dcc3b97 | 701 | oh->name, oh->main_clk); |
81d7c6ff | 702 | |
63c85238 PW |
703 | return ret; |
704 | } | |
705 | ||
706 | /** | |
887adeac | 707 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
708 | * @oh: struct omap_hwmod * |
709 | * | |
710 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
711 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
712 | */ | |
713 | static int _init_interface_clks(struct omap_hwmod *oh) | |
714 | { | |
5d95dde7 | 715 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 716 | struct list_head *p; |
63c85238 | 717 | struct clk *c; |
5d95dde7 | 718 | int i = 0; |
63c85238 PW |
719 | int ret = 0; |
720 | ||
11cd4b94 | 721 | p = oh->slave_ports.next; |
2221b5cd | 722 | |
5d95dde7 | 723 | while (i < oh->slaves_cnt) { |
11cd4b94 | 724 | os = _fetch_next_ocp_if(&p, &i); |
50ebdac2 | 725 | if (!os->clk) |
63c85238 PW |
726 | continue; |
727 | ||
6ea74cb9 RN |
728 | c = clk_get(NULL, os->clk); |
729 | if (IS_ERR(c)) { | |
20383d82 BC |
730 | pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
731 | oh->name, os->clk); | |
63c85238 | 732 | ret = -EINVAL; |
dc75925d | 733 | } |
63c85238 | 734 | os->_clk = c; |
4d7cb45e RN |
735 | /* |
736 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
737 | * to do something meaningful. Today its just a no-op. | |
738 | * If clk_prepare() is used at some point to do things like | |
739 | * voltage scaling etc, then this would have to be moved to | |
740 | * some point where subsystems like i2c and pmic become | |
741 | * available. | |
742 | */ | |
743 | clk_prepare(os->_clk); | |
63c85238 PW |
744 | } |
745 | ||
746 | return ret; | |
747 | } | |
748 | ||
749 | /** | |
750 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
751 | * @oh: struct omap_hwmod * | |
752 | * | |
753 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
754 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
755 | */ | |
756 | static int _init_opt_clks(struct omap_hwmod *oh) | |
757 | { | |
758 | struct omap_hwmod_opt_clk *oc; | |
759 | struct clk *c; | |
760 | int i; | |
761 | int ret = 0; | |
762 | ||
763 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
6ea74cb9 RN |
764 | c = clk_get(NULL, oc->clk); |
765 | if (IS_ERR(c)) { | |
20383d82 BC |
766 | pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
767 | oh->name, oc->clk); | |
63c85238 | 768 | ret = -EINVAL; |
dc75925d | 769 | } |
63c85238 | 770 | oc->_clk = c; |
4d7cb45e RN |
771 | /* |
772 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
773 | * to do something meaningful. Today its just a no-op. | |
774 | * If clk_prepare() is used at some point to do things like | |
775 | * voltage scaling etc, then this would have to be moved to | |
776 | * some point where subsystems like i2c and pmic become | |
777 | * available. | |
778 | */ | |
779 | clk_prepare(oc->_clk); | |
63c85238 PW |
780 | } |
781 | ||
782 | return ret; | |
783 | } | |
784 | ||
785 | /** | |
786 | * _enable_clocks - enable hwmod main clock and interface clocks | |
787 | * @oh: struct omap_hwmod * | |
788 | * | |
789 | * Enables all clocks necessary for register reads and writes to succeed | |
790 | * on the hwmod @oh. Returns 0. | |
791 | */ | |
792 | static int _enable_clocks(struct omap_hwmod *oh) | |
793 | { | |
5d95dde7 | 794 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 795 | struct list_head *p; |
5d95dde7 | 796 | int i = 0; |
63c85238 PW |
797 | |
798 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
799 | ||
4d3ae5a9 | 800 | if (oh->_clk) |
63c85238 PW |
801 | clk_enable(oh->_clk); |
802 | ||
11cd4b94 | 803 | p = oh->slave_ports.next; |
2221b5cd | 804 | |
5d95dde7 | 805 | while (i < oh->slaves_cnt) { |
11cd4b94 | 806 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 807 | |
5d95dde7 PW |
808 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
809 | clk_enable(os->_clk); | |
63c85238 PW |
810 | } |
811 | ||
812 | /* The opt clocks are controlled by the device driver. */ | |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
817 | /** | |
818 | * _disable_clocks - disable hwmod main clock and interface clocks | |
819 | * @oh: struct omap_hwmod * | |
820 | * | |
821 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
822 | */ | |
823 | static int _disable_clocks(struct omap_hwmod *oh) | |
824 | { | |
5d95dde7 | 825 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 826 | struct list_head *p; |
5d95dde7 | 827 | int i = 0; |
63c85238 PW |
828 | |
829 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
830 | ||
4d3ae5a9 | 831 | if (oh->_clk) |
63c85238 PW |
832 | clk_disable(oh->_clk); |
833 | ||
11cd4b94 | 834 | p = oh->slave_ports.next; |
2221b5cd | 835 | |
5d95dde7 | 836 | while (i < oh->slaves_cnt) { |
11cd4b94 | 837 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 838 | |
5d95dde7 PW |
839 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
840 | clk_disable(os->_clk); | |
63c85238 PW |
841 | } |
842 | ||
843 | /* The opt clocks are controlled by the device driver. */ | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
96835af9 BC |
848 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
849 | { | |
850 | struct omap_hwmod_opt_clk *oc; | |
851 | int i; | |
852 | ||
853 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
854 | ||
855 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
856 | if (oc->_clk) { | |
857 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
5dcc3b97 | 858 | __clk_get_name(oc->_clk)); |
96835af9 BC |
859 | clk_enable(oc->_clk); |
860 | } | |
861 | } | |
862 | ||
863 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
864 | { | |
865 | struct omap_hwmod_opt_clk *oc; | |
866 | int i; | |
867 | ||
868 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
869 | ||
870 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
871 | if (oc->_clk) { | |
872 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
5dcc3b97 | 873 | __clk_get_name(oc->_clk)); |
96835af9 BC |
874 | clk_disable(oc->_clk); |
875 | } | |
876 | } | |
877 | ||
45c38252 | 878 | /** |
3d9f0327 | 879 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
45c38252 BC |
880 | * @oh: struct omap_hwmod * |
881 | * | |
882 | * Enables the PRCM module mode related to the hwmod @oh. | |
883 | * No return value. | |
884 | */ | |
3d9f0327 | 885 | static void _omap4_enable_module(struct omap_hwmod *oh) |
45c38252 | 886 | { |
45c38252 BC |
887 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
888 | return; | |
889 | ||
3d9f0327 KH |
890 | pr_debug("omap_hwmod: %s: %s: %d\n", |
891 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
45c38252 BC |
892 | |
893 | omap4_cminst_module_enable(oh->prcm.omap4.modulemode, | |
894 | oh->clkdm->prcm_partition, | |
895 | oh->clkdm->cm_inst, | |
896 | oh->clkdm->clkdm_offs, | |
897 | oh->prcm.omap4.clkctrl_offs); | |
898 | } | |
899 | ||
1688bf19 VH |
900 | /** |
901 | * _am33xx_enable_module - enable CLKCTRL modulemode on AM33XX | |
902 | * @oh: struct omap_hwmod * | |
903 | * | |
904 | * Enables the PRCM module mode related to the hwmod @oh. | |
905 | * No return value. | |
906 | */ | |
907 | static void _am33xx_enable_module(struct omap_hwmod *oh) | |
908 | { | |
909 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
910 | return; | |
911 | ||
912 | pr_debug("omap_hwmod: %s: %s: %d\n", | |
913 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
914 | ||
915 | am33xx_cm_module_enable(oh->prcm.omap4.modulemode, oh->clkdm->cm_inst, | |
916 | oh->clkdm->clkdm_offs, | |
917 | oh->prcm.omap4.clkctrl_offs); | |
918 | } | |
919 | ||
45c38252 | 920 | /** |
bfc141e3 BC |
921 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
922 | * @oh: struct omap_hwmod * | |
923 | * | |
924 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
925 | * does not have an IDLEST bit or if the module successfully enters | |
926 | * slave idle; otherwise, pass along the return value of the | |
927 | * appropriate *_cm*_wait_module_idle() function. | |
928 | */ | |
929 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
930 | { | |
2b026d13 | 931 | if (!oh) |
bfc141e3 BC |
932 | return -EINVAL; |
933 | ||
2b026d13 | 934 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm) |
bfc141e3 BC |
935 | return 0; |
936 | ||
937 | if (oh->flags & HWMOD_NO_IDLEST) | |
938 | return 0; | |
939 | ||
940 | return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition, | |
941 | oh->clkdm->cm_inst, | |
942 | oh->clkdm->clkdm_offs, | |
943 | oh->prcm.omap4.clkctrl_offs); | |
944 | } | |
945 | ||
1688bf19 VH |
946 | /** |
947 | * _am33xx_wait_target_disable - wait for a module to be disabled on AM33XX | |
948 | * @oh: struct omap_hwmod * | |
949 | * | |
950 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
951 | * does not have an IDLEST bit or if the module successfully enters | |
952 | * slave idle; otherwise, pass along the return value of the | |
953 | * appropriate *_cm*_wait_module_idle() function. | |
954 | */ | |
955 | static int _am33xx_wait_target_disable(struct omap_hwmod *oh) | |
956 | { | |
957 | if (!oh) | |
958 | return -EINVAL; | |
959 | ||
960 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
961 | return 0; | |
962 | ||
963 | if (oh->flags & HWMOD_NO_IDLEST) | |
964 | return 0; | |
965 | ||
966 | return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst, | |
967 | oh->clkdm->clkdm_offs, | |
968 | oh->prcm.omap4.clkctrl_offs); | |
969 | } | |
970 | ||
212738a4 PW |
971 | /** |
972 | * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh | |
973 | * @oh: struct omap_hwmod *oh | |
974 | * | |
975 | * Count and return the number of MPU IRQs associated with the hwmod | |
976 | * @oh. Used to allocate struct resource data. Returns 0 if @oh is | |
977 | * NULL. | |
978 | */ | |
979 | static int _count_mpu_irqs(struct omap_hwmod *oh) | |
980 | { | |
981 | struct omap_hwmod_irq_info *ohii; | |
982 | int i = 0; | |
983 | ||
984 | if (!oh || !oh->mpu_irqs) | |
985 | return 0; | |
986 | ||
987 | do { | |
988 | ohii = &oh->mpu_irqs[i++]; | |
989 | } while (ohii->irq != -1); | |
990 | ||
cc1b0765 | 991 | return i-1; |
212738a4 PW |
992 | } |
993 | ||
bc614958 PW |
994 | /** |
995 | * _count_sdma_reqs - count the number of SDMA request lines associated with @oh | |
996 | * @oh: struct omap_hwmod *oh | |
997 | * | |
998 | * Count and return the number of SDMA request lines associated with | |
999 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1000 | * if @oh is NULL. | |
1001 | */ | |
1002 | static int _count_sdma_reqs(struct omap_hwmod *oh) | |
1003 | { | |
1004 | struct omap_hwmod_dma_info *ohdi; | |
1005 | int i = 0; | |
1006 | ||
1007 | if (!oh || !oh->sdma_reqs) | |
1008 | return 0; | |
1009 | ||
1010 | do { | |
1011 | ohdi = &oh->sdma_reqs[i++]; | |
1012 | } while (ohdi->dma_req != -1); | |
1013 | ||
cc1b0765 | 1014 | return i-1; |
bc614958 PW |
1015 | } |
1016 | ||
78183f3f PW |
1017 | /** |
1018 | * _count_ocp_if_addr_spaces - count the number of address space entries for @oh | |
1019 | * @oh: struct omap_hwmod *oh | |
1020 | * | |
1021 | * Count and return the number of address space ranges associated with | |
1022 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1023 | * if @oh is NULL. | |
1024 | */ | |
1025 | static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) | |
1026 | { | |
1027 | struct omap_hwmod_addr_space *mem; | |
1028 | int i = 0; | |
1029 | ||
1030 | if (!os || !os->addr) | |
1031 | return 0; | |
1032 | ||
1033 | do { | |
1034 | mem = &os->addr[i++]; | |
1035 | } while (mem->pa_start != mem->pa_end); | |
1036 | ||
cc1b0765 | 1037 | return i-1; |
78183f3f PW |
1038 | } |
1039 | ||
5e8370f1 PW |
1040 | /** |
1041 | * _get_mpu_irq_by_name - fetch MPU interrupt line number by name | |
1042 | * @oh: struct omap_hwmod * to operate on | |
1043 | * @name: pointer to the name of the MPU interrupt number to fetch (optional) | |
1044 | * @irq: pointer to an unsigned int to store the MPU IRQ number to | |
1045 | * | |
1046 | * Retrieve a MPU hardware IRQ line number named by @name associated | |
1047 | * with the IP block pointed to by @oh. The IRQ number will be filled | |
1048 | * into the address pointed to by @dma. When @name is non-null, the | |
1049 | * IRQ line number associated with the named entry will be returned. | |
1050 | * If @name is null, the first matching entry will be returned. Data | |
1051 | * order is not meaningful in hwmod data, so callers are strongly | |
1052 | * encouraged to use a non-null @name whenever possible to avoid | |
1053 | * unpredictable effects if hwmod data is later added that causes data | |
1054 | * ordering to change. Returns 0 upon success or a negative error | |
1055 | * code upon error. | |
1056 | */ | |
1057 | static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, | |
1058 | unsigned int *irq) | |
1059 | { | |
1060 | int i; | |
1061 | bool found = false; | |
1062 | ||
1063 | if (!oh->mpu_irqs) | |
1064 | return -ENOENT; | |
1065 | ||
1066 | i = 0; | |
1067 | while (oh->mpu_irqs[i].irq != -1) { | |
1068 | if (name == oh->mpu_irqs[i].name || | |
1069 | !strcmp(name, oh->mpu_irqs[i].name)) { | |
1070 | found = true; | |
1071 | break; | |
1072 | } | |
1073 | i++; | |
1074 | } | |
1075 | ||
1076 | if (!found) | |
1077 | return -ENOENT; | |
1078 | ||
1079 | *irq = oh->mpu_irqs[i].irq; | |
1080 | ||
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | /** | |
1085 | * _get_sdma_req_by_name - fetch SDMA request line ID by name | |
1086 | * @oh: struct omap_hwmod * to operate on | |
1087 | * @name: pointer to the name of the SDMA request line to fetch (optional) | |
1088 | * @dma: pointer to an unsigned int to store the request line ID to | |
1089 | * | |
1090 | * Retrieve an SDMA request line ID named by @name on the IP block | |
1091 | * pointed to by @oh. The ID will be filled into the address pointed | |
1092 | * to by @dma. When @name is non-null, the request line ID associated | |
1093 | * with the named entry will be returned. If @name is null, the first | |
1094 | * matching entry will be returned. Data order is not meaningful in | |
1095 | * hwmod data, so callers are strongly encouraged to use a non-null | |
1096 | * @name whenever possible to avoid unpredictable effects if hwmod | |
1097 | * data is later added that causes data ordering to change. Returns 0 | |
1098 | * upon success or a negative error code upon error. | |
1099 | */ | |
1100 | static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, | |
1101 | unsigned int *dma) | |
1102 | { | |
1103 | int i; | |
1104 | bool found = false; | |
1105 | ||
1106 | if (!oh->sdma_reqs) | |
1107 | return -ENOENT; | |
1108 | ||
1109 | i = 0; | |
1110 | while (oh->sdma_reqs[i].dma_req != -1) { | |
1111 | if (name == oh->sdma_reqs[i].name || | |
1112 | !strcmp(name, oh->sdma_reqs[i].name)) { | |
1113 | found = true; | |
1114 | break; | |
1115 | } | |
1116 | i++; | |
1117 | } | |
1118 | ||
1119 | if (!found) | |
1120 | return -ENOENT; | |
1121 | ||
1122 | *dma = oh->sdma_reqs[i].dma_req; | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | /** | |
1128 | * _get_addr_space_by_name - fetch address space start & end by name | |
1129 | * @oh: struct omap_hwmod * to operate on | |
1130 | * @name: pointer to the name of the address space to fetch (optional) | |
1131 | * @pa_start: pointer to a u32 to store the starting address to | |
1132 | * @pa_end: pointer to a u32 to store the ending address to | |
1133 | * | |
1134 | * Retrieve address space start and end addresses for the IP block | |
1135 | * pointed to by @oh. The data will be filled into the addresses | |
1136 | * pointed to by @pa_start and @pa_end. When @name is non-null, the | |
1137 | * address space data associated with the named entry will be | |
1138 | * returned. If @name is null, the first matching entry will be | |
1139 | * returned. Data order is not meaningful in hwmod data, so callers | |
1140 | * are strongly encouraged to use a non-null @name whenever possible | |
1141 | * to avoid unpredictable effects if hwmod data is later added that | |
1142 | * causes data ordering to change. Returns 0 upon success or a | |
1143 | * negative error code upon error. | |
1144 | */ | |
1145 | static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, | |
1146 | u32 *pa_start, u32 *pa_end) | |
1147 | { | |
1148 | int i, j; | |
1149 | struct omap_hwmod_ocp_if *os; | |
2221b5cd | 1150 | struct list_head *p = NULL; |
5e8370f1 PW |
1151 | bool found = false; |
1152 | ||
11cd4b94 | 1153 | p = oh->slave_ports.next; |
2221b5cd | 1154 | |
5d95dde7 PW |
1155 | i = 0; |
1156 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 1157 | os = _fetch_next_ocp_if(&p, &i); |
5e8370f1 PW |
1158 | |
1159 | if (!os->addr) | |
1160 | return -ENOENT; | |
1161 | ||
1162 | j = 0; | |
1163 | while (os->addr[j].pa_start != os->addr[j].pa_end) { | |
1164 | if (name == os->addr[j].name || | |
1165 | !strcmp(name, os->addr[j].name)) { | |
1166 | found = true; | |
1167 | break; | |
1168 | } | |
1169 | j++; | |
1170 | } | |
1171 | ||
1172 | if (found) | |
1173 | break; | |
1174 | } | |
1175 | ||
1176 | if (!found) | |
1177 | return -ENOENT; | |
1178 | ||
1179 | *pa_start = os->addr[j].pa_start; | |
1180 | *pa_end = os->addr[j].pa_end; | |
1181 | ||
1182 | return 0; | |
1183 | } | |
1184 | ||
63c85238 | 1185 | /** |
24dbc213 | 1186 | * _save_mpu_port_index - find and save the index to @oh's MPU port |
63c85238 PW |
1187 | * @oh: struct omap_hwmod * |
1188 | * | |
24dbc213 PW |
1189 | * Determines the array index of the OCP slave port that the MPU uses |
1190 | * to address the device, and saves it into the struct omap_hwmod. | |
1191 | * Intended to be called during hwmod registration only. No return | |
1192 | * value. | |
63c85238 | 1193 | */ |
24dbc213 | 1194 | static void __init _save_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 1195 | { |
24dbc213 | 1196 | struct omap_hwmod_ocp_if *os = NULL; |
11cd4b94 | 1197 | struct list_head *p; |
5d95dde7 | 1198 | int i = 0; |
63c85238 | 1199 | |
5d95dde7 | 1200 | if (!oh) |
24dbc213 PW |
1201 | return; |
1202 | ||
1203 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
63c85238 | 1204 | |
11cd4b94 | 1205 | p = oh->slave_ports.next; |
2221b5cd | 1206 | |
5d95dde7 | 1207 | while (i < oh->slaves_cnt) { |
11cd4b94 | 1208 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 1209 | if (os->user & OCP_USER_MPU) { |
2221b5cd | 1210 | oh->_mpu_port = os; |
24dbc213 | 1211 | oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; |
63c85238 PW |
1212 | break; |
1213 | } | |
1214 | } | |
1215 | ||
24dbc213 | 1216 | return; |
63c85238 PW |
1217 | } |
1218 | ||
2d6141ba PW |
1219 | /** |
1220 | * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU | |
1221 | * @oh: struct omap_hwmod * | |
1222 | * | |
1223 | * Given a pointer to a struct omap_hwmod record @oh, return a pointer | |
1224 | * to the struct omap_hwmod_ocp_if record that is used by the MPU to | |
1225 | * communicate with the IP block. This interface need not be directly | |
1226 | * connected to the MPU (and almost certainly is not), but is directly | |
1227 | * connected to the IP block represented by @oh. Returns a pointer | |
1228 | * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon | |
1229 | * error or if there does not appear to be a path from the MPU to this | |
1230 | * IP block. | |
1231 | */ | |
1232 | static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) | |
1233 | { | |
1234 | if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) | |
1235 | return NULL; | |
1236 | ||
11cd4b94 | 1237 | return oh->_mpu_port; |
2d6141ba PW |
1238 | }; |
1239 | ||
63c85238 | 1240 | /** |
c9aafd23 | 1241 | * _find_mpu_rt_addr_space - return MPU register target address space for @oh |
63c85238 PW |
1242 | * @oh: struct omap_hwmod * |
1243 | * | |
c9aafd23 PW |
1244 | * Returns a pointer to the struct omap_hwmod_addr_space record representing |
1245 | * the register target MPU address space; or returns NULL upon error. | |
63c85238 | 1246 | */ |
c9aafd23 | 1247 | static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) |
63c85238 PW |
1248 | { |
1249 | struct omap_hwmod_ocp_if *os; | |
1250 | struct omap_hwmod_addr_space *mem; | |
c9aafd23 | 1251 | int found = 0, i = 0; |
63c85238 | 1252 | |
2d6141ba | 1253 | os = _find_mpu_rt_port(oh); |
24dbc213 | 1254 | if (!os || !os->addr) |
78183f3f PW |
1255 | return NULL; |
1256 | ||
1257 | do { | |
1258 | mem = &os->addr[i++]; | |
1259 | if (mem->flags & ADDR_TYPE_RT) | |
63c85238 | 1260 | found = 1; |
78183f3f | 1261 | } while (!found && mem->pa_start != mem->pa_end); |
63c85238 | 1262 | |
c9aafd23 | 1263 | return (found) ? mem : NULL; |
63c85238 PW |
1264 | } |
1265 | ||
1266 | /** | |
74ff3a68 | 1267 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
1268 | * @oh: struct omap_hwmod * |
1269 | * | |
006c7f18 PW |
1270 | * Ensure that the OCP_SYSCONFIG register for the IP block represented |
1271 | * by @oh is set to indicate to the PRCM that the IP block is active. | |
1272 | * Usually this means placing the module into smart-idle mode and | |
1273 | * smart-standby, but if there is a bug in the automatic idle handling | |
1274 | * for the IP block, it may need to be placed into the force-idle or | |
1275 | * no-idle variants of these modes. No return value. | |
63c85238 | 1276 | */ |
74ff3a68 | 1277 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 1278 | { |
43b40992 | 1279 | u8 idlemode, sf; |
63c85238 | 1280 | u32 v; |
006c7f18 | 1281 | bool clkdm_act; |
63c85238 | 1282 | |
43b40992 | 1283 | if (!oh->class->sysc) |
63c85238 PW |
1284 | return; |
1285 | ||
1286 | v = oh->_sysc_cache; | |
43b40992 | 1287 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1288 | |
43b40992 | 1289 | if (sf & SYSC_HAS_SIDLEMODE) { |
006c7f18 PW |
1290 | clkdm_act = ((oh->clkdm && |
1291 | oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) || | |
1292 | (oh->_clk && oh->_clk->clkdm && | |
1293 | oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU)); | |
1294 | if (clkdm_act && !(oh->class->sysc->idlemodes & | |
1295 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1296 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1297 | else | |
1298 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | |
1299 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
63c85238 PW |
1300 | _set_slave_idlemode(oh, idlemode, &v); |
1301 | } | |
1302 | ||
43b40992 | 1303 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1304 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1305 | idlemode = HWMOD_IDLEMODE_NO; | |
1306 | } else { | |
1307 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1308 | _enable_wakeup(oh, &v); | |
1309 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1310 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1311 | else | |
1312 | idlemode = HWMOD_IDLEMODE_SMART; | |
1313 | } | |
63c85238 PW |
1314 | _set_master_standbymode(oh, idlemode, &v); |
1315 | } | |
1316 | ||
a16b1f7f PW |
1317 | /* |
1318 | * XXX The clock framework should handle this, by | |
1319 | * calling into this code. But this must wait until the | |
1320 | * clock structures are tagged with omap_hwmod entries | |
1321 | */ | |
43b40992 PW |
1322 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1323 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
1324 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 | 1325 | |
9980ce53 RN |
1326 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1327 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
5a7ddcbd KH |
1328 | _enable_wakeup(oh, &v); |
1329 | ||
1330 | _write_sysconfig(v, oh); | |
78f26e87 HH |
1331 | |
1332 | /* | |
1333 | * Set the autoidle bit only after setting the smartidle bit | |
1334 | * Setting this will not have any impact on the other modules. | |
1335 | */ | |
1336 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1337 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1338 | 0 : 1; | |
1339 | _set_module_autoidle(oh, idlemode, &v); | |
1340 | _write_sysconfig(v, oh); | |
1341 | } | |
63c85238 PW |
1342 | } |
1343 | ||
1344 | /** | |
74ff3a68 | 1345 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1346 | * @oh: struct omap_hwmod * |
1347 | * | |
1348 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1349 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1350 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1351 | * configure it for smart-standby. No return value. | |
1352 | */ | |
74ff3a68 | 1353 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1354 | { |
43b40992 | 1355 | u8 idlemode, sf; |
63c85238 PW |
1356 | u32 v; |
1357 | ||
43b40992 | 1358 | if (!oh->class->sysc) |
63c85238 PW |
1359 | return; |
1360 | ||
1361 | v = oh->_sysc_cache; | |
43b40992 | 1362 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1363 | |
43b40992 | 1364 | if (sf & SYSC_HAS_SIDLEMODE) { |
006c7f18 PW |
1365 | /* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */ |
1366 | if (oh->flags & HWMOD_SWSUP_SIDLE || | |
1367 | !(oh->class->sysc->idlemodes & | |
1368 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1369 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1370 | else | |
1371 | idlemode = HWMOD_IDLEMODE_SMART; | |
63c85238 PW |
1372 | _set_slave_idlemode(oh, idlemode, &v); |
1373 | } | |
1374 | ||
43b40992 | 1375 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1376 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1377 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1378 | } else { | |
1379 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1380 | _enable_wakeup(oh, &v); | |
1381 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1382 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1383 | else | |
1384 | idlemode = HWMOD_IDLEMODE_SMART; | |
1385 | } | |
63c85238 PW |
1386 | _set_master_standbymode(oh, idlemode, &v); |
1387 | } | |
1388 | ||
86009eb3 BC |
1389 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1390 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
1391 | _enable_wakeup(oh, &v); | |
1392 | ||
63c85238 PW |
1393 | _write_sysconfig(v, oh); |
1394 | } | |
1395 | ||
1396 | /** | |
74ff3a68 | 1397 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1398 | * @oh: struct omap_hwmod * |
1399 | * | |
1400 | * Force the module into slave idle and master suspend. No return | |
1401 | * value. | |
1402 | */ | |
74ff3a68 | 1403 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1404 | { |
1405 | u32 v; | |
43b40992 | 1406 | u8 sf; |
63c85238 | 1407 | |
43b40992 | 1408 | if (!oh->class->sysc) |
63c85238 PW |
1409 | return; |
1410 | ||
1411 | v = oh->_sysc_cache; | |
43b40992 | 1412 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1413 | |
43b40992 | 1414 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1415 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1416 | ||
43b40992 | 1417 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1418 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1419 | ||
43b40992 | 1420 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1421 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1422 | |
1423 | _write_sysconfig(v, oh); | |
1424 | } | |
1425 | ||
1426 | /** | |
1427 | * _lookup - find an omap_hwmod by name | |
1428 | * @name: find an omap_hwmod by name | |
1429 | * | |
1430 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1431 | */ |
1432 | static struct omap_hwmod *_lookup(const char *name) | |
1433 | { | |
1434 | struct omap_hwmod *oh, *temp_oh; | |
1435 | ||
1436 | oh = NULL; | |
1437 | ||
1438 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1439 | if (!strcmp(name, temp_oh->name)) { | |
1440 | oh = temp_oh; | |
1441 | break; | |
1442 | } | |
1443 | } | |
1444 | ||
1445 | return oh; | |
1446 | } | |
868c157d | 1447 | |
6ae76997 BC |
1448 | /** |
1449 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1450 | * @oh: struct omap_hwmod * | |
1451 | * | |
1452 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1453 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
868c157d | 1454 | * Return -EINVAL if the clkdm_name lookup failed. |
6ae76997 BC |
1455 | */ |
1456 | static int _init_clkdm(struct omap_hwmod *oh) | |
1457 | { | |
3bb05dbf PW |
1458 | if (!oh->clkdm_name) { |
1459 | pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name); | |
6ae76997 | 1460 | return 0; |
3bb05dbf | 1461 | } |
6ae76997 | 1462 | |
6ae76997 BC |
1463 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
1464 | if (!oh->clkdm) { | |
1465 | pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", | |
1466 | oh->name, oh->clkdm_name); | |
1467 | return -EINVAL; | |
1468 | } | |
1469 | ||
1470 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1471 | oh->name, oh->clkdm_name); | |
1472 | ||
1473 | return 0; | |
1474 | } | |
63c85238 PW |
1475 | |
1476 | /** | |
6ae76997 BC |
1477 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1478 | * well the clockdomain. | |
63c85238 | 1479 | * @oh: struct omap_hwmod * |
97d60162 | 1480 | * @data: not used; pass NULL |
63c85238 | 1481 | * |
a2debdbd | 1482 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1483 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1484 | * success, or a negative error code on failure. | |
63c85238 | 1485 | */ |
97d60162 | 1486 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
1487 | { |
1488 | int ret = 0; | |
1489 | ||
48d54f3f PW |
1490 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1491 | return 0; | |
63c85238 PW |
1492 | |
1493 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1494 | ||
1495 | ret |= _init_main_clk(oh); | |
1496 | ret |= _init_interface_clks(oh); | |
1497 | ret |= _init_opt_clks(oh); | |
0a179eaa KH |
1498 | if (soc_ops.init_clkdm) |
1499 | ret |= soc_ops.init_clkdm(oh); | |
63c85238 | 1500 | |
f5c1f84b BC |
1501 | if (!ret) |
1502 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a BC |
1503 | else |
1504 | pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name); | |
63c85238 | 1505 | |
09c35f2f | 1506 | return ret; |
63c85238 PW |
1507 | } |
1508 | ||
5365efbe | 1509 | /** |
cc1226e7 | 1510 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1511 | * @oh: struct omap_hwmod * |
1512 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1513 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1514 | * |
1515 | * Return the bit position of the reset line that match the | |
1516 | * input name. Return -ENOENT if not found. | |
1517 | */ | |
a032d33b PW |
1518 | static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1519 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1520 | { |
1521 | int i; | |
1522 | ||
1523 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1524 | const char *rst_line = oh->rst_lines[i].name; | |
1525 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1526 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1527 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1528 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1529 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1530 | ohri->st_shift); | |
5365efbe | 1531 | |
cc1226e7 | 1532 | return 0; |
5365efbe BC |
1533 | } |
1534 | } | |
1535 | ||
1536 | return -ENOENT; | |
1537 | } | |
1538 | ||
1539 | /** | |
1540 | * _assert_hardreset - assert the HW reset line of submodules | |
1541 | * contained in the hwmod module. | |
1542 | * @oh: struct omap_hwmod * | |
1543 | * @name: name of the reset line to lookup and assert | |
1544 | * | |
b8249cf2 KH |
1545 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1546 | * reset line to be assert / deassert in order to enable fully the IP. | |
1547 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1548 | * asserting the hardreset line on the currently-booted SoC, or passes | |
1549 | * along the return value from _lookup_hardreset() or the SoC's | |
1550 | * assert_hardreset code. | |
5365efbe BC |
1551 | */ |
1552 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1553 | { | |
cc1226e7 | 1554 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1555 | int ret = -EINVAL; |
5365efbe BC |
1556 | |
1557 | if (!oh) | |
1558 | return -EINVAL; | |
1559 | ||
b8249cf2 KH |
1560 | if (!soc_ops.assert_hardreset) |
1561 | return -ENOSYS; | |
1562 | ||
cc1226e7 | 1563 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1564 | if (ret < 0) |
cc1226e7 | 1565 | return ret; |
5365efbe | 1566 | |
b8249cf2 KH |
1567 | ret = soc_ops.assert_hardreset(oh, &ohri); |
1568 | ||
1569 | return ret; | |
5365efbe BC |
1570 | } |
1571 | ||
1572 | /** | |
1573 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1574 | * in the hwmod module. | |
1575 | * @oh: struct omap_hwmod * | |
1576 | * @name: name of the reset line to look up and deassert | |
1577 | * | |
b8249cf2 KH |
1578 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1579 | * reset line to be assert / deassert in order to enable fully the IP. | |
1580 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1581 | * deasserting the hardreset line on the currently-booted SoC, or passes | |
1582 | * along the return value from _lookup_hardreset() or the SoC's | |
1583 | * deassert_hardreset code. | |
5365efbe BC |
1584 | */ |
1585 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1586 | { | |
cc1226e7 | 1587 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1588 | int ret = -EINVAL; |
e8e96dff | 1589 | int hwsup = 0; |
5365efbe BC |
1590 | |
1591 | if (!oh) | |
1592 | return -EINVAL; | |
1593 | ||
b8249cf2 KH |
1594 | if (!soc_ops.deassert_hardreset) |
1595 | return -ENOSYS; | |
1596 | ||
cc1226e7 | 1597 | ret = _lookup_hardreset(oh, name, &ohri); |
1598 | if (IS_ERR_VALUE(ret)) | |
1599 | return ret; | |
5365efbe | 1600 | |
e8e96dff ORL |
1601 | if (oh->clkdm) { |
1602 | /* | |
1603 | * A clockdomain must be in SW_SUP otherwise reset | |
1604 | * might not be completed. The clockdomain can be set | |
1605 | * in HW_AUTO only when the module become ready. | |
1606 | */ | |
1607 | hwsup = clkdm_in_hwsup(oh->clkdm); | |
1608 | ret = clkdm_hwmod_enable(oh->clkdm, oh); | |
1609 | if (ret) { | |
1610 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1611 | oh->name, oh->clkdm->name, ret); | |
1612 | return ret; | |
1613 | } | |
1614 | } | |
1615 | ||
1616 | _enable_clocks(oh); | |
1617 | if (soc_ops.enable_module) | |
1618 | soc_ops.enable_module(oh); | |
1619 | ||
b8249cf2 | 1620 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
e8e96dff ORL |
1621 | |
1622 | if (soc_ops.disable_module) | |
1623 | soc_ops.disable_module(oh); | |
1624 | _disable_clocks(oh); | |
1625 | ||
cc1226e7 | 1626 | if (ret == -EBUSY) |
5365efbe BC |
1627 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); |
1628 | ||
e8e96dff ORL |
1629 | if (!ret) { |
1630 | /* | |
1631 | * Set the clockdomain to HW_AUTO, assuming that the | |
1632 | * previous state was HW_AUTO. | |
1633 | */ | |
1634 | if (oh->clkdm && hwsup) | |
1635 | clkdm_allow_idle(oh->clkdm); | |
1636 | } else { | |
1637 | if (oh->clkdm) | |
1638 | clkdm_hwmod_disable(oh->clkdm, oh); | |
1639 | } | |
1640 | ||
cc1226e7 | 1641 | return ret; |
5365efbe BC |
1642 | } |
1643 | ||
1644 | /** | |
1645 | * _read_hardreset - read the HW reset line state of submodules | |
1646 | * contained in the hwmod module | |
1647 | * @oh: struct omap_hwmod * | |
1648 | * @name: name of the reset line to look up and read | |
1649 | * | |
b8249cf2 KH |
1650 | * Return the state of the reset line. Returns -EINVAL if @oh is |
1651 | * null, -ENOSYS if we have no way of reading the hardreset line | |
1652 | * status on the currently-booted SoC, or passes along the return | |
1653 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | |
1654 | * code. | |
5365efbe BC |
1655 | */ |
1656 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1657 | { | |
cc1226e7 | 1658 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1659 | int ret = -EINVAL; |
5365efbe BC |
1660 | |
1661 | if (!oh) | |
1662 | return -EINVAL; | |
1663 | ||
b8249cf2 KH |
1664 | if (!soc_ops.is_hardreset_asserted) |
1665 | return -ENOSYS; | |
1666 | ||
cc1226e7 | 1667 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1668 | if (ret < 0) |
cc1226e7 | 1669 | return ret; |
5365efbe | 1670 | |
b8249cf2 | 1671 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
5365efbe BC |
1672 | } |
1673 | ||
747834ab | 1674 | /** |
eb05f691 | 1675 | * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset |
747834ab PW |
1676 | * @oh: struct omap_hwmod * |
1677 | * | |
eb05f691 ORL |
1678 | * If all hardreset lines associated with @oh are asserted, then return true. |
1679 | * Otherwise, if part of @oh is out hardreset or if no hardreset lines | |
1680 | * associated with @oh are asserted, then return false. | |
747834ab | 1681 | * This function is used to avoid executing some parts of the IP block |
eb05f691 | 1682 | * enable/disable sequence if its hardreset line is set. |
747834ab | 1683 | */ |
eb05f691 | 1684 | static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh) |
747834ab | 1685 | { |
eb05f691 | 1686 | int i, rst_cnt = 0; |
747834ab PW |
1687 | |
1688 | if (oh->rst_lines_cnt == 0) | |
1689 | return false; | |
1690 | ||
1691 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1692 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
eb05f691 ORL |
1693 | rst_cnt++; |
1694 | ||
1695 | if (oh->rst_lines_cnt == rst_cnt) | |
1696 | return true; | |
747834ab PW |
1697 | |
1698 | return false; | |
1699 | } | |
1700 | ||
e9332b6e PW |
1701 | /** |
1702 | * _are_any_hardreset_lines_asserted - return true if any part of @oh is | |
1703 | * hard-reset | |
1704 | * @oh: struct omap_hwmod * | |
1705 | * | |
1706 | * If any hardreset lines associated with @oh are asserted, then | |
1707 | * return true. Otherwise, if no hardreset lines associated with @oh | |
1708 | * are asserted, or if @oh has no hardreset lines, then return false. | |
1709 | * This function is used to avoid executing some parts of the IP block | |
1710 | * enable/disable sequence if any hardreset line is set. | |
1711 | */ | |
1712 | static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) | |
1713 | { | |
1714 | int rst_cnt = 0; | |
1715 | int i; | |
1716 | ||
1717 | for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++) | |
1718 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
1719 | rst_cnt++; | |
1720 | ||
1721 | return (rst_cnt) ? true : false; | |
1722 | } | |
1723 | ||
747834ab PW |
1724 | /** |
1725 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
1726 | * @oh: struct omap_hwmod * | |
1727 | * | |
1728 | * Disable the PRCM module mode related to the hwmod @oh. | |
1729 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1730 | */ | |
1731 | static int _omap4_disable_module(struct omap_hwmod *oh) | |
1732 | { | |
1733 | int v; | |
1734 | ||
747834ab PW |
1735 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
1736 | return -EINVAL; | |
1737 | ||
eb05f691 ORL |
1738 | /* |
1739 | * Since integration code might still be doing something, only | |
1740 | * disable if all lines are under hardreset. | |
1741 | */ | |
e9332b6e | 1742 | if (_are_any_hardreset_lines_asserted(oh)) |
eb05f691 ORL |
1743 | return 0; |
1744 | ||
747834ab PW |
1745 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); |
1746 | ||
1747 | omap4_cminst_module_disable(oh->clkdm->prcm_partition, | |
1748 | oh->clkdm->cm_inst, | |
1749 | oh->clkdm->clkdm_offs, | |
1750 | oh->prcm.omap4.clkctrl_offs); | |
1751 | ||
747834ab PW |
1752 | v = _omap4_wait_target_disable(oh); |
1753 | if (v) | |
1754 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1755 | oh->name); | |
1756 | ||
1757 | return 0; | |
1758 | } | |
1759 | ||
1688bf19 VH |
1760 | /** |
1761 | * _am33xx_disable_module - enable CLKCTRL modulemode on AM33XX | |
1762 | * @oh: struct omap_hwmod * | |
1763 | * | |
1764 | * Disable the PRCM module mode related to the hwmod @oh. | |
1765 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1766 | */ | |
1767 | static int _am33xx_disable_module(struct omap_hwmod *oh) | |
1768 | { | |
1769 | int v; | |
1770 | ||
1771 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
1772 | return -EINVAL; | |
1773 | ||
1774 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); | |
1775 | ||
e9332b6e PW |
1776 | if (_are_any_hardreset_lines_asserted(oh)) |
1777 | return 0; | |
1778 | ||
1688bf19 VH |
1779 | am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs, |
1780 | oh->prcm.omap4.clkctrl_offs); | |
1781 | ||
1688bf19 VH |
1782 | v = _am33xx_wait_target_disable(oh); |
1783 | if (v) | |
1784 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1785 | oh->name); | |
1786 | ||
1787 | return 0; | |
1788 | } | |
1789 | ||
63c85238 | 1790 | /** |
bd36179e | 1791 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1792 | * @oh: struct omap_hwmod * |
1793 | * | |
1794 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1795 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1796 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1797 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1798 | * |
1799 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1800 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1801 | * use the SYSCONFIG softreset bit to provide the status. |
1802 | * | |
bd36179e PW |
1803 | * Note that some IP like McBSP do have reset control but don't have |
1804 | * reset status. | |
63c85238 | 1805 | */ |
bd36179e | 1806 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1807 | { |
387ca5bf | 1808 | u32 v, softrst_mask; |
6f8b7ff5 | 1809 | int c = 0; |
96835af9 | 1810 | int ret = 0; |
63c85238 | 1811 | |
43b40992 | 1812 | if (!oh->class->sysc || |
2cb06814 | 1813 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1814 | return -ENOENT; |
63c85238 PW |
1815 | |
1816 | /* clocks must be on for this operation */ | |
1817 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
7852ec05 PW |
1818 | pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n", |
1819 | oh->name); | |
63c85238 PW |
1820 | return -EINVAL; |
1821 | } | |
1822 | ||
96835af9 BC |
1823 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1824 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1825 | _enable_optional_clocks(oh); | |
1826 | ||
bd36179e | 1827 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1828 | |
1829 | v = oh->_sysc_cache; | |
96835af9 BC |
1830 | ret = _set_softreset(oh, &v); |
1831 | if (ret) | |
1832 | goto dis_opt_clks; | |
63c85238 PW |
1833 | _write_sysconfig(v, oh); |
1834 | ||
d99de7f5 FGL |
1835 | if (oh->class->sysc->srst_udelay) |
1836 | udelay(oh->class->sysc->srst_udelay); | |
1837 | ||
2cb06814 | 1838 | if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) |
cc7a1d2a | 1839 | omap_test_timeout((omap_hwmod_read(oh, |
2cb06814 BC |
1840 | oh->class->sysc->syss_offs) |
1841 | & SYSS_RESETDONE_MASK), | |
1842 | MAX_MODULE_SOFTRESET_WAIT, c); | |
387ca5bf RN |
1843 | else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { |
1844 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | |
cc7a1d2a | 1845 | omap_test_timeout(!(omap_hwmod_read(oh, |
2cb06814 | 1846 | oh->class->sysc->sysc_offs) |
387ca5bf | 1847 | & softrst_mask), |
2cb06814 | 1848 | MAX_MODULE_SOFTRESET_WAIT, c); |
387ca5bf | 1849 | } |
63c85238 | 1850 | |
5365efbe | 1851 | if (c == MAX_MODULE_SOFTRESET_WAIT) |
76e5589e BC |
1852 | pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1853 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
63c85238 | 1854 | else |
5365efbe | 1855 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
63c85238 PW |
1856 | |
1857 | /* | |
1858 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1859 | * _wait_target_ready() or _reset() | |
1860 | */ | |
1861 | ||
96835af9 BC |
1862 | ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; |
1863 | ||
1864 | dis_opt_clks: | |
1865 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1866 | _disable_optional_clocks(oh); | |
1867 | ||
1868 | return ret; | |
63c85238 PW |
1869 | } |
1870 | ||
bd36179e PW |
1871 | /** |
1872 | * _reset - reset an omap_hwmod | |
1873 | * @oh: struct omap_hwmod * | |
1874 | * | |
30e105c0 PW |
1875 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1876 | * function pointer defined, then call it to reset the IP block, and | |
1877 | * pass along its return value to the caller. Otherwise, if the IP | |
1878 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1879 | * associated with it, call a function to reset the IP block via that | |
1880 | * method, and pass along the return value to the caller. Finally, if | |
1881 | * the IP block has some hardreset lines associated with it, assert | |
1882 | * all of those, but do _not_ deassert them. (This is because driver | |
1883 | * authors have expressed an apparent requirement to control the | |
1884 | * deassertion of the hardreset lines themselves.) | |
1885 | * | |
1886 | * The default software reset mechanism for most OMAP IP blocks is | |
1887 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1888 | * hwmods cannot be reset via this method. Some are not targets and | |
1889 | * therefore have no OCP header registers to access. Others (like the | |
1890 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
1891 | * rare cases, custom reset code can be supplied in the struct | |
6668546f KVA |
1892 | * omap_hwmod_class .reset function pointer. |
1893 | * | |
1894 | * _set_dmadisable() is called to set the DMADISABLE bit so that it | |
1895 | * does not prevent idling of the system. This is necessary for cases | |
1896 | * where ROMCODE/BOOTLOADER uses dma and transfers control to the | |
1897 | * kernel without disabling dma. | |
1898 | * | |
1899 | * Passes along the return value from either _ocp_softreset() or the | |
1900 | * custom reset function - these must return -EINVAL if the hwmod | |
1901 | * cannot be reset this way or if the hwmod is in the wrong state, | |
1902 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
bd36179e PW |
1903 | */ |
1904 | static int _reset(struct omap_hwmod *oh) | |
1905 | { | |
30e105c0 | 1906 | int i, r; |
bd36179e PW |
1907 | |
1908 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1909 | ||
30e105c0 PW |
1910 | if (oh->class->reset) { |
1911 | r = oh->class->reset(oh); | |
1912 | } else { | |
1913 | if (oh->rst_lines_cnt > 0) { | |
1914 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1915 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
1916 | return 0; | |
1917 | } else { | |
1918 | r = _ocp_softreset(oh); | |
1919 | if (r == -ENOENT) | |
1920 | r = 0; | |
1921 | } | |
1922 | } | |
1923 | ||
6668546f KVA |
1924 | _set_dmadisable(oh); |
1925 | ||
9c8b0ec7 | 1926 | /* |
30e105c0 PW |
1927 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
1928 | * softreset. The _enable() function should be split to avoid | |
1929 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 1930 | */ |
2800852a RN |
1931 | if (oh->class->sysc) { |
1932 | _update_sysc_cache(oh); | |
1933 | _enable_sysc(oh); | |
1934 | } | |
1935 | ||
30e105c0 | 1936 | return r; |
bd36179e PW |
1937 | } |
1938 | ||
5165882a VB |
1939 | /** |
1940 | * _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain | |
1941 | * | |
1942 | * Call the appropriate PRM function to clear any logged I/O chain | |
1943 | * wakeups and to reconfigure the chain. This apparently needs to be | |
1944 | * done upon every mux change. Since hwmods can be concurrently | |
1945 | * enabled and idled, hold a spinlock around the I/O chain | |
1946 | * reconfiguration sequence. No return value. | |
1947 | * | |
1948 | * XXX When the PRM code is moved to drivers, this function can be removed, | |
1949 | * as the PRM infrastructure should abstract this. | |
1950 | */ | |
1951 | static void _reconfigure_io_chain(void) | |
1952 | { | |
1953 | unsigned long flags; | |
1954 | ||
1955 | spin_lock_irqsave(&io_chain_lock, flags); | |
1956 | ||
1957 | if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl()) | |
1958 | omap3xxx_prm_reconfigure_io_chain(); | |
1959 | else if (cpu_is_omap44xx()) | |
1960 | omap44xx_prm_reconfigure_io_chain(); | |
1961 | ||
1962 | spin_unlock_irqrestore(&io_chain_lock, flags); | |
1963 | } | |
1964 | ||
63c85238 | 1965 | /** |
dc6d1cda | 1966 | * _enable - enable an omap_hwmod |
63c85238 PW |
1967 | * @oh: struct omap_hwmod * |
1968 | * | |
1969 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
1970 | * register target. Returns -EINVAL if the hwmod is in the wrong |
1971 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 1972 | */ |
dc6d1cda | 1973 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 1974 | { |
747834ab | 1975 | int r; |
665d0013 | 1976 | int hwsup = 0; |
63c85238 | 1977 | |
34617e2a BC |
1978 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
1979 | ||
aacf0941 | 1980 | /* |
64813c3f PW |
1981 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled |
1982 | * state at init. Now that someone is really trying to enable | |
1983 | * them, just ensure that the hwmod mux is set. | |
aacf0941 RN |
1984 | */ |
1985 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
1986 | /* | |
1987 | * If the caller has mux data populated, do the mux'ing | |
1988 | * which wouldn't have been done as part of the _enable() | |
1989 | * done during setup. | |
1990 | */ | |
1991 | if (oh->mux) | |
1992 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
1993 | ||
1994 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; | |
1995 | return 0; | |
1996 | } | |
1997 | ||
63c85238 PW |
1998 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
1999 | oh->_state != _HWMOD_STATE_IDLE && | |
2000 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
2001 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
2002 | oh->name); | |
63c85238 PW |
2003 | return -EINVAL; |
2004 | } | |
2005 | ||
31f62866 | 2006 | /* |
eb05f691 | 2007 | * If an IP block contains HW reset lines and all of them are |
747834ab PW |
2008 | * asserted, we let integration code associated with that |
2009 | * block handle the enable. We've received very little | |
2010 | * information on what those driver authors need, and until | |
2011 | * detailed information is provided and the driver code is | |
2012 | * posted to the public lists, this is probably the best we | |
2013 | * can do. | |
31f62866 | 2014 | */ |
eb05f691 | 2015 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab | 2016 | return 0; |
63c85238 | 2017 | |
665d0013 RN |
2018 | /* Mux pins for device runtime if populated */ |
2019 | if (oh->mux && (!oh->mux->enabled || | |
2020 | ((oh->_state == _HWMOD_STATE_IDLE) && | |
5165882a | 2021 | oh->mux->pads_dynamic))) { |
665d0013 | 2022 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); |
5165882a VB |
2023 | _reconfigure_io_chain(); |
2024 | } | |
665d0013 RN |
2025 | |
2026 | _add_initiator_dep(oh, mpu_oh); | |
34617e2a | 2027 | |
665d0013 RN |
2028 | if (oh->clkdm) { |
2029 | /* | |
2030 | * A clockdomain must be in SW_SUP before enabling | |
2031 | * completely the module. The clockdomain can be set | |
2032 | * in HW_AUTO only when the module become ready. | |
2033 | */ | |
b71c7217 PW |
2034 | hwsup = clkdm_in_hwsup(oh->clkdm) && |
2035 | !clkdm_missing_idle_reporting(oh->clkdm); | |
665d0013 RN |
2036 | r = clkdm_hwmod_enable(oh->clkdm, oh); |
2037 | if (r) { | |
2038 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
2039 | oh->name, oh->clkdm->name, r); | |
2040 | return r; | |
2041 | } | |
34617e2a | 2042 | } |
665d0013 RN |
2043 | |
2044 | _enable_clocks(oh); | |
9ebfd285 KH |
2045 | if (soc_ops.enable_module) |
2046 | soc_ops.enable_module(oh); | |
34617e2a | 2047 | |
8f6aa8ee KH |
2048 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
2049 | -EINVAL; | |
665d0013 RN |
2050 | if (!r) { |
2051 | /* | |
2052 | * Set the clockdomain to HW_AUTO only if the target is ready, | |
2053 | * assuming that the previous state was HW_AUTO | |
2054 | */ | |
2055 | if (oh->clkdm && hwsup) | |
2056 | clkdm_allow_idle(oh->clkdm); | |
2057 | ||
2058 | oh->_state = _HWMOD_STATE_ENABLED; | |
2059 | ||
2060 | /* Access the sysconfig only if the target is ready */ | |
2061 | if (oh->class->sysc) { | |
2062 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
2063 | _update_sysc_cache(oh); | |
2064 | _enable_sysc(oh); | |
2065 | } | |
2066 | } else { | |
471a009b | 2067 | _omap4_disable_module(oh); |
665d0013 RN |
2068 | _disable_clocks(oh); |
2069 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | |
2070 | oh->name, r); | |
34617e2a | 2071 | |
665d0013 RN |
2072 | if (oh->clkdm) |
2073 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
2074 | } |
2075 | ||
63c85238 PW |
2076 | return r; |
2077 | } | |
2078 | ||
2079 | /** | |
dc6d1cda | 2080 | * _idle - idle an omap_hwmod |
63c85238 PW |
2081 | * @oh: struct omap_hwmod * |
2082 | * | |
2083 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
2084 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
2085 | * state or returns 0. | |
63c85238 | 2086 | */ |
dc6d1cda | 2087 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 2088 | { |
34617e2a BC |
2089 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
2090 | ||
63c85238 | 2091 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
2092 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
2093 | oh->name); | |
63c85238 PW |
2094 | return -EINVAL; |
2095 | } | |
2096 | ||
eb05f691 | 2097 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab PW |
2098 | return 0; |
2099 | ||
43b40992 | 2100 | if (oh->class->sysc) |
74ff3a68 | 2101 | _idle_sysc(oh); |
63c85238 | 2102 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 | 2103 | |
9ebfd285 KH |
2104 | if (soc_ops.disable_module) |
2105 | soc_ops.disable_module(oh); | |
bfc141e3 | 2106 | |
45c38252 BC |
2107 | /* |
2108 | * The module must be in idle mode before disabling any parents | |
2109 | * clocks. Otherwise, the parent clock might be disabled before | |
2110 | * the module transition is done, and thus will prevent the | |
2111 | * transition to complete properly. | |
2112 | */ | |
2113 | _disable_clocks(oh); | |
665d0013 RN |
2114 | if (oh->clkdm) |
2115 | clkdm_hwmod_disable(oh->clkdm, oh); | |
63c85238 | 2116 | |
8d9af88f | 2117 | /* Mux pins for device idle if populated */ |
5165882a | 2118 | if (oh->mux && oh->mux->pads_dynamic) { |
8d9af88f | 2119 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); |
5165882a VB |
2120 | _reconfigure_io_chain(); |
2121 | } | |
8d9af88f | 2122 | |
63c85238 PW |
2123 | oh->_state = _HWMOD_STATE_IDLE; |
2124 | ||
2125 | return 0; | |
2126 | } | |
2127 | ||
9599217a KVA |
2128 | /** |
2129 | * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit | |
2130 | * @oh: struct omap_hwmod * | |
2131 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
2132 | * | |
2133 | * Sets the IP block's OCP autoidle bit in hardware, and updates our | |
2134 | * local copy. Intended to be used by drivers that require | |
2135 | * direct manipulation of the AUTOIDLE bits. | |
2136 | * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes | |
2137 | * along the return value from _set_module_autoidle(). | |
2138 | * | |
2139 | * Any users of this function should be scrutinized carefully. | |
2140 | */ | |
2141 | int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) | |
2142 | { | |
2143 | u32 v; | |
2144 | int retval = 0; | |
2145 | unsigned long flags; | |
2146 | ||
2147 | if (!oh || oh->_state != _HWMOD_STATE_ENABLED) | |
2148 | return -EINVAL; | |
2149 | ||
2150 | spin_lock_irqsave(&oh->_lock, flags); | |
2151 | ||
2152 | v = oh->_sysc_cache; | |
2153 | ||
2154 | retval = _set_module_autoidle(oh, autoidle, &v); | |
2155 | ||
2156 | if (!retval) | |
2157 | _write_sysconfig(v, oh); | |
2158 | ||
2159 | spin_unlock_irqrestore(&oh->_lock, flags); | |
2160 | ||
2161 | return retval; | |
2162 | } | |
2163 | ||
63c85238 PW |
2164 | /** |
2165 | * _shutdown - shutdown an omap_hwmod | |
2166 | * @oh: struct omap_hwmod * | |
2167 | * | |
2168 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
2169 | * used for the hwmod is removed or unloaded or if the driver is not | |
2170 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
2171 | * state or returns 0. | |
2172 | */ | |
2173 | static int _shutdown(struct omap_hwmod *oh) | |
2174 | { | |
9c8b0ec7 | 2175 | int ret, i; |
e4dc8f50 PW |
2176 | u8 prev_state; |
2177 | ||
63c85238 PW |
2178 | if (oh->_state != _HWMOD_STATE_IDLE && |
2179 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
2180 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
2181 | oh->name); | |
63c85238 PW |
2182 | return -EINVAL; |
2183 | } | |
2184 | ||
eb05f691 | 2185 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab PW |
2186 | return 0; |
2187 | ||
63c85238 PW |
2188 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); |
2189 | ||
e4dc8f50 PW |
2190 | if (oh->class->pre_shutdown) { |
2191 | prev_state = oh->_state; | |
2192 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2193 | _enable(oh); |
e4dc8f50 PW |
2194 | ret = oh->class->pre_shutdown(oh); |
2195 | if (ret) { | |
2196 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2197 | _idle(oh); |
e4dc8f50 PW |
2198 | return ret; |
2199 | } | |
2200 | } | |
2201 | ||
6481c73c MV |
2202 | if (oh->class->sysc) { |
2203 | if (oh->_state == _HWMOD_STATE_IDLE) | |
2204 | _enable(oh); | |
74ff3a68 | 2205 | _shutdown_sysc(oh); |
6481c73c | 2206 | } |
5365efbe | 2207 | |
3827f949 BC |
2208 | /* clocks and deps are already disabled in idle */ |
2209 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
2210 | _del_initiator_dep(oh, mpu_oh); | |
2211 | /* XXX what about the other system initiators here? dma, dsp */ | |
9ebfd285 KH |
2212 | if (soc_ops.disable_module) |
2213 | soc_ops.disable_module(oh); | |
45c38252 | 2214 | _disable_clocks(oh); |
665d0013 RN |
2215 | if (oh->clkdm) |
2216 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 2217 | } |
63c85238 PW |
2218 | /* XXX Should this code also force-disable the optional clocks? */ |
2219 | ||
9c8b0ec7 PW |
2220 | for (i = 0; i < oh->rst_lines_cnt; i++) |
2221 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 2222 | |
8d9af88f TL |
2223 | /* Mux pins to safe mode or use populated off mode values */ |
2224 | if (oh->mux) | |
2225 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); | |
63c85238 PW |
2226 | |
2227 | oh->_state = _HWMOD_STATE_DISABLED; | |
2228 | ||
2229 | return 0; | |
2230 | } | |
2231 | ||
381d033a PW |
2232 | /** |
2233 | * _init_mpu_rt_base - populate the virtual address for a hwmod | |
2234 | * @oh: struct omap_hwmod * to locate the virtual address | |
2235 | * | |
2236 | * Cache the virtual address used by the MPU to access this IP block's | |
2237 | * registers. This address is needed early so the OCP registers that | |
2238 | * are part of the device's address space can be ioremapped properly. | |
2239 | * No return value. | |
2240 | */ | |
2241 | static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) | |
2242 | { | |
c9aafd23 PW |
2243 | struct omap_hwmod_addr_space *mem; |
2244 | void __iomem *va_start; | |
2245 | ||
2246 | if (!oh) | |
2247 | return; | |
2248 | ||
2221b5cd PW |
2249 | _save_mpu_port_index(oh); |
2250 | ||
381d033a PW |
2251 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
2252 | return; | |
2253 | ||
c9aafd23 PW |
2254 | mem = _find_mpu_rt_addr_space(oh); |
2255 | if (!mem) { | |
2256 | pr_debug("omap_hwmod: %s: no MPU register target found\n", | |
2257 | oh->name); | |
2258 | return; | |
2259 | } | |
2260 | ||
2261 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
2262 | if (!va_start) { | |
2263 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
2264 | return; | |
2265 | } | |
2266 | ||
2267 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | |
2268 | oh->name, va_start); | |
2269 | ||
2270 | oh->_mpu_rt_va = va_start; | |
381d033a PW |
2271 | } |
2272 | ||
2273 | /** | |
2274 | * _init - initialize internal data for the hwmod @oh | |
2275 | * @oh: struct omap_hwmod * | |
2276 | * @n: (unused) | |
2277 | * | |
2278 | * Look up the clocks and the address space used by the MPU to access | |
2279 | * registers belonging to the hwmod @oh. @oh must already be | |
2280 | * registered at this point. This is the first of two phases for | |
2281 | * hwmod initialization. Code called here does not touch any hardware | |
2282 | * registers, it simply prepares internal data structures. Returns 0 | |
2283 | * upon success or if the hwmod isn't registered, or -EINVAL upon | |
2284 | * failure. | |
2285 | */ | |
2286 | static int __init _init(struct omap_hwmod *oh, void *data) | |
2287 | { | |
2288 | int r; | |
2289 | ||
2290 | if (oh->_state != _HWMOD_STATE_REGISTERED) | |
2291 | return 0; | |
2292 | ||
2293 | _init_mpu_rt_base(oh, NULL); | |
2294 | ||
2295 | r = _init_clocks(oh, NULL); | |
2296 | if (IS_ERR_VALUE(r)) { | |
2297 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); | |
2298 | return -EINVAL; | |
2299 | } | |
2300 | ||
2301 | oh->_state = _HWMOD_STATE_INITIALIZED; | |
2302 | ||
2303 | return 0; | |
2304 | } | |
2305 | ||
63c85238 | 2306 | /** |
64813c3f | 2307 | * _setup_iclk_autoidle - configure an IP block's interface clocks |
63c85238 PW |
2308 | * @oh: struct omap_hwmod * |
2309 | * | |
64813c3f PW |
2310 | * Set up the module's interface clocks. XXX This function is still mostly |
2311 | * a stub; implementing this properly requires iclk autoidle usecounting in | |
2312 | * the clock code. No return value. | |
63c85238 | 2313 | */ |
64813c3f | 2314 | static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) |
63c85238 | 2315 | { |
5d95dde7 | 2316 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 2317 | struct list_head *p; |
5d95dde7 | 2318 | int i = 0; |
381d033a | 2319 | if (oh->_state != _HWMOD_STATE_INITIALIZED) |
64813c3f | 2320 | return; |
48d54f3f | 2321 | |
11cd4b94 | 2322 | p = oh->slave_ports.next; |
63c85238 | 2323 | |
5d95dde7 | 2324 | while (i < oh->slaves_cnt) { |
11cd4b94 | 2325 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 | 2326 | if (!os->_clk) |
64813c3f | 2327 | continue; |
63c85238 | 2328 | |
64813c3f PW |
2329 | if (os->flags & OCPIF_SWSUP_IDLE) { |
2330 | /* XXX omap_iclk_deny_idle(c); */ | |
2331 | } else { | |
2332 | /* XXX omap_iclk_allow_idle(c); */ | |
5d95dde7 | 2333 | clk_enable(os->_clk); |
63c85238 PW |
2334 | } |
2335 | } | |
2336 | ||
64813c3f PW |
2337 | return; |
2338 | } | |
2339 | ||
2340 | /** | |
2341 | * _setup_reset - reset an IP block during the setup process | |
2342 | * @oh: struct omap_hwmod * | |
2343 | * | |
2344 | * Reset the IP block corresponding to the hwmod @oh during the setup | |
2345 | * process. The IP block is first enabled so it can be successfully | |
2346 | * reset. Returns 0 upon success or a negative error code upon | |
2347 | * failure. | |
2348 | */ | |
2349 | static int __init _setup_reset(struct omap_hwmod *oh) | |
2350 | { | |
2351 | int r; | |
2352 | ||
2353 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2354 | return -EINVAL; | |
63c85238 | 2355 | |
747834ab PW |
2356 | if (oh->rst_lines_cnt == 0) { |
2357 | r = _enable(oh); | |
2358 | if (r) { | |
2359 | pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", | |
2360 | oh->name, oh->_state); | |
2361 | return -EINVAL; | |
2362 | } | |
9a23dfe1 | 2363 | } |
63c85238 | 2364 | |
2800852a | 2365 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
64813c3f PW |
2366 | r = _reset(oh); |
2367 | ||
2368 | return r; | |
2369 | } | |
2370 | ||
2371 | /** | |
2372 | * _setup_postsetup - transition to the appropriate state after _setup | |
2373 | * @oh: struct omap_hwmod * | |
2374 | * | |
2375 | * Place an IP block represented by @oh into a "post-setup" state -- | |
2376 | * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that | |
2377 | * this function is called at the end of _setup().) The postsetup | |
2378 | * state for an IP block can be changed by calling | |
2379 | * omap_hwmod_enter_postsetup_state() early in the boot process, | |
2380 | * before one of the omap_hwmod_setup*() functions are called for the | |
2381 | * IP block. | |
2382 | * | |
2383 | * The IP block stays in this state until a PM runtime-based driver is | |
2384 | * loaded for that IP block. A post-setup state of IDLE is | |
2385 | * appropriate for almost all IP blocks with runtime PM-enabled | |
2386 | * drivers, since those drivers are able to enable the IP block. A | |
2387 | * post-setup state of ENABLED is appropriate for kernels with PM | |
2388 | * runtime disabled. The DISABLED state is appropriate for unusual IP | |
2389 | * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers | |
2390 | * included, since the WDTIMER starts running on reset and will reset | |
2391 | * the MPU if left active. | |
2392 | * | |
2393 | * This post-setup mechanism is deprecated. Once all of the OMAP | |
2394 | * drivers have been converted to use PM runtime, and all of the IP | |
2395 | * block data and interconnect data is available to the hwmod code, it | |
2396 | * should be possible to replace this mechanism with a "lazy reset" | |
2397 | * arrangement. In a "lazy reset" setup, each IP block is enabled | |
2398 | * when the driver first probes, then all remaining IP blocks without | |
2399 | * drivers are either shut down or enabled after the drivers have | |
2400 | * loaded. However, this cannot take place until the above | |
2401 | * preconditions have been met, since otherwise the late reset code | |
2402 | * has no way of knowing which IP blocks are in use by drivers, and | |
2403 | * which ones are unused. | |
2404 | * | |
2405 | * No return value. | |
2406 | */ | |
2407 | static void __init _setup_postsetup(struct omap_hwmod *oh) | |
2408 | { | |
2409 | u8 postsetup_state; | |
2410 | ||
2411 | if (oh->rst_lines_cnt > 0) | |
2412 | return; | |
76e5589e | 2413 | |
2092e5cc PW |
2414 | postsetup_state = oh->_postsetup_state; |
2415 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
2416 | postsetup_state = _HWMOD_STATE_ENABLED; | |
2417 | ||
2418 | /* | |
2419 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
2420 | * it should be set by the core code as a runtime flag during startup | |
2421 | */ | |
2422 | if ((oh->flags & HWMOD_INIT_NO_IDLE) && | |
aacf0941 RN |
2423 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
2424 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 2425 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 2426 | } |
2092e5cc PW |
2427 | |
2428 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2429 | _idle(oh); |
2092e5cc PW |
2430 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
2431 | _shutdown(oh); | |
2432 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2433 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2434 | oh->name, postsetup_state); | |
63c85238 | 2435 | |
64813c3f PW |
2436 | return; |
2437 | } | |
2438 | ||
2439 | /** | |
2440 | * _setup - prepare IP block hardware for use | |
2441 | * @oh: struct omap_hwmod * | |
2442 | * @n: (unused, pass NULL) | |
2443 | * | |
2444 | * Configure the IP block represented by @oh. This may include | |
2445 | * enabling the IP block, resetting it, and placing it into a | |
2446 | * post-setup state, depending on the type of IP block and applicable | |
2447 | * flags. IP blocks are reset to prevent any previous configuration | |
2448 | * by the bootloader or previous operating system from interfering | |
2449 | * with power management or other parts of the system. The reset can | |
2450 | * be avoided; see omap_hwmod_no_setup_reset(). This is the second of | |
2451 | * two phases for hwmod initialization. Code called here generally | |
2452 | * affects the IP block hardware, or system integration hardware | |
2453 | * associated with the IP block. Returns 0. | |
2454 | */ | |
2455 | static int __init _setup(struct omap_hwmod *oh, void *data) | |
2456 | { | |
2457 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2458 | return 0; | |
2459 | ||
2460 | _setup_iclk_autoidle(oh); | |
2461 | ||
2462 | if (!_setup_reset(oh)) | |
2463 | _setup_postsetup(oh); | |
2464 | ||
63c85238 PW |
2465 | return 0; |
2466 | } | |
2467 | ||
63c85238 | 2468 | /** |
0102b627 | 2469 | * _register - register a struct omap_hwmod |
63c85238 PW |
2470 | * @oh: struct omap_hwmod * |
2471 | * | |
43b40992 PW |
2472 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
2473 | * already has been registered by the same name; -EINVAL if the | |
2474 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
2475 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
2476 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
2477 | * success. | |
63c85238 PW |
2478 | * |
2479 | * XXX The data should be copied into bootmem, so the original data | |
2480 | * should be marked __initdata and freed after init. This would allow | |
2481 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
2482 | * that the copy process would be relatively complex due to the large number | |
2483 | * of substructures. | |
2484 | */ | |
01592df9 | 2485 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 2486 | { |
43b40992 PW |
2487 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
2488 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
2489 | return -EINVAL; |
2490 | ||
63c85238 PW |
2491 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
2492 | ||
ce35b244 BC |
2493 | if (_lookup(oh->name)) |
2494 | return -EEXIST; | |
63c85238 | 2495 | |
63c85238 PW |
2496 | list_add_tail(&oh->node, &omap_hwmod_list); |
2497 | ||
2221b5cd PW |
2498 | INIT_LIST_HEAD(&oh->master_ports); |
2499 | INIT_LIST_HEAD(&oh->slave_ports); | |
dc6d1cda | 2500 | spin_lock_init(&oh->_lock); |
2092e5cc | 2501 | |
63c85238 PW |
2502 | oh->_state = _HWMOD_STATE_REGISTERED; |
2503 | ||
569edd70 PW |
2504 | /* |
2505 | * XXX Rather than doing a strcmp(), this should test a flag | |
2506 | * set in the hwmod data, inserted by the autogenerator code. | |
2507 | */ | |
2508 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
2509 | mpu_oh = oh; | |
63c85238 | 2510 | |
569edd70 | 2511 | return 0; |
63c85238 PW |
2512 | } |
2513 | ||
2221b5cd PW |
2514 | /** |
2515 | * _alloc_links - return allocated memory for hwmod links | |
2516 | * @ml: pointer to a struct omap_hwmod_link * for the master link | |
2517 | * @sl: pointer to a struct omap_hwmod_link * for the slave link | |
2518 | * | |
2519 | * Return pointers to two struct omap_hwmod_link records, via the | |
2520 | * addresses pointed to by @ml and @sl. Will first attempt to return | |
2521 | * memory allocated as part of a large initial block, but if that has | |
2522 | * been exhausted, will allocate memory itself. Since ideally this | |
2523 | * second allocation path will never occur, the number of these | |
2524 | * 'supplemental' allocations will be logged when debugging is | |
2525 | * enabled. Returns 0. | |
2526 | */ | |
2527 | static int __init _alloc_links(struct omap_hwmod_link **ml, | |
2528 | struct omap_hwmod_link **sl) | |
2529 | { | |
2530 | unsigned int sz; | |
2531 | ||
2532 | if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) { | |
2533 | *ml = &linkspace[free_ls++]; | |
2534 | *sl = &linkspace[free_ls++]; | |
2535 | return 0; | |
2536 | } | |
2537 | ||
2538 | sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; | |
2539 | ||
2540 | *sl = NULL; | |
2541 | *ml = alloc_bootmem(sz); | |
2542 | ||
2543 | memset(*ml, 0, sz); | |
2544 | ||
2545 | *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); | |
2546 | ||
2547 | ls_supp++; | |
2548 | pr_debug("omap_hwmod: supplemental link allocations needed: %d\n", | |
2549 | ls_supp * LINKS_PER_OCP_IF); | |
2550 | ||
2551 | return 0; | |
2552 | }; | |
2553 | ||
2554 | /** | |
2555 | * _add_link - add an interconnect between two IP blocks | |
2556 | * @oi: pointer to a struct omap_hwmod_ocp_if record | |
2557 | * | |
2558 | * Add struct omap_hwmod_link records connecting the master IP block | |
2559 | * specified in @oi->master to @oi, and connecting the slave IP block | |
2560 | * specified in @oi->slave to @oi. This code is assumed to run before | |
2561 | * preemption or SMP has been enabled, thus avoiding the need for | |
2562 | * locking in this code. Changes to this assumption will require | |
2563 | * additional locking. Returns 0. | |
2564 | */ | |
2565 | static int __init _add_link(struct omap_hwmod_ocp_if *oi) | |
2566 | { | |
2567 | struct omap_hwmod_link *ml, *sl; | |
2568 | ||
2569 | pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, | |
2570 | oi->slave->name); | |
2571 | ||
2572 | _alloc_links(&ml, &sl); | |
2573 | ||
2574 | ml->ocp_if = oi; | |
2575 | INIT_LIST_HEAD(&ml->node); | |
2576 | list_add(&ml->node, &oi->master->master_ports); | |
2577 | oi->master->masters_cnt++; | |
2578 | ||
2579 | sl->ocp_if = oi; | |
2580 | INIT_LIST_HEAD(&sl->node); | |
2581 | list_add(&sl->node, &oi->slave->slave_ports); | |
2582 | oi->slave->slaves_cnt++; | |
2583 | ||
2584 | return 0; | |
2585 | } | |
2586 | ||
2587 | /** | |
2588 | * _register_link - register a struct omap_hwmod_ocp_if | |
2589 | * @oi: struct omap_hwmod_ocp_if * | |
2590 | * | |
2591 | * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it | |
2592 | * has already been registered; -EINVAL if @oi is NULL or if the | |
2593 | * record pointed to by @oi is missing required fields; or 0 upon | |
2594 | * success. | |
2595 | * | |
2596 | * XXX The data should be copied into bootmem, so the original data | |
2597 | * should be marked __initdata and freed after init. This would allow | |
2598 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. | |
2599 | */ | |
2600 | static int __init _register_link(struct omap_hwmod_ocp_if *oi) | |
2601 | { | |
2602 | if (!oi || !oi->master || !oi->slave || !oi->user) | |
2603 | return -EINVAL; | |
2604 | ||
2605 | if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) | |
2606 | return -EEXIST; | |
2607 | ||
2608 | pr_debug("omap_hwmod: registering link from %s to %s\n", | |
2609 | oi->master->name, oi->slave->name); | |
2610 | ||
2611 | /* | |
2612 | * Register the connected hwmods, if they haven't been | |
2613 | * registered already | |
2614 | */ | |
2615 | if (oi->master->_state != _HWMOD_STATE_REGISTERED) | |
2616 | _register(oi->master); | |
2617 | ||
2618 | if (oi->slave->_state != _HWMOD_STATE_REGISTERED) | |
2619 | _register(oi->slave); | |
2620 | ||
2621 | _add_link(oi); | |
2622 | ||
2623 | oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; | |
2624 | ||
2625 | return 0; | |
2626 | } | |
2627 | ||
2628 | /** | |
2629 | * _alloc_linkspace - allocate large block of hwmod links | |
2630 | * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count | |
2631 | * | |
2632 | * Allocate a large block of struct omap_hwmod_link records. This | |
2633 | * improves boot time significantly by avoiding the need to allocate | |
2634 | * individual records one by one. If the number of records to | |
2635 | * allocate in the block hasn't been manually specified, this function | |
2636 | * will count the number of struct omap_hwmod_ocp_if records in @ois | |
2637 | * and use that to determine the allocation size. For SoC families | |
2638 | * that require multiple list registrations, such as OMAP3xxx, this | |
2639 | * estimation process isn't optimal, so manual estimation is advised | |
2640 | * in those cases. Returns -EEXIST if the allocation has already occurred | |
2641 | * or 0 upon success. | |
2642 | */ | |
2643 | static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) | |
2644 | { | |
2645 | unsigned int i = 0; | |
2646 | unsigned int sz; | |
2647 | ||
2648 | if (linkspace) { | |
2649 | WARN(1, "linkspace already allocated\n"); | |
2650 | return -EEXIST; | |
2651 | } | |
2652 | ||
2653 | if (max_ls == 0) | |
2654 | while (ois[i++]) | |
2655 | max_ls += LINKS_PER_OCP_IF; | |
2656 | ||
2657 | sz = sizeof(struct omap_hwmod_link) * max_ls; | |
2658 | ||
2659 | pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", | |
2660 | __func__, sz, max_ls); | |
2661 | ||
2662 | linkspace = alloc_bootmem(sz); | |
2663 | ||
2664 | memset(linkspace, 0, sz); | |
2665 | ||
2666 | return 0; | |
2667 | } | |
0102b627 | 2668 | |
8f6aa8ee KH |
2669 | /* Static functions intended only for use in soc_ops field function pointers */ |
2670 | ||
2671 | /** | |
ff4ae5d9 | 2672 | * _omap2xxx_wait_target_ready - wait for a module to leave slave idle |
8f6aa8ee KH |
2673 | * @oh: struct omap_hwmod * |
2674 | * | |
2675 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2676 | * does not have an IDLEST bit or if the module successfully leaves | |
2677 | * slave idle; otherwise, pass along the return value of the | |
2678 | * appropriate *_cm*_wait_module_ready() function. | |
2679 | */ | |
ff4ae5d9 | 2680 | static int _omap2xxx_wait_target_ready(struct omap_hwmod *oh) |
8f6aa8ee KH |
2681 | { |
2682 | if (!oh) | |
2683 | return -EINVAL; | |
2684 | ||
2685 | if (oh->flags & HWMOD_NO_IDLEST) | |
2686 | return 0; | |
2687 | ||
2688 | if (!_find_mpu_rt_port(oh)) | |
2689 | return 0; | |
2690 | ||
2691 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2692 | ||
ff4ae5d9 PW |
2693 | return omap2xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs, |
2694 | oh->prcm.omap2.idlest_reg_id, | |
2695 | oh->prcm.omap2.idlest_idle_bit); | |
2696 | } | |
2697 | ||
2698 | /** | |
2699 | * _omap3xxx_wait_target_ready - wait for a module to leave slave idle | |
2700 | * @oh: struct omap_hwmod * | |
2701 | * | |
2702 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2703 | * does not have an IDLEST bit or if the module successfully leaves | |
2704 | * slave idle; otherwise, pass along the return value of the | |
2705 | * appropriate *_cm*_wait_module_ready() function. | |
2706 | */ | |
2707 | static int _omap3xxx_wait_target_ready(struct omap_hwmod *oh) | |
2708 | { | |
2709 | if (!oh) | |
2710 | return -EINVAL; | |
2711 | ||
2712 | if (oh->flags & HWMOD_NO_IDLEST) | |
2713 | return 0; | |
2714 | ||
2715 | if (!_find_mpu_rt_port(oh)) | |
2716 | return 0; | |
2717 | ||
2718 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2719 | ||
2720 | return omap3xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs, | |
2721 | oh->prcm.omap2.idlest_reg_id, | |
2722 | oh->prcm.omap2.idlest_idle_bit); | |
8f6aa8ee KH |
2723 | } |
2724 | ||
2725 | /** | |
2726 | * _omap4_wait_target_ready - wait for a module to leave slave idle | |
2727 | * @oh: struct omap_hwmod * | |
2728 | * | |
2729 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2730 | * does not have an IDLEST bit or if the module successfully leaves | |
2731 | * slave idle; otherwise, pass along the return value of the | |
2732 | * appropriate *_cm*_wait_module_ready() function. | |
2733 | */ | |
2734 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | |
2735 | { | |
2b026d13 | 2736 | if (!oh) |
8f6aa8ee KH |
2737 | return -EINVAL; |
2738 | ||
2b026d13 | 2739 | if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm) |
8f6aa8ee KH |
2740 | return 0; |
2741 | ||
2742 | if (!_find_mpu_rt_port(oh)) | |
2743 | return 0; | |
2744 | ||
2745 | /* XXX check module SIDLEMODE, hardreset status */ | |
2746 | ||
2747 | return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, | |
2748 | oh->clkdm->cm_inst, | |
2749 | oh->clkdm->clkdm_offs, | |
2750 | oh->prcm.omap4.clkctrl_offs); | |
2751 | } | |
2752 | ||
1688bf19 VH |
2753 | /** |
2754 | * _am33xx_wait_target_ready - wait for a module to leave slave idle | |
2755 | * @oh: struct omap_hwmod * | |
2756 | * | |
2757 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2758 | * does not have an IDLEST bit or if the module successfully leaves | |
2759 | * slave idle; otherwise, pass along the return value of the | |
2760 | * appropriate *_cm*_wait_module_ready() function. | |
2761 | */ | |
2762 | static int _am33xx_wait_target_ready(struct omap_hwmod *oh) | |
2763 | { | |
2764 | if (!oh || !oh->clkdm) | |
2765 | return -EINVAL; | |
2766 | ||
2767 | if (oh->flags & HWMOD_NO_IDLEST) | |
2768 | return 0; | |
2769 | ||
2770 | if (!_find_mpu_rt_port(oh)) | |
2771 | return 0; | |
2772 | ||
2773 | /* XXX check module SIDLEMODE, hardreset status */ | |
2774 | ||
2775 | return am33xx_cm_wait_module_ready(oh->clkdm->cm_inst, | |
2776 | oh->clkdm->clkdm_offs, | |
2777 | oh->prcm.omap4.clkctrl_offs); | |
2778 | } | |
2779 | ||
b8249cf2 KH |
2780 | /** |
2781 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2782 | * @oh: struct omap_hwmod * to assert hardreset | |
2783 | * @ohri: hardreset line data | |
2784 | * | |
2785 | * Call omap2_prm_assert_hardreset() with parameters extracted from | |
2786 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2787 | * use as an soc_ops function pointer. Passes along the return value | |
2788 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | |
2789 | * for removal when the PRM code is moved into drivers/. | |
2790 | */ | |
2791 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | |
2792 | struct omap_hwmod_rst_info *ohri) | |
2793 | { | |
2794 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | |
2795 | ohri->rst_shift); | |
2796 | } | |
2797 | ||
2798 | /** | |
2799 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2800 | * @oh: struct omap_hwmod * to deassert hardreset | |
2801 | * @ohri: hardreset line data | |
2802 | * | |
2803 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | |
2804 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2805 | * use as an soc_ops function pointer. Passes along the return value | |
2806 | * from omap2_prm_deassert_hardreset(). XXX This function is | |
2807 | * scheduled for removal when the PRM code is moved into drivers/. | |
2808 | */ | |
2809 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | |
2810 | struct omap_hwmod_rst_info *ohri) | |
2811 | { | |
2812 | return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | |
2813 | ohri->rst_shift, | |
2814 | ohri->st_shift); | |
2815 | } | |
2816 | ||
2817 | /** | |
2818 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | |
2819 | * @oh: struct omap_hwmod * to test hardreset | |
2820 | * @ohri: hardreset line data | |
2821 | * | |
2822 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | |
2823 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2824 | * intended for use as an soc_ops function pointer. Passes along the | |
2825 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | |
2826 | * function is scheduled for removal when the PRM code is moved into | |
2827 | * drivers/. | |
2828 | */ | |
2829 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | |
2830 | struct omap_hwmod_rst_info *ohri) | |
2831 | { | |
2832 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | |
2833 | ohri->st_shift); | |
2834 | } | |
2835 | ||
2836 | /** | |
2837 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2838 | * @oh: struct omap_hwmod * to assert hardreset | |
2839 | * @ohri: hardreset line data | |
2840 | * | |
2841 | * Call omap4_prminst_assert_hardreset() with parameters extracted | |
2842 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2843 | * intended for use as an soc_ops function pointer. Passes along the | |
2844 | * return value from omap4_prminst_assert_hardreset(). XXX This | |
2845 | * function is scheduled for removal when the PRM code is moved into | |
2846 | * drivers/. | |
2847 | */ | |
2848 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | |
2849 | struct omap_hwmod_rst_info *ohri) | |
b8249cf2 | 2850 | { |
07b3a139 PW |
2851 | if (!oh->clkdm) |
2852 | return -EINVAL; | |
2853 | ||
b8249cf2 KH |
2854 | return omap4_prminst_assert_hardreset(ohri->rst_shift, |
2855 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2856 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2857 | oh->prcm.omap4.rstctrl_offs); | |
2858 | } | |
2859 | ||
2860 | /** | |
2861 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2862 | * @oh: struct omap_hwmod * to deassert hardreset | |
2863 | * @ohri: hardreset line data | |
2864 | * | |
2865 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | |
2866 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2867 | * intended for use as an soc_ops function pointer. Passes along the | |
2868 | * return value from omap4_prminst_deassert_hardreset(). XXX This | |
2869 | * function is scheduled for removal when the PRM code is moved into | |
2870 | * drivers/. | |
2871 | */ | |
2872 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | |
2873 | struct omap_hwmod_rst_info *ohri) | |
2874 | { | |
07b3a139 PW |
2875 | if (!oh->clkdm) |
2876 | return -EINVAL; | |
2877 | ||
b8249cf2 KH |
2878 | if (ohri->st_shift) |
2879 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
2880 | oh->name, ohri->name); | |
2881 | return omap4_prminst_deassert_hardreset(ohri->rst_shift, | |
2882 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2883 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2884 | oh->prcm.omap4.rstctrl_offs); | |
2885 | } | |
2886 | ||
2887 | /** | |
2888 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | |
2889 | * @oh: struct omap_hwmod * to test hardreset | |
2890 | * @ohri: hardreset line data | |
2891 | * | |
2892 | * Call omap4_prminst_is_hardreset_asserted() with parameters | |
2893 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
2894 | * Only intended for use as an soc_ops function pointer. Passes along | |
2895 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | |
2896 | * This function is scheduled for removal when the PRM code is moved | |
2897 | * into drivers/. | |
2898 | */ | |
2899 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | |
2900 | struct omap_hwmod_rst_info *ohri) | |
2901 | { | |
07b3a139 PW |
2902 | if (!oh->clkdm) |
2903 | return -EINVAL; | |
2904 | ||
b8249cf2 KH |
2905 | return omap4_prminst_is_hardreset_asserted(ohri->rst_shift, |
2906 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2907 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2908 | oh->prcm.omap4.rstctrl_offs); | |
2909 | } | |
2910 | ||
1688bf19 VH |
2911 | /** |
2912 | * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
2913 | * @oh: struct omap_hwmod * to assert hardreset | |
2914 | * @ohri: hardreset line data | |
2915 | * | |
2916 | * Call am33xx_prminst_assert_hardreset() with parameters extracted | |
2917 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2918 | * intended for use as an soc_ops function pointer. Passes along the | |
2919 | * return value from am33xx_prminst_assert_hardreset(). XXX This | |
2920 | * function is scheduled for removal when the PRM code is moved into | |
2921 | * drivers/. | |
2922 | */ | |
2923 | static int _am33xx_assert_hardreset(struct omap_hwmod *oh, | |
2924 | struct omap_hwmod_rst_info *ohri) | |
2925 | ||
2926 | { | |
2927 | return am33xx_prm_assert_hardreset(ohri->rst_shift, | |
2928 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2929 | oh->prcm.omap4.rstctrl_offs); | |
2930 | } | |
2931 | ||
2932 | /** | |
2933 | * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
2934 | * @oh: struct omap_hwmod * to deassert hardreset | |
2935 | * @ohri: hardreset line data | |
2936 | * | |
2937 | * Call am33xx_prminst_deassert_hardreset() with parameters extracted | |
2938 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2939 | * intended for use as an soc_ops function pointer. Passes along the | |
2940 | * return value from am33xx_prminst_deassert_hardreset(). XXX This | |
2941 | * function is scheduled for removal when the PRM code is moved into | |
2942 | * drivers/. | |
2943 | */ | |
2944 | static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, | |
2945 | struct omap_hwmod_rst_info *ohri) | |
2946 | { | |
2947 | if (ohri->st_shift) | |
2948 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
2949 | oh->name, ohri->name); | |
2950 | ||
2951 | return am33xx_prm_deassert_hardreset(ohri->rst_shift, | |
2952 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2953 | oh->prcm.omap4.rstctrl_offs, | |
2954 | oh->prcm.omap4.rstst_offs); | |
2955 | } | |
2956 | ||
2957 | /** | |
2958 | * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args | |
2959 | * @oh: struct omap_hwmod * to test hardreset | |
2960 | * @ohri: hardreset line data | |
2961 | * | |
2962 | * Call am33xx_prminst_is_hardreset_asserted() with parameters | |
2963 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
2964 | * Only intended for use as an soc_ops function pointer. Passes along | |
2965 | * the return value from am33xx_prminst_is_hardreset_asserted(). XXX | |
2966 | * This function is scheduled for removal when the PRM code is moved | |
2967 | * into drivers/. | |
2968 | */ | |
2969 | static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh, | |
2970 | struct omap_hwmod_rst_info *ohri) | |
2971 | { | |
2972 | return am33xx_prm_is_hardreset_asserted(ohri->rst_shift, | |
2973 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2974 | oh->prcm.omap4.rstctrl_offs); | |
2975 | } | |
2976 | ||
0102b627 BC |
2977 | /* Public functions */ |
2978 | ||
2979 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
2980 | { | |
2981 | if (oh->flags & HWMOD_16BIT_REG) | |
2982 | return __raw_readw(oh->_mpu_rt_va + reg_offs); | |
2983 | else | |
2984 | return __raw_readl(oh->_mpu_rt_va + reg_offs); | |
2985 | } | |
2986 | ||
2987 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
2988 | { | |
2989 | if (oh->flags & HWMOD_16BIT_REG) | |
2990 | __raw_writew(v, oh->_mpu_rt_va + reg_offs); | |
2991 | else | |
2992 | __raw_writel(v, oh->_mpu_rt_va + reg_offs); | |
2993 | } | |
2994 | ||
6d3c55fd A |
2995 | /** |
2996 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
2997 | * @oh: struct omap_hwmod * | |
2998 | * | |
2999 | * This is a public function exposed to drivers. Some drivers may need to do | |
3000 | * some settings before and after resetting the device. Those drivers after | |
3001 | * doing the necessary settings could use this function to start a reset by | |
3002 | * setting the SYSCONFIG.SOFTRESET bit. | |
3003 | */ | |
3004 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
3005 | { | |
3c55c1ba PW |
3006 | u32 v; |
3007 | int ret; | |
3008 | ||
3009 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
3010 | return -EINVAL; |
3011 | ||
3c55c1ba PW |
3012 | v = oh->_sysc_cache; |
3013 | ret = _set_softreset(oh, &v); | |
3014 | if (ret) | |
3015 | goto error; | |
3016 | _write_sysconfig(v, oh); | |
3017 | ||
3018 | error: | |
3019 | return ret; | |
6d3c55fd A |
3020 | } |
3021 | ||
0102b627 BC |
3022 | /** |
3023 | * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode | |
3024 | * @oh: struct omap_hwmod * | |
3025 | * @idlemode: SIDLEMODE field bits (shifted to bit 0) | |
3026 | * | |
3027 | * Sets the IP block's OCP slave idlemode in hardware, and updates our | |
3028 | * local copy. Intended to be used by drivers that have some erratum | |
3029 | * that requires direct manipulation of the SIDLEMODE bits. Returns | |
3030 | * -EINVAL if @oh is null, or passes along the return value from | |
3031 | * _set_slave_idlemode(). | |
3032 | * | |
3033 | * XXX Does this function have any current users? If not, we should | |
3034 | * remove it; it is better to let the rest of the hwmod code handle this. | |
3035 | * Any users of this function should be scrutinized carefully. | |
3036 | */ | |
3037 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) | |
3038 | { | |
3039 | u32 v; | |
3040 | int retval = 0; | |
3041 | ||
3042 | if (!oh) | |
3043 | return -EINVAL; | |
3044 | ||
3045 | v = oh->_sysc_cache; | |
3046 | ||
3047 | retval = _set_slave_idlemode(oh, idlemode, &v); | |
3048 | if (!retval) | |
3049 | _write_sysconfig(v, oh); | |
3050 | ||
3051 | return retval; | |
3052 | } | |
3053 | ||
63c85238 PW |
3054 | /** |
3055 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
3056 | * @name: name of the omap_hwmod to look up | |
3057 | * | |
3058 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
3059 | * struct omap_hwmod *, or NULL upon error. | |
3060 | */ | |
3061 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
3062 | { | |
3063 | struct omap_hwmod *oh; | |
3064 | ||
3065 | if (!name) | |
3066 | return NULL; | |
3067 | ||
63c85238 | 3068 | oh = _lookup(name); |
63c85238 PW |
3069 | |
3070 | return oh; | |
3071 | } | |
3072 | ||
3073 | /** | |
3074 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
3075 | * @fn: pointer to a callback function | |
97d60162 | 3076 | * @data: void * data to pass to callback function |
63c85238 PW |
3077 | * |
3078 | * Call @fn for each registered omap_hwmod, passing @data to each | |
3079 | * function. @fn must return 0 for success or any other value for | |
3080 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
3081 | * will stop and the non-zero return value will be passed to the | |
3082 | * caller of omap_hwmod_for_each(). @fn is called with | |
3083 | * omap_hwmod_for_each() held. | |
3084 | */ | |
97d60162 PW |
3085 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
3086 | void *data) | |
63c85238 PW |
3087 | { |
3088 | struct omap_hwmod *temp_oh; | |
30ebad9d | 3089 | int ret = 0; |
63c85238 PW |
3090 | |
3091 | if (!fn) | |
3092 | return -EINVAL; | |
3093 | ||
63c85238 | 3094 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 3095 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
3096 | if (ret) |
3097 | break; | |
3098 | } | |
63c85238 PW |
3099 | |
3100 | return ret; | |
3101 | } | |
3102 | ||
2221b5cd PW |
3103 | /** |
3104 | * omap_hwmod_register_links - register an array of hwmod links | |
3105 | * @ois: pointer to an array of omap_hwmod_ocp_if to register | |
3106 | * | |
3107 | * Intended to be called early in boot before the clock framework is | |
3108 | * initialized. If @ois is not null, will register all omap_hwmods | |
9ebfd285 KH |
3109 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
3110 | * omap_hwmod_init() hasn't been called before calling this function, | |
3111 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | |
3112 | * success. | |
2221b5cd PW |
3113 | */ |
3114 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | |
3115 | { | |
3116 | int r, i; | |
3117 | ||
9ebfd285 KH |
3118 | if (!inited) |
3119 | return -EINVAL; | |
3120 | ||
2221b5cd PW |
3121 | if (!ois) |
3122 | return 0; | |
3123 | ||
2221b5cd PW |
3124 | if (!linkspace) { |
3125 | if (_alloc_linkspace(ois)) { | |
3126 | pr_err("omap_hwmod: could not allocate link space\n"); | |
3127 | return -ENOMEM; | |
3128 | } | |
3129 | } | |
3130 | ||
3131 | i = 0; | |
3132 | do { | |
3133 | r = _register_link(ois[i]); | |
3134 | WARN(r && r != -EEXIST, | |
3135 | "omap_hwmod: _register_link(%s -> %s) returned %d\n", | |
3136 | ois[i]->master->name, ois[i]->slave->name, r); | |
3137 | } while (ois[++i]); | |
3138 | ||
3139 | return 0; | |
3140 | } | |
3141 | ||
381d033a PW |
3142 | /** |
3143 | * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up | |
3144 | * @oh: pointer to the hwmod currently being set up (usually not the MPU) | |
3145 | * | |
3146 | * If the hwmod data corresponding to the MPU subsystem IP block | |
3147 | * hasn't been initialized and set up yet, do so now. This must be | |
3148 | * done first since sleep dependencies may be added from other hwmods | |
3149 | * to the MPU. Intended to be called only by omap_hwmod_setup*(). No | |
3150 | * return value. | |
63c85238 | 3151 | */ |
381d033a | 3152 | static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) |
e7c7d760 | 3153 | { |
381d033a PW |
3154 | if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) |
3155 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
3156 | __func__, MPU_INITIATOR_NAME); | |
3157 | else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) | |
3158 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
e7c7d760 TL |
3159 | } |
3160 | ||
63c85238 | 3161 | /** |
a2debdbd PW |
3162 | * omap_hwmod_setup_one - set up a single hwmod |
3163 | * @oh_name: const char * name of the already-registered hwmod to set up | |
3164 | * | |
381d033a PW |
3165 | * Initialize and set up a single hwmod. Intended to be used for a |
3166 | * small number of early devices, such as the timer IP blocks used for | |
3167 | * the scheduler clock. Must be called after omap2_clk_init(). | |
3168 | * Resolves the struct clk names to struct clk pointers for each | |
3169 | * registered omap_hwmod. Also calls _setup() on each hwmod. Returns | |
3170 | * -EINVAL upon error or 0 upon success. | |
a2debdbd PW |
3171 | */ |
3172 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
3173 | { |
3174 | struct omap_hwmod *oh; | |
63c85238 | 3175 | |
a2debdbd PW |
3176 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
3177 | ||
a2debdbd PW |
3178 | oh = _lookup(oh_name); |
3179 | if (!oh) { | |
3180 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
3181 | return -EINVAL; | |
3182 | } | |
63c85238 | 3183 | |
381d033a | 3184 | _ensure_mpu_hwmod_is_setup(oh); |
63c85238 | 3185 | |
381d033a | 3186 | _init(oh, NULL); |
a2debdbd PW |
3187 | _setup(oh, NULL); |
3188 | ||
63c85238 PW |
3189 | return 0; |
3190 | } | |
3191 | ||
3192 | /** | |
381d033a | 3193 | * omap_hwmod_setup_all - set up all registered IP blocks |
63c85238 | 3194 | * |
381d033a PW |
3195 | * Initialize and set up all IP blocks registered with the hwmod code. |
3196 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
3197 | * names to struct clk pointers for each registered omap_hwmod. Also | |
3198 | * calls _setup() on each hwmod. Returns 0 upon success. | |
63c85238 | 3199 | */ |
550c8092 | 3200 | static int __init omap_hwmod_setup_all(void) |
63c85238 | 3201 | { |
381d033a | 3202 | _ensure_mpu_hwmod_is_setup(NULL); |
63c85238 | 3203 | |
381d033a | 3204 | omap_hwmod_for_each(_init, NULL); |
2092e5cc | 3205 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
3206 | |
3207 | return 0; | |
3208 | } | |
550c8092 | 3209 | core_initcall(omap_hwmod_setup_all); |
63c85238 | 3210 | |
63c85238 PW |
3211 | /** |
3212 | * omap_hwmod_enable - enable an omap_hwmod | |
3213 | * @oh: struct omap_hwmod * | |
3214 | * | |
74ff3a68 | 3215 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
3216 | * Returns -EINVAL on error or passes along the return value from _enable(). |
3217 | */ | |
3218 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
3219 | { | |
3220 | int r; | |
dc6d1cda | 3221 | unsigned long flags; |
63c85238 PW |
3222 | |
3223 | if (!oh) | |
3224 | return -EINVAL; | |
3225 | ||
dc6d1cda PW |
3226 | spin_lock_irqsave(&oh->_lock, flags); |
3227 | r = _enable(oh); | |
3228 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3229 | |
3230 | return r; | |
3231 | } | |
3232 | ||
3233 | /** | |
3234 | * omap_hwmod_idle - idle an omap_hwmod | |
3235 | * @oh: struct omap_hwmod * | |
3236 | * | |
74ff3a68 | 3237 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
3238 | * Returns -EINVAL on error or passes along the return value from _idle(). |
3239 | */ | |
3240 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
3241 | { | |
dc6d1cda PW |
3242 | unsigned long flags; |
3243 | ||
63c85238 PW |
3244 | if (!oh) |
3245 | return -EINVAL; | |
3246 | ||
dc6d1cda PW |
3247 | spin_lock_irqsave(&oh->_lock, flags); |
3248 | _idle(oh); | |
3249 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3250 | |
3251 | return 0; | |
3252 | } | |
3253 | ||
3254 | /** | |
3255 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
3256 | * @oh: struct omap_hwmod * | |
3257 | * | |
74ff3a68 | 3258 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
3259 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
3260 | * the return value from _shutdown(). | |
3261 | */ | |
3262 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
3263 | { | |
dc6d1cda PW |
3264 | unsigned long flags; |
3265 | ||
63c85238 PW |
3266 | if (!oh) |
3267 | return -EINVAL; | |
3268 | ||
dc6d1cda | 3269 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3270 | _shutdown(oh); |
dc6d1cda | 3271 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3272 | |
3273 | return 0; | |
3274 | } | |
3275 | ||
3276 | /** | |
3277 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
3278 | * @oh: struct omap_hwmod *oh | |
3279 | * | |
3280 | * Intended to be called by the omap_device code. | |
3281 | */ | |
3282 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
3283 | { | |
dc6d1cda PW |
3284 | unsigned long flags; |
3285 | ||
3286 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 3287 | _enable_clocks(oh); |
dc6d1cda | 3288 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3289 | |
3290 | return 0; | |
3291 | } | |
3292 | ||
3293 | /** | |
3294 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
3295 | * @oh: struct omap_hwmod *oh | |
3296 | * | |
3297 | * Intended to be called by the omap_device code. | |
3298 | */ | |
3299 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
3300 | { | |
dc6d1cda PW |
3301 | unsigned long flags; |
3302 | ||
3303 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 3304 | _disable_clocks(oh); |
dc6d1cda | 3305 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3306 | |
3307 | return 0; | |
3308 | } | |
3309 | ||
3310 | /** | |
3311 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
3312 | * @oh: struct omap_hwmod *oh | |
3313 | * | |
3314 | * Intended to be called by drivers and core code when all posted | |
3315 | * writes to a device must complete before continuing further | |
3316 | * execution (for example, after clearing some device IRQSTATUS | |
3317 | * register bits) | |
3318 | * | |
3319 | * XXX what about targets with multiple OCP threads? | |
3320 | */ | |
3321 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
3322 | { | |
3323 | BUG_ON(!oh); | |
3324 | ||
43b40992 | 3325 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
4f8a428d RK |
3326 | WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n", |
3327 | oh->name); | |
63c85238 PW |
3328 | return; |
3329 | } | |
3330 | ||
3331 | /* | |
3332 | * Forces posted writes to complete on the OCP thread handling | |
3333 | * register writes | |
3334 | */ | |
cc7a1d2a | 3335 | omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
3336 | } |
3337 | ||
3338 | /** | |
3339 | * omap_hwmod_reset - reset the hwmod | |
3340 | * @oh: struct omap_hwmod * | |
3341 | * | |
3342 | * Under some conditions, a driver may wish to reset the entire device. | |
3343 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 3344 | * the return value from _reset(). |
63c85238 PW |
3345 | */ |
3346 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
3347 | { | |
3348 | int r; | |
dc6d1cda | 3349 | unsigned long flags; |
63c85238 | 3350 | |
9b579114 | 3351 | if (!oh) |
63c85238 PW |
3352 | return -EINVAL; |
3353 | ||
dc6d1cda | 3354 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3355 | r = _reset(oh); |
dc6d1cda | 3356 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3357 | |
3358 | return r; | |
3359 | } | |
3360 | ||
5e8370f1 PW |
3361 | /* |
3362 | * IP block data retrieval functions | |
3363 | */ | |
3364 | ||
63c85238 PW |
3365 | /** |
3366 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
3367 | * @oh: struct omap_hwmod * | |
3368 | * @res: pointer to the first element of an array of struct resource to fill | |
3369 | * | |
3370 | * Count the number of struct resource array elements necessary to | |
3371 | * contain omap_hwmod @oh resources. Intended to be called by code | |
3372 | * that registers omap_devices. Intended to be used to determine the | |
3373 | * size of a dynamically-allocated struct resource array, before | |
3374 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
3375 | * resource array elements needed. | |
3376 | * | |
3377 | * XXX This code is not optimized. It could attempt to merge adjacent | |
3378 | * resource IDs. | |
3379 | * | |
3380 | */ | |
3381 | int omap_hwmod_count_resources(struct omap_hwmod *oh) | |
3382 | { | |
5d95dde7 | 3383 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3384 | struct list_head *p; |
5d95dde7 PW |
3385 | int ret; |
3386 | int i = 0; | |
63c85238 | 3387 | |
bc614958 | 3388 | ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); |
63c85238 | 3389 | |
11cd4b94 | 3390 | p = oh->slave_ports.next; |
2221b5cd | 3391 | |
5d95dde7 | 3392 | while (i < oh->slaves_cnt) { |
11cd4b94 | 3393 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 PW |
3394 | ret += _count_ocp_if_addr_spaces(os); |
3395 | } | |
63c85238 PW |
3396 | |
3397 | return ret; | |
3398 | } | |
3399 | ||
3400 | /** | |
3401 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
3402 | * @oh: struct omap_hwmod * | |
3403 | * @res: pointer to the first element of an array of struct resource to fill | |
3404 | * | |
3405 | * Fill the struct resource array @res with resource data from the | |
3406 | * omap_hwmod @oh. Intended to be called by code that registers | |
3407 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3408 | * number of array elements filled. | |
3409 | */ | |
3410 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
3411 | { | |
5d95dde7 | 3412 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3413 | struct list_head *p; |
5d95dde7 | 3414 | int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; |
63c85238 PW |
3415 | int r = 0; |
3416 | ||
3417 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
3418 | ||
212738a4 PW |
3419 | mpu_irqs_cnt = _count_mpu_irqs(oh); |
3420 | for (i = 0; i < mpu_irqs_cnt; i++) { | |
718bfd76 PW |
3421 | (res + r)->name = (oh->mpu_irqs + i)->name; |
3422 | (res + r)->start = (oh->mpu_irqs + i)->irq; | |
3423 | (res + r)->end = (oh->mpu_irqs + i)->irq; | |
63c85238 PW |
3424 | (res + r)->flags = IORESOURCE_IRQ; |
3425 | r++; | |
3426 | } | |
3427 | ||
bc614958 PW |
3428 | sdma_reqs_cnt = _count_sdma_reqs(oh); |
3429 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
9ee9fff9 BC |
3430 | (res + r)->name = (oh->sdma_reqs + i)->name; |
3431 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3432 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
3433 | (res + r)->flags = IORESOURCE_DMA; |
3434 | r++; | |
3435 | } | |
3436 | ||
11cd4b94 | 3437 | p = oh->slave_ports.next; |
2221b5cd | 3438 | |
5d95dde7 PW |
3439 | i = 0; |
3440 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 3441 | os = _fetch_next_ocp_if(&p, &i); |
78183f3f | 3442 | addr_cnt = _count_ocp_if_addr_spaces(os); |
63c85238 | 3443 | |
78183f3f | 3444 | for (j = 0; j < addr_cnt; j++) { |
cd503802 | 3445 | (res + r)->name = (os->addr + j)->name; |
63c85238 PW |
3446 | (res + r)->start = (os->addr + j)->pa_start; |
3447 | (res + r)->end = (os->addr + j)->pa_end; | |
3448 | (res + r)->flags = IORESOURCE_MEM; | |
3449 | r++; | |
3450 | } | |
3451 | } | |
3452 | ||
3453 | return r; | |
3454 | } | |
3455 | ||
b82b04e8 VH |
3456 | /** |
3457 | * omap_hwmod_fill_dma_resources - fill struct resource array with dma data | |
3458 | * @oh: struct omap_hwmod * | |
3459 | * @res: pointer to the array of struct resource to fill | |
3460 | * | |
3461 | * Fill the struct resource array @res with dma resource data from the | |
3462 | * omap_hwmod @oh. Intended to be called by code that registers | |
3463 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3464 | * number of array elements filled. | |
3465 | */ | |
3466 | int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res) | |
3467 | { | |
3468 | int i, sdma_reqs_cnt; | |
3469 | int r = 0; | |
3470 | ||
3471 | sdma_reqs_cnt = _count_sdma_reqs(oh); | |
3472 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
3473 | (res + r)->name = (oh->sdma_reqs + i)->name; | |
3474 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3475 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
3476 | (res + r)->flags = IORESOURCE_DMA; | |
3477 | r++; | |
3478 | } | |
3479 | ||
3480 | return r; | |
3481 | } | |
3482 | ||
5e8370f1 PW |
3483 | /** |
3484 | * omap_hwmod_get_resource_byname - fetch IP block integration data by name | |
3485 | * @oh: struct omap_hwmod * to operate on | |
3486 | * @type: one of the IORESOURCE_* constants from include/linux/ioport.h | |
3487 | * @name: pointer to the name of the data to fetch (optional) | |
3488 | * @rsrc: pointer to a struct resource, allocated by the caller | |
3489 | * | |
3490 | * Retrieve MPU IRQ, SDMA request line, or address space start/end | |
3491 | * data for the IP block pointed to by @oh. The data will be filled | |
3492 | * into a struct resource record pointed to by @rsrc. The struct | |
3493 | * resource must be allocated by the caller. When @name is non-null, | |
3494 | * the data associated with the matching entry in the IRQ/SDMA/address | |
3495 | * space hwmod data arrays will be returned. If @name is null, the | |
3496 | * first array entry will be returned. Data order is not meaningful | |
3497 | * in hwmod data, so callers are strongly encouraged to use a non-null | |
3498 | * @name whenever possible to avoid unpredictable effects if hwmod | |
3499 | * data is later added that causes data ordering to change. This | |
3500 | * function is only intended for use by OMAP core code. Device | |
3501 | * drivers should not call this function - the appropriate bus-related | |
3502 | * data accessor functions should be used instead. Returns 0 upon | |
3503 | * success or a negative error code upon error. | |
3504 | */ | |
3505 | int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, | |
3506 | const char *name, struct resource *rsrc) | |
3507 | { | |
3508 | int r; | |
3509 | unsigned int irq, dma; | |
3510 | u32 pa_start, pa_end; | |
3511 | ||
3512 | if (!oh || !rsrc) | |
3513 | return -EINVAL; | |
3514 | ||
3515 | if (type == IORESOURCE_IRQ) { | |
3516 | r = _get_mpu_irq_by_name(oh, name, &irq); | |
3517 | if (r) | |
3518 | return r; | |
3519 | ||
3520 | rsrc->start = irq; | |
3521 | rsrc->end = irq; | |
3522 | } else if (type == IORESOURCE_DMA) { | |
3523 | r = _get_sdma_req_by_name(oh, name, &dma); | |
3524 | if (r) | |
3525 | return r; | |
3526 | ||
3527 | rsrc->start = dma; | |
3528 | rsrc->end = dma; | |
3529 | } else if (type == IORESOURCE_MEM) { | |
3530 | r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); | |
3531 | if (r) | |
3532 | return r; | |
3533 | ||
3534 | rsrc->start = pa_start; | |
3535 | rsrc->end = pa_end; | |
3536 | } else { | |
3537 | return -EINVAL; | |
3538 | } | |
3539 | ||
3540 | rsrc->flags = type; | |
3541 | rsrc->name = name; | |
3542 | ||
3543 | return 0; | |
3544 | } | |
3545 | ||
63c85238 PW |
3546 | /** |
3547 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
3548 | * @oh: struct omap_hwmod * | |
3549 | * | |
3550 | * Return the powerdomain pointer associated with the OMAP module | |
3551 | * @oh's main clock. If @oh does not have a main clk, return the | |
3552 | * powerdomain associated with the interface clock associated with the | |
3553 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
3554 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
3555 | * success. | |
3556 | */ | |
3557 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
3558 | { | |
3559 | struct clk *c; | |
2d6141ba | 3560 | struct omap_hwmod_ocp_if *oi; |
63c85238 PW |
3561 | |
3562 | if (!oh) | |
3563 | return NULL; | |
3564 | ||
3565 | if (oh->_clk) { | |
3566 | c = oh->_clk; | |
3567 | } else { | |
2d6141ba PW |
3568 | oi = _find_mpu_rt_port(oh); |
3569 | if (!oi) | |
63c85238 | 3570 | return NULL; |
2d6141ba | 3571 | c = oi->_clk; |
63c85238 PW |
3572 | } |
3573 | ||
d5647c18 TG |
3574 | if (!c->clkdm) |
3575 | return NULL; | |
3576 | ||
63c85238 PW |
3577 | return c->clkdm->pwrdm.ptr; |
3578 | ||
3579 | } | |
3580 | ||
db2a60bf PW |
3581 | /** |
3582 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
3583 | * @oh: struct omap_hwmod * | |
3584 | * | |
3585 | * Returns the virtual address corresponding to the beginning of the | |
3586 | * module's register target, in the address range that is intended to | |
3587 | * be used by the MPU. Returns the virtual address upon success or NULL | |
3588 | * upon error. | |
3589 | */ | |
3590 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
3591 | { | |
3592 | if (!oh) | |
3593 | return NULL; | |
3594 | ||
3595 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
3596 | return NULL; | |
3597 | ||
3598 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
3599 | return NULL; | |
3600 | ||
3601 | return oh->_mpu_rt_va; | |
3602 | } | |
3603 | ||
63c85238 PW |
3604 | /** |
3605 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
3606 | * @oh: struct omap_hwmod * | |
3607 | * @init_oh: struct omap_hwmod * (initiator) | |
3608 | * | |
3609 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
3610 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3611 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3612 | * code needs to add/del initiator dependencies dynamically | |
3613 | * before/after accessing a device. Returns the return value from | |
3614 | * _add_initiator_dep(). | |
3615 | * | |
3616 | * XXX Keep a usecount in the clockdomain code | |
3617 | */ | |
3618 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
3619 | struct omap_hwmod *init_oh) | |
3620 | { | |
3621 | return _add_initiator_dep(oh, init_oh); | |
3622 | } | |
3623 | ||
3624 | /* | |
3625 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
3626 | * for context save/restore operations? | |
3627 | */ | |
3628 | ||
3629 | /** | |
3630 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
3631 | * @oh: struct omap_hwmod * | |
3632 | * @init_oh: struct omap_hwmod * (initiator) | |
3633 | * | |
3634 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
3635 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3636 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3637 | * code needs to add/del initiator dependencies dynamically | |
3638 | * before/after accessing a device. Returns the return value from | |
3639 | * _del_initiator_dep(). | |
3640 | * | |
3641 | * XXX Keep a usecount in the clockdomain code | |
3642 | */ | |
3643 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
3644 | struct omap_hwmod *init_oh) | |
3645 | { | |
3646 | return _del_initiator_dep(oh, init_oh); | |
3647 | } | |
3648 | ||
63c85238 PW |
3649 | /** |
3650 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
3651 | * @oh: struct omap_hwmod * | |
3652 | * | |
3653 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
3654 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
3655 | * this IP block if it has dynamic mux entries. Eventually this | |
3656 | * should set PRCM wakeup registers to cause the PRCM to receive | |
3657 | * wakeup events from the module. Does not set any wakeup routing | |
3658 | * registers beyond this point - if the module is to wake up any other | |
3659 | * module or subsystem, that must be set separately. Called by | |
3660 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3661 | */ |
3662 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
3663 | { | |
dc6d1cda | 3664 | unsigned long flags; |
5a7ddcbd | 3665 | u32 v; |
dc6d1cda | 3666 | |
dc6d1cda | 3667 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3668 | |
3669 | if (oh->class->sysc && | |
3670 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3671 | v = oh->_sysc_cache; | |
3672 | _enable_wakeup(oh, &v); | |
3673 | _write_sysconfig(v, oh); | |
3674 | } | |
3675 | ||
eceec009 | 3676 | _set_idle_ioring_wakeup(oh, true); |
dc6d1cda | 3677 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3678 | |
3679 | return 0; | |
3680 | } | |
3681 | ||
3682 | /** | |
3683 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
3684 | * @oh: struct omap_hwmod * | |
3685 | * | |
3686 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
3687 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
3688 | * events for this IP block if it has dynamic mux entries. Eventually | |
3689 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
3690 | * wakeup events from the module. Does not set any wakeup routing | |
3691 | * registers beyond this point - if the module is to wake up any other | |
3692 | * module or subsystem, that must be set separately. Called by | |
3693 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3694 | */ |
3695 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
3696 | { | |
dc6d1cda | 3697 | unsigned long flags; |
5a7ddcbd | 3698 | u32 v; |
dc6d1cda | 3699 | |
dc6d1cda | 3700 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3701 | |
3702 | if (oh->class->sysc && | |
3703 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3704 | v = oh->_sysc_cache; | |
3705 | _disable_wakeup(oh, &v); | |
3706 | _write_sysconfig(v, oh); | |
3707 | } | |
3708 | ||
eceec009 | 3709 | _set_idle_ioring_wakeup(oh, false); |
dc6d1cda | 3710 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3711 | |
3712 | return 0; | |
3713 | } | |
43b40992 | 3714 | |
aee48e3c PW |
3715 | /** |
3716 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
3717 | * contained in the hwmod module. | |
3718 | * @oh: struct omap_hwmod * | |
3719 | * @name: name of the reset line to lookup and assert | |
3720 | * | |
3721 | * Some IP like dsp, ipu or iva contain processor that require | |
3722 | * an HW reset line to be assert / deassert in order to enable fully | |
3723 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3724 | * yet supported on this OMAP; otherwise, passes along the return value | |
3725 | * from _assert_hardreset(). | |
3726 | */ | |
3727 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
3728 | { | |
3729 | int ret; | |
dc6d1cda | 3730 | unsigned long flags; |
aee48e3c PW |
3731 | |
3732 | if (!oh) | |
3733 | return -EINVAL; | |
3734 | ||
dc6d1cda | 3735 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3736 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 3737 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3738 | |
3739 | return ret; | |
3740 | } | |
3741 | ||
3742 | /** | |
3743 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
3744 | * contained in the hwmod module. | |
3745 | * @oh: struct omap_hwmod * | |
3746 | * @name: name of the reset line to look up and deassert | |
3747 | * | |
3748 | * Some IP like dsp, ipu or iva contain processor that require | |
3749 | * an HW reset line to be assert / deassert in order to enable fully | |
3750 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3751 | * yet supported on this OMAP; otherwise, passes along the return value | |
3752 | * from _deassert_hardreset(). | |
3753 | */ | |
3754 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
3755 | { | |
3756 | int ret; | |
dc6d1cda | 3757 | unsigned long flags; |
aee48e3c PW |
3758 | |
3759 | if (!oh) | |
3760 | return -EINVAL; | |
3761 | ||
dc6d1cda | 3762 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3763 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 3764 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3765 | |
3766 | return ret; | |
3767 | } | |
3768 | ||
3769 | /** | |
3770 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
3771 | * contained in the hwmod module | |
3772 | * @oh: struct omap_hwmod * | |
3773 | * @name: name of the reset line to look up and read | |
3774 | * | |
3775 | * Return the current state of the hwmod @oh's reset line named @name: | |
3776 | * returns -EINVAL upon parameter error or if this operation | |
3777 | * is unsupported on the current OMAP; otherwise, passes along the return | |
3778 | * value from _read_hardreset(). | |
3779 | */ | |
3780 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
3781 | { | |
3782 | int ret; | |
dc6d1cda | 3783 | unsigned long flags; |
aee48e3c PW |
3784 | |
3785 | if (!oh) | |
3786 | return -EINVAL; | |
3787 | ||
dc6d1cda | 3788 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3789 | ret = _read_hardreset(oh, name); |
dc6d1cda | 3790 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3791 | |
3792 | return ret; | |
3793 | } | |
3794 | ||
3795 | ||
43b40992 PW |
3796 | /** |
3797 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
3798 | * @classname: struct omap_hwmod_class name to search for | |
3799 | * @fn: callback function pointer to call for each hwmod in class @classname | |
3800 | * @user: arbitrary context data to pass to the callback function | |
3801 | * | |
ce35b244 BC |
3802 | * For each omap_hwmod of class @classname, call @fn. |
3803 | * If the callback function returns something other than | |
43b40992 PW |
3804 | * zero, the iterator is terminated, and the callback function's return |
3805 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
3806 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
3807 | */ | |
3808 | int omap_hwmod_for_each_by_class(const char *classname, | |
3809 | int (*fn)(struct omap_hwmod *oh, | |
3810 | void *user), | |
3811 | void *user) | |
3812 | { | |
3813 | struct omap_hwmod *temp_oh; | |
3814 | int ret = 0; | |
3815 | ||
3816 | if (!classname || !fn) | |
3817 | return -EINVAL; | |
3818 | ||
3819 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
3820 | __func__, classname); | |
3821 | ||
43b40992 PW |
3822 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
3823 | if (!strcmp(temp_oh->class->name, classname)) { | |
3824 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
3825 | __func__, temp_oh->name); | |
3826 | ret = (*fn)(temp_oh, user); | |
3827 | if (ret) | |
3828 | break; | |
3829 | } | |
3830 | } | |
3831 | ||
43b40992 PW |
3832 | if (ret) |
3833 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
3834 | __func__, ret); | |
3835 | ||
3836 | return ret; | |
3837 | } | |
3838 | ||
2092e5cc PW |
3839 | /** |
3840 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
3841 | * @oh: struct omap_hwmod * | |
3842 | * @state: state that _setup() should leave the hwmod in | |
3843 | * | |
550c8092 | 3844 | * Sets the hwmod state that @oh will enter at the end of _setup() |
64813c3f PW |
3845 | * (called by omap_hwmod_setup_*()). See also the documentation |
3846 | * for _setup_postsetup(), above. Returns 0 upon success or | |
3847 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
3848 | * in the wrong state. | |
2092e5cc PW |
3849 | */ |
3850 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
3851 | { | |
3852 | int ret; | |
dc6d1cda | 3853 | unsigned long flags; |
2092e5cc PW |
3854 | |
3855 | if (!oh) | |
3856 | return -EINVAL; | |
3857 | ||
3858 | if (state != _HWMOD_STATE_DISABLED && | |
3859 | state != _HWMOD_STATE_ENABLED && | |
3860 | state != _HWMOD_STATE_IDLE) | |
3861 | return -EINVAL; | |
3862 | ||
dc6d1cda | 3863 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
3864 | |
3865 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3866 | ret = -EINVAL; | |
3867 | goto ohsps_unlock; | |
3868 | } | |
3869 | ||
3870 | oh->_postsetup_state = state; | |
3871 | ret = 0; | |
3872 | ||
3873 | ohsps_unlock: | |
dc6d1cda | 3874 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
3875 | |
3876 | return ret; | |
3877 | } | |
c80705aa KH |
3878 | |
3879 | /** | |
3880 | * omap_hwmod_get_context_loss_count - get lost context count | |
3881 | * @oh: struct omap_hwmod * | |
3882 | * | |
3883 | * Query the powerdomain of of @oh to get the context loss | |
3884 | * count for this device. | |
3885 | * | |
3886 | * Returns the context loss count of the powerdomain assocated with @oh | |
3887 | * upon success, or zero if no powerdomain exists for @oh. | |
3888 | */ | |
fc013873 | 3889 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
3890 | { |
3891 | struct powerdomain *pwrdm; | |
3892 | int ret = 0; | |
3893 | ||
3894 | pwrdm = omap_hwmod_get_pwrdm(oh); | |
3895 | if (pwrdm) | |
3896 | ret = pwrdm_get_context_loss_count(pwrdm); | |
3897 | ||
3898 | return ret; | |
3899 | } | |
43b01643 PW |
3900 | |
3901 | /** | |
3902 | * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup | |
3903 | * @oh: struct omap_hwmod * | |
3904 | * | |
3905 | * Prevent the hwmod @oh from being reset during the setup process. | |
3906 | * Intended for use by board-*.c files on boards with devices that | |
3907 | * cannot tolerate being reset. Must be called before the hwmod has | |
3908 | * been set up. Returns 0 upon success or negative error code upon | |
3909 | * failure. | |
3910 | */ | |
3911 | int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) | |
3912 | { | |
3913 | if (!oh) | |
3914 | return -EINVAL; | |
3915 | ||
3916 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3917 | pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n", | |
3918 | oh->name); | |
3919 | return -EINVAL; | |
3920 | } | |
3921 | ||
3922 | oh->flags |= HWMOD_INIT_NO_RESET; | |
3923 | ||
3924 | return 0; | |
3925 | } | |
abc2d545 TK |
3926 | |
3927 | /** | |
3928 | * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ | |
3929 | * @oh: struct omap_hwmod * containing hwmod mux entries | |
3930 | * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup | |
3931 | * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup | |
3932 | * | |
3933 | * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux | |
3934 | * entry number @pad_idx for the hwmod @oh, trigger the interrupt | |
3935 | * service routine for the hwmod's mpu_irqs array index @irq_idx. If | |
3936 | * this function is not called for a given pad_idx, then the ISR | |
3937 | * associated with @oh's first MPU IRQ will be triggered when an I/O | |
3938 | * pad wakeup occurs on that pad. Note that @pad_idx is the index of | |
3939 | * the _dynamic or wakeup_ entry: if there are other entries not | |
3940 | * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these | |
3941 | * entries are NOT COUNTED in the dynamic pad index. This function | |
3942 | * must be called separately for each pad that requires its interrupt | |
3943 | * to be re-routed this way. Returns -EINVAL if there is an argument | |
3944 | * problem or if @oh does not have hwmod mux entries or MPU IRQs; | |
3945 | * returns -ENOMEM if memory cannot be allocated; or 0 upon success. | |
3946 | * | |
3947 | * XXX This function interface is fragile. Rather than using array | |
3948 | * indexes, which are subject to unpredictable change, it should be | |
3949 | * using hwmod IRQ names, and some other stable key for the hwmod mux | |
3950 | * pad records. | |
3951 | */ | |
3952 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) | |
3953 | { | |
3954 | int nr_irqs; | |
3955 | ||
3956 | might_sleep(); | |
3957 | ||
3958 | if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 || | |
3959 | pad_idx >= oh->mux->nr_pads_dynamic) | |
3960 | return -EINVAL; | |
3961 | ||
3962 | /* Check the number of available mpu_irqs */ | |
3963 | for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++) | |
3964 | ; | |
3965 | ||
3966 | if (irq_idx >= nr_irqs) | |
3967 | return -EINVAL; | |
3968 | ||
3969 | if (!oh->mux->irqs) { | |
3970 | /* XXX What frees this? */ | |
3971 | oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic, | |
3972 | GFP_KERNEL); | |
3973 | if (!oh->mux->irqs) | |
3974 | return -ENOMEM; | |
3975 | } | |
3976 | oh->mux->irqs[pad_idx] = irq_idx; | |
3977 | ||
3978 | return 0; | |
3979 | } | |
9ebfd285 KH |
3980 | |
3981 | /** | |
3982 | * omap_hwmod_init - initialize the hwmod code | |
3983 | * | |
3984 | * Sets up some function pointers needed by the hwmod code to operate on the | |
3985 | * currently-booted SoC. Intended to be called once during kernel init | |
3986 | * before any hwmods are registered. No return value. | |
3987 | */ | |
3988 | void __init omap_hwmod_init(void) | |
3989 | { | |
ff4ae5d9 PW |
3990 | if (cpu_is_omap24xx()) { |
3991 | soc_ops.wait_target_ready = _omap2xxx_wait_target_ready; | |
3992 | soc_ops.assert_hardreset = _omap2_assert_hardreset; | |
3993 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3994 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
3995 | } else if (cpu_is_omap34xx()) { | |
3996 | soc_ops.wait_target_ready = _omap3xxx_wait_target_ready; | |
b8249cf2 KH |
3997 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
3998 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3999 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
05e152c7 | 4000 | } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { |
9ebfd285 KH |
4001 | soc_ops.enable_module = _omap4_enable_module; |
4002 | soc_ops.disable_module = _omap4_disable_module; | |
8f6aa8ee | 4003 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
b8249cf2 KH |
4004 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
4005 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | |
4006 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | |
0a179eaa | 4007 | soc_ops.init_clkdm = _init_clkdm; |
1688bf19 VH |
4008 | } else if (soc_is_am33xx()) { |
4009 | soc_ops.enable_module = _am33xx_enable_module; | |
4010 | soc_ops.disable_module = _am33xx_disable_module; | |
4011 | soc_ops.wait_target_ready = _am33xx_wait_target_ready; | |
4012 | soc_ops.assert_hardreset = _am33xx_assert_hardreset; | |
4013 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; | |
4014 | soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; | |
4015 | soc_ops.init_clkdm = _init_clkdm; | |
8f6aa8ee KH |
4016 | } else { |
4017 | WARN(1, "omap_hwmod: unknown SoC type\n"); | |
9ebfd285 KH |
4018 | } |
4019 | ||
4020 | inited = true; | |
4021 | } | |
68c9a95e TL |
4022 | |
4023 | /** | |
4024 | * omap_hwmod_get_main_clk - get pointer to main clock name | |
4025 | * @oh: struct omap_hwmod * | |
4026 | * | |
4027 | * Returns the main clock name assocated with @oh upon success, | |
4028 | * or NULL if @oh is NULL. | |
4029 | */ | |
4030 | const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) | |
4031 | { | |
4032 | if (!oh) | |
4033 | return NULL; | |
4034 | ||
4035 | return oh->main_clk; | |
4036 | } |