OMAP2+: hwmod: allow multiple calls to omap_hwmod_init()
[linux-2.6-block.git] / arch / arm / mach-omap2 / omap_hwmod.c
CommitLineData
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1/*
2 * omap_hwmod implementation for OMAP2/3/4
3 *
db2a60bf 4 * Copyright (C) 2009-2010 Nokia Corporation
63c85238 5 *
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6 * Paul Walmsley, Benoît Cousson, Kevin Hilman
7 *
8 * Created in collaboration with (alphabetical order): Thara Gopinath,
9 * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand
10 * Sawant, Santosh Shilimkar, Richard Woodruff
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11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
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16 * Introduction
17 * ------------
18 * One way to view an OMAP SoC is as a collection of largely unrelated
19 * IP blocks connected by interconnects. The IP blocks include
20 * devices such as ARM processors, audio serial interfaces, UARTs,
21 * etc. Some of these devices, like the DSP, are created by TI;
22 * others, like the SGX, largely originate from external vendors. In
23 * TI's documentation, on-chip devices are referred to as "OMAP
24 * modules." Some of these IP blocks are identical across several
25 * OMAP versions. Others are revised frequently.
63c85238 26 *
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27 * These OMAP modules are tied together by various interconnects.
28 * Most of the address and data flow between modules is via OCP-based
29 * interconnects such as the L3 and L4 buses; but there are other
30 * interconnects that distribute the hardware clock tree, handle idle
31 * and reset signaling, supply power, and connect the modules to
32 * various pads or balls on the OMAP package.
33 *
34 * OMAP hwmod provides a consistent way to describe the on-chip
35 * hardware blocks and their integration into the rest of the chip.
36 * This description can be automatically generated from the TI
37 * hardware database. OMAP hwmod provides a standard, consistent API
38 * to reset, enable, idle, and disable these hardware blocks. And
39 * hwmod provides a way for other core code, such as the Linux device
40 * code or the OMAP power management and address space mapping code,
41 * to query the hardware database.
42 *
43 * Using hwmod
44 * -----------
45 * Drivers won't call hwmod functions directly. That is done by the
46 * omap_device code, and in rare occasions, by custom integration code
47 * in arch/arm/ *omap*. The omap_device code includes functions to
48 * build a struct platform_device using omap_hwmod data, and that is
49 * currently how hwmod data is communicated to drivers and to the
50 * Linux driver model. Most drivers will call omap_hwmod functions only
51 * indirectly, via pm_runtime*() functions.
52 *
53 * From a layering perspective, here is where the OMAP hwmod code
54 * fits into the kernel software stack:
55 *
56 * +-------------------------------+
57 * | Device driver code |
58 * | (e.g., drivers/) |
59 * +-------------------------------+
60 * | Linux driver model |
61 * | (platform_device / |
62 * | platform_driver data/code) |
63 * +-------------------------------+
64 * | OMAP core-driver integration |
65 * |(arch/arm/mach-omap2/devices.c)|
66 * +-------------------------------+
67 * | omap_device code |
68 * | (../plat-omap/omap_device.c) |
69 * +-------------------------------+
70 * ----> | omap_hwmod code/data | <-----
71 * | (../mach-omap2/omap_hwmod*) |
72 * +-------------------------------+
73 * | OMAP clock/PRCM/register fns |
74 * | (__raw_{read,write}l, clk*) |
75 * +-------------------------------+
76 *
77 * Device drivers should not contain any OMAP-specific code or data in
78 * them. They should only contain code to operate the IP block that
79 * the driver is responsible for. This is because these IP blocks can
80 * also appear in other SoCs, either from TI (such as DaVinci) or from
81 * other manufacturers; and drivers should be reusable across other
82 * platforms.
83 *
84 * The OMAP hwmod code also will attempt to reset and idle all on-chip
85 * devices upon boot. The goal here is for the kernel to be
86 * completely self-reliant and independent from bootloaders. This is
87 * to ensure a repeatable configuration, both to ensure consistent
88 * runtime behavior, and to make it easier for others to reproduce
89 * bugs.
90 *
91 * OMAP module activity states
92 * ---------------------------
93 * The hwmod code considers modules to be in one of several activity
94 * states. IP blocks start out in an UNKNOWN state, then once they
95 * are registered via the hwmod code, proceed to the REGISTERED state.
96 * Once their clock names are resolved to clock pointers, the module
97 * enters the CLKS_INITED state; and finally, once the module has been
98 * reset and the integration registers programmed, the INITIALIZED state
99 * is entered. The hwmod code will then place the module into either
100 * the IDLE state to save power, or in the case of a critical system
101 * module, the ENABLED state.
102 *
103 * OMAP core integration code can then call omap_hwmod*() functions
104 * directly to move the module between the IDLE, ENABLED, and DISABLED
105 * states, as needed. This is done during both the PM idle loop, and
106 * in the OMAP core integration code's implementation of the PM runtime
107 * functions.
108 *
109 * References
110 * ----------
111 * This is a partial list.
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112 * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
113 * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
114 * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
115 * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
116 * - Open Core Protocol Specification 2.2
117 *
118 * To do:
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119 * - handle IO mapping
120 * - bus throughput & module latency measurement code
121 *
122 * XXX add tests at the beginning of each function to ensure the hwmod is
123 * in the appropriate state
124 * XXX error return values should be checked to ensure that they are
125 * appropriate
126 */
127#undef DEBUG
128
129#include <linux/kernel.h>
130#include <linux/errno.h>
131#include <linux/io.h>
132#include <linux/clk.h>
133#include <linux/delay.h>
134#include <linux/err.h>
135#include <linux/list.h>
136#include <linux/mutex.h>
dc6d1cda 137#include <linux/spinlock.h>
63c85238 138
6f8b7ff5 139#include <plat/common.h>
ce491cf8 140#include <plat/cpu.h>
1540f214 141#include "clockdomain.h"
72e06d08 142#include "powerdomain.h"
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143#include <plat/clock.h>
144#include <plat/omap_hwmod.h>
5365efbe 145#include <plat/prcm.h>
63c85238 146
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147#include "cm2xxx_3xxx.h"
148#include "cm44xx.h"
149#include "prm2xxx_3xxx.h"
d198b514 150#include "prm44xx.h"
8d9af88f 151#include "mux.h"
63c85238 152
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153/* Maximum microseconds to wait for OMAP module to softreset */
154#define MAX_MODULE_SOFTRESET_WAIT 10000
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155
156/* Name of the OMAP hwmod for the MPU */
5c2c0296 157#define MPU_INITIATOR_NAME "mpu"
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158
159/* omap_hwmod_list contains all registered struct omap_hwmods */
160static LIST_HEAD(omap_hwmod_list);
161
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162/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
163static struct omap_hwmod *mpu_oh;
164
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165
166/* Private functions */
167
168/**
169 * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
170 * @oh: struct omap_hwmod *
171 *
172 * Load the current value of the hwmod OCP_SYSCONFIG register into the
173 * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no
174 * OCP_SYSCONFIG register or 0 upon success.
175 */
176static int _update_sysc_cache(struct omap_hwmod *oh)
177{
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178 if (!oh->class->sysc) {
179 WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
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180 return -EINVAL;
181 }
182
183 /* XXX ensure module interface clock is up */
184
cc7a1d2a 185 oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
63c85238 186
43b40992 187 if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE))
883edfdd 188 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
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189
190 return 0;
191}
192
193/**
194 * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register
195 * @v: OCP_SYSCONFIG value to write
196 * @oh: struct omap_hwmod *
197 *
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198 * Write @v into the module class' OCP_SYSCONFIG register, if it has
199 * one. No return value.
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200 */
201static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
202{
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203 if (!oh->class->sysc) {
204 WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
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205 return;
206 }
207
208 /* XXX ensure module interface clock is up */
209
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210 /* Module might have lost context, always update cache and register */
211 oh->_sysc_cache = v;
212 omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
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213}
214
215/**
216 * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v
217 * @oh: struct omap_hwmod *
218 * @standbymode: MIDLEMODE field bits
219 * @v: pointer to register contents to modify
220 *
221 * Update the master standby mode bits in @v to be @standbymode for
222 * the @oh hwmod. Does not write to the hardware. Returns -EINVAL
223 * upon error or 0 upon success.
224 */
225static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode,
226 u32 *v)
227{
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228 u32 mstandby_mask;
229 u8 mstandby_shift;
230
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231 if (!oh->class->sysc ||
232 !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE))
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233 return -EINVAL;
234
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235 if (!oh->class->sysc->sysc_fields) {
236 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
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237 return -EINVAL;
238 }
239
43b40992 240 mstandby_shift = oh->class->sysc->sysc_fields->midle_shift;
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241 mstandby_mask = (0x3 << mstandby_shift);
242
243 *v &= ~mstandby_mask;
244 *v |= __ffs(standbymode) << mstandby_shift;
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245
246 return 0;
247}
248
249/**
250 * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v
251 * @oh: struct omap_hwmod *
252 * @idlemode: SIDLEMODE field bits
253 * @v: pointer to register contents to modify
254 *
255 * Update the slave idle mode bits in @v to be @idlemode for the @oh
256 * hwmod. Does not write to the hardware. Returns -EINVAL upon error
257 * or 0 upon success.
258 */
259static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v)
260{
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261 u32 sidle_mask;
262 u8 sidle_shift;
263
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264 if (!oh->class->sysc ||
265 !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE))
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266 return -EINVAL;
267
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268 if (!oh->class->sysc->sysc_fields) {
269 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
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270 return -EINVAL;
271 }
272
43b40992 273 sidle_shift = oh->class->sysc->sysc_fields->sidle_shift;
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274 sidle_mask = (0x3 << sidle_shift);
275
276 *v &= ~sidle_mask;
277 *v |= __ffs(idlemode) << sidle_shift;
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278
279 return 0;
280}
281
282/**
283 * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
284 * @oh: struct omap_hwmod *
285 * @clockact: CLOCKACTIVITY field bits
286 * @v: pointer to register contents to modify
287 *
288 * Update the clockactivity mode bits in @v to be @clockact for the
289 * @oh hwmod. Used for additional powersaving on some modules. Does
290 * not write to the hardware. Returns -EINVAL upon error or 0 upon
291 * success.
292 */
293static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v)
294{
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295 u32 clkact_mask;
296 u8 clkact_shift;
297
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298 if (!oh->class->sysc ||
299 !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
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300 return -EINVAL;
301
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302 if (!oh->class->sysc->sysc_fields) {
303 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
358f0e63
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304 return -EINVAL;
305 }
306
43b40992 307 clkact_shift = oh->class->sysc->sysc_fields->clkact_shift;
358f0e63
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308 clkact_mask = (0x3 << clkact_shift);
309
310 *v &= ~clkact_mask;
311 *v |= clockact << clkact_shift;
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312
313 return 0;
314}
315
316/**
317 * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
318 * @oh: struct omap_hwmod *
319 * @v: pointer to register contents to modify
320 *
321 * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon
322 * error or 0 upon success.
323 */
324static int _set_softreset(struct omap_hwmod *oh, u32 *v)
325{
358f0e63
TG
326 u32 softrst_mask;
327
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328 if (!oh->class->sysc ||
329 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
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330 return -EINVAL;
331
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332 if (!oh->class->sysc->sysc_fields) {
333 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
358f0e63
TG
334 return -EINVAL;
335 }
336
43b40992 337 softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
358f0e63
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338
339 *v |= softrst_mask;
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340
341 return 0;
342}
343
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344/**
345 * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
346 * @oh: struct omap_hwmod *
347 * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
348 * @v: pointer to register contents to modify
349 *
350 * Update the module autoidle bit in @v to be @autoidle for the @oh
351 * hwmod. The autoidle bit controls whether the module can gate
352 * internal clocks automatically when it isn't doing anything; the
353 * exact function of this bit varies on a per-module basis. This
354 * function does not write to the hardware. Returns -EINVAL upon
355 * error or 0 upon success.
356 */
357static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
358 u32 *v)
359{
358f0e63
TG
360 u32 autoidle_mask;
361 u8 autoidle_shift;
362
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363 if (!oh->class->sysc ||
364 !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE))
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365 return -EINVAL;
366
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367 if (!oh->class->sysc->sysc_fields) {
368 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
358f0e63
TG
369 return -EINVAL;
370 }
371
43b40992 372 autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift;
358f0e63
TG
373 autoidle_mask = (0x3 << autoidle_shift);
374
375 *v &= ~autoidle_mask;
376 *v |= autoidle << autoidle_shift;
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377
378 return 0;
379}
380
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381/**
382 * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
383 * @oh: struct omap_hwmod *
384 *
385 * Allow the hardware module @oh to send wakeups. Returns -EINVAL
386 * upon error or 0 upon success.
387 */
5a7ddcbd 388static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
63c85238 389{
5a7ddcbd 390 u32 wakeup_mask;
63c85238 391
43b40992 392 if (!oh->class->sysc ||
86009eb3
BC
393 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
394 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
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395 return -EINVAL;
396
43b40992
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397 if (!oh->class->sysc->sysc_fields) {
398 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
358f0e63
TG
399 return -EINVAL;
400 }
401
43b40992 402 wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
358f0e63 403
5a7ddcbd 404 *v |= wakeup_mask;
63c85238 405
86009eb3
BC
406 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
407 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
408
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409 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
410
411 oh->_int_flags |= _HWMOD_WAKEUP_ENABLED;
412
413 return 0;
414}
415
416/**
417 * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
418 * @oh: struct omap_hwmod *
419 *
420 * Prevent the hardware module @oh to send wakeups. Returns -EINVAL
421 * upon error or 0 upon success.
422 */
5a7ddcbd 423static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
63c85238 424{
5a7ddcbd 425 u32 wakeup_mask;
63c85238 426
43b40992 427 if (!oh->class->sysc ||
86009eb3
BC
428 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
429 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
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430 return -EINVAL;
431
43b40992
PW
432 if (!oh->class->sysc->sysc_fields) {
433 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
358f0e63
TG
434 return -EINVAL;
435 }
436
43b40992 437 wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
358f0e63 438
5a7ddcbd 439 *v &= ~wakeup_mask;
63c85238 440
86009eb3
BC
441 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
442 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
443
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444 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
445
446 oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED;
447
448 return 0;
449}
450
451/**
452 * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active
453 * @oh: struct omap_hwmod *
454 *
455 * Prevent the hardware module @oh from entering idle while the
456 * hardare module initiator @init_oh is active. Useful when a module
457 * will be accessed by a particular initiator (e.g., if a module will
458 * be accessed by the IVA, there should be a sleepdep between the IVA
459 * initiator and the module). Only applies to modules in smart-idle
460 * mode. Returns -EINVAL upon error or passes along
55ed9694 461 * clkdm_add_sleepdep() value upon success.
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462 */
463static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
464{
465 if (!oh->_clk)
466 return -EINVAL;
467
55ed9694 468 return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
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469}
470
471/**
472 * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active
473 * @oh: struct omap_hwmod *
474 *
475 * Allow the hardware module @oh to enter idle while the hardare
476 * module initiator @init_oh is active. Useful when a module will not
477 * be accessed by a particular initiator (e.g., if a module will not
478 * be accessed by the IVA, there should be no sleepdep between the IVA
479 * initiator and the module). Only applies to modules in smart-idle
480 * mode. Returns -EINVAL upon error or passes along
55ed9694 481 * clkdm_del_sleepdep() value upon success.
63c85238
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482 */
483static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
484{
485 if (!oh->_clk)
486 return -EINVAL;
487
55ed9694 488 return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
63c85238
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489}
490
491/**
492 * _init_main_clk - get a struct clk * for the the hwmod's main functional clk
493 * @oh: struct omap_hwmod *
494 *
495 * Called from _init_clocks(). Populates the @oh _clk (main
496 * functional clock pointer) if a main_clk is present. Returns 0 on
497 * success or -EINVAL on error.
498 */
499static int _init_main_clk(struct omap_hwmod *oh)
500{
63c85238
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501 int ret = 0;
502
50ebdac2 503 if (!oh->main_clk)
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504 return 0;
505
63403384 506 oh->_clk = omap_clk_get_by_name(oh->main_clk);
dc75925d 507 if (!oh->_clk) {
20383d82
BC
508 pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
509 oh->name, oh->main_clk);
63403384 510 return -EINVAL;
dc75925d 511 }
63c85238 512
63403384
BC
513 if (!oh->_clk->clkdm)
514 pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
515 oh->main_clk, oh->_clk->name);
81d7c6ff 516
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517 return ret;
518}
519
520/**
887adeac 521 * _init_interface_clks - get a struct clk * for the the hwmod's interface clks
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522 * @oh: struct omap_hwmod *
523 *
524 * Called from _init_clocks(). Populates the @oh OCP slave interface
525 * clock pointers. Returns 0 on success or -EINVAL on error.
526 */
527static int _init_interface_clks(struct omap_hwmod *oh)
528{
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529 struct clk *c;
530 int i;
531 int ret = 0;
532
533 if (oh->slaves_cnt == 0)
534 return 0;
535
682fdc96
BC
536 for (i = 0; i < oh->slaves_cnt; i++) {
537 struct omap_hwmod_ocp_if *os = oh->slaves[i];
538
50ebdac2 539 if (!os->clk)
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540 continue;
541
50ebdac2 542 c = omap_clk_get_by_name(os->clk);
dc75925d 543 if (!c) {
20383d82
BC
544 pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
545 oh->name, os->clk);
63c85238 546 ret = -EINVAL;
dc75925d 547 }
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548 os->_clk = c;
549 }
550
551 return ret;
552}
553
554/**
555 * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks
556 * @oh: struct omap_hwmod *
557 *
558 * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk
559 * clock pointers. Returns 0 on success or -EINVAL on error.
560 */
561static int _init_opt_clks(struct omap_hwmod *oh)
562{
563 struct omap_hwmod_opt_clk *oc;
564 struct clk *c;
565 int i;
566 int ret = 0;
567
568 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
50ebdac2 569 c = omap_clk_get_by_name(oc->clk);
dc75925d 570 if (!c) {
20383d82
BC
571 pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
572 oh->name, oc->clk);
63c85238 573 ret = -EINVAL;
dc75925d 574 }
63c85238
PW
575 oc->_clk = c;
576 }
577
578 return ret;
579}
580
581/**
582 * _enable_clocks - enable hwmod main clock and interface clocks
583 * @oh: struct omap_hwmod *
584 *
585 * Enables all clocks necessary for register reads and writes to succeed
586 * on the hwmod @oh. Returns 0.
587 */
588static int _enable_clocks(struct omap_hwmod *oh)
589{
63c85238
PW
590 int i;
591
592 pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
593
4d3ae5a9 594 if (oh->_clk)
63c85238
PW
595 clk_enable(oh->_clk);
596
597 if (oh->slaves_cnt > 0) {
682fdc96
BC
598 for (i = 0; i < oh->slaves_cnt; i++) {
599 struct omap_hwmod_ocp_if *os = oh->slaves[i];
63c85238
PW
600 struct clk *c = os->_clk;
601
4d3ae5a9 602 if (c && (os->flags & OCPIF_SWSUP_IDLE))
63c85238
PW
603 clk_enable(c);
604 }
605 }
606
607 /* The opt clocks are controlled by the device driver. */
608
609 return 0;
610}
611
612/**
613 * _disable_clocks - disable hwmod main clock and interface clocks
614 * @oh: struct omap_hwmod *
615 *
616 * Disables the hwmod @oh main functional and interface clocks. Returns 0.
617 */
618static int _disable_clocks(struct omap_hwmod *oh)
619{
63c85238
PW
620 int i;
621
622 pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
623
4d3ae5a9 624 if (oh->_clk)
63c85238
PW
625 clk_disable(oh->_clk);
626
627 if (oh->slaves_cnt > 0) {
682fdc96
BC
628 for (i = 0; i < oh->slaves_cnt; i++) {
629 struct omap_hwmod_ocp_if *os = oh->slaves[i];
63c85238
PW
630 struct clk *c = os->_clk;
631
4d3ae5a9 632 if (c && (os->flags & OCPIF_SWSUP_IDLE))
63c85238
PW
633 clk_disable(c);
634 }
635 }
636
637 /* The opt clocks are controlled by the device driver. */
638
639 return 0;
640}
641
96835af9
BC
642static void _enable_optional_clocks(struct omap_hwmod *oh)
643{
644 struct omap_hwmod_opt_clk *oc;
645 int i;
646
647 pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name);
648
649 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
650 if (oc->_clk) {
651 pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
652 oc->_clk->name);
653 clk_enable(oc->_clk);
654 }
655}
656
657static void _disable_optional_clocks(struct omap_hwmod *oh)
658{
659 struct omap_hwmod_opt_clk *oc;
660 int i;
661
662 pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name);
663
664 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
665 if (oc->_clk) {
666 pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
667 oc->_clk->name);
668 clk_disable(oc->_clk);
669 }
670}
671
63c85238
PW
672/**
673 * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
674 * @oh: struct omap_hwmod *
675 *
676 * Returns the array index of the OCP slave port that the MPU
677 * addresses the device on, or -EINVAL upon error or not found.
678 */
01592df9 679static int __init _find_mpu_port_index(struct omap_hwmod *oh)
63c85238 680{
63c85238
PW
681 int i;
682 int found = 0;
683
684 if (!oh || oh->slaves_cnt == 0)
685 return -EINVAL;
686
682fdc96
BC
687 for (i = 0; i < oh->slaves_cnt; i++) {
688 struct omap_hwmod_ocp_if *os = oh->slaves[i];
689
63c85238
PW
690 if (os->user & OCP_USER_MPU) {
691 found = 1;
692 break;
693 }
694 }
695
696 if (found)
697 pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n",
698 oh->name, i);
699 else
700 pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n",
701 oh->name);
702
703 return (found) ? i : -EINVAL;
704}
705
706/**
707 * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU
708 * @oh: struct omap_hwmod *
709 *
710 * Return the virtual address of the base of the register target of
711 * device @oh, or NULL on error.
712 */
01592df9 713static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
63c85238
PW
714{
715 struct omap_hwmod_ocp_if *os;
716 struct omap_hwmod_addr_space *mem;
717 int i;
718 int found = 0;
986a13f5 719 void __iomem *va_start;
63c85238
PW
720
721 if (!oh || oh->slaves_cnt == 0)
722 return NULL;
723
682fdc96 724 os = oh->slaves[index];
63c85238
PW
725
726 for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) {
727 if (mem->flags & ADDR_TYPE_RT) {
728 found = 1;
729 break;
730 }
731 }
732
986a13f5
TL
733 if (found) {
734 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
735 if (!va_start) {
736 pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
737 return NULL;
738 }
63c85238 739 pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
986a13f5
TL
740 oh->name, va_start);
741 } else {
63c85238
PW
742 pr_debug("omap_hwmod: %s: no MPU register target found\n",
743 oh->name);
986a13f5 744 }
63c85238 745
986a13f5 746 return (found) ? va_start : NULL;
63c85238
PW
747}
748
749/**
74ff3a68 750 * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
63c85238
PW
751 * @oh: struct omap_hwmod *
752 *
753 * If module is marked as SWSUP_SIDLE, force the module out of slave
754 * idle; otherwise, configure it for smart-idle. If module is marked
755 * as SWSUP_MSUSPEND, force the module out of master standby;
756 * otherwise, configure it for smart-standby. No return value.
757 */
74ff3a68 758static void _enable_sysc(struct omap_hwmod *oh)
63c85238 759{
43b40992 760 u8 idlemode, sf;
63c85238
PW
761 u32 v;
762
43b40992 763 if (!oh->class->sysc)
63c85238
PW
764 return;
765
766 v = oh->_sysc_cache;
43b40992 767 sf = oh->class->sysc->sysc_flags;
63c85238 768
43b40992 769 if (sf & SYSC_HAS_SIDLEMODE) {
63c85238
PW
770 idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
771 HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
772 _set_slave_idlemode(oh, idlemode, &v);
773 }
774
43b40992 775 if (sf & SYSC_HAS_MIDLEMODE) {
63c85238
PW
776 idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
777 HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
778 _set_master_standbymode(oh, idlemode, &v);
779 }
780
a16b1f7f
PW
781 /*
782 * XXX The clock framework should handle this, by
783 * calling into this code. But this must wait until the
784 * clock structures are tagged with omap_hwmod entries
785 */
43b40992
PW
786 if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) &&
787 (sf & SYSC_HAS_CLOCKACTIVITY))
788 _set_clockactivity(oh, oh->class->sysc->clockact, &v);
63c85238 789
9980ce53
RN
790 /* If slave is in SMARTIDLE, also enable wakeup */
791 if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
5a7ddcbd
KH
792 _enable_wakeup(oh, &v);
793
794 _write_sysconfig(v, oh);
78f26e87
HH
795
796 /*
797 * Set the autoidle bit only after setting the smartidle bit
798 * Setting this will not have any impact on the other modules.
799 */
800 if (sf & SYSC_HAS_AUTOIDLE) {
801 idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
802 0 : 1;
803 _set_module_autoidle(oh, idlemode, &v);
804 _write_sysconfig(v, oh);
805 }
63c85238
PW
806}
807
808/**
74ff3a68 809 * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG
63c85238
PW
810 * @oh: struct omap_hwmod *
811 *
812 * If module is marked as SWSUP_SIDLE, force the module into slave
813 * idle; otherwise, configure it for smart-idle. If module is marked
814 * as SWSUP_MSUSPEND, force the module into master standby; otherwise,
815 * configure it for smart-standby. No return value.
816 */
74ff3a68 817static void _idle_sysc(struct omap_hwmod *oh)
63c85238 818{
43b40992 819 u8 idlemode, sf;
63c85238
PW
820 u32 v;
821
43b40992 822 if (!oh->class->sysc)
63c85238
PW
823 return;
824
825 v = oh->_sysc_cache;
43b40992 826 sf = oh->class->sysc->sysc_flags;
63c85238 827
43b40992 828 if (sf & SYSC_HAS_SIDLEMODE) {
63c85238
PW
829 idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
830 HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
831 _set_slave_idlemode(oh, idlemode, &v);
832 }
833
43b40992 834 if (sf & SYSC_HAS_MIDLEMODE) {
63c85238
PW
835 idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
836 HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
837 _set_master_standbymode(oh, idlemode, &v);
838 }
839
86009eb3
BC
840 /* If slave is in SMARTIDLE, also enable wakeup */
841 if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
842 _enable_wakeup(oh, &v);
843
63c85238
PW
844 _write_sysconfig(v, oh);
845}
846
847/**
74ff3a68 848 * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG
63c85238
PW
849 * @oh: struct omap_hwmod *
850 *
851 * Force the module into slave idle and master suspend. No return
852 * value.
853 */
74ff3a68 854static void _shutdown_sysc(struct omap_hwmod *oh)
63c85238
PW
855{
856 u32 v;
43b40992 857 u8 sf;
63c85238 858
43b40992 859 if (!oh->class->sysc)
63c85238
PW
860 return;
861
862 v = oh->_sysc_cache;
43b40992 863 sf = oh->class->sysc->sysc_flags;
63c85238 864
43b40992 865 if (sf & SYSC_HAS_SIDLEMODE)
63c85238
PW
866 _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v);
867
43b40992 868 if (sf & SYSC_HAS_MIDLEMODE)
63c85238
PW
869 _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
870
43b40992 871 if (sf & SYSC_HAS_AUTOIDLE)
726072e5 872 _set_module_autoidle(oh, 1, &v);
63c85238
PW
873
874 _write_sysconfig(v, oh);
875}
876
877/**
878 * _lookup - find an omap_hwmod by name
879 * @name: find an omap_hwmod by name
880 *
881 * Return a pointer to an omap_hwmod by name, or NULL if not found.
63c85238
PW
882 */
883static struct omap_hwmod *_lookup(const char *name)
884{
885 struct omap_hwmod *oh, *temp_oh;
886
887 oh = NULL;
888
889 list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
890 if (!strcmp(name, temp_oh->name)) {
891 oh = temp_oh;
892 break;
893 }
894 }
895
896 return oh;
897}
898
899/**
900 * _init_clocks - clk_get() all clocks associated with this hwmod
901 * @oh: struct omap_hwmod *
97d60162 902 * @data: not used; pass NULL
63c85238
PW
903 *
904 * Called by omap_hwmod_late_init() (after omap2_clk_init()).
12b1fdb4
KH
905 * Resolves all clock names embedded in the hwmod. Returns -EINVAL if
906 * the omap_hwmod has not yet been registered or if the clocks have
907 * already been initialized, 0 on success, or a non-zero error on
908 * failure.
63c85238 909 */
97d60162 910static int _init_clocks(struct omap_hwmod *oh, void *data)
63c85238
PW
911{
912 int ret = 0;
913
914 if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED))
915 return -EINVAL;
916
917 pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
918
919 ret |= _init_main_clk(oh);
920 ret |= _init_interface_clks(oh);
921 ret |= _init_opt_clks(oh);
922
f5c1f84b
BC
923 if (!ret)
924 oh->_state = _HWMOD_STATE_CLKS_INITED;
63c85238 925
f5c1f84b 926 return 0;
63c85238
PW
927}
928
929/**
930 * _wait_target_ready - wait for a module to leave slave idle
931 * @oh: struct omap_hwmod *
932 *
933 * Wait for a module @oh to leave slave idle. Returns 0 if the module
934 * does not have an IDLEST bit or if the module successfully leaves
935 * slave idle; otherwise, pass along the return value of the
936 * appropriate *_cm_wait_module_ready() function.
937 */
938static int _wait_target_ready(struct omap_hwmod *oh)
939{
940 struct omap_hwmod_ocp_if *os;
941 int ret;
942
943 if (!oh)
944 return -EINVAL;
945
946 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
947 return 0;
948
682fdc96 949 os = oh->slaves[oh->_mpu_port_index];
63c85238 950
33f7ec81 951 if (oh->flags & HWMOD_NO_IDLEST)
63c85238
PW
952 return 0;
953
954 /* XXX check module SIDLEMODE */
955
956 /* XXX check clock enable states */
957
958 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
959 ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
960 oh->prcm.omap2.idlest_reg_id,
961 oh->prcm.omap2.idlest_idle_bit);
63c85238 962 } else if (cpu_is_omap44xx()) {
9a23dfe1 963 ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg);
63c85238
PW
964 } else {
965 BUG();
966 };
967
968 return ret;
969}
970
5365efbe
BC
971/**
972 * _lookup_hardreset - return the register bit shift for this hwmod/reset line
973 * @oh: struct omap_hwmod *
974 * @name: name of the reset line in the context of this hwmod
975 *
976 * Return the bit position of the reset line that match the
977 * input name. Return -ENOENT if not found.
978 */
979static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name)
980{
981 int i;
982
983 for (i = 0; i < oh->rst_lines_cnt; i++) {
984 const char *rst_line = oh->rst_lines[i].name;
985 if (!strcmp(rst_line, name)) {
986 u8 shift = oh->rst_lines[i].rst_shift;
987 pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n",
988 oh->name, rst_line, shift);
989
990 return shift;
991 }
992 }
993
994 return -ENOENT;
995}
996
997/**
998 * _assert_hardreset - assert the HW reset line of submodules
999 * contained in the hwmod module.
1000 * @oh: struct omap_hwmod *
1001 * @name: name of the reset line to lookup and assert
1002 *
1003 * Some IP like dsp, ipu or iva contain processor that require
1004 * an HW reset line to be assert / deassert in order to enable fully
1005 * the IP.
1006 */
1007static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
1008{
1009 u8 shift;
1010
1011 if (!oh)
1012 return -EINVAL;
1013
1014 shift = _lookup_hardreset(oh, name);
1015 if (IS_ERR_VALUE(shift))
1016 return shift;
1017
1018 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1019 return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
1020 shift);
1021 else if (cpu_is_omap44xx())
1022 return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg,
1023 shift);
1024 else
1025 return -EINVAL;
1026}
1027
1028/**
1029 * _deassert_hardreset - deassert the HW reset line of submodules contained
1030 * in the hwmod module.
1031 * @oh: struct omap_hwmod *
1032 * @name: name of the reset line to look up and deassert
1033 *
1034 * Some IP like dsp, ipu or iva contain processor that require
1035 * an HW reset line to be assert / deassert in order to enable fully
1036 * the IP.
1037 */
1038static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1039{
1040 u8 shift;
1041 int r;
1042
1043 if (!oh)
1044 return -EINVAL;
1045
1046 shift = _lookup_hardreset(oh, name);
1047 if (IS_ERR_VALUE(shift))
1048 return shift;
1049
1050 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1051 r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
1052 shift);
1053 else if (cpu_is_omap44xx())
1054 r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
1055 shift);
1056 else
1057 return -EINVAL;
1058
1059 if (r == -EBUSY)
1060 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
1061
1062 return r;
1063}
1064
1065/**
1066 * _read_hardreset - read the HW reset line state of submodules
1067 * contained in the hwmod module
1068 * @oh: struct omap_hwmod *
1069 * @name: name of the reset line to look up and read
1070 *
1071 * Return the state of the reset line.
1072 */
1073static int _read_hardreset(struct omap_hwmod *oh, const char *name)
1074{
1075 u8 shift;
1076
1077 if (!oh)
1078 return -EINVAL;
1079
1080 shift = _lookup_hardreset(oh, name);
1081 if (IS_ERR_VALUE(shift))
1082 return shift;
1083
1084 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1085 return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
1086 shift);
1087 } else if (cpu_is_omap44xx()) {
1088 return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg,
1089 shift);
1090 } else {
1091 return -EINVAL;
1092 }
1093}
1094
63c85238 1095/**
bd36179e 1096 * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
63c85238
PW
1097 * @oh: struct omap_hwmod *
1098 *
1099 * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be
12b1fdb4
KH
1100 * enabled for this to work. Returns -EINVAL if the hwmod cannot be
1101 * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
1102 * the module did not reset in time, or 0 upon success.
2cb06814
BC
1103 *
1104 * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
bd36179e 1105 * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
2cb06814
BC
1106 * use the SYSCONFIG softreset bit to provide the status.
1107 *
bd36179e
PW
1108 * Note that some IP like McBSP do have reset control but don't have
1109 * reset status.
63c85238 1110 */
bd36179e 1111static int _ocp_softreset(struct omap_hwmod *oh)
63c85238 1112{
96835af9 1113 u32 v;
6f8b7ff5 1114 int c = 0;
96835af9 1115 int ret = 0;
63c85238 1116
43b40992 1117 if (!oh->class->sysc ||
2cb06814 1118 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
63c85238
PW
1119 return -EINVAL;
1120
1121 /* clocks must be on for this operation */
1122 if (oh->_state != _HWMOD_STATE_ENABLED) {
76e5589e
BC
1123 pr_warning("omap_hwmod: %s: reset can only be entered from "
1124 "enabled state\n", oh->name);
63c85238
PW
1125 return -EINVAL;
1126 }
1127
96835af9
BC
1128 /* For some modules, all optionnal clocks need to be enabled as well */
1129 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1130 _enable_optional_clocks(oh);
1131
bd36179e 1132 pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name);
63c85238
PW
1133
1134 v = oh->_sysc_cache;
96835af9
BC
1135 ret = _set_softreset(oh, &v);
1136 if (ret)
1137 goto dis_opt_clks;
63c85238
PW
1138 _write_sysconfig(v, oh);
1139
2cb06814 1140 if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
cc7a1d2a 1141 omap_test_timeout((omap_hwmod_read(oh,
2cb06814
BC
1142 oh->class->sysc->syss_offs)
1143 & SYSS_RESETDONE_MASK),
1144 MAX_MODULE_SOFTRESET_WAIT, c);
1145 else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS)
cc7a1d2a 1146 omap_test_timeout(!(omap_hwmod_read(oh,
2cb06814
BC
1147 oh->class->sysc->sysc_offs)
1148 & SYSC_TYPE2_SOFTRESET_MASK),
1149 MAX_MODULE_SOFTRESET_WAIT, c);
63c85238 1150
5365efbe 1151 if (c == MAX_MODULE_SOFTRESET_WAIT)
76e5589e
BC
1152 pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
1153 oh->name, MAX_MODULE_SOFTRESET_WAIT);
63c85238 1154 else
5365efbe 1155 pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
63c85238
PW
1156
1157 /*
1158 * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
1159 * _wait_target_ready() or _reset()
1160 */
1161
96835af9
BC
1162 ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
1163
1164dis_opt_clks:
1165 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1166 _disable_optional_clocks(oh);
1167
1168 return ret;
63c85238
PW
1169}
1170
bd36179e
PW
1171/**
1172 * _reset - reset an omap_hwmod
1173 * @oh: struct omap_hwmod *
1174 *
1175 * Resets an omap_hwmod @oh. The default software reset mechanism for
1176 * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET
1177 * bit. However, some hwmods cannot be reset via this method: some
1178 * are not targets and therefore have no OCP header registers to
1179 * access; others (like the IVA) have idiosyncratic reset sequences.
1180 * So for these relatively rare cases, custom reset code can be
1181 * supplied in the struct omap_hwmod_class .reset function pointer.
1182 * Passes along the return value from either _reset() or the custom
1183 * reset function - these must return -EINVAL if the hwmod cannot be
1184 * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if
1185 * the module did not reset in time, or 0 upon success.
1186 */
1187static int _reset(struct omap_hwmod *oh)
1188{
1189 int ret;
1190
1191 pr_debug("omap_hwmod: %s: resetting\n", oh->name);
1192
1193 ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh);
1194
1195 return ret;
1196}
1197
63c85238 1198/**
dc6d1cda 1199 * _enable - enable an omap_hwmod
63c85238
PW
1200 * @oh: struct omap_hwmod *
1201 *
1202 * Enables an omap_hwmod @oh such that the MPU can access the hwmod's
dc6d1cda
PW
1203 * register target. Returns -EINVAL if the hwmod is in the wrong
1204 * state or passes along the return value of _wait_target_ready().
63c85238 1205 */
dc6d1cda 1206static int _enable(struct omap_hwmod *oh)
63c85238
PW
1207{
1208 int r;
1209
1210 if (oh->_state != _HWMOD_STATE_INITIALIZED &&
1211 oh->_state != _HWMOD_STATE_IDLE &&
1212 oh->_state != _HWMOD_STATE_DISABLED) {
1213 WARN(1, "omap_hwmod: %s: enabled state can only be entered "
1214 "from initialized, idle, or disabled state\n", oh->name);
1215 return -EINVAL;
1216 }
1217
1218 pr_debug("omap_hwmod: %s: enabling\n", oh->name);
1219
5365efbe
BC
1220 /*
1221 * If an IP contains only one HW reset line, then de-assert it in order
1222 * to allow to enable the clocks. Otherwise the PRCM will return
1223 * Intransition status, and the init will failed.
1224 */
1225 if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
1226 oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1)
1227 _deassert_hardreset(oh, oh->rst_lines[0].name);
1228
8d9af88f
TL
1229 /* Mux pins for device runtime if populated */
1230 if (oh->mux)
1231 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
63c85238
PW
1232
1233 _add_initiator_dep(oh, mpu_oh);
1234 _enable_clocks(oh);
1235
63c85238 1236 r = _wait_target_ready(oh);
9a23dfe1 1237 if (!r) {
63c85238
PW
1238 oh->_state = _HWMOD_STATE_ENABLED;
1239
9a23dfe1
BC
1240 /* Access the sysconfig only if the target is ready */
1241 if (oh->class->sysc) {
1242 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
1243 _update_sysc_cache(oh);
74ff3a68 1244 _enable_sysc(oh);
9a23dfe1
BC
1245 }
1246 } else {
f2dd7e09 1247 _disable_clocks(oh);
9a23dfe1
BC
1248 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
1249 oh->name, r);
1250 }
1251
63c85238
PW
1252 return r;
1253}
1254
1255/**
dc6d1cda 1256 * _idle - idle an omap_hwmod
63c85238
PW
1257 * @oh: struct omap_hwmod *
1258 *
1259 * Idles an omap_hwmod @oh. This should be called once the hwmod has
dc6d1cda
PW
1260 * no further work. Returns -EINVAL if the hwmod is in the wrong
1261 * state or returns 0.
63c85238 1262 */
dc6d1cda 1263static int _idle(struct omap_hwmod *oh)
63c85238
PW
1264{
1265 if (oh->_state != _HWMOD_STATE_ENABLED) {
1266 WARN(1, "omap_hwmod: %s: idle state can only be entered from "
1267 "enabled state\n", oh->name);
1268 return -EINVAL;
1269 }
1270
1271 pr_debug("omap_hwmod: %s: idling\n", oh->name);
1272
43b40992 1273 if (oh->class->sysc)
74ff3a68 1274 _idle_sysc(oh);
63c85238
PW
1275 _del_initiator_dep(oh, mpu_oh);
1276 _disable_clocks(oh);
1277
8d9af88f
TL
1278 /* Mux pins for device idle if populated */
1279 if (oh->mux)
1280 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
1281
63c85238
PW
1282 oh->_state = _HWMOD_STATE_IDLE;
1283
1284 return 0;
1285}
1286
1287/**
1288 * _shutdown - shutdown an omap_hwmod
1289 * @oh: struct omap_hwmod *
1290 *
1291 * Shut down an omap_hwmod @oh. This should be called when the driver
1292 * used for the hwmod is removed or unloaded or if the driver is not
1293 * used by the system. Returns -EINVAL if the hwmod is in the wrong
1294 * state or returns 0.
1295 */
1296static int _shutdown(struct omap_hwmod *oh)
1297{
e4dc8f50
PW
1298 int ret;
1299 u8 prev_state;
1300
63c85238
PW
1301 if (oh->_state != _HWMOD_STATE_IDLE &&
1302 oh->_state != _HWMOD_STATE_ENABLED) {
1303 WARN(1, "omap_hwmod: %s: disabled state can only be entered "
1304 "from idle, or enabled state\n", oh->name);
1305 return -EINVAL;
1306 }
1307
1308 pr_debug("omap_hwmod: %s: disabling\n", oh->name);
1309
e4dc8f50
PW
1310 if (oh->class->pre_shutdown) {
1311 prev_state = oh->_state;
1312 if (oh->_state == _HWMOD_STATE_IDLE)
dc6d1cda 1313 _enable(oh);
e4dc8f50
PW
1314 ret = oh->class->pre_shutdown(oh);
1315 if (ret) {
1316 if (prev_state == _HWMOD_STATE_IDLE)
dc6d1cda 1317 _idle(oh);
e4dc8f50
PW
1318 return ret;
1319 }
1320 }
1321
43b40992 1322 if (oh->class->sysc)
74ff3a68 1323 _shutdown_sysc(oh);
3827f949 1324
5365efbe
BC
1325 /*
1326 * If an IP contains only one HW reset line, then assert it
1327 * before disabling the clocks and shutting down the IP.
1328 */
1329 if (oh->rst_lines_cnt == 1)
1330 _assert_hardreset(oh, oh->rst_lines[0].name);
1331
3827f949
BC
1332 /* clocks and deps are already disabled in idle */
1333 if (oh->_state == _HWMOD_STATE_ENABLED) {
1334 _del_initiator_dep(oh, mpu_oh);
1335 /* XXX what about the other system initiators here? dma, dsp */
1336 _disable_clocks(oh);
1337 }
63c85238
PW
1338 /* XXX Should this code also force-disable the optional clocks? */
1339
8d9af88f
TL
1340 /* Mux pins to safe mode or use populated off mode values */
1341 if (oh->mux)
1342 omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
63c85238
PW
1343
1344 oh->_state = _HWMOD_STATE_DISABLED;
1345
1346 return 0;
1347}
1348
63c85238
PW
1349/**
1350 * _setup - do initial configuration of omap_hwmod
1351 * @oh: struct omap_hwmod *
1352 *
1353 * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
2092e5cc
PW
1354 * OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the
1355 * wrong state or returns 0.
63c85238 1356 */
97d60162 1357static int _setup(struct omap_hwmod *oh, void *data)
63c85238 1358{
9a23dfe1 1359 int i, r;
2092e5cc 1360 u8 postsetup_state;
97d60162 1361
63c85238
PW
1362 /* Set iclk autoidle mode */
1363 if (oh->slaves_cnt > 0) {
682fdc96
BC
1364 for (i = 0; i < oh->slaves_cnt; i++) {
1365 struct omap_hwmod_ocp_if *os = oh->slaves[i];
63c85238
PW
1366 struct clk *c = os->_clk;
1367
4d3ae5a9 1368 if (!c)
63c85238
PW
1369 continue;
1370
1371 if (os->flags & OCPIF_SWSUP_IDLE) {
1372 /* XXX omap_iclk_deny_idle(c); */
1373 } else {
1374 /* XXX omap_iclk_allow_idle(c); */
1375 clk_enable(c);
1376 }
1377 }
1378 }
1379
1380 oh->_state = _HWMOD_STATE_INITIALIZED;
1381
5365efbe
BC
1382 /*
1383 * In the case of hwmod with hardreset that should not be
1384 * de-assert at boot time, we have to keep the module
1385 * initialized, because we cannot enable it properly with the
1386 * reset asserted. Exit without warning because that behavior is
1387 * expected.
1388 */
1389 if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1)
1390 return 0;
1391
dc6d1cda 1392 r = _enable(oh);
9a23dfe1
BC
1393 if (r) {
1394 pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
1395 oh->name, oh->_state);
1396 return 0;
1397 }
63c85238 1398
b835d014 1399 if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
76e5589e
BC
1400 _reset(oh);
1401
b835d014 1402 /*
76e5589e 1403 * OCP_SYSCONFIG bits need to be reprogrammed after a softreset.
dc6d1cda 1404 * The _enable() function should be split to
76e5589e 1405 * avoid the rewrite of the OCP_SYSCONFIG register.
b835d014 1406 */
43b40992 1407 if (oh->class->sysc) {
b835d014 1408 _update_sysc_cache(oh);
74ff3a68 1409 _enable_sysc(oh);
b835d014
PW
1410 }
1411 }
63c85238 1412
2092e5cc
PW
1413 postsetup_state = oh->_postsetup_state;
1414 if (postsetup_state == _HWMOD_STATE_UNKNOWN)
1415 postsetup_state = _HWMOD_STATE_ENABLED;
1416
1417 /*
1418 * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data -
1419 * it should be set by the core code as a runtime flag during startup
1420 */
1421 if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
1422 (postsetup_state == _HWMOD_STATE_IDLE))
1423 postsetup_state = _HWMOD_STATE_ENABLED;
1424
1425 if (postsetup_state == _HWMOD_STATE_IDLE)
dc6d1cda 1426 _idle(oh);
2092e5cc
PW
1427 else if (postsetup_state == _HWMOD_STATE_DISABLED)
1428 _shutdown(oh);
1429 else if (postsetup_state != _HWMOD_STATE_ENABLED)
1430 WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
1431 oh->name, postsetup_state);
63c85238
PW
1432
1433 return 0;
1434}
1435
63c85238 1436/**
0102b627 1437 * _register - register a struct omap_hwmod
63c85238
PW
1438 * @oh: struct omap_hwmod *
1439 *
43b40992
PW
1440 * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod
1441 * already has been registered by the same name; -EINVAL if the
1442 * omap_hwmod is in the wrong state, if @oh is NULL, if the
1443 * omap_hwmod's class field is NULL; if the omap_hwmod is missing a
1444 * name, or if the omap_hwmod's class is missing a name; or 0 upon
1445 * success.
63c85238
PW
1446 *
1447 * XXX The data should be copied into bootmem, so the original data
1448 * should be marked __initdata and freed after init. This would allow
1449 * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note
1450 * that the copy process would be relatively complex due to the large number
1451 * of substructures.
1452 */
01592df9 1453static int __init _register(struct omap_hwmod *oh)
63c85238
PW
1454{
1455 int ret, ms_id;
1456
43b40992
PW
1457 if (!oh || !oh->name || !oh->class || !oh->class->name ||
1458 (oh->_state != _HWMOD_STATE_UNKNOWN))
63c85238
PW
1459 return -EINVAL;
1460
63c85238
PW
1461 pr_debug("omap_hwmod: %s: registering\n", oh->name);
1462
ce35b244
BC
1463 if (_lookup(oh->name))
1464 return -EEXIST;
63c85238
PW
1465
1466 ms_id = _find_mpu_port_index(oh);
e7c7d760 1467 if (!IS_ERR_VALUE(ms_id))
63c85238 1468 oh->_mpu_port_index = ms_id;
e7c7d760 1469 else
63c85238 1470 oh->_int_flags |= _HWMOD_NO_MPU_PORT;
63c85238
PW
1471
1472 list_add_tail(&oh->node, &omap_hwmod_list);
1473
dc6d1cda 1474 spin_lock_init(&oh->_lock);
2092e5cc 1475
63c85238
PW
1476 oh->_state = _HWMOD_STATE_REGISTERED;
1477
1478 ret = 0;
1479
63c85238
PW
1480 return ret;
1481}
1482
0102b627
BC
1483
1484/* Public functions */
1485
1486u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
1487{
1488 if (oh->flags & HWMOD_16BIT_REG)
1489 return __raw_readw(oh->_mpu_rt_va + reg_offs);
1490 else
1491 return __raw_readl(oh->_mpu_rt_va + reg_offs);
1492}
1493
1494void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
1495{
1496 if (oh->flags & HWMOD_16BIT_REG)
1497 __raw_writew(v, oh->_mpu_rt_va + reg_offs);
1498 else
1499 __raw_writel(v, oh->_mpu_rt_va + reg_offs);
1500}
1501
1502/**
1503 * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
1504 * @oh: struct omap_hwmod *
1505 * @idlemode: SIDLEMODE field bits (shifted to bit 0)
1506 *
1507 * Sets the IP block's OCP slave idlemode in hardware, and updates our
1508 * local copy. Intended to be used by drivers that have some erratum
1509 * that requires direct manipulation of the SIDLEMODE bits. Returns
1510 * -EINVAL if @oh is null, or passes along the return value from
1511 * _set_slave_idlemode().
1512 *
1513 * XXX Does this function have any current users? If not, we should
1514 * remove it; it is better to let the rest of the hwmod code handle this.
1515 * Any users of this function should be scrutinized carefully.
1516 */
1517int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode)
1518{
1519 u32 v;
1520 int retval = 0;
1521
1522 if (!oh)
1523 return -EINVAL;
1524
1525 v = oh->_sysc_cache;
1526
1527 retval = _set_slave_idlemode(oh, idlemode, &v);
1528 if (!retval)
1529 _write_sysconfig(v, oh);
1530
1531 return retval;
1532}
1533
63c85238
PW
1534/**
1535 * omap_hwmod_lookup - look up a registered omap_hwmod by name
1536 * @name: name of the omap_hwmod to look up
1537 *
1538 * Given a @name of an omap_hwmod, return a pointer to the registered
1539 * struct omap_hwmod *, or NULL upon error.
1540 */
1541struct omap_hwmod *omap_hwmod_lookup(const char *name)
1542{
1543 struct omap_hwmod *oh;
1544
1545 if (!name)
1546 return NULL;
1547
63c85238 1548 oh = _lookup(name);
63c85238
PW
1549
1550 return oh;
1551}
1552
1553/**
1554 * omap_hwmod_for_each - call function for each registered omap_hwmod
1555 * @fn: pointer to a callback function
97d60162 1556 * @data: void * data to pass to callback function
63c85238
PW
1557 *
1558 * Call @fn for each registered omap_hwmod, passing @data to each
1559 * function. @fn must return 0 for success or any other value for
1560 * failure. If @fn returns non-zero, the iteration across omap_hwmods
1561 * will stop and the non-zero return value will be passed to the
1562 * caller of omap_hwmod_for_each(). @fn is called with
1563 * omap_hwmod_for_each() held.
1564 */
97d60162
PW
1565int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
1566 void *data)
63c85238
PW
1567{
1568 struct omap_hwmod *temp_oh;
1569 int ret;
1570
1571 if (!fn)
1572 return -EINVAL;
1573
63c85238 1574 list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
97d60162 1575 ret = (*fn)(temp_oh, data);
63c85238
PW
1576 if (ret)
1577 break;
1578 }
63c85238
PW
1579
1580 return ret;
1581}
1582
1583
1584/**
1585 * omap_hwmod_init - init omap_hwmod code and register hwmods
1586 * @ohs: pointer to an array of omap_hwmods to register
1587 *
1588 * Intended to be called early in boot before the clock framework is
1589 * initialized. If @ohs is not null, will register all omap_hwmods
1590 * listed in @ohs that are valid for this chip. Returns -EINVAL if
1591 * omap_hwmod_init() has already been called or 0 otherwise.
1592 */
01592df9 1593int __init omap_hwmod_init(struct omap_hwmod **ohs)
63c85238 1594{
bac1a0f0 1595 int r, i;
63c85238
PW
1596
1597 if (!ohs)
1598 return 0;
1599
bac1a0f0
PW
1600 i = 0;
1601 do {
1602 if (!omap_chip_is(ohs[i]->omap_chip))
1603 continue;
1604
1605 r = _register(ohs[i]);
1606 WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
1607 r);
1608 } while (ohs[++i]);
63c85238
PW
1609
1610 return 0;
1611}
1612
e7c7d760
TL
1613/*
1614 * _populate_mpu_rt_base - populate the virtual address for a hwmod
1615 *
1616 * Must be called only from omap_hwmod_late_init so ioremap works properly.
1617 * Assumes the caller takes care of locking if needed.
1618 *
1619 */
1620static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
1621{
1622 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
1623 return 0;
1624
1625 oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
1626 if (!oh->_mpu_rt_va)
1627 pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n",
1628 __func__, oh->name);
1629
1630 return 0;
1631}
1632
63c85238
PW
1633/**
1634 * omap_hwmod_late_init - do some post-clock framework initialization
1635 *
1636 * Must be called after omap2_clk_init(). Resolves the struct clk names
1637 * to struct clk pointers for each registered omap_hwmod. Also calls
1638 * _setup() on each hwmod. Returns 0.
1639 */
44dc046e 1640static int __init omap_hwmod_late_init(void)
63c85238
PW
1641{
1642 int r;
1643
e7c7d760
TL
1644 r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
1645
63c85238 1646 /* XXX check return value */
97d60162 1647 r = omap_hwmod_for_each(_init_clocks, NULL);
63c85238
PW
1648 WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n");
1649
1650 mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME);
1651 WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n",
1652 MPU_INITIATOR_NAME);
1653
2092e5cc 1654 omap_hwmod_for_each(_setup, NULL);
63c85238
PW
1655
1656 return 0;
1657}
44dc046e 1658core_initcall(omap_hwmod_late_init);
63c85238 1659
63c85238
PW
1660/**
1661 * omap_hwmod_enable - enable an omap_hwmod
1662 * @oh: struct omap_hwmod *
1663 *
74ff3a68 1664 * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable().
63c85238
PW
1665 * Returns -EINVAL on error or passes along the return value from _enable().
1666 */
1667int omap_hwmod_enable(struct omap_hwmod *oh)
1668{
1669 int r;
dc6d1cda 1670 unsigned long flags;
63c85238
PW
1671
1672 if (!oh)
1673 return -EINVAL;
1674
dc6d1cda
PW
1675 spin_lock_irqsave(&oh->_lock, flags);
1676 r = _enable(oh);
1677 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
1678
1679 return r;
1680}
1681
1682/**
1683 * omap_hwmod_idle - idle an omap_hwmod
1684 * @oh: struct omap_hwmod *
1685 *
74ff3a68 1686 * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle().
63c85238
PW
1687 * Returns -EINVAL on error or passes along the return value from _idle().
1688 */
1689int omap_hwmod_idle(struct omap_hwmod *oh)
1690{
dc6d1cda
PW
1691 unsigned long flags;
1692
63c85238
PW
1693 if (!oh)
1694 return -EINVAL;
1695
dc6d1cda
PW
1696 spin_lock_irqsave(&oh->_lock, flags);
1697 _idle(oh);
1698 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
1699
1700 return 0;
1701}
1702
1703/**
1704 * omap_hwmod_shutdown - shutdown an omap_hwmod
1705 * @oh: struct omap_hwmod *
1706 *
74ff3a68 1707 * Shutdown an omap_hwmod @oh. Intended to be called by
63c85238
PW
1708 * omap_device_shutdown(). Returns -EINVAL on error or passes along
1709 * the return value from _shutdown().
1710 */
1711int omap_hwmod_shutdown(struct omap_hwmod *oh)
1712{
dc6d1cda
PW
1713 unsigned long flags;
1714
63c85238
PW
1715 if (!oh)
1716 return -EINVAL;
1717
dc6d1cda 1718 spin_lock_irqsave(&oh->_lock, flags);
63c85238 1719 _shutdown(oh);
dc6d1cda 1720 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
1721
1722 return 0;
1723}
1724
1725/**
1726 * omap_hwmod_enable_clocks - enable main_clk, all interface clocks
1727 * @oh: struct omap_hwmod *oh
1728 *
1729 * Intended to be called by the omap_device code.
1730 */
1731int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
1732{
dc6d1cda
PW
1733 unsigned long flags;
1734
1735 spin_lock_irqsave(&oh->_lock, flags);
63c85238 1736 _enable_clocks(oh);
dc6d1cda 1737 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
1738
1739 return 0;
1740}
1741
1742/**
1743 * omap_hwmod_disable_clocks - disable main_clk, all interface clocks
1744 * @oh: struct omap_hwmod *oh
1745 *
1746 * Intended to be called by the omap_device code.
1747 */
1748int omap_hwmod_disable_clocks(struct omap_hwmod *oh)
1749{
dc6d1cda
PW
1750 unsigned long flags;
1751
1752 spin_lock_irqsave(&oh->_lock, flags);
63c85238 1753 _disable_clocks(oh);
dc6d1cda 1754 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
1755
1756 return 0;
1757}
1758
1759/**
1760 * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete
1761 * @oh: struct omap_hwmod *oh
1762 *
1763 * Intended to be called by drivers and core code when all posted
1764 * writes to a device must complete before continuing further
1765 * execution (for example, after clearing some device IRQSTATUS
1766 * register bits)
1767 *
1768 * XXX what about targets with multiple OCP threads?
1769 */
1770void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
1771{
1772 BUG_ON(!oh);
1773
43b40992 1774 if (!oh->class->sysc || !oh->class->sysc->sysc_flags) {
63c85238
PW
1775 WARN(1, "omap_device: %s: OCP barrier impossible due to "
1776 "device configuration\n", oh->name);
1777 return;
1778 }
1779
1780 /*
1781 * Forces posted writes to complete on the OCP thread handling
1782 * register writes
1783 */
cc7a1d2a 1784 omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
63c85238
PW
1785}
1786
1787/**
1788 * omap_hwmod_reset - reset the hwmod
1789 * @oh: struct omap_hwmod *
1790 *
1791 * Under some conditions, a driver may wish to reset the entire device.
1792 * Called from omap_device code. Returns -EINVAL on error or passes along
9b579114 1793 * the return value from _reset().
63c85238
PW
1794 */
1795int omap_hwmod_reset(struct omap_hwmod *oh)
1796{
1797 int r;
dc6d1cda 1798 unsigned long flags;
63c85238 1799
9b579114 1800 if (!oh)
63c85238
PW
1801 return -EINVAL;
1802
dc6d1cda 1803 spin_lock_irqsave(&oh->_lock, flags);
63c85238 1804 r = _reset(oh);
dc6d1cda 1805 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
1806
1807 return r;
1808}
1809
1810/**
1811 * omap_hwmod_count_resources - count number of struct resources needed by hwmod
1812 * @oh: struct omap_hwmod *
1813 * @res: pointer to the first element of an array of struct resource to fill
1814 *
1815 * Count the number of struct resource array elements necessary to
1816 * contain omap_hwmod @oh resources. Intended to be called by code
1817 * that registers omap_devices. Intended to be used to determine the
1818 * size of a dynamically-allocated struct resource array, before
1819 * calling omap_hwmod_fill_resources(). Returns the number of struct
1820 * resource array elements needed.
1821 *
1822 * XXX This code is not optimized. It could attempt to merge adjacent
1823 * resource IDs.
1824 *
1825 */
1826int omap_hwmod_count_resources(struct omap_hwmod *oh)
1827{
1828 int ret, i;
1829
9ee9fff9 1830 ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt;
63c85238
PW
1831
1832 for (i = 0; i < oh->slaves_cnt; i++)
682fdc96 1833 ret += oh->slaves[i]->addr_cnt;
63c85238
PW
1834
1835 return ret;
1836}
1837
1838/**
1839 * omap_hwmod_fill_resources - fill struct resource array with hwmod data
1840 * @oh: struct omap_hwmod *
1841 * @res: pointer to the first element of an array of struct resource to fill
1842 *
1843 * Fill the struct resource array @res with resource data from the
1844 * omap_hwmod @oh. Intended to be called by code that registers
1845 * omap_devices. See also omap_hwmod_count_resources(). Returns the
1846 * number of array elements filled.
1847 */
1848int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
1849{
1850 int i, j;
1851 int r = 0;
1852
1853 /* For each IRQ, DMA, memory area, fill in array.*/
1854
1855 for (i = 0; i < oh->mpu_irqs_cnt; i++) {
718bfd76
PW
1856 (res + r)->name = (oh->mpu_irqs + i)->name;
1857 (res + r)->start = (oh->mpu_irqs + i)->irq;
1858 (res + r)->end = (oh->mpu_irqs + i)->irq;
63c85238
PW
1859 (res + r)->flags = IORESOURCE_IRQ;
1860 r++;
1861 }
1862
9ee9fff9
BC
1863 for (i = 0; i < oh->sdma_reqs_cnt; i++) {
1864 (res + r)->name = (oh->sdma_reqs + i)->name;
1865 (res + r)->start = (oh->sdma_reqs + i)->dma_req;
1866 (res + r)->end = (oh->sdma_reqs + i)->dma_req;
63c85238
PW
1867 (res + r)->flags = IORESOURCE_DMA;
1868 r++;
1869 }
1870
1871 for (i = 0; i < oh->slaves_cnt; i++) {
1872 struct omap_hwmod_ocp_if *os;
1873
682fdc96 1874 os = oh->slaves[i];
63c85238
PW
1875
1876 for (j = 0; j < os->addr_cnt; j++) {
1877 (res + r)->start = (os->addr + j)->pa_start;
1878 (res + r)->end = (os->addr + j)->pa_end;
1879 (res + r)->flags = IORESOURCE_MEM;
1880 r++;
1881 }
1882 }
1883
1884 return r;
1885}
1886
1887/**
1888 * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
1889 * @oh: struct omap_hwmod *
1890 *
1891 * Return the powerdomain pointer associated with the OMAP module
1892 * @oh's main clock. If @oh does not have a main clk, return the
1893 * powerdomain associated with the interface clock associated with the
1894 * module's MPU port. (XXX Perhaps this should use the SDMA port
1895 * instead?) Returns NULL on error, or a struct powerdomain * on
1896 * success.
1897 */
1898struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
1899{
1900 struct clk *c;
1901
1902 if (!oh)
1903 return NULL;
1904
1905 if (oh->_clk) {
1906 c = oh->_clk;
1907 } else {
1908 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
1909 return NULL;
1910 c = oh->slaves[oh->_mpu_port_index]->_clk;
1911 }
1912
d5647c18
TG
1913 if (!c->clkdm)
1914 return NULL;
1915
63c85238
PW
1916 return c->clkdm->pwrdm.ptr;
1917
1918}
1919
db2a60bf
PW
1920/**
1921 * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU)
1922 * @oh: struct omap_hwmod *
1923 *
1924 * Returns the virtual address corresponding to the beginning of the
1925 * module's register target, in the address range that is intended to
1926 * be used by the MPU. Returns the virtual address upon success or NULL
1927 * upon error.
1928 */
1929void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh)
1930{
1931 if (!oh)
1932 return NULL;
1933
1934 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
1935 return NULL;
1936
1937 if (oh->_state == _HWMOD_STATE_UNKNOWN)
1938 return NULL;
1939
1940 return oh->_mpu_rt_va;
1941}
1942
63c85238
PW
1943/**
1944 * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh
1945 * @oh: struct omap_hwmod *
1946 * @init_oh: struct omap_hwmod * (initiator)
1947 *
1948 * Add a sleep dependency between the initiator @init_oh and @oh.
1949 * Intended to be called by DSP/Bridge code via platform_data for the
1950 * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge
1951 * code needs to add/del initiator dependencies dynamically
1952 * before/after accessing a device. Returns the return value from
1953 * _add_initiator_dep().
1954 *
1955 * XXX Keep a usecount in the clockdomain code
1956 */
1957int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
1958 struct omap_hwmod *init_oh)
1959{
1960 return _add_initiator_dep(oh, init_oh);
1961}
1962
1963/*
1964 * XXX what about functions for drivers to save/restore ocp_sysconfig
1965 * for context save/restore operations?
1966 */
1967
1968/**
1969 * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh
1970 * @oh: struct omap_hwmod *
1971 * @init_oh: struct omap_hwmod * (initiator)
1972 *
1973 * Remove a sleep dependency between the initiator @init_oh and @oh.
1974 * Intended to be called by DSP/Bridge code via platform_data for the
1975 * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge
1976 * code needs to add/del initiator dependencies dynamically
1977 * before/after accessing a device. Returns the return value from
1978 * _del_initiator_dep().
1979 *
1980 * XXX Keep a usecount in the clockdomain code
1981 */
1982int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
1983 struct omap_hwmod *init_oh)
1984{
1985 return _del_initiator_dep(oh, init_oh);
1986}
1987
63c85238
PW
1988/**
1989 * omap_hwmod_enable_wakeup - allow device to wake up the system
1990 * @oh: struct omap_hwmod *
1991 *
1992 * Sets the module OCP socket ENAWAKEUP bit to allow the module to
1993 * send wakeups to the PRCM. Eventually this should sets PRCM wakeup
1994 * registers to cause the PRCM to receive wakeup events from the
1995 * module. Does not set any wakeup routing registers beyond this
1996 * point - if the module is to wake up any other module or subsystem,
1997 * that must be set separately. Called by omap_device code. Returns
1998 * -EINVAL on error or 0 upon success.
1999 */
2000int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
2001{
dc6d1cda 2002 unsigned long flags;
5a7ddcbd 2003 u32 v;
dc6d1cda 2004
43b40992
PW
2005 if (!oh->class->sysc ||
2006 !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
63c85238
PW
2007 return -EINVAL;
2008
dc6d1cda 2009 spin_lock_irqsave(&oh->_lock, flags);
5a7ddcbd
KH
2010 v = oh->_sysc_cache;
2011 _enable_wakeup(oh, &v);
2012 _write_sysconfig(v, oh);
dc6d1cda 2013 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
2014
2015 return 0;
2016}
2017
2018/**
2019 * omap_hwmod_disable_wakeup - prevent device from waking the system
2020 * @oh: struct omap_hwmod *
2021 *
2022 * Clears the module OCP socket ENAWAKEUP bit to prevent the module
2023 * from sending wakeups to the PRCM. Eventually this should clear
2024 * PRCM wakeup registers to cause the PRCM to ignore wakeup events
2025 * from the module. Does not set any wakeup routing registers beyond
2026 * this point - if the module is to wake up any other module or
2027 * subsystem, that must be set separately. Called by omap_device
2028 * code. Returns -EINVAL on error or 0 upon success.
2029 */
2030int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
2031{
dc6d1cda 2032 unsigned long flags;
5a7ddcbd 2033 u32 v;
dc6d1cda 2034
43b40992
PW
2035 if (!oh->class->sysc ||
2036 !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP))
63c85238
PW
2037 return -EINVAL;
2038
dc6d1cda 2039 spin_lock_irqsave(&oh->_lock, flags);
5a7ddcbd
KH
2040 v = oh->_sysc_cache;
2041 _disable_wakeup(oh, &v);
2042 _write_sysconfig(v, oh);
dc6d1cda 2043 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
2044
2045 return 0;
2046}
43b40992 2047
aee48e3c
PW
2048/**
2049 * omap_hwmod_assert_hardreset - assert the HW reset line of submodules
2050 * contained in the hwmod module.
2051 * @oh: struct omap_hwmod *
2052 * @name: name of the reset line to lookup and assert
2053 *
2054 * Some IP like dsp, ipu or iva contain processor that require
2055 * an HW reset line to be assert / deassert in order to enable fully
2056 * the IP. Returns -EINVAL if @oh is null or if the operation is not
2057 * yet supported on this OMAP; otherwise, passes along the return value
2058 * from _assert_hardreset().
2059 */
2060int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
2061{
2062 int ret;
dc6d1cda 2063 unsigned long flags;
aee48e3c
PW
2064
2065 if (!oh)
2066 return -EINVAL;
2067
dc6d1cda 2068 spin_lock_irqsave(&oh->_lock, flags);
aee48e3c 2069 ret = _assert_hardreset(oh, name);
dc6d1cda 2070 spin_unlock_irqrestore(&oh->_lock, flags);
aee48e3c
PW
2071
2072 return ret;
2073}
2074
2075/**
2076 * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules
2077 * contained in the hwmod module.
2078 * @oh: struct omap_hwmod *
2079 * @name: name of the reset line to look up and deassert
2080 *
2081 * Some IP like dsp, ipu or iva contain processor that require
2082 * an HW reset line to be assert / deassert in order to enable fully
2083 * the IP. Returns -EINVAL if @oh is null or if the operation is not
2084 * yet supported on this OMAP; otherwise, passes along the return value
2085 * from _deassert_hardreset().
2086 */
2087int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
2088{
2089 int ret;
dc6d1cda 2090 unsigned long flags;
aee48e3c
PW
2091
2092 if (!oh)
2093 return -EINVAL;
2094
dc6d1cda 2095 spin_lock_irqsave(&oh->_lock, flags);
aee48e3c 2096 ret = _deassert_hardreset(oh, name);
dc6d1cda 2097 spin_unlock_irqrestore(&oh->_lock, flags);
aee48e3c
PW
2098
2099 return ret;
2100}
2101
2102/**
2103 * omap_hwmod_read_hardreset - read the HW reset line state of submodules
2104 * contained in the hwmod module
2105 * @oh: struct omap_hwmod *
2106 * @name: name of the reset line to look up and read
2107 *
2108 * Return the current state of the hwmod @oh's reset line named @name:
2109 * returns -EINVAL upon parameter error or if this operation
2110 * is unsupported on the current OMAP; otherwise, passes along the return
2111 * value from _read_hardreset().
2112 */
2113int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
2114{
2115 int ret;
dc6d1cda 2116 unsigned long flags;
aee48e3c
PW
2117
2118 if (!oh)
2119 return -EINVAL;
2120
dc6d1cda 2121 spin_lock_irqsave(&oh->_lock, flags);
aee48e3c 2122 ret = _read_hardreset(oh, name);
dc6d1cda 2123 spin_unlock_irqrestore(&oh->_lock, flags);
aee48e3c
PW
2124
2125 return ret;
2126}
2127
2128
43b40992
PW
2129/**
2130 * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
2131 * @classname: struct omap_hwmod_class name to search for
2132 * @fn: callback function pointer to call for each hwmod in class @classname
2133 * @user: arbitrary context data to pass to the callback function
2134 *
ce35b244
BC
2135 * For each omap_hwmod of class @classname, call @fn.
2136 * If the callback function returns something other than
43b40992
PW
2137 * zero, the iterator is terminated, and the callback function's return
2138 * value is passed back to the caller. Returns 0 upon success, -EINVAL
2139 * if @classname or @fn are NULL, or passes back the error code from @fn.
2140 */
2141int omap_hwmod_for_each_by_class(const char *classname,
2142 int (*fn)(struct omap_hwmod *oh,
2143 void *user),
2144 void *user)
2145{
2146 struct omap_hwmod *temp_oh;
2147 int ret = 0;
2148
2149 if (!classname || !fn)
2150 return -EINVAL;
2151
2152 pr_debug("omap_hwmod: %s: looking for modules of class %s\n",
2153 __func__, classname);
2154
43b40992
PW
2155 list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
2156 if (!strcmp(temp_oh->class->name, classname)) {
2157 pr_debug("omap_hwmod: %s: %s: calling callback fn\n",
2158 __func__, temp_oh->name);
2159 ret = (*fn)(temp_oh, user);
2160 if (ret)
2161 break;
2162 }
2163 }
2164
43b40992
PW
2165 if (ret)
2166 pr_debug("omap_hwmod: %s: iterator terminated early: %d\n",
2167 __func__, ret);
2168
2169 return ret;
2170}
2171
2092e5cc
PW
2172/**
2173 * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod
2174 * @oh: struct omap_hwmod *
2175 * @state: state that _setup() should leave the hwmod in
2176 *
2177 * Sets the hwmod state that @oh will enter at the end of _setup() (called by
2178 * omap_hwmod_late_init()). Only valid to call between calls to
2179 * omap_hwmod_init() and omap_hwmod_late_init(). Returns 0 upon success or
2180 * -EINVAL if there is a problem with the arguments or if the hwmod is
2181 * in the wrong state.
2182 */
2183int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
2184{
2185 int ret;
dc6d1cda 2186 unsigned long flags;
2092e5cc
PW
2187
2188 if (!oh)
2189 return -EINVAL;
2190
2191 if (state != _HWMOD_STATE_DISABLED &&
2192 state != _HWMOD_STATE_ENABLED &&
2193 state != _HWMOD_STATE_IDLE)
2194 return -EINVAL;
2195
dc6d1cda 2196 spin_lock_irqsave(&oh->_lock, flags);
2092e5cc
PW
2197
2198 if (oh->_state != _HWMOD_STATE_REGISTERED) {
2199 ret = -EINVAL;
2200 goto ohsps_unlock;
2201 }
2202
2203 oh->_postsetup_state = state;
2204 ret = 0;
2205
2206ohsps_unlock:
dc6d1cda 2207 spin_unlock_irqrestore(&oh->_lock, flags);
2092e5cc
PW
2208
2209 return ret;
2210}
c80705aa
KH
2211
2212/**
2213 * omap_hwmod_get_context_loss_count - get lost context count
2214 * @oh: struct omap_hwmod *
2215 *
2216 * Query the powerdomain of of @oh to get the context loss
2217 * count for this device.
2218 *
2219 * Returns the context loss count of the powerdomain assocated with @oh
2220 * upon success, or zero if no powerdomain exists for @oh.
2221 */
2222u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
2223{
2224 struct powerdomain *pwrdm;
2225 int ret = 0;
2226
2227 pwrdm = omap_hwmod_get_pwrdm(oh);
2228 if (pwrdm)
2229 ret = pwrdm_get_context_loss_count(pwrdm);
2230
2231 return ret;
2232}