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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, BenoƮt Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
75 | * | (__raw_{read,write}l, clk*) | | |
76 | * +-------------------------------+ | |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
133 | #include <linux/clk.h> | |
134 | #include <linux/delay.h> | |
135 | #include <linux/err.h> | |
136 | #include <linux/list.h> | |
137 | #include <linux/mutex.h> | |
dc6d1cda | 138 | #include <linux/spinlock.h> |
abc2d545 | 139 | #include <linux/slab.h> |
2221b5cd | 140 | #include <linux/bootmem.h> |
63c85238 | 141 | |
a135eaae | 142 | #include "clock.h" |
2a296c8f | 143 | #include "omap_hwmod.h" |
63c85238 | 144 | |
dbc04161 TL |
145 | #include "soc.h" |
146 | #include "common.h" | |
147 | #include "clockdomain.h" | |
148 | #include "powerdomain.h" | |
ff4ae5d9 PW |
149 | #include "cm2xxx.h" |
150 | #include "cm3xxx.h" | |
d0f0631d | 151 | #include "cminst44xx.h" |
1688bf19 | 152 | #include "cm33xx.h" |
b13159af | 153 | #include "prm.h" |
139563ad | 154 | #include "prm3xxx.h" |
d198b514 | 155 | #include "prm44xx.h" |
1688bf19 | 156 | #include "prm33xx.h" |
eaac329d | 157 | #include "prminst44xx.h" |
8d9af88f | 158 | #include "mux.h" |
5165882a | 159 | #include "pm.h" |
63c85238 | 160 | |
63c85238 | 161 | /* Name of the OMAP hwmod for the MPU */ |
5c2c0296 | 162 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 | 163 | |
2221b5cd PW |
164 | /* |
165 | * Number of struct omap_hwmod_link records per struct | |
166 | * omap_hwmod_ocp_if record (master->slave and slave->master) | |
167 | */ | |
168 | #define LINKS_PER_OCP_IF 2 | |
169 | ||
9ebfd285 KH |
170 | /** |
171 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | |
172 | * @enable_module: function to enable a module (via MODULEMODE) | |
173 | * @disable_module: function to disable a module (via MODULEMODE) | |
174 | * | |
175 | * XXX Eventually this functionality will be hidden inside the PRM/CM | |
176 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | |
177 | * conditionals in this code. | |
178 | */ | |
179 | struct omap_hwmod_soc_ops { | |
180 | void (*enable_module)(struct omap_hwmod *oh); | |
181 | int (*disable_module)(struct omap_hwmod *oh); | |
8f6aa8ee | 182 | int (*wait_target_ready)(struct omap_hwmod *oh); |
b8249cf2 KH |
183 | int (*assert_hardreset)(struct omap_hwmod *oh, |
184 | struct omap_hwmod_rst_info *ohri); | |
185 | int (*deassert_hardreset)(struct omap_hwmod *oh, | |
186 | struct omap_hwmod_rst_info *ohri); | |
187 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | |
188 | struct omap_hwmod_rst_info *ohri); | |
0a179eaa | 189 | int (*init_clkdm)(struct omap_hwmod *oh); |
9ebfd285 KH |
190 | }; |
191 | ||
192 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | |
193 | static struct omap_hwmod_soc_ops soc_ops; | |
194 | ||
63c85238 PW |
195 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
196 | static LIST_HEAD(omap_hwmod_list); | |
197 | ||
63c85238 PW |
198 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
199 | static struct omap_hwmod *mpu_oh; | |
200 | ||
5165882a VB |
201 | /* io_chain_lock: used to serialize reconfigurations of the I/O chain */ |
202 | static DEFINE_SPINLOCK(io_chain_lock); | |
203 | ||
2221b5cd PW |
204 | /* |
205 | * linkspace: ptr to a buffer that struct omap_hwmod_link records are | |
206 | * allocated from - used to reduce the number of small memory | |
207 | * allocations, which has a significant impact on performance | |
208 | */ | |
209 | static struct omap_hwmod_link *linkspace; | |
210 | ||
211 | /* | |
212 | * free_ls, max_ls: array indexes into linkspace; representing the | |
213 | * next free struct omap_hwmod_link index, and the maximum number of | |
214 | * struct omap_hwmod_link records allocated (respectively) | |
215 | */ | |
216 | static unsigned short free_ls, max_ls, ls_supp; | |
63c85238 | 217 | |
9ebfd285 KH |
218 | /* inited: set to true once the hwmod code is initialized */ |
219 | static bool inited; | |
220 | ||
63c85238 PW |
221 | /* Private functions */ |
222 | ||
5d95dde7 | 223 | /** |
11cd4b94 | 224 | * _fetch_next_ocp_if - return the next OCP interface in a list |
2221b5cd | 225 | * @p: ptr to a ptr to the list_head inside the ocp_if to return |
11cd4b94 PW |
226 | * @i: pointer to the index of the element pointed to by @p in the list |
227 | * | |
228 | * Return a pointer to the struct omap_hwmod_ocp_if record | |
229 | * containing the struct list_head pointed to by @p, and increment | |
230 | * @p such that a future call to this routine will return the next | |
231 | * record. | |
5d95dde7 PW |
232 | */ |
233 | static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p, | |
5d95dde7 PW |
234 | int *i) |
235 | { | |
236 | struct omap_hwmod_ocp_if *oi; | |
237 | ||
11cd4b94 PW |
238 | oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if; |
239 | *p = (*p)->next; | |
2221b5cd | 240 | |
5d95dde7 PW |
241 | *i = *i + 1; |
242 | ||
243 | return oi; | |
244 | } | |
245 | ||
63c85238 PW |
246 | /** |
247 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
248 | * @oh: struct omap_hwmod * | |
249 | * | |
250 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
251 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
252 | * OCP_SYSCONFIG register or 0 upon success. | |
253 | */ | |
254 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
255 | { | |
43b40992 PW |
256 | if (!oh->class->sysc) { |
257 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
258 | return -EINVAL; |
259 | } | |
260 | ||
261 | /* XXX ensure module interface clock is up */ | |
262 | ||
cc7a1d2a | 263 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 264 | |
43b40992 | 265 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 266 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
267 | |
268 | return 0; | |
269 | } | |
270 | ||
271 | /** | |
272 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
273 | * @v: OCP_SYSCONFIG value to write | |
274 | * @oh: struct omap_hwmod * | |
275 | * | |
43b40992 PW |
276 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
277 | * one. No return value. | |
63c85238 PW |
278 | */ |
279 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
280 | { | |
43b40992 PW |
281 | if (!oh->class->sysc) { |
282 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
283 | return; |
284 | } | |
285 | ||
286 | /* XXX ensure module interface clock is up */ | |
287 | ||
233cbe5b RN |
288 | /* Module might have lost context, always update cache and register */ |
289 | oh->_sysc_cache = v; | |
290 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); | |
63c85238 PW |
291 | } |
292 | ||
293 | /** | |
294 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
295 | * @oh: struct omap_hwmod * | |
296 | * @standbymode: MIDLEMODE field bits | |
297 | * @v: pointer to register contents to modify | |
298 | * | |
299 | * Update the master standby mode bits in @v to be @standbymode for | |
300 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
301 | * upon error or 0 upon success. | |
302 | */ | |
303 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
304 | u32 *v) | |
305 | { | |
358f0e63 TG |
306 | u32 mstandby_mask; |
307 | u8 mstandby_shift; | |
308 | ||
43b40992 PW |
309 | if (!oh->class->sysc || |
310 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
311 | return -EINVAL; |
312 | ||
43b40992 PW |
313 | if (!oh->class->sysc->sysc_fields) { |
314 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
315 | return -EINVAL; |
316 | } | |
317 | ||
43b40992 | 318 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
319 | mstandby_mask = (0x3 << mstandby_shift); |
320 | ||
321 | *v &= ~mstandby_mask; | |
322 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
323 | |
324 | return 0; | |
325 | } | |
326 | ||
327 | /** | |
328 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
329 | * @oh: struct omap_hwmod * | |
330 | * @idlemode: SIDLEMODE field bits | |
331 | * @v: pointer to register contents to modify | |
332 | * | |
333 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
334 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
335 | * or 0 upon success. | |
336 | */ | |
337 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
338 | { | |
358f0e63 TG |
339 | u32 sidle_mask; |
340 | u8 sidle_shift; | |
341 | ||
43b40992 PW |
342 | if (!oh->class->sysc || |
343 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
344 | return -EINVAL; |
345 | ||
43b40992 PW |
346 | if (!oh->class->sysc->sysc_fields) { |
347 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
348 | return -EINVAL; |
349 | } | |
350 | ||
43b40992 | 351 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
352 | sidle_mask = (0x3 << sidle_shift); |
353 | ||
354 | *v &= ~sidle_mask; | |
355 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
356 | |
357 | return 0; | |
358 | } | |
359 | ||
360 | /** | |
361 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
362 | * @oh: struct omap_hwmod * | |
363 | * @clockact: CLOCKACTIVITY field bits | |
364 | * @v: pointer to register contents to modify | |
365 | * | |
366 | * Update the clockactivity mode bits in @v to be @clockact for the | |
367 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
368 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
369 | * success. | |
370 | */ | |
371 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
372 | { | |
358f0e63 TG |
373 | u32 clkact_mask; |
374 | u8 clkact_shift; | |
375 | ||
43b40992 PW |
376 | if (!oh->class->sysc || |
377 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
378 | return -EINVAL; |
379 | ||
43b40992 PW |
380 | if (!oh->class->sysc->sysc_fields) { |
381 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
382 | return -EINVAL; |
383 | } | |
384 | ||
43b40992 | 385 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
386 | clkact_mask = (0x3 << clkact_shift); |
387 | ||
388 | *v &= ~clkact_mask; | |
389 | *v |= clockact << clkact_shift; | |
63c85238 PW |
390 | |
391 | return 0; | |
392 | } | |
393 | ||
394 | /** | |
395 | * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
396 | * @oh: struct omap_hwmod * | |
397 | * @v: pointer to register contents to modify | |
398 | * | |
399 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
400 | * error or 0 upon success. | |
401 | */ | |
402 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
403 | { | |
358f0e63 TG |
404 | u32 softrst_mask; |
405 | ||
43b40992 PW |
406 | if (!oh->class->sysc || |
407 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
408 | return -EINVAL; |
409 | ||
43b40992 PW |
410 | if (!oh->class->sysc->sysc_fields) { |
411 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
412 | return -EINVAL; |
413 | } | |
414 | ||
43b40992 | 415 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
416 | |
417 | *v |= softrst_mask; | |
63c85238 PW |
418 | |
419 | return 0; | |
420 | } | |
421 | ||
6668546f KVA |
422 | /** |
423 | * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v | |
424 | * @oh: struct omap_hwmod * | |
425 | * | |
426 | * The DMADISABLE bit is a semi-automatic bit present in sysconfig register | |
427 | * of some modules. When the DMA must perform read/write accesses, the | |
428 | * DMADISABLE bit is cleared by the hardware. But when the DMA must stop | |
429 | * for power management, software must set the DMADISABLE bit back to 1. | |
430 | * | |
431 | * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon | |
432 | * error or 0 upon success. | |
433 | */ | |
434 | static int _set_dmadisable(struct omap_hwmod *oh) | |
435 | { | |
436 | u32 v; | |
437 | u32 dmadisable_mask; | |
438 | ||
439 | if (!oh->class->sysc || | |
440 | !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE)) | |
441 | return -EINVAL; | |
442 | ||
443 | if (!oh->class->sysc->sysc_fields) { | |
444 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
445 | return -EINVAL; | |
446 | } | |
447 | ||
448 | /* clocks must be on for this operation */ | |
449 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
450 | pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name); | |
451 | return -EINVAL; | |
452 | } | |
453 | ||
454 | pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name); | |
455 | ||
456 | v = oh->_sysc_cache; | |
457 | dmadisable_mask = | |
458 | (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift); | |
459 | v |= dmadisable_mask; | |
460 | _write_sysconfig(v, oh); | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
726072e5 PW |
465 | /** |
466 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
467 | * @oh: struct omap_hwmod * | |
468 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
469 | * @v: pointer to register contents to modify | |
470 | * | |
471 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
472 | * hwmod. The autoidle bit controls whether the module can gate | |
473 | * internal clocks automatically when it isn't doing anything; the | |
474 | * exact function of this bit varies on a per-module basis. This | |
475 | * function does not write to the hardware. Returns -EINVAL upon | |
476 | * error or 0 upon success. | |
477 | */ | |
478 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
479 | u32 *v) | |
480 | { | |
358f0e63 TG |
481 | u32 autoidle_mask; |
482 | u8 autoidle_shift; | |
483 | ||
43b40992 PW |
484 | if (!oh->class->sysc || |
485 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
486 | return -EINVAL; |
487 | ||
43b40992 PW |
488 | if (!oh->class->sysc->sysc_fields) { |
489 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
490 | return -EINVAL; |
491 | } | |
492 | ||
43b40992 | 493 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 494 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
495 | |
496 | *v &= ~autoidle_mask; | |
497 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
498 | |
499 | return 0; | |
500 | } | |
501 | ||
eceec009 G |
502 | /** |
503 | * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux | |
504 | * @oh: struct omap_hwmod * | |
505 | * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable | |
506 | * | |
507 | * Set or clear the I/O pad wakeup flag in the mux entries for the | |
508 | * hwmod @oh. This function changes the @oh->mux->pads_dynamic array | |
509 | * in memory. If the hwmod is currently idled, and the new idle | |
510 | * values don't match the previous ones, this function will also | |
511 | * update the SCM PADCTRL registers. Otherwise, if the hwmod is not | |
512 | * currently idled, this function won't touch the hardware: the new | |
513 | * mux settings are written to the SCM PADCTRL registers when the | |
514 | * hwmod is idled. No return value. | |
515 | */ | |
516 | static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake) | |
517 | { | |
518 | struct omap_device_pad *pad; | |
519 | bool change = false; | |
520 | u16 prev_idle; | |
521 | int j; | |
522 | ||
523 | if (!oh->mux || !oh->mux->enabled) | |
524 | return; | |
525 | ||
526 | for (j = 0; j < oh->mux->nr_pads_dynamic; j++) { | |
527 | pad = oh->mux->pads_dynamic[j]; | |
528 | ||
529 | if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP)) | |
530 | continue; | |
531 | ||
532 | prev_idle = pad->idle; | |
533 | ||
534 | if (set_wake) | |
535 | pad->idle |= OMAP_WAKEUP_EN; | |
536 | else | |
537 | pad->idle &= ~OMAP_WAKEUP_EN; | |
538 | ||
539 | if (prev_idle != pad->idle) | |
540 | change = true; | |
541 | } | |
542 | ||
543 | if (change && oh->_state == _HWMOD_STATE_IDLE) | |
544 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); | |
545 | } | |
546 | ||
63c85238 PW |
547 | /** |
548 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
549 | * @oh: struct omap_hwmod * | |
550 | * | |
551 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
552 | * upon error or 0 upon success. | |
553 | */ | |
5a7ddcbd | 554 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 555 | { |
43b40992 | 556 | if (!oh->class->sysc || |
86009eb3 | 557 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
558 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
559 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
560 | return -EINVAL; |
561 | ||
43b40992 PW |
562 | if (!oh->class->sysc->sysc_fields) { |
563 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
564 | return -EINVAL; |
565 | } | |
566 | ||
1fe74113 BC |
567 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
568 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 569 | |
86009eb3 BC |
570 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
571 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
572 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
573 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 574 | |
63c85238 PW |
575 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
576 | ||
577 | oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
582 | /** | |
583 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
584 | * @oh: struct omap_hwmod * | |
585 | * | |
586 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
587 | * upon error or 0 upon success. | |
588 | */ | |
5a7ddcbd | 589 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 590 | { |
43b40992 | 591 | if (!oh->class->sysc || |
86009eb3 | 592 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
593 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
594 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
595 | return -EINVAL; |
596 | ||
43b40992 PW |
597 | if (!oh->class->sysc->sysc_fields) { |
598 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
599 | return -EINVAL; |
600 | } | |
601 | ||
1fe74113 BC |
602 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
603 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 604 | |
86009eb3 BC |
605 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
606 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 | 607 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
561038f0 | 608 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v); |
86009eb3 | 609 | |
63c85238 PW |
610 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
611 | ||
612 | oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | /** | |
618 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
619 | * @oh: struct omap_hwmod * | |
620 | * | |
621 | * Prevent the hardware module @oh from entering idle while the | |
622 | * hardare module initiator @init_oh is active. Useful when a module | |
623 | * will be accessed by a particular initiator (e.g., if a module will | |
624 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
625 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
626 | * mode. If the clockdomain is marked as not needing autodeps, return |
627 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
628 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
629 | */ |
630 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
631 | { | |
632 | if (!oh->_clk) | |
633 | return -EINVAL; | |
634 | ||
570b54c7 PW |
635 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
636 | return 0; | |
637 | ||
55ed9694 | 638 | return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
639 | } |
640 | ||
641 | /** | |
642 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
643 | * @oh: struct omap_hwmod * | |
644 | * | |
645 | * Allow the hardware module @oh to enter idle while the hardare | |
646 | * module initiator @init_oh is active. Useful when a module will not | |
647 | * be accessed by a particular initiator (e.g., if a module will not | |
648 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
649 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
650 | * mode. If the clockdomain is marked as not needing autodeps, return |
651 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
652 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
653 | */ |
654 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
655 | { | |
656 | if (!oh->_clk) | |
657 | return -EINVAL; | |
658 | ||
570b54c7 PW |
659 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
660 | return 0; | |
661 | ||
55ed9694 | 662 | return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
663 | } |
664 | ||
665 | /** | |
666 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
667 | * @oh: struct omap_hwmod * | |
668 | * | |
669 | * Called from _init_clocks(). Populates the @oh _clk (main | |
670 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
671 | * success or -EINVAL on error. | |
672 | */ | |
673 | static int _init_main_clk(struct omap_hwmod *oh) | |
674 | { | |
63c85238 PW |
675 | int ret = 0; |
676 | ||
50ebdac2 | 677 | if (!oh->main_clk) |
63c85238 PW |
678 | return 0; |
679 | ||
6ea74cb9 RN |
680 | oh->_clk = clk_get(NULL, oh->main_clk); |
681 | if (IS_ERR(oh->_clk)) { | |
20383d82 BC |
682 | pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
683 | oh->name, oh->main_clk); | |
63403384 | 684 | return -EINVAL; |
dc75925d | 685 | } |
4d7cb45e RN |
686 | /* |
687 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
688 | * to do something meaningful. Today its just a no-op. | |
689 | * If clk_prepare() is used at some point to do things like | |
690 | * voltage scaling etc, then this would have to be moved to | |
691 | * some point where subsystems like i2c and pmic become | |
692 | * available. | |
693 | */ | |
694 | clk_prepare(oh->_clk); | |
63c85238 | 695 | |
63403384 | 696 | if (!oh->_clk->clkdm) |
3bb05dbf | 697 | pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", |
5dcc3b97 | 698 | oh->name, oh->main_clk); |
81d7c6ff | 699 | |
63c85238 PW |
700 | return ret; |
701 | } | |
702 | ||
703 | /** | |
887adeac | 704 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
705 | * @oh: struct omap_hwmod * |
706 | * | |
707 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
708 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
709 | */ | |
710 | static int _init_interface_clks(struct omap_hwmod *oh) | |
711 | { | |
5d95dde7 | 712 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 713 | struct list_head *p; |
63c85238 | 714 | struct clk *c; |
5d95dde7 | 715 | int i = 0; |
63c85238 PW |
716 | int ret = 0; |
717 | ||
11cd4b94 | 718 | p = oh->slave_ports.next; |
2221b5cd | 719 | |
5d95dde7 | 720 | while (i < oh->slaves_cnt) { |
11cd4b94 | 721 | os = _fetch_next_ocp_if(&p, &i); |
50ebdac2 | 722 | if (!os->clk) |
63c85238 PW |
723 | continue; |
724 | ||
6ea74cb9 RN |
725 | c = clk_get(NULL, os->clk); |
726 | if (IS_ERR(c)) { | |
20383d82 BC |
727 | pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
728 | oh->name, os->clk); | |
63c85238 | 729 | ret = -EINVAL; |
dc75925d | 730 | } |
63c85238 | 731 | os->_clk = c; |
4d7cb45e RN |
732 | /* |
733 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
734 | * to do something meaningful. Today its just a no-op. | |
735 | * If clk_prepare() is used at some point to do things like | |
736 | * voltage scaling etc, then this would have to be moved to | |
737 | * some point where subsystems like i2c and pmic become | |
738 | * available. | |
739 | */ | |
740 | clk_prepare(os->_clk); | |
63c85238 PW |
741 | } |
742 | ||
743 | return ret; | |
744 | } | |
745 | ||
746 | /** | |
747 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
748 | * @oh: struct omap_hwmod * | |
749 | * | |
750 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
751 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
752 | */ | |
753 | static int _init_opt_clks(struct omap_hwmod *oh) | |
754 | { | |
755 | struct omap_hwmod_opt_clk *oc; | |
756 | struct clk *c; | |
757 | int i; | |
758 | int ret = 0; | |
759 | ||
760 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
6ea74cb9 RN |
761 | c = clk_get(NULL, oc->clk); |
762 | if (IS_ERR(c)) { | |
20383d82 BC |
763 | pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
764 | oh->name, oc->clk); | |
63c85238 | 765 | ret = -EINVAL; |
dc75925d | 766 | } |
63c85238 | 767 | oc->_clk = c; |
4d7cb45e RN |
768 | /* |
769 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
770 | * to do something meaningful. Today its just a no-op. | |
771 | * If clk_prepare() is used at some point to do things like | |
772 | * voltage scaling etc, then this would have to be moved to | |
773 | * some point where subsystems like i2c and pmic become | |
774 | * available. | |
775 | */ | |
776 | clk_prepare(oc->_clk); | |
63c85238 PW |
777 | } |
778 | ||
779 | return ret; | |
780 | } | |
781 | ||
782 | /** | |
783 | * _enable_clocks - enable hwmod main clock and interface clocks | |
784 | * @oh: struct omap_hwmod * | |
785 | * | |
786 | * Enables all clocks necessary for register reads and writes to succeed | |
787 | * on the hwmod @oh. Returns 0. | |
788 | */ | |
789 | static int _enable_clocks(struct omap_hwmod *oh) | |
790 | { | |
5d95dde7 | 791 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 792 | struct list_head *p; |
5d95dde7 | 793 | int i = 0; |
63c85238 PW |
794 | |
795 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
796 | ||
4d3ae5a9 | 797 | if (oh->_clk) |
63c85238 PW |
798 | clk_enable(oh->_clk); |
799 | ||
11cd4b94 | 800 | p = oh->slave_ports.next; |
2221b5cd | 801 | |
5d95dde7 | 802 | while (i < oh->slaves_cnt) { |
11cd4b94 | 803 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 804 | |
5d95dde7 PW |
805 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
806 | clk_enable(os->_clk); | |
63c85238 PW |
807 | } |
808 | ||
809 | /* The opt clocks are controlled by the device driver. */ | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
814 | /** | |
815 | * _disable_clocks - disable hwmod main clock and interface clocks | |
816 | * @oh: struct omap_hwmod * | |
817 | * | |
818 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
819 | */ | |
820 | static int _disable_clocks(struct omap_hwmod *oh) | |
821 | { | |
5d95dde7 | 822 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 823 | struct list_head *p; |
5d95dde7 | 824 | int i = 0; |
63c85238 PW |
825 | |
826 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
827 | ||
4d3ae5a9 | 828 | if (oh->_clk) |
63c85238 PW |
829 | clk_disable(oh->_clk); |
830 | ||
11cd4b94 | 831 | p = oh->slave_ports.next; |
2221b5cd | 832 | |
5d95dde7 | 833 | while (i < oh->slaves_cnt) { |
11cd4b94 | 834 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 835 | |
5d95dde7 PW |
836 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
837 | clk_disable(os->_clk); | |
63c85238 PW |
838 | } |
839 | ||
840 | /* The opt clocks are controlled by the device driver. */ | |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
96835af9 BC |
845 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
846 | { | |
847 | struct omap_hwmod_opt_clk *oc; | |
848 | int i; | |
849 | ||
850 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
851 | ||
852 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
853 | if (oc->_clk) { | |
854 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
5dcc3b97 | 855 | __clk_get_name(oc->_clk)); |
96835af9 BC |
856 | clk_enable(oc->_clk); |
857 | } | |
858 | } | |
859 | ||
860 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
861 | { | |
862 | struct omap_hwmod_opt_clk *oc; | |
863 | int i; | |
864 | ||
865 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
866 | ||
867 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
868 | if (oc->_clk) { | |
869 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
5dcc3b97 | 870 | __clk_get_name(oc->_clk)); |
96835af9 BC |
871 | clk_disable(oc->_clk); |
872 | } | |
873 | } | |
874 | ||
45c38252 | 875 | /** |
3d9f0327 | 876 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
45c38252 BC |
877 | * @oh: struct omap_hwmod * |
878 | * | |
879 | * Enables the PRCM module mode related to the hwmod @oh. | |
880 | * No return value. | |
881 | */ | |
3d9f0327 | 882 | static void _omap4_enable_module(struct omap_hwmod *oh) |
45c38252 | 883 | { |
45c38252 BC |
884 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
885 | return; | |
886 | ||
3d9f0327 KH |
887 | pr_debug("omap_hwmod: %s: %s: %d\n", |
888 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
45c38252 BC |
889 | |
890 | omap4_cminst_module_enable(oh->prcm.omap4.modulemode, | |
891 | oh->clkdm->prcm_partition, | |
892 | oh->clkdm->cm_inst, | |
893 | oh->clkdm->clkdm_offs, | |
894 | oh->prcm.omap4.clkctrl_offs); | |
895 | } | |
896 | ||
1688bf19 VH |
897 | /** |
898 | * _am33xx_enable_module - enable CLKCTRL modulemode on AM33XX | |
899 | * @oh: struct omap_hwmod * | |
900 | * | |
901 | * Enables the PRCM module mode related to the hwmod @oh. | |
902 | * No return value. | |
903 | */ | |
904 | static void _am33xx_enable_module(struct omap_hwmod *oh) | |
905 | { | |
906 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
907 | return; | |
908 | ||
909 | pr_debug("omap_hwmod: %s: %s: %d\n", | |
910 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
911 | ||
912 | am33xx_cm_module_enable(oh->prcm.omap4.modulemode, oh->clkdm->cm_inst, | |
913 | oh->clkdm->clkdm_offs, | |
914 | oh->prcm.omap4.clkctrl_offs); | |
915 | } | |
916 | ||
45c38252 | 917 | /** |
bfc141e3 BC |
918 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
919 | * @oh: struct omap_hwmod * | |
920 | * | |
921 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
922 | * does not have an IDLEST bit or if the module successfully enters | |
923 | * slave idle; otherwise, pass along the return value of the | |
924 | * appropriate *_cm*_wait_module_idle() function. | |
925 | */ | |
926 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
927 | { | |
2b026d13 | 928 | if (!oh) |
bfc141e3 BC |
929 | return -EINVAL; |
930 | ||
2b026d13 | 931 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm) |
bfc141e3 BC |
932 | return 0; |
933 | ||
934 | if (oh->flags & HWMOD_NO_IDLEST) | |
935 | return 0; | |
936 | ||
937 | return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition, | |
938 | oh->clkdm->cm_inst, | |
939 | oh->clkdm->clkdm_offs, | |
940 | oh->prcm.omap4.clkctrl_offs); | |
941 | } | |
942 | ||
1688bf19 VH |
943 | /** |
944 | * _am33xx_wait_target_disable - wait for a module to be disabled on AM33XX | |
945 | * @oh: struct omap_hwmod * | |
946 | * | |
947 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
948 | * does not have an IDLEST bit or if the module successfully enters | |
949 | * slave idle; otherwise, pass along the return value of the | |
950 | * appropriate *_cm*_wait_module_idle() function. | |
951 | */ | |
952 | static int _am33xx_wait_target_disable(struct omap_hwmod *oh) | |
953 | { | |
954 | if (!oh) | |
955 | return -EINVAL; | |
956 | ||
957 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
958 | return 0; | |
959 | ||
960 | if (oh->flags & HWMOD_NO_IDLEST) | |
961 | return 0; | |
962 | ||
963 | return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst, | |
964 | oh->clkdm->clkdm_offs, | |
965 | oh->prcm.omap4.clkctrl_offs); | |
966 | } | |
967 | ||
212738a4 PW |
968 | /** |
969 | * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh | |
970 | * @oh: struct omap_hwmod *oh | |
971 | * | |
972 | * Count and return the number of MPU IRQs associated with the hwmod | |
973 | * @oh. Used to allocate struct resource data. Returns 0 if @oh is | |
974 | * NULL. | |
975 | */ | |
976 | static int _count_mpu_irqs(struct omap_hwmod *oh) | |
977 | { | |
978 | struct omap_hwmod_irq_info *ohii; | |
979 | int i = 0; | |
980 | ||
981 | if (!oh || !oh->mpu_irqs) | |
982 | return 0; | |
983 | ||
984 | do { | |
985 | ohii = &oh->mpu_irqs[i++]; | |
986 | } while (ohii->irq != -1); | |
987 | ||
cc1b0765 | 988 | return i-1; |
212738a4 PW |
989 | } |
990 | ||
bc614958 PW |
991 | /** |
992 | * _count_sdma_reqs - count the number of SDMA request lines associated with @oh | |
993 | * @oh: struct omap_hwmod *oh | |
994 | * | |
995 | * Count and return the number of SDMA request lines associated with | |
996 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
997 | * if @oh is NULL. | |
998 | */ | |
999 | static int _count_sdma_reqs(struct omap_hwmod *oh) | |
1000 | { | |
1001 | struct omap_hwmod_dma_info *ohdi; | |
1002 | int i = 0; | |
1003 | ||
1004 | if (!oh || !oh->sdma_reqs) | |
1005 | return 0; | |
1006 | ||
1007 | do { | |
1008 | ohdi = &oh->sdma_reqs[i++]; | |
1009 | } while (ohdi->dma_req != -1); | |
1010 | ||
cc1b0765 | 1011 | return i-1; |
bc614958 PW |
1012 | } |
1013 | ||
78183f3f PW |
1014 | /** |
1015 | * _count_ocp_if_addr_spaces - count the number of address space entries for @oh | |
1016 | * @oh: struct omap_hwmod *oh | |
1017 | * | |
1018 | * Count and return the number of address space ranges associated with | |
1019 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1020 | * if @oh is NULL. | |
1021 | */ | |
1022 | static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) | |
1023 | { | |
1024 | struct omap_hwmod_addr_space *mem; | |
1025 | int i = 0; | |
1026 | ||
1027 | if (!os || !os->addr) | |
1028 | return 0; | |
1029 | ||
1030 | do { | |
1031 | mem = &os->addr[i++]; | |
1032 | } while (mem->pa_start != mem->pa_end); | |
1033 | ||
cc1b0765 | 1034 | return i-1; |
78183f3f PW |
1035 | } |
1036 | ||
5e8370f1 PW |
1037 | /** |
1038 | * _get_mpu_irq_by_name - fetch MPU interrupt line number by name | |
1039 | * @oh: struct omap_hwmod * to operate on | |
1040 | * @name: pointer to the name of the MPU interrupt number to fetch (optional) | |
1041 | * @irq: pointer to an unsigned int to store the MPU IRQ number to | |
1042 | * | |
1043 | * Retrieve a MPU hardware IRQ line number named by @name associated | |
1044 | * with the IP block pointed to by @oh. The IRQ number will be filled | |
1045 | * into the address pointed to by @dma. When @name is non-null, the | |
1046 | * IRQ line number associated with the named entry will be returned. | |
1047 | * If @name is null, the first matching entry will be returned. Data | |
1048 | * order is not meaningful in hwmod data, so callers are strongly | |
1049 | * encouraged to use a non-null @name whenever possible to avoid | |
1050 | * unpredictable effects if hwmod data is later added that causes data | |
1051 | * ordering to change. Returns 0 upon success or a negative error | |
1052 | * code upon error. | |
1053 | */ | |
1054 | static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, | |
1055 | unsigned int *irq) | |
1056 | { | |
1057 | int i; | |
1058 | bool found = false; | |
1059 | ||
1060 | if (!oh->mpu_irqs) | |
1061 | return -ENOENT; | |
1062 | ||
1063 | i = 0; | |
1064 | while (oh->mpu_irqs[i].irq != -1) { | |
1065 | if (name == oh->mpu_irqs[i].name || | |
1066 | !strcmp(name, oh->mpu_irqs[i].name)) { | |
1067 | found = true; | |
1068 | break; | |
1069 | } | |
1070 | i++; | |
1071 | } | |
1072 | ||
1073 | if (!found) | |
1074 | return -ENOENT; | |
1075 | ||
1076 | *irq = oh->mpu_irqs[i].irq; | |
1077 | ||
1078 | return 0; | |
1079 | } | |
1080 | ||
1081 | /** | |
1082 | * _get_sdma_req_by_name - fetch SDMA request line ID by name | |
1083 | * @oh: struct omap_hwmod * to operate on | |
1084 | * @name: pointer to the name of the SDMA request line to fetch (optional) | |
1085 | * @dma: pointer to an unsigned int to store the request line ID to | |
1086 | * | |
1087 | * Retrieve an SDMA request line ID named by @name on the IP block | |
1088 | * pointed to by @oh. The ID will be filled into the address pointed | |
1089 | * to by @dma. When @name is non-null, the request line ID associated | |
1090 | * with the named entry will be returned. If @name is null, the first | |
1091 | * matching entry will be returned. Data order is not meaningful in | |
1092 | * hwmod data, so callers are strongly encouraged to use a non-null | |
1093 | * @name whenever possible to avoid unpredictable effects if hwmod | |
1094 | * data is later added that causes data ordering to change. Returns 0 | |
1095 | * upon success or a negative error code upon error. | |
1096 | */ | |
1097 | static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, | |
1098 | unsigned int *dma) | |
1099 | { | |
1100 | int i; | |
1101 | bool found = false; | |
1102 | ||
1103 | if (!oh->sdma_reqs) | |
1104 | return -ENOENT; | |
1105 | ||
1106 | i = 0; | |
1107 | while (oh->sdma_reqs[i].dma_req != -1) { | |
1108 | if (name == oh->sdma_reqs[i].name || | |
1109 | !strcmp(name, oh->sdma_reqs[i].name)) { | |
1110 | found = true; | |
1111 | break; | |
1112 | } | |
1113 | i++; | |
1114 | } | |
1115 | ||
1116 | if (!found) | |
1117 | return -ENOENT; | |
1118 | ||
1119 | *dma = oh->sdma_reqs[i].dma_req; | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | /** | |
1125 | * _get_addr_space_by_name - fetch address space start & end by name | |
1126 | * @oh: struct omap_hwmod * to operate on | |
1127 | * @name: pointer to the name of the address space to fetch (optional) | |
1128 | * @pa_start: pointer to a u32 to store the starting address to | |
1129 | * @pa_end: pointer to a u32 to store the ending address to | |
1130 | * | |
1131 | * Retrieve address space start and end addresses for the IP block | |
1132 | * pointed to by @oh. The data will be filled into the addresses | |
1133 | * pointed to by @pa_start and @pa_end. When @name is non-null, the | |
1134 | * address space data associated with the named entry will be | |
1135 | * returned. If @name is null, the first matching entry will be | |
1136 | * returned. Data order is not meaningful in hwmod data, so callers | |
1137 | * are strongly encouraged to use a non-null @name whenever possible | |
1138 | * to avoid unpredictable effects if hwmod data is later added that | |
1139 | * causes data ordering to change. Returns 0 upon success or a | |
1140 | * negative error code upon error. | |
1141 | */ | |
1142 | static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, | |
1143 | u32 *pa_start, u32 *pa_end) | |
1144 | { | |
1145 | int i, j; | |
1146 | struct omap_hwmod_ocp_if *os; | |
2221b5cd | 1147 | struct list_head *p = NULL; |
5e8370f1 PW |
1148 | bool found = false; |
1149 | ||
11cd4b94 | 1150 | p = oh->slave_ports.next; |
2221b5cd | 1151 | |
5d95dde7 PW |
1152 | i = 0; |
1153 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 1154 | os = _fetch_next_ocp_if(&p, &i); |
5e8370f1 PW |
1155 | |
1156 | if (!os->addr) | |
1157 | return -ENOENT; | |
1158 | ||
1159 | j = 0; | |
1160 | while (os->addr[j].pa_start != os->addr[j].pa_end) { | |
1161 | if (name == os->addr[j].name || | |
1162 | !strcmp(name, os->addr[j].name)) { | |
1163 | found = true; | |
1164 | break; | |
1165 | } | |
1166 | j++; | |
1167 | } | |
1168 | ||
1169 | if (found) | |
1170 | break; | |
1171 | } | |
1172 | ||
1173 | if (!found) | |
1174 | return -ENOENT; | |
1175 | ||
1176 | *pa_start = os->addr[j].pa_start; | |
1177 | *pa_end = os->addr[j].pa_end; | |
1178 | ||
1179 | return 0; | |
1180 | } | |
1181 | ||
63c85238 | 1182 | /** |
24dbc213 | 1183 | * _save_mpu_port_index - find and save the index to @oh's MPU port |
63c85238 PW |
1184 | * @oh: struct omap_hwmod * |
1185 | * | |
24dbc213 PW |
1186 | * Determines the array index of the OCP slave port that the MPU uses |
1187 | * to address the device, and saves it into the struct omap_hwmod. | |
1188 | * Intended to be called during hwmod registration only. No return | |
1189 | * value. | |
63c85238 | 1190 | */ |
24dbc213 | 1191 | static void __init _save_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 1192 | { |
24dbc213 | 1193 | struct omap_hwmod_ocp_if *os = NULL; |
11cd4b94 | 1194 | struct list_head *p; |
5d95dde7 | 1195 | int i = 0; |
63c85238 | 1196 | |
5d95dde7 | 1197 | if (!oh) |
24dbc213 PW |
1198 | return; |
1199 | ||
1200 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
63c85238 | 1201 | |
11cd4b94 | 1202 | p = oh->slave_ports.next; |
2221b5cd | 1203 | |
5d95dde7 | 1204 | while (i < oh->slaves_cnt) { |
11cd4b94 | 1205 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 1206 | if (os->user & OCP_USER_MPU) { |
2221b5cd | 1207 | oh->_mpu_port = os; |
24dbc213 | 1208 | oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; |
63c85238 PW |
1209 | break; |
1210 | } | |
1211 | } | |
1212 | ||
24dbc213 | 1213 | return; |
63c85238 PW |
1214 | } |
1215 | ||
2d6141ba PW |
1216 | /** |
1217 | * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU | |
1218 | * @oh: struct omap_hwmod * | |
1219 | * | |
1220 | * Given a pointer to a struct omap_hwmod record @oh, return a pointer | |
1221 | * to the struct omap_hwmod_ocp_if record that is used by the MPU to | |
1222 | * communicate with the IP block. This interface need not be directly | |
1223 | * connected to the MPU (and almost certainly is not), but is directly | |
1224 | * connected to the IP block represented by @oh. Returns a pointer | |
1225 | * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon | |
1226 | * error or if there does not appear to be a path from the MPU to this | |
1227 | * IP block. | |
1228 | */ | |
1229 | static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) | |
1230 | { | |
1231 | if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) | |
1232 | return NULL; | |
1233 | ||
11cd4b94 | 1234 | return oh->_mpu_port; |
2d6141ba PW |
1235 | }; |
1236 | ||
63c85238 | 1237 | /** |
c9aafd23 | 1238 | * _find_mpu_rt_addr_space - return MPU register target address space for @oh |
63c85238 PW |
1239 | * @oh: struct omap_hwmod * |
1240 | * | |
c9aafd23 PW |
1241 | * Returns a pointer to the struct omap_hwmod_addr_space record representing |
1242 | * the register target MPU address space; or returns NULL upon error. | |
63c85238 | 1243 | */ |
c9aafd23 | 1244 | static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) |
63c85238 PW |
1245 | { |
1246 | struct omap_hwmod_ocp_if *os; | |
1247 | struct omap_hwmod_addr_space *mem; | |
c9aafd23 | 1248 | int found = 0, i = 0; |
63c85238 | 1249 | |
2d6141ba | 1250 | os = _find_mpu_rt_port(oh); |
24dbc213 | 1251 | if (!os || !os->addr) |
78183f3f PW |
1252 | return NULL; |
1253 | ||
1254 | do { | |
1255 | mem = &os->addr[i++]; | |
1256 | if (mem->flags & ADDR_TYPE_RT) | |
63c85238 | 1257 | found = 1; |
78183f3f | 1258 | } while (!found && mem->pa_start != mem->pa_end); |
63c85238 | 1259 | |
c9aafd23 | 1260 | return (found) ? mem : NULL; |
63c85238 PW |
1261 | } |
1262 | ||
1263 | /** | |
74ff3a68 | 1264 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
1265 | * @oh: struct omap_hwmod * |
1266 | * | |
006c7f18 PW |
1267 | * Ensure that the OCP_SYSCONFIG register for the IP block represented |
1268 | * by @oh is set to indicate to the PRCM that the IP block is active. | |
1269 | * Usually this means placing the module into smart-idle mode and | |
1270 | * smart-standby, but if there is a bug in the automatic idle handling | |
1271 | * for the IP block, it may need to be placed into the force-idle or | |
1272 | * no-idle variants of these modes. No return value. | |
63c85238 | 1273 | */ |
74ff3a68 | 1274 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 1275 | { |
43b40992 | 1276 | u8 idlemode, sf; |
63c85238 | 1277 | u32 v; |
006c7f18 | 1278 | bool clkdm_act; |
63c85238 | 1279 | |
43b40992 | 1280 | if (!oh->class->sysc) |
63c85238 PW |
1281 | return; |
1282 | ||
1283 | v = oh->_sysc_cache; | |
43b40992 | 1284 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1285 | |
43b40992 | 1286 | if (sf & SYSC_HAS_SIDLEMODE) { |
006c7f18 PW |
1287 | clkdm_act = ((oh->clkdm && |
1288 | oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) || | |
1289 | (oh->_clk && oh->_clk->clkdm && | |
1290 | oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU)); | |
1291 | if (clkdm_act && !(oh->class->sysc->idlemodes & | |
1292 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1293 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1294 | else | |
1295 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | |
1296 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
63c85238 PW |
1297 | _set_slave_idlemode(oh, idlemode, &v); |
1298 | } | |
1299 | ||
43b40992 | 1300 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1301 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1302 | idlemode = HWMOD_IDLEMODE_NO; | |
1303 | } else { | |
1304 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1305 | _enable_wakeup(oh, &v); | |
1306 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1307 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1308 | else | |
1309 | idlemode = HWMOD_IDLEMODE_SMART; | |
1310 | } | |
63c85238 PW |
1311 | _set_master_standbymode(oh, idlemode, &v); |
1312 | } | |
1313 | ||
a16b1f7f PW |
1314 | /* |
1315 | * XXX The clock framework should handle this, by | |
1316 | * calling into this code. But this must wait until the | |
1317 | * clock structures are tagged with omap_hwmod entries | |
1318 | */ | |
43b40992 PW |
1319 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1320 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
1321 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 | 1322 | |
9980ce53 RN |
1323 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1324 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
5a7ddcbd KH |
1325 | _enable_wakeup(oh, &v); |
1326 | ||
1327 | _write_sysconfig(v, oh); | |
78f26e87 HH |
1328 | |
1329 | /* | |
1330 | * Set the autoidle bit only after setting the smartidle bit | |
1331 | * Setting this will not have any impact on the other modules. | |
1332 | */ | |
1333 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1334 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1335 | 0 : 1; | |
1336 | _set_module_autoidle(oh, idlemode, &v); | |
1337 | _write_sysconfig(v, oh); | |
1338 | } | |
63c85238 PW |
1339 | } |
1340 | ||
1341 | /** | |
74ff3a68 | 1342 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1343 | * @oh: struct omap_hwmod * |
1344 | * | |
1345 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1346 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1347 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1348 | * configure it for smart-standby. No return value. | |
1349 | */ | |
74ff3a68 | 1350 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1351 | { |
43b40992 | 1352 | u8 idlemode, sf; |
63c85238 PW |
1353 | u32 v; |
1354 | ||
43b40992 | 1355 | if (!oh->class->sysc) |
63c85238 PW |
1356 | return; |
1357 | ||
1358 | v = oh->_sysc_cache; | |
43b40992 | 1359 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1360 | |
43b40992 | 1361 | if (sf & SYSC_HAS_SIDLEMODE) { |
006c7f18 PW |
1362 | /* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */ |
1363 | if (oh->flags & HWMOD_SWSUP_SIDLE || | |
1364 | !(oh->class->sysc->idlemodes & | |
1365 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1366 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1367 | else | |
1368 | idlemode = HWMOD_IDLEMODE_SMART; | |
63c85238 PW |
1369 | _set_slave_idlemode(oh, idlemode, &v); |
1370 | } | |
1371 | ||
43b40992 | 1372 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1373 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1374 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1375 | } else { | |
1376 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1377 | _enable_wakeup(oh, &v); | |
1378 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1379 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1380 | else | |
1381 | idlemode = HWMOD_IDLEMODE_SMART; | |
1382 | } | |
63c85238 PW |
1383 | _set_master_standbymode(oh, idlemode, &v); |
1384 | } | |
1385 | ||
86009eb3 BC |
1386 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1387 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
1388 | _enable_wakeup(oh, &v); | |
1389 | ||
63c85238 PW |
1390 | _write_sysconfig(v, oh); |
1391 | } | |
1392 | ||
1393 | /** | |
74ff3a68 | 1394 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1395 | * @oh: struct omap_hwmod * |
1396 | * | |
1397 | * Force the module into slave idle and master suspend. No return | |
1398 | * value. | |
1399 | */ | |
74ff3a68 | 1400 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1401 | { |
1402 | u32 v; | |
43b40992 | 1403 | u8 sf; |
63c85238 | 1404 | |
43b40992 | 1405 | if (!oh->class->sysc) |
63c85238 PW |
1406 | return; |
1407 | ||
1408 | v = oh->_sysc_cache; | |
43b40992 | 1409 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1410 | |
43b40992 | 1411 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1412 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1413 | ||
43b40992 | 1414 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1415 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1416 | ||
43b40992 | 1417 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1418 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1419 | |
1420 | _write_sysconfig(v, oh); | |
1421 | } | |
1422 | ||
1423 | /** | |
1424 | * _lookup - find an omap_hwmod by name | |
1425 | * @name: find an omap_hwmod by name | |
1426 | * | |
1427 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1428 | */ |
1429 | static struct omap_hwmod *_lookup(const char *name) | |
1430 | { | |
1431 | struct omap_hwmod *oh, *temp_oh; | |
1432 | ||
1433 | oh = NULL; | |
1434 | ||
1435 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1436 | if (!strcmp(name, temp_oh->name)) { | |
1437 | oh = temp_oh; | |
1438 | break; | |
1439 | } | |
1440 | } | |
1441 | ||
1442 | return oh; | |
1443 | } | |
868c157d | 1444 | |
6ae76997 BC |
1445 | /** |
1446 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1447 | * @oh: struct omap_hwmod * | |
1448 | * | |
1449 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1450 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
868c157d | 1451 | * Return -EINVAL if the clkdm_name lookup failed. |
6ae76997 BC |
1452 | */ |
1453 | static int _init_clkdm(struct omap_hwmod *oh) | |
1454 | { | |
3bb05dbf PW |
1455 | if (!oh->clkdm_name) { |
1456 | pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name); | |
6ae76997 | 1457 | return 0; |
3bb05dbf | 1458 | } |
6ae76997 | 1459 | |
6ae76997 BC |
1460 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
1461 | if (!oh->clkdm) { | |
1462 | pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", | |
1463 | oh->name, oh->clkdm_name); | |
1464 | return -EINVAL; | |
1465 | } | |
1466 | ||
1467 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1468 | oh->name, oh->clkdm_name); | |
1469 | ||
1470 | return 0; | |
1471 | } | |
63c85238 PW |
1472 | |
1473 | /** | |
6ae76997 BC |
1474 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1475 | * well the clockdomain. | |
63c85238 | 1476 | * @oh: struct omap_hwmod * |
97d60162 | 1477 | * @data: not used; pass NULL |
63c85238 | 1478 | * |
a2debdbd | 1479 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1480 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1481 | * success, or a negative error code on failure. | |
63c85238 | 1482 | */ |
97d60162 | 1483 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
1484 | { |
1485 | int ret = 0; | |
1486 | ||
48d54f3f PW |
1487 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1488 | return 0; | |
63c85238 PW |
1489 | |
1490 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1491 | ||
1492 | ret |= _init_main_clk(oh); | |
1493 | ret |= _init_interface_clks(oh); | |
1494 | ret |= _init_opt_clks(oh); | |
0a179eaa KH |
1495 | if (soc_ops.init_clkdm) |
1496 | ret |= soc_ops.init_clkdm(oh); | |
63c85238 | 1497 | |
f5c1f84b BC |
1498 | if (!ret) |
1499 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a BC |
1500 | else |
1501 | pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name); | |
63c85238 | 1502 | |
09c35f2f | 1503 | return ret; |
63c85238 PW |
1504 | } |
1505 | ||
5365efbe | 1506 | /** |
cc1226e7 | 1507 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1508 | * @oh: struct omap_hwmod * |
1509 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1510 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1511 | * |
1512 | * Return the bit position of the reset line that match the | |
1513 | * input name. Return -ENOENT if not found. | |
1514 | */ | |
a032d33b PW |
1515 | static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1516 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1517 | { |
1518 | int i; | |
1519 | ||
1520 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1521 | const char *rst_line = oh->rst_lines[i].name; | |
1522 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1523 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1524 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1525 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1526 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1527 | ohri->st_shift); | |
5365efbe | 1528 | |
cc1226e7 | 1529 | return 0; |
5365efbe BC |
1530 | } |
1531 | } | |
1532 | ||
1533 | return -ENOENT; | |
1534 | } | |
1535 | ||
1536 | /** | |
1537 | * _assert_hardreset - assert the HW reset line of submodules | |
1538 | * contained in the hwmod module. | |
1539 | * @oh: struct omap_hwmod * | |
1540 | * @name: name of the reset line to lookup and assert | |
1541 | * | |
b8249cf2 KH |
1542 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1543 | * reset line to be assert / deassert in order to enable fully the IP. | |
1544 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1545 | * asserting the hardreset line on the currently-booted SoC, or passes | |
1546 | * along the return value from _lookup_hardreset() or the SoC's | |
1547 | * assert_hardreset code. | |
5365efbe BC |
1548 | */ |
1549 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1550 | { | |
cc1226e7 | 1551 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1552 | int ret = -EINVAL; |
5365efbe BC |
1553 | |
1554 | if (!oh) | |
1555 | return -EINVAL; | |
1556 | ||
b8249cf2 KH |
1557 | if (!soc_ops.assert_hardreset) |
1558 | return -ENOSYS; | |
1559 | ||
cc1226e7 | 1560 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1561 | if (ret < 0) |
cc1226e7 | 1562 | return ret; |
5365efbe | 1563 | |
b8249cf2 KH |
1564 | ret = soc_ops.assert_hardreset(oh, &ohri); |
1565 | ||
1566 | return ret; | |
5365efbe BC |
1567 | } |
1568 | ||
1569 | /** | |
1570 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1571 | * in the hwmod module. | |
1572 | * @oh: struct omap_hwmod * | |
1573 | * @name: name of the reset line to look up and deassert | |
1574 | * | |
b8249cf2 KH |
1575 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1576 | * reset line to be assert / deassert in order to enable fully the IP. | |
1577 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1578 | * deasserting the hardreset line on the currently-booted SoC, or passes | |
1579 | * along the return value from _lookup_hardreset() or the SoC's | |
1580 | * deassert_hardreset code. | |
5365efbe BC |
1581 | */ |
1582 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1583 | { | |
cc1226e7 | 1584 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1585 | int ret = -EINVAL; |
e8e96dff | 1586 | int hwsup = 0; |
5365efbe BC |
1587 | |
1588 | if (!oh) | |
1589 | return -EINVAL; | |
1590 | ||
b8249cf2 KH |
1591 | if (!soc_ops.deassert_hardreset) |
1592 | return -ENOSYS; | |
1593 | ||
cc1226e7 | 1594 | ret = _lookup_hardreset(oh, name, &ohri); |
1595 | if (IS_ERR_VALUE(ret)) | |
1596 | return ret; | |
5365efbe | 1597 | |
e8e96dff ORL |
1598 | if (oh->clkdm) { |
1599 | /* | |
1600 | * A clockdomain must be in SW_SUP otherwise reset | |
1601 | * might not be completed. The clockdomain can be set | |
1602 | * in HW_AUTO only when the module become ready. | |
1603 | */ | |
1604 | hwsup = clkdm_in_hwsup(oh->clkdm); | |
1605 | ret = clkdm_hwmod_enable(oh->clkdm, oh); | |
1606 | if (ret) { | |
1607 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1608 | oh->name, oh->clkdm->name, ret); | |
1609 | return ret; | |
1610 | } | |
1611 | } | |
1612 | ||
1613 | _enable_clocks(oh); | |
1614 | if (soc_ops.enable_module) | |
1615 | soc_ops.enable_module(oh); | |
1616 | ||
b8249cf2 | 1617 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
e8e96dff ORL |
1618 | |
1619 | if (soc_ops.disable_module) | |
1620 | soc_ops.disable_module(oh); | |
1621 | _disable_clocks(oh); | |
1622 | ||
cc1226e7 | 1623 | if (ret == -EBUSY) |
5365efbe BC |
1624 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); |
1625 | ||
e8e96dff ORL |
1626 | if (!ret) { |
1627 | /* | |
1628 | * Set the clockdomain to HW_AUTO, assuming that the | |
1629 | * previous state was HW_AUTO. | |
1630 | */ | |
1631 | if (oh->clkdm && hwsup) | |
1632 | clkdm_allow_idle(oh->clkdm); | |
1633 | } else { | |
1634 | if (oh->clkdm) | |
1635 | clkdm_hwmod_disable(oh->clkdm, oh); | |
1636 | } | |
1637 | ||
cc1226e7 | 1638 | return ret; |
5365efbe BC |
1639 | } |
1640 | ||
1641 | /** | |
1642 | * _read_hardreset - read the HW reset line state of submodules | |
1643 | * contained in the hwmod module | |
1644 | * @oh: struct omap_hwmod * | |
1645 | * @name: name of the reset line to look up and read | |
1646 | * | |
b8249cf2 KH |
1647 | * Return the state of the reset line. Returns -EINVAL if @oh is |
1648 | * null, -ENOSYS if we have no way of reading the hardreset line | |
1649 | * status on the currently-booted SoC, or passes along the return | |
1650 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | |
1651 | * code. | |
5365efbe BC |
1652 | */ |
1653 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1654 | { | |
cc1226e7 | 1655 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1656 | int ret = -EINVAL; |
5365efbe BC |
1657 | |
1658 | if (!oh) | |
1659 | return -EINVAL; | |
1660 | ||
b8249cf2 KH |
1661 | if (!soc_ops.is_hardreset_asserted) |
1662 | return -ENOSYS; | |
1663 | ||
cc1226e7 | 1664 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1665 | if (ret < 0) |
cc1226e7 | 1666 | return ret; |
5365efbe | 1667 | |
b8249cf2 | 1668 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
5365efbe BC |
1669 | } |
1670 | ||
747834ab | 1671 | /** |
eb05f691 | 1672 | * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset |
747834ab PW |
1673 | * @oh: struct omap_hwmod * |
1674 | * | |
eb05f691 ORL |
1675 | * If all hardreset lines associated with @oh are asserted, then return true. |
1676 | * Otherwise, if part of @oh is out hardreset or if no hardreset lines | |
1677 | * associated with @oh are asserted, then return false. | |
747834ab | 1678 | * This function is used to avoid executing some parts of the IP block |
eb05f691 | 1679 | * enable/disable sequence if its hardreset line is set. |
747834ab | 1680 | */ |
eb05f691 | 1681 | static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh) |
747834ab | 1682 | { |
eb05f691 | 1683 | int i, rst_cnt = 0; |
747834ab PW |
1684 | |
1685 | if (oh->rst_lines_cnt == 0) | |
1686 | return false; | |
1687 | ||
1688 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1689 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
eb05f691 ORL |
1690 | rst_cnt++; |
1691 | ||
1692 | if (oh->rst_lines_cnt == rst_cnt) | |
1693 | return true; | |
747834ab PW |
1694 | |
1695 | return false; | |
1696 | } | |
1697 | ||
e9332b6e PW |
1698 | /** |
1699 | * _are_any_hardreset_lines_asserted - return true if any part of @oh is | |
1700 | * hard-reset | |
1701 | * @oh: struct omap_hwmod * | |
1702 | * | |
1703 | * If any hardreset lines associated with @oh are asserted, then | |
1704 | * return true. Otherwise, if no hardreset lines associated with @oh | |
1705 | * are asserted, or if @oh has no hardreset lines, then return false. | |
1706 | * This function is used to avoid executing some parts of the IP block | |
1707 | * enable/disable sequence if any hardreset line is set. | |
1708 | */ | |
1709 | static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) | |
1710 | { | |
1711 | int rst_cnt = 0; | |
1712 | int i; | |
1713 | ||
1714 | for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++) | |
1715 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
1716 | rst_cnt++; | |
1717 | ||
1718 | return (rst_cnt) ? true : false; | |
1719 | } | |
1720 | ||
747834ab PW |
1721 | /** |
1722 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
1723 | * @oh: struct omap_hwmod * | |
1724 | * | |
1725 | * Disable the PRCM module mode related to the hwmod @oh. | |
1726 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1727 | */ | |
1728 | static int _omap4_disable_module(struct omap_hwmod *oh) | |
1729 | { | |
1730 | int v; | |
1731 | ||
747834ab PW |
1732 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
1733 | return -EINVAL; | |
1734 | ||
eb05f691 ORL |
1735 | /* |
1736 | * Since integration code might still be doing something, only | |
1737 | * disable if all lines are under hardreset. | |
1738 | */ | |
e9332b6e | 1739 | if (_are_any_hardreset_lines_asserted(oh)) |
eb05f691 ORL |
1740 | return 0; |
1741 | ||
747834ab PW |
1742 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); |
1743 | ||
1744 | omap4_cminst_module_disable(oh->clkdm->prcm_partition, | |
1745 | oh->clkdm->cm_inst, | |
1746 | oh->clkdm->clkdm_offs, | |
1747 | oh->prcm.omap4.clkctrl_offs); | |
1748 | ||
747834ab PW |
1749 | v = _omap4_wait_target_disable(oh); |
1750 | if (v) | |
1751 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1752 | oh->name); | |
1753 | ||
1754 | return 0; | |
1755 | } | |
1756 | ||
1688bf19 VH |
1757 | /** |
1758 | * _am33xx_disable_module - enable CLKCTRL modulemode on AM33XX | |
1759 | * @oh: struct omap_hwmod * | |
1760 | * | |
1761 | * Disable the PRCM module mode related to the hwmod @oh. | |
1762 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1763 | */ | |
1764 | static int _am33xx_disable_module(struct omap_hwmod *oh) | |
1765 | { | |
1766 | int v; | |
1767 | ||
1768 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
1769 | return -EINVAL; | |
1770 | ||
1771 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); | |
1772 | ||
e9332b6e PW |
1773 | if (_are_any_hardreset_lines_asserted(oh)) |
1774 | return 0; | |
1775 | ||
1688bf19 VH |
1776 | am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs, |
1777 | oh->prcm.omap4.clkctrl_offs); | |
1778 | ||
1688bf19 VH |
1779 | v = _am33xx_wait_target_disable(oh); |
1780 | if (v) | |
1781 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1782 | oh->name); | |
1783 | ||
1784 | return 0; | |
1785 | } | |
1786 | ||
63c85238 | 1787 | /** |
bd36179e | 1788 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1789 | * @oh: struct omap_hwmod * |
1790 | * | |
1791 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1792 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1793 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1794 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1795 | * |
1796 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1797 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1798 | * use the SYSCONFIG softreset bit to provide the status. |
1799 | * | |
bd36179e PW |
1800 | * Note that some IP like McBSP do have reset control but don't have |
1801 | * reset status. | |
63c85238 | 1802 | */ |
bd36179e | 1803 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1804 | { |
387ca5bf | 1805 | u32 v, softrst_mask; |
6f8b7ff5 | 1806 | int c = 0; |
96835af9 | 1807 | int ret = 0; |
63c85238 | 1808 | |
43b40992 | 1809 | if (!oh->class->sysc || |
2cb06814 | 1810 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1811 | return -ENOENT; |
63c85238 PW |
1812 | |
1813 | /* clocks must be on for this operation */ | |
1814 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
7852ec05 PW |
1815 | pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n", |
1816 | oh->name); | |
63c85238 PW |
1817 | return -EINVAL; |
1818 | } | |
1819 | ||
96835af9 BC |
1820 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1821 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1822 | _enable_optional_clocks(oh); | |
1823 | ||
bd36179e | 1824 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1825 | |
1826 | v = oh->_sysc_cache; | |
96835af9 BC |
1827 | ret = _set_softreset(oh, &v); |
1828 | if (ret) | |
1829 | goto dis_opt_clks; | |
63c85238 PW |
1830 | _write_sysconfig(v, oh); |
1831 | ||
d99de7f5 FGL |
1832 | if (oh->class->sysc->srst_udelay) |
1833 | udelay(oh->class->sysc->srst_udelay); | |
1834 | ||
2cb06814 | 1835 | if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) |
cc7a1d2a | 1836 | omap_test_timeout((omap_hwmod_read(oh, |
2cb06814 BC |
1837 | oh->class->sysc->syss_offs) |
1838 | & SYSS_RESETDONE_MASK), | |
1839 | MAX_MODULE_SOFTRESET_WAIT, c); | |
387ca5bf RN |
1840 | else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { |
1841 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | |
cc7a1d2a | 1842 | omap_test_timeout(!(omap_hwmod_read(oh, |
2cb06814 | 1843 | oh->class->sysc->sysc_offs) |
387ca5bf | 1844 | & softrst_mask), |
2cb06814 | 1845 | MAX_MODULE_SOFTRESET_WAIT, c); |
387ca5bf | 1846 | } |
63c85238 | 1847 | |
5365efbe | 1848 | if (c == MAX_MODULE_SOFTRESET_WAIT) |
76e5589e BC |
1849 | pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1850 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
63c85238 | 1851 | else |
5365efbe | 1852 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
63c85238 PW |
1853 | |
1854 | /* | |
1855 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1856 | * _wait_target_ready() or _reset() | |
1857 | */ | |
1858 | ||
96835af9 BC |
1859 | ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; |
1860 | ||
1861 | dis_opt_clks: | |
1862 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1863 | _disable_optional_clocks(oh); | |
1864 | ||
1865 | return ret; | |
63c85238 PW |
1866 | } |
1867 | ||
bd36179e PW |
1868 | /** |
1869 | * _reset - reset an omap_hwmod | |
1870 | * @oh: struct omap_hwmod * | |
1871 | * | |
30e105c0 PW |
1872 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1873 | * function pointer defined, then call it to reset the IP block, and | |
1874 | * pass along its return value to the caller. Otherwise, if the IP | |
1875 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1876 | * associated with it, call a function to reset the IP block via that | |
1877 | * method, and pass along the return value to the caller. Finally, if | |
1878 | * the IP block has some hardreset lines associated with it, assert | |
1879 | * all of those, but do _not_ deassert them. (This is because driver | |
1880 | * authors have expressed an apparent requirement to control the | |
1881 | * deassertion of the hardreset lines themselves.) | |
1882 | * | |
1883 | * The default software reset mechanism for most OMAP IP blocks is | |
1884 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1885 | * hwmods cannot be reset via this method. Some are not targets and | |
1886 | * therefore have no OCP header registers to access. Others (like the | |
1887 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
1888 | * rare cases, custom reset code can be supplied in the struct | |
6668546f KVA |
1889 | * omap_hwmod_class .reset function pointer. |
1890 | * | |
1891 | * _set_dmadisable() is called to set the DMADISABLE bit so that it | |
1892 | * does not prevent idling of the system. This is necessary for cases | |
1893 | * where ROMCODE/BOOTLOADER uses dma and transfers control to the | |
1894 | * kernel without disabling dma. | |
1895 | * | |
1896 | * Passes along the return value from either _ocp_softreset() or the | |
1897 | * custom reset function - these must return -EINVAL if the hwmod | |
1898 | * cannot be reset this way or if the hwmod is in the wrong state, | |
1899 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
bd36179e PW |
1900 | */ |
1901 | static int _reset(struct omap_hwmod *oh) | |
1902 | { | |
30e105c0 | 1903 | int i, r; |
bd36179e PW |
1904 | |
1905 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1906 | ||
30e105c0 PW |
1907 | if (oh->class->reset) { |
1908 | r = oh->class->reset(oh); | |
1909 | } else { | |
1910 | if (oh->rst_lines_cnt > 0) { | |
1911 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1912 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
1913 | return 0; | |
1914 | } else { | |
1915 | r = _ocp_softreset(oh); | |
1916 | if (r == -ENOENT) | |
1917 | r = 0; | |
1918 | } | |
1919 | } | |
1920 | ||
6668546f KVA |
1921 | _set_dmadisable(oh); |
1922 | ||
9c8b0ec7 | 1923 | /* |
30e105c0 PW |
1924 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
1925 | * softreset. The _enable() function should be split to avoid | |
1926 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 1927 | */ |
2800852a RN |
1928 | if (oh->class->sysc) { |
1929 | _update_sysc_cache(oh); | |
1930 | _enable_sysc(oh); | |
1931 | } | |
1932 | ||
30e105c0 | 1933 | return r; |
bd36179e PW |
1934 | } |
1935 | ||
5165882a VB |
1936 | /** |
1937 | * _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain | |
1938 | * | |
1939 | * Call the appropriate PRM function to clear any logged I/O chain | |
1940 | * wakeups and to reconfigure the chain. This apparently needs to be | |
1941 | * done upon every mux change. Since hwmods can be concurrently | |
1942 | * enabled and idled, hold a spinlock around the I/O chain | |
1943 | * reconfiguration sequence. No return value. | |
1944 | * | |
1945 | * XXX When the PRM code is moved to drivers, this function can be removed, | |
1946 | * as the PRM infrastructure should abstract this. | |
1947 | */ | |
1948 | static void _reconfigure_io_chain(void) | |
1949 | { | |
1950 | unsigned long flags; | |
1951 | ||
1952 | spin_lock_irqsave(&io_chain_lock, flags); | |
1953 | ||
1954 | if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl()) | |
1955 | omap3xxx_prm_reconfigure_io_chain(); | |
1956 | else if (cpu_is_omap44xx()) | |
1957 | omap44xx_prm_reconfigure_io_chain(); | |
1958 | ||
1959 | spin_unlock_irqrestore(&io_chain_lock, flags); | |
1960 | } | |
1961 | ||
63c85238 | 1962 | /** |
dc6d1cda | 1963 | * _enable - enable an omap_hwmod |
63c85238 PW |
1964 | * @oh: struct omap_hwmod * |
1965 | * | |
1966 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
1967 | * register target. Returns -EINVAL if the hwmod is in the wrong |
1968 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 1969 | */ |
dc6d1cda | 1970 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 1971 | { |
747834ab | 1972 | int r; |
665d0013 | 1973 | int hwsup = 0; |
63c85238 | 1974 | |
34617e2a BC |
1975 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
1976 | ||
aacf0941 | 1977 | /* |
64813c3f PW |
1978 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled |
1979 | * state at init. Now that someone is really trying to enable | |
1980 | * them, just ensure that the hwmod mux is set. | |
aacf0941 RN |
1981 | */ |
1982 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
1983 | /* | |
1984 | * If the caller has mux data populated, do the mux'ing | |
1985 | * which wouldn't have been done as part of the _enable() | |
1986 | * done during setup. | |
1987 | */ | |
1988 | if (oh->mux) | |
1989 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
1990 | ||
1991 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; | |
1992 | return 0; | |
1993 | } | |
1994 | ||
63c85238 PW |
1995 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
1996 | oh->_state != _HWMOD_STATE_IDLE && | |
1997 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
1998 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
1999 | oh->name); | |
63c85238 PW |
2000 | return -EINVAL; |
2001 | } | |
2002 | ||
31f62866 | 2003 | /* |
eb05f691 | 2004 | * If an IP block contains HW reset lines and all of them are |
747834ab PW |
2005 | * asserted, we let integration code associated with that |
2006 | * block handle the enable. We've received very little | |
2007 | * information on what those driver authors need, and until | |
2008 | * detailed information is provided and the driver code is | |
2009 | * posted to the public lists, this is probably the best we | |
2010 | * can do. | |
31f62866 | 2011 | */ |
eb05f691 | 2012 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab | 2013 | return 0; |
63c85238 | 2014 | |
665d0013 RN |
2015 | /* Mux pins for device runtime if populated */ |
2016 | if (oh->mux && (!oh->mux->enabled || | |
2017 | ((oh->_state == _HWMOD_STATE_IDLE) && | |
5165882a | 2018 | oh->mux->pads_dynamic))) { |
665d0013 | 2019 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); |
5165882a VB |
2020 | _reconfigure_io_chain(); |
2021 | } | |
665d0013 RN |
2022 | |
2023 | _add_initiator_dep(oh, mpu_oh); | |
34617e2a | 2024 | |
665d0013 RN |
2025 | if (oh->clkdm) { |
2026 | /* | |
2027 | * A clockdomain must be in SW_SUP before enabling | |
2028 | * completely the module. The clockdomain can be set | |
2029 | * in HW_AUTO only when the module become ready. | |
2030 | */ | |
b71c7217 PW |
2031 | hwsup = clkdm_in_hwsup(oh->clkdm) && |
2032 | !clkdm_missing_idle_reporting(oh->clkdm); | |
665d0013 RN |
2033 | r = clkdm_hwmod_enable(oh->clkdm, oh); |
2034 | if (r) { | |
2035 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
2036 | oh->name, oh->clkdm->name, r); | |
2037 | return r; | |
2038 | } | |
34617e2a | 2039 | } |
665d0013 RN |
2040 | |
2041 | _enable_clocks(oh); | |
9ebfd285 KH |
2042 | if (soc_ops.enable_module) |
2043 | soc_ops.enable_module(oh); | |
34617e2a | 2044 | |
8f6aa8ee KH |
2045 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
2046 | -EINVAL; | |
665d0013 RN |
2047 | if (!r) { |
2048 | /* | |
2049 | * Set the clockdomain to HW_AUTO only if the target is ready, | |
2050 | * assuming that the previous state was HW_AUTO | |
2051 | */ | |
2052 | if (oh->clkdm && hwsup) | |
2053 | clkdm_allow_idle(oh->clkdm); | |
2054 | ||
2055 | oh->_state = _HWMOD_STATE_ENABLED; | |
2056 | ||
2057 | /* Access the sysconfig only if the target is ready */ | |
2058 | if (oh->class->sysc) { | |
2059 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
2060 | _update_sysc_cache(oh); | |
2061 | _enable_sysc(oh); | |
2062 | } | |
2063 | } else { | |
2577a4a6 PW |
2064 | if (soc_ops.disable_module) |
2065 | soc_ops.disable_module(oh); | |
665d0013 RN |
2066 | _disable_clocks(oh); |
2067 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | |
2068 | oh->name, r); | |
34617e2a | 2069 | |
665d0013 RN |
2070 | if (oh->clkdm) |
2071 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
2072 | } |
2073 | ||
63c85238 PW |
2074 | return r; |
2075 | } | |
2076 | ||
2077 | /** | |
dc6d1cda | 2078 | * _idle - idle an omap_hwmod |
63c85238 PW |
2079 | * @oh: struct omap_hwmod * |
2080 | * | |
2081 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
2082 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
2083 | * state or returns 0. | |
63c85238 | 2084 | */ |
dc6d1cda | 2085 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 2086 | { |
34617e2a BC |
2087 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
2088 | ||
63c85238 | 2089 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
2090 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
2091 | oh->name); | |
63c85238 PW |
2092 | return -EINVAL; |
2093 | } | |
2094 | ||
eb05f691 | 2095 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab PW |
2096 | return 0; |
2097 | ||
43b40992 | 2098 | if (oh->class->sysc) |
74ff3a68 | 2099 | _idle_sysc(oh); |
63c85238 | 2100 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 | 2101 | |
9ebfd285 KH |
2102 | if (soc_ops.disable_module) |
2103 | soc_ops.disable_module(oh); | |
bfc141e3 | 2104 | |
45c38252 BC |
2105 | /* |
2106 | * The module must be in idle mode before disabling any parents | |
2107 | * clocks. Otherwise, the parent clock might be disabled before | |
2108 | * the module transition is done, and thus will prevent the | |
2109 | * transition to complete properly. | |
2110 | */ | |
2111 | _disable_clocks(oh); | |
665d0013 RN |
2112 | if (oh->clkdm) |
2113 | clkdm_hwmod_disable(oh->clkdm, oh); | |
63c85238 | 2114 | |
8d9af88f | 2115 | /* Mux pins for device idle if populated */ |
5165882a | 2116 | if (oh->mux && oh->mux->pads_dynamic) { |
8d9af88f | 2117 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); |
5165882a VB |
2118 | _reconfigure_io_chain(); |
2119 | } | |
8d9af88f | 2120 | |
63c85238 PW |
2121 | oh->_state = _HWMOD_STATE_IDLE; |
2122 | ||
2123 | return 0; | |
2124 | } | |
2125 | ||
9599217a KVA |
2126 | /** |
2127 | * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit | |
2128 | * @oh: struct omap_hwmod * | |
2129 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
2130 | * | |
2131 | * Sets the IP block's OCP autoidle bit in hardware, and updates our | |
2132 | * local copy. Intended to be used by drivers that require | |
2133 | * direct manipulation of the AUTOIDLE bits. | |
2134 | * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes | |
2135 | * along the return value from _set_module_autoidle(). | |
2136 | * | |
2137 | * Any users of this function should be scrutinized carefully. | |
2138 | */ | |
2139 | int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) | |
2140 | { | |
2141 | u32 v; | |
2142 | int retval = 0; | |
2143 | unsigned long flags; | |
2144 | ||
2145 | if (!oh || oh->_state != _HWMOD_STATE_ENABLED) | |
2146 | return -EINVAL; | |
2147 | ||
2148 | spin_lock_irqsave(&oh->_lock, flags); | |
2149 | ||
2150 | v = oh->_sysc_cache; | |
2151 | ||
2152 | retval = _set_module_autoidle(oh, autoidle, &v); | |
2153 | ||
2154 | if (!retval) | |
2155 | _write_sysconfig(v, oh); | |
2156 | ||
2157 | spin_unlock_irqrestore(&oh->_lock, flags); | |
2158 | ||
2159 | return retval; | |
2160 | } | |
2161 | ||
63c85238 PW |
2162 | /** |
2163 | * _shutdown - shutdown an omap_hwmod | |
2164 | * @oh: struct omap_hwmod * | |
2165 | * | |
2166 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
2167 | * used for the hwmod is removed or unloaded or if the driver is not | |
2168 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
2169 | * state or returns 0. | |
2170 | */ | |
2171 | static int _shutdown(struct omap_hwmod *oh) | |
2172 | { | |
9c8b0ec7 | 2173 | int ret, i; |
e4dc8f50 PW |
2174 | u8 prev_state; |
2175 | ||
63c85238 PW |
2176 | if (oh->_state != _HWMOD_STATE_IDLE && |
2177 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
2178 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
2179 | oh->name); | |
63c85238 PW |
2180 | return -EINVAL; |
2181 | } | |
2182 | ||
eb05f691 | 2183 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab PW |
2184 | return 0; |
2185 | ||
63c85238 PW |
2186 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); |
2187 | ||
e4dc8f50 PW |
2188 | if (oh->class->pre_shutdown) { |
2189 | prev_state = oh->_state; | |
2190 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2191 | _enable(oh); |
e4dc8f50 PW |
2192 | ret = oh->class->pre_shutdown(oh); |
2193 | if (ret) { | |
2194 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2195 | _idle(oh); |
e4dc8f50 PW |
2196 | return ret; |
2197 | } | |
2198 | } | |
2199 | ||
6481c73c MV |
2200 | if (oh->class->sysc) { |
2201 | if (oh->_state == _HWMOD_STATE_IDLE) | |
2202 | _enable(oh); | |
74ff3a68 | 2203 | _shutdown_sysc(oh); |
6481c73c | 2204 | } |
5365efbe | 2205 | |
3827f949 BC |
2206 | /* clocks and deps are already disabled in idle */ |
2207 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
2208 | _del_initiator_dep(oh, mpu_oh); | |
2209 | /* XXX what about the other system initiators here? dma, dsp */ | |
9ebfd285 KH |
2210 | if (soc_ops.disable_module) |
2211 | soc_ops.disable_module(oh); | |
45c38252 | 2212 | _disable_clocks(oh); |
665d0013 RN |
2213 | if (oh->clkdm) |
2214 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 2215 | } |
63c85238 PW |
2216 | /* XXX Should this code also force-disable the optional clocks? */ |
2217 | ||
9c8b0ec7 PW |
2218 | for (i = 0; i < oh->rst_lines_cnt; i++) |
2219 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 2220 | |
8d9af88f TL |
2221 | /* Mux pins to safe mode or use populated off mode values */ |
2222 | if (oh->mux) | |
2223 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); | |
63c85238 PW |
2224 | |
2225 | oh->_state = _HWMOD_STATE_DISABLED; | |
2226 | ||
2227 | return 0; | |
2228 | } | |
2229 | ||
381d033a PW |
2230 | /** |
2231 | * _init_mpu_rt_base - populate the virtual address for a hwmod | |
2232 | * @oh: struct omap_hwmod * to locate the virtual address | |
2233 | * | |
2234 | * Cache the virtual address used by the MPU to access this IP block's | |
2235 | * registers. This address is needed early so the OCP registers that | |
2236 | * are part of the device's address space can be ioremapped properly. | |
2237 | * No return value. | |
2238 | */ | |
2239 | static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) | |
2240 | { | |
c9aafd23 PW |
2241 | struct omap_hwmod_addr_space *mem; |
2242 | void __iomem *va_start; | |
2243 | ||
2244 | if (!oh) | |
2245 | return; | |
2246 | ||
2221b5cd PW |
2247 | _save_mpu_port_index(oh); |
2248 | ||
381d033a PW |
2249 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
2250 | return; | |
2251 | ||
c9aafd23 PW |
2252 | mem = _find_mpu_rt_addr_space(oh); |
2253 | if (!mem) { | |
2254 | pr_debug("omap_hwmod: %s: no MPU register target found\n", | |
2255 | oh->name); | |
2256 | return; | |
2257 | } | |
2258 | ||
2259 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
2260 | if (!va_start) { | |
2261 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
2262 | return; | |
2263 | } | |
2264 | ||
2265 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | |
2266 | oh->name, va_start); | |
2267 | ||
2268 | oh->_mpu_rt_va = va_start; | |
381d033a PW |
2269 | } |
2270 | ||
2271 | /** | |
2272 | * _init - initialize internal data for the hwmod @oh | |
2273 | * @oh: struct omap_hwmod * | |
2274 | * @n: (unused) | |
2275 | * | |
2276 | * Look up the clocks and the address space used by the MPU to access | |
2277 | * registers belonging to the hwmod @oh. @oh must already be | |
2278 | * registered at this point. This is the first of two phases for | |
2279 | * hwmod initialization. Code called here does not touch any hardware | |
2280 | * registers, it simply prepares internal data structures. Returns 0 | |
2281 | * upon success or if the hwmod isn't registered, or -EINVAL upon | |
2282 | * failure. | |
2283 | */ | |
2284 | static int __init _init(struct omap_hwmod *oh, void *data) | |
2285 | { | |
2286 | int r; | |
2287 | ||
2288 | if (oh->_state != _HWMOD_STATE_REGISTERED) | |
2289 | return 0; | |
2290 | ||
2291 | _init_mpu_rt_base(oh, NULL); | |
2292 | ||
2293 | r = _init_clocks(oh, NULL); | |
2294 | if (IS_ERR_VALUE(r)) { | |
2295 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); | |
2296 | return -EINVAL; | |
2297 | } | |
2298 | ||
2299 | oh->_state = _HWMOD_STATE_INITIALIZED; | |
2300 | ||
2301 | return 0; | |
2302 | } | |
2303 | ||
63c85238 | 2304 | /** |
64813c3f | 2305 | * _setup_iclk_autoidle - configure an IP block's interface clocks |
63c85238 PW |
2306 | * @oh: struct omap_hwmod * |
2307 | * | |
64813c3f PW |
2308 | * Set up the module's interface clocks. XXX This function is still mostly |
2309 | * a stub; implementing this properly requires iclk autoidle usecounting in | |
2310 | * the clock code. No return value. | |
63c85238 | 2311 | */ |
64813c3f | 2312 | static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) |
63c85238 | 2313 | { |
5d95dde7 | 2314 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 2315 | struct list_head *p; |
5d95dde7 | 2316 | int i = 0; |
381d033a | 2317 | if (oh->_state != _HWMOD_STATE_INITIALIZED) |
64813c3f | 2318 | return; |
48d54f3f | 2319 | |
11cd4b94 | 2320 | p = oh->slave_ports.next; |
63c85238 | 2321 | |
5d95dde7 | 2322 | while (i < oh->slaves_cnt) { |
11cd4b94 | 2323 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 | 2324 | if (!os->_clk) |
64813c3f | 2325 | continue; |
63c85238 | 2326 | |
64813c3f PW |
2327 | if (os->flags & OCPIF_SWSUP_IDLE) { |
2328 | /* XXX omap_iclk_deny_idle(c); */ | |
2329 | } else { | |
2330 | /* XXX omap_iclk_allow_idle(c); */ | |
5d95dde7 | 2331 | clk_enable(os->_clk); |
63c85238 PW |
2332 | } |
2333 | } | |
2334 | ||
64813c3f PW |
2335 | return; |
2336 | } | |
2337 | ||
2338 | /** | |
2339 | * _setup_reset - reset an IP block during the setup process | |
2340 | * @oh: struct omap_hwmod * | |
2341 | * | |
2342 | * Reset the IP block corresponding to the hwmod @oh during the setup | |
2343 | * process. The IP block is first enabled so it can be successfully | |
2344 | * reset. Returns 0 upon success or a negative error code upon | |
2345 | * failure. | |
2346 | */ | |
2347 | static int __init _setup_reset(struct omap_hwmod *oh) | |
2348 | { | |
2349 | int r; | |
2350 | ||
2351 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2352 | return -EINVAL; | |
63c85238 | 2353 | |
747834ab PW |
2354 | if (oh->rst_lines_cnt == 0) { |
2355 | r = _enable(oh); | |
2356 | if (r) { | |
2357 | pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", | |
2358 | oh->name, oh->_state); | |
2359 | return -EINVAL; | |
2360 | } | |
9a23dfe1 | 2361 | } |
63c85238 | 2362 | |
2800852a | 2363 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
64813c3f PW |
2364 | r = _reset(oh); |
2365 | ||
2366 | return r; | |
2367 | } | |
2368 | ||
2369 | /** | |
2370 | * _setup_postsetup - transition to the appropriate state after _setup | |
2371 | * @oh: struct omap_hwmod * | |
2372 | * | |
2373 | * Place an IP block represented by @oh into a "post-setup" state -- | |
2374 | * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that | |
2375 | * this function is called at the end of _setup().) The postsetup | |
2376 | * state for an IP block can be changed by calling | |
2377 | * omap_hwmod_enter_postsetup_state() early in the boot process, | |
2378 | * before one of the omap_hwmod_setup*() functions are called for the | |
2379 | * IP block. | |
2380 | * | |
2381 | * The IP block stays in this state until a PM runtime-based driver is | |
2382 | * loaded for that IP block. A post-setup state of IDLE is | |
2383 | * appropriate for almost all IP blocks with runtime PM-enabled | |
2384 | * drivers, since those drivers are able to enable the IP block. A | |
2385 | * post-setup state of ENABLED is appropriate for kernels with PM | |
2386 | * runtime disabled. The DISABLED state is appropriate for unusual IP | |
2387 | * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers | |
2388 | * included, since the WDTIMER starts running on reset and will reset | |
2389 | * the MPU if left active. | |
2390 | * | |
2391 | * This post-setup mechanism is deprecated. Once all of the OMAP | |
2392 | * drivers have been converted to use PM runtime, and all of the IP | |
2393 | * block data and interconnect data is available to the hwmod code, it | |
2394 | * should be possible to replace this mechanism with a "lazy reset" | |
2395 | * arrangement. In a "lazy reset" setup, each IP block is enabled | |
2396 | * when the driver first probes, then all remaining IP blocks without | |
2397 | * drivers are either shut down or enabled after the drivers have | |
2398 | * loaded. However, this cannot take place until the above | |
2399 | * preconditions have been met, since otherwise the late reset code | |
2400 | * has no way of knowing which IP blocks are in use by drivers, and | |
2401 | * which ones are unused. | |
2402 | * | |
2403 | * No return value. | |
2404 | */ | |
2405 | static void __init _setup_postsetup(struct omap_hwmod *oh) | |
2406 | { | |
2407 | u8 postsetup_state; | |
2408 | ||
2409 | if (oh->rst_lines_cnt > 0) | |
2410 | return; | |
76e5589e | 2411 | |
2092e5cc PW |
2412 | postsetup_state = oh->_postsetup_state; |
2413 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
2414 | postsetup_state = _HWMOD_STATE_ENABLED; | |
2415 | ||
2416 | /* | |
2417 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
2418 | * it should be set by the core code as a runtime flag during startup | |
2419 | */ | |
2420 | if ((oh->flags & HWMOD_INIT_NO_IDLE) && | |
aacf0941 RN |
2421 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
2422 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 2423 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 2424 | } |
2092e5cc PW |
2425 | |
2426 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2427 | _idle(oh); |
2092e5cc PW |
2428 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
2429 | _shutdown(oh); | |
2430 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2431 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2432 | oh->name, postsetup_state); | |
63c85238 | 2433 | |
64813c3f PW |
2434 | return; |
2435 | } | |
2436 | ||
2437 | /** | |
2438 | * _setup - prepare IP block hardware for use | |
2439 | * @oh: struct omap_hwmod * | |
2440 | * @n: (unused, pass NULL) | |
2441 | * | |
2442 | * Configure the IP block represented by @oh. This may include | |
2443 | * enabling the IP block, resetting it, and placing it into a | |
2444 | * post-setup state, depending on the type of IP block and applicable | |
2445 | * flags. IP blocks are reset to prevent any previous configuration | |
2446 | * by the bootloader or previous operating system from interfering | |
2447 | * with power management or other parts of the system. The reset can | |
2448 | * be avoided; see omap_hwmod_no_setup_reset(). This is the second of | |
2449 | * two phases for hwmod initialization. Code called here generally | |
2450 | * affects the IP block hardware, or system integration hardware | |
2451 | * associated with the IP block. Returns 0. | |
2452 | */ | |
2453 | static int __init _setup(struct omap_hwmod *oh, void *data) | |
2454 | { | |
2455 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2456 | return 0; | |
2457 | ||
2458 | _setup_iclk_autoidle(oh); | |
2459 | ||
2460 | if (!_setup_reset(oh)) | |
2461 | _setup_postsetup(oh); | |
2462 | ||
63c85238 PW |
2463 | return 0; |
2464 | } | |
2465 | ||
63c85238 | 2466 | /** |
0102b627 | 2467 | * _register - register a struct omap_hwmod |
63c85238 PW |
2468 | * @oh: struct omap_hwmod * |
2469 | * | |
43b40992 PW |
2470 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
2471 | * already has been registered by the same name; -EINVAL if the | |
2472 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
2473 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
2474 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
2475 | * success. | |
63c85238 PW |
2476 | * |
2477 | * XXX The data should be copied into bootmem, so the original data | |
2478 | * should be marked __initdata and freed after init. This would allow | |
2479 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
2480 | * that the copy process would be relatively complex due to the large number | |
2481 | * of substructures. | |
2482 | */ | |
01592df9 | 2483 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 2484 | { |
43b40992 PW |
2485 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
2486 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
2487 | return -EINVAL; |
2488 | ||
63c85238 PW |
2489 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
2490 | ||
ce35b244 BC |
2491 | if (_lookup(oh->name)) |
2492 | return -EEXIST; | |
63c85238 | 2493 | |
63c85238 PW |
2494 | list_add_tail(&oh->node, &omap_hwmod_list); |
2495 | ||
2221b5cd PW |
2496 | INIT_LIST_HEAD(&oh->master_ports); |
2497 | INIT_LIST_HEAD(&oh->slave_ports); | |
dc6d1cda | 2498 | spin_lock_init(&oh->_lock); |
2092e5cc | 2499 | |
63c85238 PW |
2500 | oh->_state = _HWMOD_STATE_REGISTERED; |
2501 | ||
569edd70 PW |
2502 | /* |
2503 | * XXX Rather than doing a strcmp(), this should test a flag | |
2504 | * set in the hwmod data, inserted by the autogenerator code. | |
2505 | */ | |
2506 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
2507 | mpu_oh = oh; | |
63c85238 | 2508 | |
569edd70 | 2509 | return 0; |
63c85238 PW |
2510 | } |
2511 | ||
2221b5cd PW |
2512 | /** |
2513 | * _alloc_links - return allocated memory for hwmod links | |
2514 | * @ml: pointer to a struct omap_hwmod_link * for the master link | |
2515 | * @sl: pointer to a struct omap_hwmod_link * for the slave link | |
2516 | * | |
2517 | * Return pointers to two struct omap_hwmod_link records, via the | |
2518 | * addresses pointed to by @ml and @sl. Will first attempt to return | |
2519 | * memory allocated as part of a large initial block, but if that has | |
2520 | * been exhausted, will allocate memory itself. Since ideally this | |
2521 | * second allocation path will never occur, the number of these | |
2522 | * 'supplemental' allocations will be logged when debugging is | |
2523 | * enabled. Returns 0. | |
2524 | */ | |
2525 | static int __init _alloc_links(struct omap_hwmod_link **ml, | |
2526 | struct omap_hwmod_link **sl) | |
2527 | { | |
2528 | unsigned int sz; | |
2529 | ||
2530 | if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) { | |
2531 | *ml = &linkspace[free_ls++]; | |
2532 | *sl = &linkspace[free_ls++]; | |
2533 | return 0; | |
2534 | } | |
2535 | ||
2536 | sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; | |
2537 | ||
2538 | *sl = NULL; | |
2539 | *ml = alloc_bootmem(sz); | |
2540 | ||
2541 | memset(*ml, 0, sz); | |
2542 | ||
2543 | *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); | |
2544 | ||
2545 | ls_supp++; | |
2546 | pr_debug("omap_hwmod: supplemental link allocations needed: %d\n", | |
2547 | ls_supp * LINKS_PER_OCP_IF); | |
2548 | ||
2549 | return 0; | |
2550 | }; | |
2551 | ||
2552 | /** | |
2553 | * _add_link - add an interconnect between two IP blocks | |
2554 | * @oi: pointer to a struct omap_hwmod_ocp_if record | |
2555 | * | |
2556 | * Add struct omap_hwmod_link records connecting the master IP block | |
2557 | * specified in @oi->master to @oi, and connecting the slave IP block | |
2558 | * specified in @oi->slave to @oi. This code is assumed to run before | |
2559 | * preemption or SMP has been enabled, thus avoiding the need for | |
2560 | * locking in this code. Changes to this assumption will require | |
2561 | * additional locking. Returns 0. | |
2562 | */ | |
2563 | static int __init _add_link(struct omap_hwmod_ocp_if *oi) | |
2564 | { | |
2565 | struct omap_hwmod_link *ml, *sl; | |
2566 | ||
2567 | pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, | |
2568 | oi->slave->name); | |
2569 | ||
2570 | _alloc_links(&ml, &sl); | |
2571 | ||
2572 | ml->ocp_if = oi; | |
2573 | INIT_LIST_HEAD(&ml->node); | |
2574 | list_add(&ml->node, &oi->master->master_ports); | |
2575 | oi->master->masters_cnt++; | |
2576 | ||
2577 | sl->ocp_if = oi; | |
2578 | INIT_LIST_HEAD(&sl->node); | |
2579 | list_add(&sl->node, &oi->slave->slave_ports); | |
2580 | oi->slave->slaves_cnt++; | |
2581 | ||
2582 | return 0; | |
2583 | } | |
2584 | ||
2585 | /** | |
2586 | * _register_link - register a struct omap_hwmod_ocp_if | |
2587 | * @oi: struct omap_hwmod_ocp_if * | |
2588 | * | |
2589 | * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it | |
2590 | * has already been registered; -EINVAL if @oi is NULL or if the | |
2591 | * record pointed to by @oi is missing required fields; or 0 upon | |
2592 | * success. | |
2593 | * | |
2594 | * XXX The data should be copied into bootmem, so the original data | |
2595 | * should be marked __initdata and freed after init. This would allow | |
2596 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. | |
2597 | */ | |
2598 | static int __init _register_link(struct omap_hwmod_ocp_if *oi) | |
2599 | { | |
2600 | if (!oi || !oi->master || !oi->slave || !oi->user) | |
2601 | return -EINVAL; | |
2602 | ||
2603 | if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) | |
2604 | return -EEXIST; | |
2605 | ||
2606 | pr_debug("omap_hwmod: registering link from %s to %s\n", | |
2607 | oi->master->name, oi->slave->name); | |
2608 | ||
2609 | /* | |
2610 | * Register the connected hwmods, if they haven't been | |
2611 | * registered already | |
2612 | */ | |
2613 | if (oi->master->_state != _HWMOD_STATE_REGISTERED) | |
2614 | _register(oi->master); | |
2615 | ||
2616 | if (oi->slave->_state != _HWMOD_STATE_REGISTERED) | |
2617 | _register(oi->slave); | |
2618 | ||
2619 | _add_link(oi); | |
2620 | ||
2621 | oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; | |
2622 | ||
2623 | return 0; | |
2624 | } | |
2625 | ||
2626 | /** | |
2627 | * _alloc_linkspace - allocate large block of hwmod links | |
2628 | * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count | |
2629 | * | |
2630 | * Allocate a large block of struct omap_hwmod_link records. This | |
2631 | * improves boot time significantly by avoiding the need to allocate | |
2632 | * individual records one by one. If the number of records to | |
2633 | * allocate in the block hasn't been manually specified, this function | |
2634 | * will count the number of struct omap_hwmod_ocp_if records in @ois | |
2635 | * and use that to determine the allocation size. For SoC families | |
2636 | * that require multiple list registrations, such as OMAP3xxx, this | |
2637 | * estimation process isn't optimal, so manual estimation is advised | |
2638 | * in those cases. Returns -EEXIST if the allocation has already occurred | |
2639 | * or 0 upon success. | |
2640 | */ | |
2641 | static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) | |
2642 | { | |
2643 | unsigned int i = 0; | |
2644 | unsigned int sz; | |
2645 | ||
2646 | if (linkspace) { | |
2647 | WARN(1, "linkspace already allocated\n"); | |
2648 | return -EEXIST; | |
2649 | } | |
2650 | ||
2651 | if (max_ls == 0) | |
2652 | while (ois[i++]) | |
2653 | max_ls += LINKS_PER_OCP_IF; | |
2654 | ||
2655 | sz = sizeof(struct omap_hwmod_link) * max_ls; | |
2656 | ||
2657 | pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", | |
2658 | __func__, sz, max_ls); | |
2659 | ||
2660 | linkspace = alloc_bootmem(sz); | |
2661 | ||
2662 | memset(linkspace, 0, sz); | |
2663 | ||
2664 | return 0; | |
2665 | } | |
0102b627 | 2666 | |
8f6aa8ee KH |
2667 | /* Static functions intended only for use in soc_ops field function pointers */ |
2668 | ||
2669 | /** | |
ff4ae5d9 | 2670 | * _omap2xxx_wait_target_ready - wait for a module to leave slave idle |
8f6aa8ee KH |
2671 | * @oh: struct omap_hwmod * |
2672 | * | |
2673 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2674 | * does not have an IDLEST bit or if the module successfully leaves | |
2675 | * slave idle; otherwise, pass along the return value of the | |
2676 | * appropriate *_cm*_wait_module_ready() function. | |
2677 | */ | |
ff4ae5d9 | 2678 | static int _omap2xxx_wait_target_ready(struct omap_hwmod *oh) |
8f6aa8ee KH |
2679 | { |
2680 | if (!oh) | |
2681 | return -EINVAL; | |
2682 | ||
2683 | if (oh->flags & HWMOD_NO_IDLEST) | |
2684 | return 0; | |
2685 | ||
2686 | if (!_find_mpu_rt_port(oh)) | |
2687 | return 0; | |
2688 | ||
2689 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2690 | ||
ff4ae5d9 PW |
2691 | return omap2xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs, |
2692 | oh->prcm.omap2.idlest_reg_id, | |
2693 | oh->prcm.omap2.idlest_idle_bit); | |
2694 | } | |
2695 | ||
2696 | /** | |
2697 | * _omap3xxx_wait_target_ready - wait for a module to leave slave idle | |
2698 | * @oh: struct omap_hwmod * | |
2699 | * | |
2700 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2701 | * does not have an IDLEST bit or if the module successfully leaves | |
2702 | * slave idle; otherwise, pass along the return value of the | |
2703 | * appropriate *_cm*_wait_module_ready() function. | |
2704 | */ | |
2705 | static int _omap3xxx_wait_target_ready(struct omap_hwmod *oh) | |
2706 | { | |
2707 | if (!oh) | |
2708 | return -EINVAL; | |
2709 | ||
2710 | if (oh->flags & HWMOD_NO_IDLEST) | |
2711 | return 0; | |
2712 | ||
2713 | if (!_find_mpu_rt_port(oh)) | |
2714 | return 0; | |
2715 | ||
2716 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2717 | ||
2718 | return omap3xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs, | |
2719 | oh->prcm.omap2.idlest_reg_id, | |
2720 | oh->prcm.omap2.idlest_idle_bit); | |
8f6aa8ee KH |
2721 | } |
2722 | ||
2723 | /** | |
2724 | * _omap4_wait_target_ready - wait for a module to leave slave idle | |
2725 | * @oh: struct omap_hwmod * | |
2726 | * | |
2727 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2728 | * does not have an IDLEST bit or if the module successfully leaves | |
2729 | * slave idle; otherwise, pass along the return value of the | |
2730 | * appropriate *_cm*_wait_module_ready() function. | |
2731 | */ | |
2732 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | |
2733 | { | |
2b026d13 | 2734 | if (!oh) |
8f6aa8ee KH |
2735 | return -EINVAL; |
2736 | ||
2b026d13 | 2737 | if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm) |
8f6aa8ee KH |
2738 | return 0; |
2739 | ||
2740 | if (!_find_mpu_rt_port(oh)) | |
2741 | return 0; | |
2742 | ||
2743 | /* XXX check module SIDLEMODE, hardreset status */ | |
2744 | ||
2745 | return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, | |
2746 | oh->clkdm->cm_inst, | |
2747 | oh->clkdm->clkdm_offs, | |
2748 | oh->prcm.omap4.clkctrl_offs); | |
2749 | } | |
2750 | ||
1688bf19 VH |
2751 | /** |
2752 | * _am33xx_wait_target_ready - wait for a module to leave slave idle | |
2753 | * @oh: struct omap_hwmod * | |
2754 | * | |
2755 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2756 | * does not have an IDLEST bit or if the module successfully leaves | |
2757 | * slave idle; otherwise, pass along the return value of the | |
2758 | * appropriate *_cm*_wait_module_ready() function. | |
2759 | */ | |
2760 | static int _am33xx_wait_target_ready(struct omap_hwmod *oh) | |
2761 | { | |
2762 | if (!oh || !oh->clkdm) | |
2763 | return -EINVAL; | |
2764 | ||
2765 | if (oh->flags & HWMOD_NO_IDLEST) | |
2766 | return 0; | |
2767 | ||
2768 | if (!_find_mpu_rt_port(oh)) | |
2769 | return 0; | |
2770 | ||
2771 | /* XXX check module SIDLEMODE, hardreset status */ | |
2772 | ||
2773 | return am33xx_cm_wait_module_ready(oh->clkdm->cm_inst, | |
2774 | oh->clkdm->clkdm_offs, | |
2775 | oh->prcm.omap4.clkctrl_offs); | |
2776 | } | |
2777 | ||
b8249cf2 KH |
2778 | /** |
2779 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2780 | * @oh: struct omap_hwmod * to assert hardreset | |
2781 | * @ohri: hardreset line data | |
2782 | * | |
2783 | * Call omap2_prm_assert_hardreset() with parameters extracted from | |
2784 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2785 | * use as an soc_ops function pointer. Passes along the return value | |
2786 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | |
2787 | * for removal when the PRM code is moved into drivers/. | |
2788 | */ | |
2789 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | |
2790 | struct omap_hwmod_rst_info *ohri) | |
2791 | { | |
2792 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | |
2793 | ohri->rst_shift); | |
2794 | } | |
2795 | ||
2796 | /** | |
2797 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2798 | * @oh: struct omap_hwmod * to deassert hardreset | |
2799 | * @ohri: hardreset line data | |
2800 | * | |
2801 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | |
2802 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2803 | * use as an soc_ops function pointer. Passes along the return value | |
2804 | * from omap2_prm_deassert_hardreset(). XXX This function is | |
2805 | * scheduled for removal when the PRM code is moved into drivers/. | |
2806 | */ | |
2807 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | |
2808 | struct omap_hwmod_rst_info *ohri) | |
2809 | { | |
2810 | return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | |
2811 | ohri->rst_shift, | |
2812 | ohri->st_shift); | |
2813 | } | |
2814 | ||
2815 | /** | |
2816 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | |
2817 | * @oh: struct omap_hwmod * to test hardreset | |
2818 | * @ohri: hardreset line data | |
2819 | * | |
2820 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | |
2821 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2822 | * intended for use as an soc_ops function pointer. Passes along the | |
2823 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | |
2824 | * function is scheduled for removal when the PRM code is moved into | |
2825 | * drivers/. | |
2826 | */ | |
2827 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | |
2828 | struct omap_hwmod_rst_info *ohri) | |
2829 | { | |
2830 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | |
2831 | ohri->st_shift); | |
2832 | } | |
2833 | ||
2834 | /** | |
2835 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2836 | * @oh: struct omap_hwmod * to assert hardreset | |
2837 | * @ohri: hardreset line data | |
2838 | * | |
2839 | * Call omap4_prminst_assert_hardreset() with parameters extracted | |
2840 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2841 | * intended for use as an soc_ops function pointer. Passes along the | |
2842 | * return value from omap4_prminst_assert_hardreset(). XXX This | |
2843 | * function is scheduled for removal when the PRM code is moved into | |
2844 | * drivers/. | |
2845 | */ | |
2846 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | |
2847 | struct omap_hwmod_rst_info *ohri) | |
b8249cf2 | 2848 | { |
07b3a139 PW |
2849 | if (!oh->clkdm) |
2850 | return -EINVAL; | |
2851 | ||
b8249cf2 KH |
2852 | return omap4_prminst_assert_hardreset(ohri->rst_shift, |
2853 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2854 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2855 | oh->prcm.omap4.rstctrl_offs); | |
2856 | } | |
2857 | ||
2858 | /** | |
2859 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2860 | * @oh: struct omap_hwmod * to deassert hardreset | |
2861 | * @ohri: hardreset line data | |
2862 | * | |
2863 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | |
2864 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2865 | * intended for use as an soc_ops function pointer. Passes along the | |
2866 | * return value from omap4_prminst_deassert_hardreset(). XXX This | |
2867 | * function is scheduled for removal when the PRM code is moved into | |
2868 | * drivers/. | |
2869 | */ | |
2870 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | |
2871 | struct omap_hwmod_rst_info *ohri) | |
2872 | { | |
07b3a139 PW |
2873 | if (!oh->clkdm) |
2874 | return -EINVAL; | |
2875 | ||
b8249cf2 KH |
2876 | if (ohri->st_shift) |
2877 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
2878 | oh->name, ohri->name); | |
2879 | return omap4_prminst_deassert_hardreset(ohri->rst_shift, | |
2880 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2881 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2882 | oh->prcm.omap4.rstctrl_offs); | |
2883 | } | |
2884 | ||
2885 | /** | |
2886 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | |
2887 | * @oh: struct omap_hwmod * to test hardreset | |
2888 | * @ohri: hardreset line data | |
2889 | * | |
2890 | * Call omap4_prminst_is_hardreset_asserted() with parameters | |
2891 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
2892 | * Only intended for use as an soc_ops function pointer. Passes along | |
2893 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | |
2894 | * This function is scheduled for removal when the PRM code is moved | |
2895 | * into drivers/. | |
2896 | */ | |
2897 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | |
2898 | struct omap_hwmod_rst_info *ohri) | |
2899 | { | |
07b3a139 PW |
2900 | if (!oh->clkdm) |
2901 | return -EINVAL; | |
2902 | ||
b8249cf2 KH |
2903 | return omap4_prminst_is_hardreset_asserted(ohri->rst_shift, |
2904 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2905 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2906 | oh->prcm.omap4.rstctrl_offs); | |
2907 | } | |
2908 | ||
1688bf19 VH |
2909 | /** |
2910 | * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
2911 | * @oh: struct omap_hwmod * to assert hardreset | |
2912 | * @ohri: hardreset line data | |
2913 | * | |
2914 | * Call am33xx_prminst_assert_hardreset() with parameters extracted | |
2915 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2916 | * intended for use as an soc_ops function pointer. Passes along the | |
2917 | * return value from am33xx_prminst_assert_hardreset(). XXX This | |
2918 | * function is scheduled for removal when the PRM code is moved into | |
2919 | * drivers/. | |
2920 | */ | |
2921 | static int _am33xx_assert_hardreset(struct omap_hwmod *oh, | |
2922 | struct omap_hwmod_rst_info *ohri) | |
2923 | ||
2924 | { | |
2925 | return am33xx_prm_assert_hardreset(ohri->rst_shift, | |
2926 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2927 | oh->prcm.omap4.rstctrl_offs); | |
2928 | } | |
2929 | ||
2930 | /** | |
2931 | * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
2932 | * @oh: struct omap_hwmod * to deassert hardreset | |
2933 | * @ohri: hardreset line data | |
2934 | * | |
2935 | * Call am33xx_prminst_deassert_hardreset() with parameters extracted | |
2936 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2937 | * intended for use as an soc_ops function pointer. Passes along the | |
2938 | * return value from am33xx_prminst_deassert_hardreset(). XXX This | |
2939 | * function is scheduled for removal when the PRM code is moved into | |
2940 | * drivers/. | |
2941 | */ | |
2942 | static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, | |
2943 | struct omap_hwmod_rst_info *ohri) | |
2944 | { | |
2945 | if (ohri->st_shift) | |
2946 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
2947 | oh->name, ohri->name); | |
2948 | ||
2949 | return am33xx_prm_deassert_hardreset(ohri->rst_shift, | |
2950 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2951 | oh->prcm.omap4.rstctrl_offs, | |
2952 | oh->prcm.omap4.rstst_offs); | |
2953 | } | |
2954 | ||
2955 | /** | |
2956 | * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args | |
2957 | * @oh: struct omap_hwmod * to test hardreset | |
2958 | * @ohri: hardreset line data | |
2959 | * | |
2960 | * Call am33xx_prminst_is_hardreset_asserted() with parameters | |
2961 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
2962 | * Only intended for use as an soc_ops function pointer. Passes along | |
2963 | * the return value from am33xx_prminst_is_hardreset_asserted(). XXX | |
2964 | * This function is scheduled for removal when the PRM code is moved | |
2965 | * into drivers/. | |
2966 | */ | |
2967 | static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh, | |
2968 | struct omap_hwmod_rst_info *ohri) | |
2969 | { | |
2970 | return am33xx_prm_is_hardreset_asserted(ohri->rst_shift, | |
2971 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2972 | oh->prcm.omap4.rstctrl_offs); | |
2973 | } | |
2974 | ||
0102b627 BC |
2975 | /* Public functions */ |
2976 | ||
2977 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
2978 | { | |
2979 | if (oh->flags & HWMOD_16BIT_REG) | |
2980 | return __raw_readw(oh->_mpu_rt_va + reg_offs); | |
2981 | else | |
2982 | return __raw_readl(oh->_mpu_rt_va + reg_offs); | |
2983 | } | |
2984 | ||
2985 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
2986 | { | |
2987 | if (oh->flags & HWMOD_16BIT_REG) | |
2988 | __raw_writew(v, oh->_mpu_rt_va + reg_offs); | |
2989 | else | |
2990 | __raw_writel(v, oh->_mpu_rt_va + reg_offs); | |
2991 | } | |
2992 | ||
6d3c55fd A |
2993 | /** |
2994 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
2995 | * @oh: struct omap_hwmod * | |
2996 | * | |
2997 | * This is a public function exposed to drivers. Some drivers may need to do | |
2998 | * some settings before and after resetting the device. Those drivers after | |
2999 | * doing the necessary settings could use this function to start a reset by | |
3000 | * setting the SYSCONFIG.SOFTRESET bit. | |
3001 | */ | |
3002 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
3003 | { | |
3c55c1ba PW |
3004 | u32 v; |
3005 | int ret; | |
3006 | ||
3007 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
3008 | return -EINVAL; |
3009 | ||
3c55c1ba PW |
3010 | v = oh->_sysc_cache; |
3011 | ret = _set_softreset(oh, &v); | |
3012 | if (ret) | |
3013 | goto error; | |
3014 | _write_sysconfig(v, oh); | |
3015 | ||
3016 | error: | |
3017 | return ret; | |
6d3c55fd A |
3018 | } |
3019 | ||
0102b627 BC |
3020 | /** |
3021 | * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode | |
3022 | * @oh: struct omap_hwmod * | |
3023 | * @idlemode: SIDLEMODE field bits (shifted to bit 0) | |
3024 | * | |
3025 | * Sets the IP block's OCP slave idlemode in hardware, and updates our | |
3026 | * local copy. Intended to be used by drivers that have some erratum | |
3027 | * that requires direct manipulation of the SIDLEMODE bits. Returns | |
3028 | * -EINVAL if @oh is null, or passes along the return value from | |
3029 | * _set_slave_idlemode(). | |
3030 | * | |
3031 | * XXX Does this function have any current users? If not, we should | |
3032 | * remove it; it is better to let the rest of the hwmod code handle this. | |
3033 | * Any users of this function should be scrutinized carefully. | |
3034 | */ | |
3035 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) | |
3036 | { | |
3037 | u32 v; | |
3038 | int retval = 0; | |
3039 | ||
3040 | if (!oh) | |
3041 | return -EINVAL; | |
3042 | ||
3043 | v = oh->_sysc_cache; | |
3044 | ||
3045 | retval = _set_slave_idlemode(oh, idlemode, &v); | |
3046 | if (!retval) | |
3047 | _write_sysconfig(v, oh); | |
3048 | ||
3049 | return retval; | |
3050 | } | |
3051 | ||
63c85238 PW |
3052 | /** |
3053 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
3054 | * @name: name of the omap_hwmod to look up | |
3055 | * | |
3056 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
3057 | * struct omap_hwmod *, or NULL upon error. | |
3058 | */ | |
3059 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
3060 | { | |
3061 | struct omap_hwmod *oh; | |
3062 | ||
3063 | if (!name) | |
3064 | return NULL; | |
3065 | ||
63c85238 | 3066 | oh = _lookup(name); |
63c85238 PW |
3067 | |
3068 | return oh; | |
3069 | } | |
3070 | ||
3071 | /** | |
3072 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
3073 | * @fn: pointer to a callback function | |
97d60162 | 3074 | * @data: void * data to pass to callback function |
63c85238 PW |
3075 | * |
3076 | * Call @fn for each registered omap_hwmod, passing @data to each | |
3077 | * function. @fn must return 0 for success or any other value for | |
3078 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
3079 | * will stop and the non-zero return value will be passed to the | |
3080 | * caller of omap_hwmod_for_each(). @fn is called with | |
3081 | * omap_hwmod_for_each() held. | |
3082 | */ | |
97d60162 PW |
3083 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
3084 | void *data) | |
63c85238 PW |
3085 | { |
3086 | struct omap_hwmod *temp_oh; | |
30ebad9d | 3087 | int ret = 0; |
63c85238 PW |
3088 | |
3089 | if (!fn) | |
3090 | return -EINVAL; | |
3091 | ||
63c85238 | 3092 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 3093 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
3094 | if (ret) |
3095 | break; | |
3096 | } | |
63c85238 PW |
3097 | |
3098 | return ret; | |
3099 | } | |
3100 | ||
2221b5cd PW |
3101 | /** |
3102 | * omap_hwmod_register_links - register an array of hwmod links | |
3103 | * @ois: pointer to an array of omap_hwmod_ocp_if to register | |
3104 | * | |
3105 | * Intended to be called early in boot before the clock framework is | |
3106 | * initialized. If @ois is not null, will register all omap_hwmods | |
9ebfd285 KH |
3107 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
3108 | * omap_hwmod_init() hasn't been called before calling this function, | |
3109 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | |
3110 | * success. | |
2221b5cd PW |
3111 | */ |
3112 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | |
3113 | { | |
3114 | int r, i; | |
3115 | ||
9ebfd285 KH |
3116 | if (!inited) |
3117 | return -EINVAL; | |
3118 | ||
2221b5cd PW |
3119 | if (!ois) |
3120 | return 0; | |
3121 | ||
2221b5cd PW |
3122 | if (!linkspace) { |
3123 | if (_alloc_linkspace(ois)) { | |
3124 | pr_err("omap_hwmod: could not allocate link space\n"); | |
3125 | return -ENOMEM; | |
3126 | } | |
3127 | } | |
3128 | ||
3129 | i = 0; | |
3130 | do { | |
3131 | r = _register_link(ois[i]); | |
3132 | WARN(r && r != -EEXIST, | |
3133 | "omap_hwmod: _register_link(%s -> %s) returned %d\n", | |
3134 | ois[i]->master->name, ois[i]->slave->name, r); | |
3135 | } while (ois[++i]); | |
3136 | ||
3137 | return 0; | |
3138 | } | |
3139 | ||
381d033a PW |
3140 | /** |
3141 | * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up | |
3142 | * @oh: pointer to the hwmod currently being set up (usually not the MPU) | |
3143 | * | |
3144 | * If the hwmod data corresponding to the MPU subsystem IP block | |
3145 | * hasn't been initialized and set up yet, do so now. This must be | |
3146 | * done first since sleep dependencies may be added from other hwmods | |
3147 | * to the MPU. Intended to be called only by omap_hwmod_setup*(). No | |
3148 | * return value. | |
63c85238 | 3149 | */ |
381d033a | 3150 | static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) |
e7c7d760 | 3151 | { |
381d033a PW |
3152 | if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) |
3153 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
3154 | __func__, MPU_INITIATOR_NAME); | |
3155 | else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) | |
3156 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
e7c7d760 TL |
3157 | } |
3158 | ||
63c85238 | 3159 | /** |
a2debdbd PW |
3160 | * omap_hwmod_setup_one - set up a single hwmod |
3161 | * @oh_name: const char * name of the already-registered hwmod to set up | |
3162 | * | |
381d033a PW |
3163 | * Initialize and set up a single hwmod. Intended to be used for a |
3164 | * small number of early devices, such as the timer IP blocks used for | |
3165 | * the scheduler clock. Must be called after omap2_clk_init(). | |
3166 | * Resolves the struct clk names to struct clk pointers for each | |
3167 | * registered omap_hwmod. Also calls _setup() on each hwmod. Returns | |
3168 | * -EINVAL upon error or 0 upon success. | |
a2debdbd PW |
3169 | */ |
3170 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
3171 | { |
3172 | struct omap_hwmod *oh; | |
63c85238 | 3173 | |
a2debdbd PW |
3174 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
3175 | ||
a2debdbd PW |
3176 | oh = _lookup(oh_name); |
3177 | if (!oh) { | |
3178 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
3179 | return -EINVAL; | |
3180 | } | |
63c85238 | 3181 | |
381d033a | 3182 | _ensure_mpu_hwmod_is_setup(oh); |
63c85238 | 3183 | |
381d033a | 3184 | _init(oh, NULL); |
a2debdbd PW |
3185 | _setup(oh, NULL); |
3186 | ||
63c85238 PW |
3187 | return 0; |
3188 | } | |
3189 | ||
3190 | /** | |
381d033a | 3191 | * omap_hwmod_setup_all - set up all registered IP blocks |
63c85238 | 3192 | * |
381d033a PW |
3193 | * Initialize and set up all IP blocks registered with the hwmod code. |
3194 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
3195 | * names to struct clk pointers for each registered omap_hwmod. Also | |
3196 | * calls _setup() on each hwmod. Returns 0 upon success. | |
63c85238 | 3197 | */ |
550c8092 | 3198 | static int __init omap_hwmod_setup_all(void) |
63c85238 | 3199 | { |
381d033a | 3200 | _ensure_mpu_hwmod_is_setup(NULL); |
63c85238 | 3201 | |
381d033a | 3202 | omap_hwmod_for_each(_init, NULL); |
2092e5cc | 3203 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
3204 | |
3205 | return 0; | |
3206 | } | |
550c8092 | 3207 | core_initcall(omap_hwmod_setup_all); |
63c85238 | 3208 | |
63c85238 PW |
3209 | /** |
3210 | * omap_hwmod_enable - enable an omap_hwmod | |
3211 | * @oh: struct omap_hwmod * | |
3212 | * | |
74ff3a68 | 3213 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
3214 | * Returns -EINVAL on error or passes along the return value from _enable(). |
3215 | */ | |
3216 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
3217 | { | |
3218 | int r; | |
dc6d1cda | 3219 | unsigned long flags; |
63c85238 PW |
3220 | |
3221 | if (!oh) | |
3222 | return -EINVAL; | |
3223 | ||
dc6d1cda PW |
3224 | spin_lock_irqsave(&oh->_lock, flags); |
3225 | r = _enable(oh); | |
3226 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3227 | |
3228 | return r; | |
3229 | } | |
3230 | ||
3231 | /** | |
3232 | * omap_hwmod_idle - idle an omap_hwmod | |
3233 | * @oh: struct omap_hwmod * | |
3234 | * | |
74ff3a68 | 3235 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
3236 | * Returns -EINVAL on error or passes along the return value from _idle(). |
3237 | */ | |
3238 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
3239 | { | |
dc6d1cda PW |
3240 | unsigned long flags; |
3241 | ||
63c85238 PW |
3242 | if (!oh) |
3243 | return -EINVAL; | |
3244 | ||
dc6d1cda PW |
3245 | spin_lock_irqsave(&oh->_lock, flags); |
3246 | _idle(oh); | |
3247 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3248 | |
3249 | return 0; | |
3250 | } | |
3251 | ||
3252 | /** | |
3253 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
3254 | * @oh: struct omap_hwmod * | |
3255 | * | |
74ff3a68 | 3256 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
3257 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
3258 | * the return value from _shutdown(). | |
3259 | */ | |
3260 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
3261 | { | |
dc6d1cda PW |
3262 | unsigned long flags; |
3263 | ||
63c85238 PW |
3264 | if (!oh) |
3265 | return -EINVAL; | |
3266 | ||
dc6d1cda | 3267 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3268 | _shutdown(oh); |
dc6d1cda | 3269 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3270 | |
3271 | return 0; | |
3272 | } | |
3273 | ||
3274 | /** | |
3275 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
3276 | * @oh: struct omap_hwmod *oh | |
3277 | * | |
3278 | * Intended to be called by the omap_device code. | |
3279 | */ | |
3280 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
3281 | { | |
dc6d1cda PW |
3282 | unsigned long flags; |
3283 | ||
3284 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 3285 | _enable_clocks(oh); |
dc6d1cda | 3286 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3287 | |
3288 | return 0; | |
3289 | } | |
3290 | ||
3291 | /** | |
3292 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
3293 | * @oh: struct omap_hwmod *oh | |
3294 | * | |
3295 | * Intended to be called by the omap_device code. | |
3296 | */ | |
3297 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
3298 | { | |
dc6d1cda PW |
3299 | unsigned long flags; |
3300 | ||
3301 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 3302 | _disable_clocks(oh); |
dc6d1cda | 3303 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3304 | |
3305 | return 0; | |
3306 | } | |
3307 | ||
3308 | /** | |
3309 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
3310 | * @oh: struct omap_hwmod *oh | |
3311 | * | |
3312 | * Intended to be called by drivers and core code when all posted | |
3313 | * writes to a device must complete before continuing further | |
3314 | * execution (for example, after clearing some device IRQSTATUS | |
3315 | * register bits) | |
3316 | * | |
3317 | * XXX what about targets with multiple OCP threads? | |
3318 | */ | |
3319 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
3320 | { | |
3321 | BUG_ON(!oh); | |
3322 | ||
43b40992 | 3323 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
4f8a428d RK |
3324 | WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n", |
3325 | oh->name); | |
63c85238 PW |
3326 | return; |
3327 | } | |
3328 | ||
3329 | /* | |
3330 | * Forces posted writes to complete on the OCP thread handling | |
3331 | * register writes | |
3332 | */ | |
cc7a1d2a | 3333 | omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
3334 | } |
3335 | ||
3336 | /** | |
3337 | * omap_hwmod_reset - reset the hwmod | |
3338 | * @oh: struct omap_hwmod * | |
3339 | * | |
3340 | * Under some conditions, a driver may wish to reset the entire device. | |
3341 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 3342 | * the return value from _reset(). |
63c85238 PW |
3343 | */ |
3344 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
3345 | { | |
3346 | int r; | |
dc6d1cda | 3347 | unsigned long flags; |
63c85238 | 3348 | |
9b579114 | 3349 | if (!oh) |
63c85238 PW |
3350 | return -EINVAL; |
3351 | ||
dc6d1cda | 3352 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3353 | r = _reset(oh); |
dc6d1cda | 3354 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3355 | |
3356 | return r; | |
3357 | } | |
3358 | ||
5e8370f1 PW |
3359 | /* |
3360 | * IP block data retrieval functions | |
3361 | */ | |
3362 | ||
63c85238 PW |
3363 | /** |
3364 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
3365 | * @oh: struct omap_hwmod * | |
3366 | * @res: pointer to the first element of an array of struct resource to fill | |
3367 | * | |
3368 | * Count the number of struct resource array elements necessary to | |
3369 | * contain omap_hwmod @oh resources. Intended to be called by code | |
3370 | * that registers omap_devices. Intended to be used to determine the | |
3371 | * size of a dynamically-allocated struct resource array, before | |
3372 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
3373 | * resource array elements needed. | |
3374 | * | |
3375 | * XXX This code is not optimized. It could attempt to merge adjacent | |
3376 | * resource IDs. | |
3377 | * | |
3378 | */ | |
3379 | int omap_hwmod_count_resources(struct omap_hwmod *oh) | |
3380 | { | |
5d95dde7 | 3381 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3382 | struct list_head *p; |
5d95dde7 PW |
3383 | int ret; |
3384 | int i = 0; | |
63c85238 | 3385 | |
bc614958 | 3386 | ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); |
63c85238 | 3387 | |
11cd4b94 | 3388 | p = oh->slave_ports.next; |
2221b5cd | 3389 | |
5d95dde7 | 3390 | while (i < oh->slaves_cnt) { |
11cd4b94 | 3391 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 PW |
3392 | ret += _count_ocp_if_addr_spaces(os); |
3393 | } | |
63c85238 PW |
3394 | |
3395 | return ret; | |
3396 | } | |
3397 | ||
3398 | /** | |
3399 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
3400 | * @oh: struct omap_hwmod * | |
3401 | * @res: pointer to the first element of an array of struct resource to fill | |
3402 | * | |
3403 | * Fill the struct resource array @res with resource data from the | |
3404 | * omap_hwmod @oh. Intended to be called by code that registers | |
3405 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3406 | * number of array elements filled. | |
3407 | */ | |
3408 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
3409 | { | |
5d95dde7 | 3410 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3411 | struct list_head *p; |
5d95dde7 | 3412 | int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; |
63c85238 PW |
3413 | int r = 0; |
3414 | ||
3415 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
3416 | ||
212738a4 PW |
3417 | mpu_irqs_cnt = _count_mpu_irqs(oh); |
3418 | for (i = 0; i < mpu_irqs_cnt; i++) { | |
718bfd76 PW |
3419 | (res + r)->name = (oh->mpu_irqs + i)->name; |
3420 | (res + r)->start = (oh->mpu_irqs + i)->irq; | |
3421 | (res + r)->end = (oh->mpu_irqs + i)->irq; | |
63c85238 PW |
3422 | (res + r)->flags = IORESOURCE_IRQ; |
3423 | r++; | |
3424 | } | |
3425 | ||
bc614958 PW |
3426 | sdma_reqs_cnt = _count_sdma_reqs(oh); |
3427 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
9ee9fff9 BC |
3428 | (res + r)->name = (oh->sdma_reqs + i)->name; |
3429 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3430 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
3431 | (res + r)->flags = IORESOURCE_DMA; |
3432 | r++; | |
3433 | } | |
3434 | ||
11cd4b94 | 3435 | p = oh->slave_ports.next; |
2221b5cd | 3436 | |
5d95dde7 PW |
3437 | i = 0; |
3438 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 3439 | os = _fetch_next_ocp_if(&p, &i); |
78183f3f | 3440 | addr_cnt = _count_ocp_if_addr_spaces(os); |
63c85238 | 3441 | |
78183f3f | 3442 | for (j = 0; j < addr_cnt; j++) { |
cd503802 | 3443 | (res + r)->name = (os->addr + j)->name; |
63c85238 PW |
3444 | (res + r)->start = (os->addr + j)->pa_start; |
3445 | (res + r)->end = (os->addr + j)->pa_end; | |
3446 | (res + r)->flags = IORESOURCE_MEM; | |
3447 | r++; | |
3448 | } | |
3449 | } | |
3450 | ||
3451 | return r; | |
3452 | } | |
3453 | ||
b82b04e8 VH |
3454 | /** |
3455 | * omap_hwmod_fill_dma_resources - fill struct resource array with dma data | |
3456 | * @oh: struct omap_hwmod * | |
3457 | * @res: pointer to the array of struct resource to fill | |
3458 | * | |
3459 | * Fill the struct resource array @res with dma resource data from the | |
3460 | * omap_hwmod @oh. Intended to be called by code that registers | |
3461 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3462 | * number of array elements filled. | |
3463 | */ | |
3464 | int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res) | |
3465 | { | |
3466 | int i, sdma_reqs_cnt; | |
3467 | int r = 0; | |
3468 | ||
3469 | sdma_reqs_cnt = _count_sdma_reqs(oh); | |
3470 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
3471 | (res + r)->name = (oh->sdma_reqs + i)->name; | |
3472 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3473 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
3474 | (res + r)->flags = IORESOURCE_DMA; | |
3475 | r++; | |
3476 | } | |
3477 | ||
3478 | return r; | |
3479 | } | |
3480 | ||
5e8370f1 PW |
3481 | /** |
3482 | * omap_hwmod_get_resource_byname - fetch IP block integration data by name | |
3483 | * @oh: struct omap_hwmod * to operate on | |
3484 | * @type: one of the IORESOURCE_* constants from include/linux/ioport.h | |
3485 | * @name: pointer to the name of the data to fetch (optional) | |
3486 | * @rsrc: pointer to a struct resource, allocated by the caller | |
3487 | * | |
3488 | * Retrieve MPU IRQ, SDMA request line, or address space start/end | |
3489 | * data for the IP block pointed to by @oh. The data will be filled | |
3490 | * into a struct resource record pointed to by @rsrc. The struct | |
3491 | * resource must be allocated by the caller. When @name is non-null, | |
3492 | * the data associated with the matching entry in the IRQ/SDMA/address | |
3493 | * space hwmod data arrays will be returned. If @name is null, the | |
3494 | * first array entry will be returned. Data order is not meaningful | |
3495 | * in hwmod data, so callers are strongly encouraged to use a non-null | |
3496 | * @name whenever possible to avoid unpredictable effects if hwmod | |
3497 | * data is later added that causes data ordering to change. This | |
3498 | * function is only intended for use by OMAP core code. Device | |
3499 | * drivers should not call this function - the appropriate bus-related | |
3500 | * data accessor functions should be used instead. Returns 0 upon | |
3501 | * success or a negative error code upon error. | |
3502 | */ | |
3503 | int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, | |
3504 | const char *name, struct resource *rsrc) | |
3505 | { | |
3506 | int r; | |
3507 | unsigned int irq, dma; | |
3508 | u32 pa_start, pa_end; | |
3509 | ||
3510 | if (!oh || !rsrc) | |
3511 | return -EINVAL; | |
3512 | ||
3513 | if (type == IORESOURCE_IRQ) { | |
3514 | r = _get_mpu_irq_by_name(oh, name, &irq); | |
3515 | if (r) | |
3516 | return r; | |
3517 | ||
3518 | rsrc->start = irq; | |
3519 | rsrc->end = irq; | |
3520 | } else if (type == IORESOURCE_DMA) { | |
3521 | r = _get_sdma_req_by_name(oh, name, &dma); | |
3522 | if (r) | |
3523 | return r; | |
3524 | ||
3525 | rsrc->start = dma; | |
3526 | rsrc->end = dma; | |
3527 | } else if (type == IORESOURCE_MEM) { | |
3528 | r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); | |
3529 | if (r) | |
3530 | return r; | |
3531 | ||
3532 | rsrc->start = pa_start; | |
3533 | rsrc->end = pa_end; | |
3534 | } else { | |
3535 | return -EINVAL; | |
3536 | } | |
3537 | ||
3538 | rsrc->flags = type; | |
3539 | rsrc->name = name; | |
3540 | ||
3541 | return 0; | |
3542 | } | |
3543 | ||
63c85238 PW |
3544 | /** |
3545 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
3546 | * @oh: struct omap_hwmod * | |
3547 | * | |
3548 | * Return the powerdomain pointer associated with the OMAP module | |
3549 | * @oh's main clock. If @oh does not have a main clk, return the | |
3550 | * powerdomain associated with the interface clock associated with the | |
3551 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
3552 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
3553 | * success. | |
3554 | */ | |
3555 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
3556 | { | |
3557 | struct clk *c; | |
2d6141ba | 3558 | struct omap_hwmod_ocp_if *oi; |
63c85238 PW |
3559 | |
3560 | if (!oh) | |
3561 | return NULL; | |
3562 | ||
3563 | if (oh->_clk) { | |
3564 | c = oh->_clk; | |
3565 | } else { | |
2d6141ba PW |
3566 | oi = _find_mpu_rt_port(oh); |
3567 | if (!oi) | |
63c85238 | 3568 | return NULL; |
2d6141ba | 3569 | c = oi->_clk; |
63c85238 PW |
3570 | } |
3571 | ||
d5647c18 TG |
3572 | if (!c->clkdm) |
3573 | return NULL; | |
3574 | ||
63c85238 PW |
3575 | return c->clkdm->pwrdm.ptr; |
3576 | ||
3577 | } | |
3578 | ||
db2a60bf PW |
3579 | /** |
3580 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
3581 | * @oh: struct omap_hwmod * | |
3582 | * | |
3583 | * Returns the virtual address corresponding to the beginning of the | |
3584 | * module's register target, in the address range that is intended to | |
3585 | * be used by the MPU. Returns the virtual address upon success or NULL | |
3586 | * upon error. | |
3587 | */ | |
3588 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
3589 | { | |
3590 | if (!oh) | |
3591 | return NULL; | |
3592 | ||
3593 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
3594 | return NULL; | |
3595 | ||
3596 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
3597 | return NULL; | |
3598 | ||
3599 | return oh->_mpu_rt_va; | |
3600 | } | |
3601 | ||
63c85238 PW |
3602 | /** |
3603 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
3604 | * @oh: struct omap_hwmod * | |
3605 | * @init_oh: struct omap_hwmod * (initiator) | |
3606 | * | |
3607 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
3608 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3609 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3610 | * code needs to add/del initiator dependencies dynamically | |
3611 | * before/after accessing a device. Returns the return value from | |
3612 | * _add_initiator_dep(). | |
3613 | * | |
3614 | * XXX Keep a usecount in the clockdomain code | |
3615 | */ | |
3616 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
3617 | struct omap_hwmod *init_oh) | |
3618 | { | |
3619 | return _add_initiator_dep(oh, init_oh); | |
3620 | } | |
3621 | ||
3622 | /* | |
3623 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
3624 | * for context save/restore operations? | |
3625 | */ | |
3626 | ||
3627 | /** | |
3628 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
3629 | * @oh: struct omap_hwmod * | |
3630 | * @init_oh: struct omap_hwmod * (initiator) | |
3631 | * | |
3632 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
3633 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3634 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3635 | * code needs to add/del initiator dependencies dynamically | |
3636 | * before/after accessing a device. Returns the return value from | |
3637 | * _del_initiator_dep(). | |
3638 | * | |
3639 | * XXX Keep a usecount in the clockdomain code | |
3640 | */ | |
3641 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
3642 | struct omap_hwmod *init_oh) | |
3643 | { | |
3644 | return _del_initiator_dep(oh, init_oh); | |
3645 | } | |
3646 | ||
63c85238 PW |
3647 | /** |
3648 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
3649 | * @oh: struct omap_hwmod * | |
3650 | * | |
3651 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
3652 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
3653 | * this IP block if it has dynamic mux entries. Eventually this | |
3654 | * should set PRCM wakeup registers to cause the PRCM to receive | |
3655 | * wakeup events from the module. Does not set any wakeup routing | |
3656 | * registers beyond this point - if the module is to wake up any other | |
3657 | * module or subsystem, that must be set separately. Called by | |
3658 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3659 | */ |
3660 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
3661 | { | |
dc6d1cda | 3662 | unsigned long flags; |
5a7ddcbd | 3663 | u32 v; |
dc6d1cda | 3664 | |
dc6d1cda | 3665 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3666 | |
3667 | if (oh->class->sysc && | |
3668 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3669 | v = oh->_sysc_cache; | |
3670 | _enable_wakeup(oh, &v); | |
3671 | _write_sysconfig(v, oh); | |
3672 | } | |
3673 | ||
eceec009 | 3674 | _set_idle_ioring_wakeup(oh, true); |
dc6d1cda | 3675 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3676 | |
3677 | return 0; | |
3678 | } | |
3679 | ||
3680 | /** | |
3681 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
3682 | * @oh: struct omap_hwmod * | |
3683 | * | |
3684 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
3685 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
3686 | * events for this IP block if it has dynamic mux entries. Eventually | |
3687 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
3688 | * wakeup events from the module. Does not set any wakeup routing | |
3689 | * registers beyond this point - if the module is to wake up any other | |
3690 | * module or subsystem, that must be set separately. Called by | |
3691 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3692 | */ |
3693 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
3694 | { | |
dc6d1cda | 3695 | unsigned long flags; |
5a7ddcbd | 3696 | u32 v; |
dc6d1cda | 3697 | |
dc6d1cda | 3698 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3699 | |
3700 | if (oh->class->sysc && | |
3701 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3702 | v = oh->_sysc_cache; | |
3703 | _disable_wakeup(oh, &v); | |
3704 | _write_sysconfig(v, oh); | |
3705 | } | |
3706 | ||
eceec009 | 3707 | _set_idle_ioring_wakeup(oh, false); |
dc6d1cda | 3708 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3709 | |
3710 | return 0; | |
3711 | } | |
43b40992 | 3712 | |
aee48e3c PW |
3713 | /** |
3714 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
3715 | * contained in the hwmod module. | |
3716 | * @oh: struct omap_hwmod * | |
3717 | * @name: name of the reset line to lookup and assert | |
3718 | * | |
3719 | * Some IP like dsp, ipu or iva contain processor that require | |
3720 | * an HW reset line to be assert / deassert in order to enable fully | |
3721 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3722 | * yet supported on this OMAP; otherwise, passes along the return value | |
3723 | * from _assert_hardreset(). | |
3724 | */ | |
3725 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
3726 | { | |
3727 | int ret; | |
dc6d1cda | 3728 | unsigned long flags; |
aee48e3c PW |
3729 | |
3730 | if (!oh) | |
3731 | return -EINVAL; | |
3732 | ||
dc6d1cda | 3733 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3734 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 3735 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3736 | |
3737 | return ret; | |
3738 | } | |
3739 | ||
3740 | /** | |
3741 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
3742 | * contained in the hwmod module. | |
3743 | * @oh: struct omap_hwmod * | |
3744 | * @name: name of the reset line to look up and deassert | |
3745 | * | |
3746 | * Some IP like dsp, ipu or iva contain processor that require | |
3747 | * an HW reset line to be assert / deassert in order to enable fully | |
3748 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3749 | * yet supported on this OMAP; otherwise, passes along the return value | |
3750 | * from _deassert_hardreset(). | |
3751 | */ | |
3752 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
3753 | { | |
3754 | int ret; | |
dc6d1cda | 3755 | unsigned long flags; |
aee48e3c PW |
3756 | |
3757 | if (!oh) | |
3758 | return -EINVAL; | |
3759 | ||
dc6d1cda | 3760 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3761 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 3762 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3763 | |
3764 | return ret; | |
3765 | } | |
3766 | ||
3767 | /** | |
3768 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
3769 | * contained in the hwmod module | |
3770 | * @oh: struct omap_hwmod * | |
3771 | * @name: name of the reset line to look up and read | |
3772 | * | |
3773 | * Return the current state of the hwmod @oh's reset line named @name: | |
3774 | * returns -EINVAL upon parameter error or if this operation | |
3775 | * is unsupported on the current OMAP; otherwise, passes along the return | |
3776 | * value from _read_hardreset(). | |
3777 | */ | |
3778 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
3779 | { | |
3780 | int ret; | |
dc6d1cda | 3781 | unsigned long flags; |
aee48e3c PW |
3782 | |
3783 | if (!oh) | |
3784 | return -EINVAL; | |
3785 | ||
dc6d1cda | 3786 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3787 | ret = _read_hardreset(oh, name); |
dc6d1cda | 3788 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3789 | |
3790 | return ret; | |
3791 | } | |
3792 | ||
3793 | ||
43b40992 PW |
3794 | /** |
3795 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
3796 | * @classname: struct omap_hwmod_class name to search for | |
3797 | * @fn: callback function pointer to call for each hwmod in class @classname | |
3798 | * @user: arbitrary context data to pass to the callback function | |
3799 | * | |
ce35b244 BC |
3800 | * For each omap_hwmod of class @classname, call @fn. |
3801 | * If the callback function returns something other than | |
43b40992 PW |
3802 | * zero, the iterator is terminated, and the callback function's return |
3803 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
3804 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
3805 | */ | |
3806 | int omap_hwmod_for_each_by_class(const char *classname, | |
3807 | int (*fn)(struct omap_hwmod *oh, | |
3808 | void *user), | |
3809 | void *user) | |
3810 | { | |
3811 | struct omap_hwmod *temp_oh; | |
3812 | int ret = 0; | |
3813 | ||
3814 | if (!classname || !fn) | |
3815 | return -EINVAL; | |
3816 | ||
3817 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
3818 | __func__, classname); | |
3819 | ||
43b40992 PW |
3820 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
3821 | if (!strcmp(temp_oh->class->name, classname)) { | |
3822 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
3823 | __func__, temp_oh->name); | |
3824 | ret = (*fn)(temp_oh, user); | |
3825 | if (ret) | |
3826 | break; | |
3827 | } | |
3828 | } | |
3829 | ||
43b40992 PW |
3830 | if (ret) |
3831 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
3832 | __func__, ret); | |
3833 | ||
3834 | return ret; | |
3835 | } | |
3836 | ||
2092e5cc PW |
3837 | /** |
3838 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
3839 | * @oh: struct omap_hwmod * | |
3840 | * @state: state that _setup() should leave the hwmod in | |
3841 | * | |
550c8092 | 3842 | * Sets the hwmod state that @oh will enter at the end of _setup() |
64813c3f PW |
3843 | * (called by omap_hwmod_setup_*()). See also the documentation |
3844 | * for _setup_postsetup(), above. Returns 0 upon success or | |
3845 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
3846 | * in the wrong state. | |
2092e5cc PW |
3847 | */ |
3848 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
3849 | { | |
3850 | int ret; | |
dc6d1cda | 3851 | unsigned long flags; |
2092e5cc PW |
3852 | |
3853 | if (!oh) | |
3854 | return -EINVAL; | |
3855 | ||
3856 | if (state != _HWMOD_STATE_DISABLED && | |
3857 | state != _HWMOD_STATE_ENABLED && | |
3858 | state != _HWMOD_STATE_IDLE) | |
3859 | return -EINVAL; | |
3860 | ||
dc6d1cda | 3861 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
3862 | |
3863 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3864 | ret = -EINVAL; | |
3865 | goto ohsps_unlock; | |
3866 | } | |
3867 | ||
3868 | oh->_postsetup_state = state; | |
3869 | ret = 0; | |
3870 | ||
3871 | ohsps_unlock: | |
dc6d1cda | 3872 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
3873 | |
3874 | return ret; | |
3875 | } | |
c80705aa KH |
3876 | |
3877 | /** | |
3878 | * omap_hwmod_get_context_loss_count - get lost context count | |
3879 | * @oh: struct omap_hwmod * | |
3880 | * | |
3881 | * Query the powerdomain of of @oh to get the context loss | |
3882 | * count for this device. | |
3883 | * | |
3884 | * Returns the context loss count of the powerdomain assocated with @oh | |
3885 | * upon success, or zero if no powerdomain exists for @oh. | |
3886 | */ | |
fc013873 | 3887 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
3888 | { |
3889 | struct powerdomain *pwrdm; | |
3890 | int ret = 0; | |
3891 | ||
3892 | pwrdm = omap_hwmod_get_pwrdm(oh); | |
3893 | if (pwrdm) | |
3894 | ret = pwrdm_get_context_loss_count(pwrdm); | |
3895 | ||
3896 | return ret; | |
3897 | } | |
43b01643 PW |
3898 | |
3899 | /** | |
3900 | * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup | |
3901 | * @oh: struct omap_hwmod * | |
3902 | * | |
3903 | * Prevent the hwmod @oh from being reset during the setup process. | |
3904 | * Intended for use by board-*.c files on boards with devices that | |
3905 | * cannot tolerate being reset. Must be called before the hwmod has | |
3906 | * been set up. Returns 0 upon success or negative error code upon | |
3907 | * failure. | |
3908 | */ | |
3909 | int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) | |
3910 | { | |
3911 | if (!oh) | |
3912 | return -EINVAL; | |
3913 | ||
3914 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3915 | pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n", | |
3916 | oh->name); | |
3917 | return -EINVAL; | |
3918 | } | |
3919 | ||
3920 | oh->flags |= HWMOD_INIT_NO_RESET; | |
3921 | ||
3922 | return 0; | |
3923 | } | |
abc2d545 TK |
3924 | |
3925 | /** | |
3926 | * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ | |
3927 | * @oh: struct omap_hwmod * containing hwmod mux entries | |
3928 | * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup | |
3929 | * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup | |
3930 | * | |
3931 | * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux | |
3932 | * entry number @pad_idx for the hwmod @oh, trigger the interrupt | |
3933 | * service routine for the hwmod's mpu_irqs array index @irq_idx. If | |
3934 | * this function is not called for a given pad_idx, then the ISR | |
3935 | * associated with @oh's first MPU IRQ will be triggered when an I/O | |
3936 | * pad wakeup occurs on that pad. Note that @pad_idx is the index of | |
3937 | * the _dynamic or wakeup_ entry: if there are other entries not | |
3938 | * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these | |
3939 | * entries are NOT COUNTED in the dynamic pad index. This function | |
3940 | * must be called separately for each pad that requires its interrupt | |
3941 | * to be re-routed this way. Returns -EINVAL if there is an argument | |
3942 | * problem or if @oh does not have hwmod mux entries or MPU IRQs; | |
3943 | * returns -ENOMEM if memory cannot be allocated; or 0 upon success. | |
3944 | * | |
3945 | * XXX This function interface is fragile. Rather than using array | |
3946 | * indexes, which are subject to unpredictable change, it should be | |
3947 | * using hwmod IRQ names, and some other stable key for the hwmod mux | |
3948 | * pad records. | |
3949 | */ | |
3950 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) | |
3951 | { | |
3952 | int nr_irqs; | |
3953 | ||
3954 | might_sleep(); | |
3955 | ||
3956 | if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 || | |
3957 | pad_idx >= oh->mux->nr_pads_dynamic) | |
3958 | return -EINVAL; | |
3959 | ||
3960 | /* Check the number of available mpu_irqs */ | |
3961 | for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++) | |
3962 | ; | |
3963 | ||
3964 | if (irq_idx >= nr_irqs) | |
3965 | return -EINVAL; | |
3966 | ||
3967 | if (!oh->mux->irqs) { | |
3968 | /* XXX What frees this? */ | |
3969 | oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic, | |
3970 | GFP_KERNEL); | |
3971 | if (!oh->mux->irqs) | |
3972 | return -ENOMEM; | |
3973 | } | |
3974 | oh->mux->irqs[pad_idx] = irq_idx; | |
3975 | ||
3976 | return 0; | |
3977 | } | |
9ebfd285 KH |
3978 | |
3979 | /** | |
3980 | * omap_hwmod_init - initialize the hwmod code | |
3981 | * | |
3982 | * Sets up some function pointers needed by the hwmod code to operate on the | |
3983 | * currently-booted SoC. Intended to be called once during kernel init | |
3984 | * before any hwmods are registered. No return value. | |
3985 | */ | |
3986 | void __init omap_hwmod_init(void) | |
3987 | { | |
ff4ae5d9 PW |
3988 | if (cpu_is_omap24xx()) { |
3989 | soc_ops.wait_target_ready = _omap2xxx_wait_target_ready; | |
3990 | soc_ops.assert_hardreset = _omap2_assert_hardreset; | |
3991 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3992 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
3993 | } else if (cpu_is_omap34xx()) { | |
3994 | soc_ops.wait_target_ready = _omap3xxx_wait_target_ready; | |
b8249cf2 KH |
3995 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
3996 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3997 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
05e152c7 | 3998 | } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { |
9ebfd285 KH |
3999 | soc_ops.enable_module = _omap4_enable_module; |
4000 | soc_ops.disable_module = _omap4_disable_module; | |
8f6aa8ee | 4001 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
b8249cf2 KH |
4002 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
4003 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | |
4004 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | |
0a179eaa | 4005 | soc_ops.init_clkdm = _init_clkdm; |
1688bf19 VH |
4006 | } else if (soc_is_am33xx()) { |
4007 | soc_ops.enable_module = _am33xx_enable_module; | |
4008 | soc_ops.disable_module = _am33xx_disable_module; | |
4009 | soc_ops.wait_target_ready = _am33xx_wait_target_ready; | |
4010 | soc_ops.assert_hardreset = _am33xx_assert_hardreset; | |
4011 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; | |
4012 | soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; | |
4013 | soc_ops.init_clkdm = _init_clkdm; | |
8f6aa8ee KH |
4014 | } else { |
4015 | WARN(1, "omap_hwmod: unknown SoC type\n"); | |
9ebfd285 KH |
4016 | } |
4017 | ||
4018 | inited = true; | |
4019 | } | |
68c9a95e TL |
4020 | |
4021 | /** | |
4022 | * omap_hwmod_get_main_clk - get pointer to main clock name | |
4023 | * @oh: struct omap_hwmod * | |
4024 | * | |
4025 | * Returns the main clock name assocated with @oh upon success, | |
4026 | * or NULL if @oh is NULL. | |
4027 | */ | |
4028 | const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) | |
4029 | { | |
4030 | if (!oh) | |
4031 | return NULL; | |
4032 | ||
4033 | return oh->main_clk; | |
4034 | } |