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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
63c85238 | 5 | * |
4788da26 PW |
6 | * Paul Walmsley, Benoît Cousson, Kevin Hilman |
7 | * | |
8 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
9 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
10 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
74ff3a68 PW |
16 | * Introduction |
17 | * ------------ | |
18 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
19 | * IP blocks connected by interconnects. The IP blocks include | |
20 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
21 | * etc. Some of these devices, like the DSP, are created by TI; | |
22 | * others, like the SGX, largely originate from external vendors. In | |
23 | * TI's documentation, on-chip devices are referred to as "OMAP | |
24 | * modules." Some of these IP blocks are identical across several | |
25 | * OMAP versions. Others are revised frequently. | |
63c85238 | 26 | * |
74ff3a68 PW |
27 | * These OMAP modules are tied together by various interconnects. |
28 | * Most of the address and data flow between modules is via OCP-based | |
29 | * interconnects such as the L3 and L4 buses; but there are other | |
30 | * interconnects that distribute the hardware clock tree, handle idle | |
31 | * and reset signaling, supply power, and connect the modules to | |
32 | * various pads or balls on the OMAP package. | |
33 | * | |
34 | * OMAP hwmod provides a consistent way to describe the on-chip | |
35 | * hardware blocks and their integration into the rest of the chip. | |
36 | * This description can be automatically generated from the TI | |
37 | * hardware database. OMAP hwmod provides a standard, consistent API | |
38 | * to reset, enable, idle, and disable these hardware blocks. And | |
39 | * hwmod provides a way for other core code, such as the Linux device | |
40 | * code or the OMAP power management and address space mapping code, | |
41 | * to query the hardware database. | |
42 | * | |
43 | * Using hwmod | |
44 | * ----------- | |
45 | * Drivers won't call hwmod functions directly. That is done by the | |
46 | * omap_device code, and in rare occasions, by custom integration code | |
47 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
48 | * build a struct platform_device using omap_hwmod data, and that is | |
49 | * currently how hwmod data is communicated to drivers and to the | |
50 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
51 | * indirectly, via pm_runtime*() functions. | |
52 | * | |
53 | * From a layering perspective, here is where the OMAP hwmod code | |
54 | * fits into the kernel software stack: | |
55 | * | |
56 | * +-------------------------------+ | |
57 | * | Device driver code | | |
58 | * | (e.g., drivers/) | | |
59 | * +-------------------------------+ | |
60 | * | Linux driver model | | |
61 | * | (platform_device / | | |
62 | * | platform_driver data/code) | | |
63 | * +-------------------------------+ | |
64 | * | OMAP core-driver integration | | |
65 | * |(arch/arm/mach-omap2/devices.c)| | |
66 | * +-------------------------------+ | |
67 | * | omap_device code | | |
68 | * | (../plat-omap/omap_device.c) | | |
69 | * +-------------------------------+ | |
70 | * ----> | omap_hwmod code/data | <----- | |
71 | * | (../mach-omap2/omap_hwmod*) | | |
72 | * +-------------------------------+ | |
73 | * | OMAP clock/PRCM/register fns | | |
74 | * | (__raw_{read,write}l, clk*) | | |
75 | * +-------------------------------+ | |
76 | * | |
77 | * Device drivers should not contain any OMAP-specific code or data in | |
78 | * them. They should only contain code to operate the IP block that | |
79 | * the driver is responsible for. This is because these IP blocks can | |
80 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
81 | * other manufacturers; and drivers should be reusable across other | |
82 | * platforms. | |
83 | * | |
84 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
85 | * devices upon boot. The goal here is for the kernel to be | |
86 | * completely self-reliant and independent from bootloaders. This is | |
87 | * to ensure a repeatable configuration, both to ensure consistent | |
88 | * runtime behavior, and to make it easier for others to reproduce | |
89 | * bugs. | |
90 | * | |
91 | * OMAP module activity states | |
92 | * --------------------------- | |
93 | * The hwmod code considers modules to be in one of several activity | |
94 | * states. IP blocks start out in an UNKNOWN state, then once they | |
95 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
96 | * Once their clock names are resolved to clock pointers, the module | |
97 | * enters the CLKS_INITED state; and finally, once the module has been | |
98 | * reset and the integration registers programmed, the INITIALIZED state | |
99 | * is entered. The hwmod code will then place the module into either | |
100 | * the IDLE state to save power, or in the case of a critical system | |
101 | * module, the ENABLED state. | |
102 | * | |
103 | * OMAP core integration code can then call omap_hwmod*() functions | |
104 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
105 | * states, as needed. This is done during both the PM idle loop, and | |
106 | * in the OMAP core integration code's implementation of the PM runtime | |
107 | * functions. | |
108 | * | |
109 | * References | |
110 | * ---------- | |
111 | * This is a partial list. | |
63c85238 PW |
112 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
113 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
114 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
115 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
116 | * - Open Core Protocol Specification 2.2 | |
117 | * | |
118 | * To do: | |
63c85238 PW |
119 | * - handle IO mapping |
120 | * - bus throughput & module latency measurement code | |
121 | * | |
122 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
123 | * in the appropriate state | |
124 | * XXX error return values should be checked to ensure that they are | |
125 | * appropriate | |
126 | */ | |
127 | #undef DEBUG | |
128 | ||
129 | #include <linux/kernel.h> | |
130 | #include <linux/errno.h> | |
131 | #include <linux/io.h> | |
132 | #include <linux/clk.h> | |
133 | #include <linux/delay.h> | |
134 | #include <linux/err.h> | |
135 | #include <linux/list.h> | |
136 | #include <linux/mutex.h> | |
dc6d1cda | 137 | #include <linux/spinlock.h> |
63c85238 | 138 | |
6f8b7ff5 | 139 | #include <plat/common.h> |
ce491cf8 | 140 | #include <plat/cpu.h> |
1540f214 | 141 | #include "clockdomain.h" |
72e06d08 | 142 | #include "powerdomain.h" |
ce491cf8 TL |
143 | #include <plat/clock.h> |
144 | #include <plat/omap_hwmod.h> | |
5365efbe | 145 | #include <plat/prcm.h> |
63c85238 | 146 | |
59fb659b PW |
147 | #include "cm2xxx_3xxx.h" |
148 | #include "cm44xx.h" | |
149 | #include "prm2xxx_3xxx.h" | |
d198b514 | 150 | #include "prm44xx.h" |
8d9af88f | 151 | #include "mux.h" |
63c85238 | 152 | |
5365efbe BC |
153 | /* Maximum microseconds to wait for OMAP module to softreset */ |
154 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | |
63c85238 PW |
155 | |
156 | /* Name of the OMAP hwmod for the MPU */ | |
5c2c0296 | 157 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 PW |
158 | |
159 | /* omap_hwmod_list contains all registered struct omap_hwmods */ | |
160 | static LIST_HEAD(omap_hwmod_list); | |
161 | ||
63c85238 PW |
162 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
163 | static struct omap_hwmod *mpu_oh; | |
164 | ||
63c85238 PW |
165 | |
166 | /* Private functions */ | |
167 | ||
168 | /** | |
169 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
170 | * @oh: struct omap_hwmod * | |
171 | * | |
172 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
173 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
174 | * OCP_SYSCONFIG register or 0 upon success. | |
175 | */ | |
176 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
177 | { | |
43b40992 PW |
178 | if (!oh->class->sysc) { |
179 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
180 | return -EINVAL; |
181 | } | |
182 | ||
183 | /* XXX ensure module interface clock is up */ | |
184 | ||
cc7a1d2a | 185 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 186 | |
43b40992 | 187 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 188 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
189 | |
190 | return 0; | |
191 | } | |
192 | ||
193 | /** | |
194 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
195 | * @v: OCP_SYSCONFIG value to write | |
196 | * @oh: struct omap_hwmod * | |
197 | * | |
43b40992 PW |
198 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
199 | * one. No return value. | |
63c85238 PW |
200 | */ |
201 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
202 | { | |
43b40992 PW |
203 | if (!oh->class->sysc) { |
204 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
205 | return; |
206 | } | |
207 | ||
208 | /* XXX ensure module interface clock is up */ | |
209 | ||
233cbe5b RN |
210 | /* Module might have lost context, always update cache and register */ |
211 | oh->_sysc_cache = v; | |
212 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); | |
63c85238 PW |
213 | } |
214 | ||
215 | /** | |
216 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
217 | * @oh: struct omap_hwmod * | |
218 | * @standbymode: MIDLEMODE field bits | |
219 | * @v: pointer to register contents to modify | |
220 | * | |
221 | * Update the master standby mode bits in @v to be @standbymode for | |
222 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
223 | * upon error or 0 upon success. | |
224 | */ | |
225 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
226 | u32 *v) | |
227 | { | |
358f0e63 TG |
228 | u32 mstandby_mask; |
229 | u8 mstandby_shift; | |
230 | ||
43b40992 PW |
231 | if (!oh->class->sysc || |
232 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
233 | return -EINVAL; |
234 | ||
43b40992 PW |
235 | if (!oh->class->sysc->sysc_fields) { |
236 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
237 | return -EINVAL; |
238 | } | |
239 | ||
43b40992 | 240 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
241 | mstandby_mask = (0x3 << mstandby_shift); |
242 | ||
243 | *v &= ~mstandby_mask; | |
244 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
245 | |
246 | return 0; | |
247 | } | |
248 | ||
249 | /** | |
250 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
251 | * @oh: struct omap_hwmod * | |
252 | * @idlemode: SIDLEMODE field bits | |
253 | * @v: pointer to register contents to modify | |
254 | * | |
255 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
256 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
257 | * or 0 upon success. | |
258 | */ | |
259 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
260 | { | |
358f0e63 TG |
261 | u32 sidle_mask; |
262 | u8 sidle_shift; | |
263 | ||
43b40992 PW |
264 | if (!oh->class->sysc || |
265 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
266 | return -EINVAL; |
267 | ||
43b40992 PW |
268 | if (!oh->class->sysc->sysc_fields) { |
269 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
270 | return -EINVAL; |
271 | } | |
272 | ||
43b40992 | 273 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
274 | sidle_mask = (0x3 << sidle_shift); |
275 | ||
276 | *v &= ~sidle_mask; | |
277 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
278 | |
279 | return 0; | |
280 | } | |
281 | ||
282 | /** | |
283 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
284 | * @oh: struct omap_hwmod * | |
285 | * @clockact: CLOCKACTIVITY field bits | |
286 | * @v: pointer to register contents to modify | |
287 | * | |
288 | * Update the clockactivity mode bits in @v to be @clockact for the | |
289 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
290 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
291 | * success. | |
292 | */ | |
293 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
294 | { | |
358f0e63 TG |
295 | u32 clkact_mask; |
296 | u8 clkact_shift; | |
297 | ||
43b40992 PW |
298 | if (!oh->class->sysc || |
299 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
300 | return -EINVAL; |
301 | ||
43b40992 PW |
302 | if (!oh->class->sysc->sysc_fields) { |
303 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
304 | return -EINVAL; |
305 | } | |
306 | ||
43b40992 | 307 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
308 | clkact_mask = (0x3 << clkact_shift); |
309 | ||
310 | *v &= ~clkact_mask; | |
311 | *v |= clockact << clkact_shift; | |
63c85238 PW |
312 | |
313 | return 0; | |
314 | } | |
315 | ||
316 | /** | |
317 | * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
318 | * @oh: struct omap_hwmod * | |
319 | * @v: pointer to register contents to modify | |
320 | * | |
321 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
322 | * error or 0 upon success. | |
323 | */ | |
324 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
325 | { | |
358f0e63 TG |
326 | u32 softrst_mask; |
327 | ||
43b40992 PW |
328 | if (!oh->class->sysc || |
329 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
330 | return -EINVAL; |
331 | ||
43b40992 PW |
332 | if (!oh->class->sysc->sysc_fields) { |
333 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
334 | return -EINVAL; |
335 | } | |
336 | ||
43b40992 | 337 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
338 | |
339 | *v |= softrst_mask; | |
63c85238 PW |
340 | |
341 | return 0; | |
342 | } | |
343 | ||
726072e5 PW |
344 | /** |
345 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
346 | * @oh: struct omap_hwmod * | |
347 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
348 | * @v: pointer to register contents to modify | |
349 | * | |
350 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
351 | * hwmod. The autoidle bit controls whether the module can gate | |
352 | * internal clocks automatically when it isn't doing anything; the | |
353 | * exact function of this bit varies on a per-module basis. This | |
354 | * function does not write to the hardware. Returns -EINVAL upon | |
355 | * error or 0 upon success. | |
356 | */ | |
357 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
358 | u32 *v) | |
359 | { | |
358f0e63 TG |
360 | u32 autoidle_mask; |
361 | u8 autoidle_shift; | |
362 | ||
43b40992 PW |
363 | if (!oh->class->sysc || |
364 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
365 | return -EINVAL; |
366 | ||
43b40992 PW |
367 | if (!oh->class->sysc->sysc_fields) { |
368 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
369 | return -EINVAL; |
370 | } | |
371 | ||
43b40992 | 372 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 373 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
374 | |
375 | *v &= ~autoidle_mask; | |
376 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
377 | |
378 | return 0; | |
379 | } | |
380 | ||
63c85238 PW |
381 | /** |
382 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
383 | * @oh: struct omap_hwmod * | |
384 | * | |
385 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
386 | * upon error or 0 upon success. | |
387 | */ | |
5a7ddcbd | 388 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 389 | { |
43b40992 | 390 | if (!oh->class->sysc || |
86009eb3 | 391 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
392 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
393 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
394 | return -EINVAL; |
395 | ||
43b40992 PW |
396 | if (!oh->class->sysc->sysc_fields) { |
397 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
398 | return -EINVAL; |
399 | } | |
400 | ||
1fe74113 BC |
401 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
402 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 403 | |
86009eb3 BC |
404 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
405 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
406 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
407 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 408 | |
63c85238 PW |
409 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
410 | ||
411 | oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
416 | /** | |
417 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
418 | * @oh: struct omap_hwmod * | |
419 | * | |
420 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
421 | * upon error or 0 upon success. | |
422 | */ | |
5a7ddcbd | 423 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 424 | { |
43b40992 | 425 | if (!oh->class->sysc || |
86009eb3 | 426 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
427 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
428 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
429 | return -EINVAL; |
430 | ||
43b40992 PW |
431 | if (!oh->class->sysc->sysc_fields) { |
432 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
433 | return -EINVAL; |
434 | } | |
435 | ||
1fe74113 BC |
436 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
437 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 438 | |
86009eb3 BC |
439 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
440 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 BC |
441 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
442 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 443 | |
63c85238 PW |
444 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
445 | ||
446 | oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; | |
447 | ||
448 | return 0; | |
449 | } | |
450 | ||
451 | /** | |
452 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
453 | * @oh: struct omap_hwmod * | |
454 | * | |
455 | * Prevent the hardware module @oh from entering idle while the | |
456 | * hardare module initiator @init_oh is active. Useful when a module | |
457 | * will be accessed by a particular initiator (e.g., if a module will | |
458 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
459 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
460 | * mode. If the clockdomain is marked as not needing autodeps, return |
461 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
462 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
463 | */ |
464 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
465 | { | |
466 | if (!oh->_clk) | |
467 | return -EINVAL; | |
468 | ||
570b54c7 PW |
469 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
470 | return 0; | |
471 | ||
55ed9694 | 472 | return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
473 | } |
474 | ||
475 | /** | |
476 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
477 | * @oh: struct omap_hwmod * | |
478 | * | |
479 | * Allow the hardware module @oh to enter idle while the hardare | |
480 | * module initiator @init_oh is active. Useful when a module will not | |
481 | * be accessed by a particular initiator (e.g., if a module will not | |
482 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
483 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
484 | * mode. If the clockdomain is marked as not needing autodeps, return |
485 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
486 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
487 | */ |
488 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
489 | { | |
490 | if (!oh->_clk) | |
491 | return -EINVAL; | |
492 | ||
570b54c7 PW |
493 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
494 | return 0; | |
495 | ||
55ed9694 | 496 | return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
497 | } |
498 | ||
499 | /** | |
500 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
501 | * @oh: struct omap_hwmod * | |
502 | * | |
503 | * Called from _init_clocks(). Populates the @oh _clk (main | |
504 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
505 | * success or -EINVAL on error. | |
506 | */ | |
507 | static int _init_main_clk(struct omap_hwmod *oh) | |
508 | { | |
63c85238 PW |
509 | int ret = 0; |
510 | ||
50ebdac2 | 511 | if (!oh->main_clk) |
63c85238 PW |
512 | return 0; |
513 | ||
63403384 | 514 | oh->_clk = omap_clk_get_by_name(oh->main_clk); |
dc75925d | 515 | if (!oh->_clk) { |
20383d82 BC |
516 | pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
517 | oh->name, oh->main_clk); | |
63403384 | 518 | return -EINVAL; |
dc75925d | 519 | } |
63c85238 | 520 | |
63403384 BC |
521 | if (!oh->_clk->clkdm) |
522 | pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", | |
523 | oh->main_clk, oh->_clk->name); | |
81d7c6ff | 524 | |
63c85238 PW |
525 | return ret; |
526 | } | |
527 | ||
528 | /** | |
887adeac | 529 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
530 | * @oh: struct omap_hwmod * |
531 | * | |
532 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
533 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
534 | */ | |
535 | static int _init_interface_clks(struct omap_hwmod *oh) | |
536 | { | |
63c85238 PW |
537 | struct clk *c; |
538 | int i; | |
539 | int ret = 0; | |
540 | ||
541 | if (oh->slaves_cnt == 0) | |
542 | return 0; | |
543 | ||
682fdc96 BC |
544 | for (i = 0; i < oh->slaves_cnt; i++) { |
545 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
546 | ||
50ebdac2 | 547 | if (!os->clk) |
63c85238 PW |
548 | continue; |
549 | ||
50ebdac2 | 550 | c = omap_clk_get_by_name(os->clk); |
dc75925d | 551 | if (!c) { |
20383d82 BC |
552 | pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
553 | oh->name, os->clk); | |
63c85238 | 554 | ret = -EINVAL; |
dc75925d | 555 | } |
63c85238 PW |
556 | os->_clk = c; |
557 | } | |
558 | ||
559 | return ret; | |
560 | } | |
561 | ||
562 | /** | |
563 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
564 | * @oh: struct omap_hwmod * | |
565 | * | |
566 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
567 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
568 | */ | |
569 | static int _init_opt_clks(struct omap_hwmod *oh) | |
570 | { | |
571 | struct omap_hwmod_opt_clk *oc; | |
572 | struct clk *c; | |
573 | int i; | |
574 | int ret = 0; | |
575 | ||
576 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
50ebdac2 | 577 | c = omap_clk_get_by_name(oc->clk); |
dc75925d | 578 | if (!c) { |
20383d82 BC |
579 | pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
580 | oh->name, oc->clk); | |
63c85238 | 581 | ret = -EINVAL; |
dc75925d | 582 | } |
63c85238 PW |
583 | oc->_clk = c; |
584 | } | |
585 | ||
586 | return ret; | |
587 | } | |
588 | ||
589 | /** | |
590 | * _enable_clocks - enable hwmod main clock and interface clocks | |
591 | * @oh: struct omap_hwmod * | |
592 | * | |
593 | * Enables all clocks necessary for register reads and writes to succeed | |
594 | * on the hwmod @oh. Returns 0. | |
595 | */ | |
596 | static int _enable_clocks(struct omap_hwmod *oh) | |
597 | { | |
63c85238 PW |
598 | int i; |
599 | ||
600 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
601 | ||
4d3ae5a9 | 602 | if (oh->_clk) |
63c85238 PW |
603 | clk_enable(oh->_clk); |
604 | ||
605 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
606 | for (i = 0; i < oh->slaves_cnt; i++) { |
607 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
608 | struct clk *c = os->_clk; |
609 | ||
4d3ae5a9 | 610 | if (c && (os->flags & OCPIF_SWSUP_IDLE)) |
63c85238 PW |
611 | clk_enable(c); |
612 | } | |
613 | } | |
614 | ||
615 | /* The opt clocks are controlled by the device driver. */ | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
620 | /** | |
621 | * _disable_clocks - disable hwmod main clock and interface clocks | |
622 | * @oh: struct omap_hwmod * | |
623 | * | |
624 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
625 | */ | |
626 | static int _disable_clocks(struct omap_hwmod *oh) | |
627 | { | |
63c85238 PW |
628 | int i; |
629 | ||
630 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
631 | ||
4d3ae5a9 | 632 | if (oh->_clk) |
63c85238 PW |
633 | clk_disable(oh->_clk); |
634 | ||
635 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
636 | for (i = 0; i < oh->slaves_cnt; i++) { |
637 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
638 | struct clk *c = os->_clk; |
639 | ||
4d3ae5a9 | 640 | if (c && (os->flags & OCPIF_SWSUP_IDLE)) |
63c85238 PW |
641 | clk_disable(c); |
642 | } | |
643 | } | |
644 | ||
645 | /* The opt clocks are controlled by the device driver. */ | |
646 | ||
647 | return 0; | |
648 | } | |
649 | ||
96835af9 BC |
650 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
651 | { | |
652 | struct omap_hwmod_opt_clk *oc; | |
653 | int i; | |
654 | ||
655 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
656 | ||
657 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
658 | if (oc->_clk) { | |
659 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
660 | oc->_clk->name); | |
661 | clk_enable(oc->_clk); | |
662 | } | |
663 | } | |
664 | ||
665 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
666 | { | |
667 | struct omap_hwmod_opt_clk *oc; | |
668 | int i; | |
669 | ||
670 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
671 | ||
672 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
673 | if (oc->_clk) { | |
674 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
675 | oc->_clk->name); | |
676 | clk_disable(oc->_clk); | |
677 | } | |
678 | } | |
679 | ||
63c85238 PW |
680 | /** |
681 | * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use | |
682 | * @oh: struct omap_hwmod * | |
683 | * | |
684 | * Returns the array index of the OCP slave port that the MPU | |
685 | * addresses the device on, or -EINVAL upon error or not found. | |
686 | */ | |
01592df9 | 687 | static int __init _find_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 688 | { |
63c85238 PW |
689 | int i; |
690 | int found = 0; | |
691 | ||
692 | if (!oh || oh->slaves_cnt == 0) | |
693 | return -EINVAL; | |
694 | ||
682fdc96 BC |
695 | for (i = 0; i < oh->slaves_cnt; i++) { |
696 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
697 | ||
63c85238 PW |
698 | if (os->user & OCP_USER_MPU) { |
699 | found = 1; | |
700 | break; | |
701 | } | |
702 | } | |
703 | ||
704 | if (found) | |
705 | pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n", | |
706 | oh->name, i); | |
707 | else | |
708 | pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n", | |
709 | oh->name); | |
710 | ||
711 | return (found) ? i : -EINVAL; | |
712 | } | |
713 | ||
714 | /** | |
715 | * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU | |
716 | * @oh: struct omap_hwmod * | |
717 | * | |
718 | * Return the virtual address of the base of the register target of | |
719 | * device @oh, or NULL on error. | |
720 | */ | |
01592df9 | 721 | static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) |
63c85238 PW |
722 | { |
723 | struct omap_hwmod_ocp_if *os; | |
724 | struct omap_hwmod_addr_space *mem; | |
725 | int i; | |
726 | int found = 0; | |
986a13f5 | 727 | void __iomem *va_start; |
63c85238 PW |
728 | |
729 | if (!oh || oh->slaves_cnt == 0) | |
730 | return NULL; | |
731 | ||
682fdc96 | 732 | os = oh->slaves[index]; |
63c85238 PW |
733 | |
734 | for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) { | |
735 | if (mem->flags & ADDR_TYPE_RT) { | |
736 | found = 1; | |
737 | break; | |
738 | } | |
739 | } | |
740 | ||
986a13f5 TL |
741 | if (found) { |
742 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
743 | if (!va_start) { | |
744 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
745 | return NULL; | |
746 | } | |
63c85238 | 747 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", |
986a13f5 TL |
748 | oh->name, va_start); |
749 | } else { | |
63c85238 PW |
750 | pr_debug("omap_hwmod: %s: no MPU register target found\n", |
751 | oh->name); | |
986a13f5 | 752 | } |
63c85238 | 753 | |
986a13f5 | 754 | return (found) ? va_start : NULL; |
63c85238 PW |
755 | } |
756 | ||
757 | /** | |
74ff3a68 | 758 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
759 | * @oh: struct omap_hwmod * |
760 | * | |
761 | * If module is marked as SWSUP_SIDLE, force the module out of slave | |
762 | * idle; otherwise, configure it for smart-idle. If module is marked | |
763 | * as SWSUP_MSUSPEND, force the module out of master standby; | |
764 | * otherwise, configure it for smart-standby. No return value. | |
765 | */ | |
74ff3a68 | 766 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 767 | { |
43b40992 | 768 | u8 idlemode, sf; |
63c85238 PW |
769 | u32 v; |
770 | ||
43b40992 | 771 | if (!oh->class->sysc) |
63c85238 PW |
772 | return; |
773 | ||
774 | v = oh->_sysc_cache; | |
43b40992 | 775 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 776 | |
43b40992 | 777 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
778 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
779 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
780 | _set_slave_idlemode(oh, idlemode, &v); | |
781 | } | |
782 | ||
43b40992 | 783 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
784 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
785 | idlemode = HWMOD_IDLEMODE_NO; | |
786 | } else { | |
787 | if (sf & SYSC_HAS_ENAWAKEUP) | |
788 | _enable_wakeup(oh, &v); | |
789 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
790 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
791 | else | |
792 | idlemode = HWMOD_IDLEMODE_SMART; | |
793 | } | |
63c85238 PW |
794 | _set_master_standbymode(oh, idlemode, &v); |
795 | } | |
796 | ||
a16b1f7f PW |
797 | /* |
798 | * XXX The clock framework should handle this, by | |
799 | * calling into this code. But this must wait until the | |
800 | * clock structures are tagged with omap_hwmod entries | |
801 | */ | |
43b40992 PW |
802 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
803 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
804 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 | 805 | |
9980ce53 RN |
806 | /* If slave is in SMARTIDLE, also enable wakeup */ |
807 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
5a7ddcbd KH |
808 | _enable_wakeup(oh, &v); |
809 | ||
810 | _write_sysconfig(v, oh); | |
78f26e87 HH |
811 | |
812 | /* | |
813 | * Set the autoidle bit only after setting the smartidle bit | |
814 | * Setting this will not have any impact on the other modules. | |
815 | */ | |
816 | if (sf & SYSC_HAS_AUTOIDLE) { | |
817 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
818 | 0 : 1; | |
819 | _set_module_autoidle(oh, idlemode, &v); | |
820 | _write_sysconfig(v, oh); | |
821 | } | |
63c85238 PW |
822 | } |
823 | ||
824 | /** | |
74ff3a68 | 825 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
826 | * @oh: struct omap_hwmod * |
827 | * | |
828 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
829 | * idle; otherwise, configure it for smart-idle. If module is marked | |
830 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
831 | * configure it for smart-standby. No return value. | |
832 | */ | |
74ff3a68 | 833 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 834 | { |
43b40992 | 835 | u8 idlemode, sf; |
63c85238 PW |
836 | u32 v; |
837 | ||
43b40992 | 838 | if (!oh->class->sysc) |
63c85238 PW |
839 | return; |
840 | ||
841 | v = oh->_sysc_cache; | |
43b40992 | 842 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 843 | |
43b40992 | 844 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
845 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
846 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | |
847 | _set_slave_idlemode(oh, idlemode, &v); | |
848 | } | |
849 | ||
43b40992 | 850 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
851 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
852 | idlemode = HWMOD_IDLEMODE_FORCE; | |
853 | } else { | |
854 | if (sf & SYSC_HAS_ENAWAKEUP) | |
855 | _enable_wakeup(oh, &v); | |
856 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
857 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
858 | else | |
859 | idlemode = HWMOD_IDLEMODE_SMART; | |
860 | } | |
63c85238 PW |
861 | _set_master_standbymode(oh, idlemode, &v); |
862 | } | |
863 | ||
86009eb3 BC |
864 | /* If slave is in SMARTIDLE, also enable wakeup */ |
865 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
866 | _enable_wakeup(oh, &v); | |
867 | ||
63c85238 PW |
868 | _write_sysconfig(v, oh); |
869 | } | |
870 | ||
871 | /** | |
74ff3a68 | 872 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
873 | * @oh: struct omap_hwmod * |
874 | * | |
875 | * Force the module into slave idle and master suspend. No return | |
876 | * value. | |
877 | */ | |
74ff3a68 | 878 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
879 | { |
880 | u32 v; | |
43b40992 | 881 | u8 sf; |
63c85238 | 882 | |
43b40992 | 883 | if (!oh->class->sysc) |
63c85238 PW |
884 | return; |
885 | ||
886 | v = oh->_sysc_cache; | |
43b40992 | 887 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 888 | |
43b40992 | 889 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
890 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
891 | ||
43b40992 | 892 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
893 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
894 | ||
43b40992 | 895 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 896 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
897 | |
898 | _write_sysconfig(v, oh); | |
899 | } | |
900 | ||
901 | /** | |
902 | * _lookup - find an omap_hwmod by name | |
903 | * @name: find an omap_hwmod by name | |
904 | * | |
905 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
906 | */ |
907 | static struct omap_hwmod *_lookup(const char *name) | |
908 | { | |
909 | struct omap_hwmod *oh, *temp_oh; | |
910 | ||
911 | oh = NULL; | |
912 | ||
913 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
914 | if (!strcmp(name, temp_oh->name)) { | |
915 | oh = temp_oh; | |
916 | break; | |
917 | } | |
918 | } | |
919 | ||
920 | return oh; | |
921 | } | |
922 | ||
923 | /** | |
924 | * _init_clocks - clk_get() all clocks associated with this hwmod | |
925 | * @oh: struct omap_hwmod * | |
97d60162 | 926 | * @data: not used; pass NULL |
63c85238 | 927 | * |
a2debdbd | 928 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
929 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
930 | * success, or a negative error code on failure. | |
63c85238 | 931 | */ |
97d60162 | 932 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
933 | { |
934 | int ret = 0; | |
935 | ||
48d54f3f PW |
936 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
937 | return 0; | |
63c85238 PW |
938 | |
939 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
940 | ||
941 | ret |= _init_main_clk(oh); | |
942 | ret |= _init_interface_clks(oh); | |
943 | ret |= _init_opt_clks(oh); | |
944 | ||
f5c1f84b BC |
945 | if (!ret) |
946 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a BC |
947 | else |
948 | pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name); | |
63c85238 | 949 | |
09c35f2f | 950 | return ret; |
63c85238 PW |
951 | } |
952 | ||
953 | /** | |
954 | * _wait_target_ready - wait for a module to leave slave idle | |
955 | * @oh: struct omap_hwmod * | |
956 | * | |
957 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
958 | * does not have an IDLEST bit or if the module successfully leaves | |
959 | * slave idle; otherwise, pass along the return value of the | |
960 | * appropriate *_cm_wait_module_ready() function. | |
961 | */ | |
962 | static int _wait_target_ready(struct omap_hwmod *oh) | |
963 | { | |
964 | struct omap_hwmod_ocp_if *os; | |
965 | int ret; | |
966 | ||
967 | if (!oh) | |
968 | return -EINVAL; | |
969 | ||
970 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
971 | return 0; | |
972 | ||
682fdc96 | 973 | os = oh->slaves[oh->_mpu_port_index]; |
63c85238 | 974 | |
33f7ec81 | 975 | if (oh->flags & HWMOD_NO_IDLEST) |
63c85238 PW |
976 | return 0; |
977 | ||
978 | /* XXX check module SIDLEMODE */ | |
979 | ||
980 | /* XXX check clock enable states */ | |
981 | ||
982 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
983 | ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, | |
984 | oh->prcm.omap2.idlest_reg_id, | |
985 | oh->prcm.omap2.idlest_idle_bit); | |
63c85238 | 986 | } else if (cpu_is_omap44xx()) { |
9a23dfe1 | 987 | ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg); |
63c85238 PW |
988 | } else { |
989 | BUG(); | |
990 | }; | |
991 | ||
992 | return ret; | |
993 | } | |
994 | ||
5365efbe | 995 | /** |
cc1226e7 | 996 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
997 | * @oh: struct omap_hwmod * |
998 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 999 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1000 | * |
1001 | * Return the bit position of the reset line that match the | |
1002 | * input name. Return -ENOENT if not found. | |
1003 | */ | |
cc1226e7 | 1004 | static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1005 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1006 | { |
1007 | int i; | |
1008 | ||
1009 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1010 | const char *rst_line = oh->rst_lines[i].name; | |
1011 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1012 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1013 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1014 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1015 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1016 | ohri->st_shift); | |
5365efbe | 1017 | |
cc1226e7 | 1018 | return 0; |
5365efbe BC |
1019 | } |
1020 | } | |
1021 | ||
1022 | return -ENOENT; | |
1023 | } | |
1024 | ||
1025 | /** | |
1026 | * _assert_hardreset - assert the HW reset line of submodules | |
1027 | * contained in the hwmod module. | |
1028 | * @oh: struct omap_hwmod * | |
1029 | * @name: name of the reset line to lookup and assert | |
1030 | * | |
1031 | * Some IP like dsp, ipu or iva contain processor that require | |
1032 | * an HW reset line to be assert / deassert in order to enable fully | |
1033 | * the IP. | |
1034 | */ | |
1035 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1036 | { | |
cc1226e7 | 1037 | struct omap_hwmod_rst_info ohri; |
1038 | u8 ret; | |
5365efbe BC |
1039 | |
1040 | if (!oh) | |
1041 | return -EINVAL; | |
1042 | ||
cc1226e7 | 1043 | ret = _lookup_hardreset(oh, name, &ohri); |
1044 | if (IS_ERR_VALUE(ret)) | |
1045 | return ret; | |
5365efbe BC |
1046 | |
1047 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1048 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | |
cc1226e7 | 1049 | ohri.rst_shift); |
5365efbe BC |
1050 | else if (cpu_is_omap44xx()) |
1051 | return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg, | |
cc1226e7 | 1052 | ohri.rst_shift); |
5365efbe BC |
1053 | else |
1054 | return -EINVAL; | |
1055 | } | |
1056 | ||
1057 | /** | |
1058 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1059 | * in the hwmod module. | |
1060 | * @oh: struct omap_hwmod * | |
1061 | * @name: name of the reset line to look up and deassert | |
1062 | * | |
1063 | * Some IP like dsp, ipu or iva contain processor that require | |
1064 | * an HW reset line to be assert / deassert in order to enable fully | |
1065 | * the IP. | |
1066 | */ | |
1067 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1068 | { | |
cc1226e7 | 1069 | struct omap_hwmod_rst_info ohri; |
1070 | int ret; | |
5365efbe BC |
1071 | |
1072 | if (!oh) | |
1073 | return -EINVAL; | |
1074 | ||
cc1226e7 | 1075 | ret = _lookup_hardreset(oh, name, &ohri); |
1076 | if (IS_ERR_VALUE(ret)) | |
1077 | return ret; | |
5365efbe | 1078 | |
cc1226e7 | 1079 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
1080 | ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | |
1081 | ohri.rst_shift, | |
1082 | ohri.st_shift); | |
1083 | } else if (cpu_is_omap44xx()) { | |
1084 | if (ohri.st_shift) | |
1085 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
1086 | oh->name, name); | |
1087 | ret = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg, | |
1088 | ohri.rst_shift); | |
1089 | } else { | |
5365efbe | 1090 | return -EINVAL; |
cc1226e7 | 1091 | } |
5365efbe | 1092 | |
cc1226e7 | 1093 | if (ret == -EBUSY) |
5365efbe BC |
1094 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); |
1095 | ||
cc1226e7 | 1096 | return ret; |
5365efbe BC |
1097 | } |
1098 | ||
1099 | /** | |
1100 | * _read_hardreset - read the HW reset line state of submodules | |
1101 | * contained in the hwmod module | |
1102 | * @oh: struct omap_hwmod * | |
1103 | * @name: name of the reset line to look up and read | |
1104 | * | |
1105 | * Return the state of the reset line. | |
1106 | */ | |
1107 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1108 | { | |
cc1226e7 | 1109 | struct omap_hwmod_rst_info ohri; |
1110 | u8 ret; | |
5365efbe BC |
1111 | |
1112 | if (!oh) | |
1113 | return -EINVAL; | |
1114 | ||
cc1226e7 | 1115 | ret = _lookup_hardreset(oh, name, &ohri); |
1116 | if (IS_ERR_VALUE(ret)) | |
1117 | return ret; | |
5365efbe BC |
1118 | |
1119 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1120 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | |
cc1226e7 | 1121 | ohri.st_shift); |
5365efbe BC |
1122 | } else if (cpu_is_omap44xx()) { |
1123 | return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg, | |
cc1226e7 | 1124 | ohri.rst_shift); |
5365efbe BC |
1125 | } else { |
1126 | return -EINVAL; | |
1127 | } | |
1128 | } | |
1129 | ||
63c85238 | 1130 | /** |
bd36179e | 1131 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1132 | * @oh: struct omap_hwmod * |
1133 | * | |
1134 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
12b1fdb4 KH |
1135 | * enabled for this to work. Returns -EINVAL if the hwmod cannot be |
1136 | * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if | |
1137 | * the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1138 | * |
1139 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1140 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1141 | * use the SYSCONFIG softreset bit to provide the status. |
1142 | * | |
bd36179e PW |
1143 | * Note that some IP like McBSP do have reset control but don't have |
1144 | * reset status. | |
63c85238 | 1145 | */ |
bd36179e | 1146 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1147 | { |
96835af9 | 1148 | u32 v; |
6f8b7ff5 | 1149 | int c = 0; |
96835af9 | 1150 | int ret = 0; |
63c85238 | 1151 | |
43b40992 | 1152 | if (!oh->class->sysc || |
2cb06814 | 1153 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
63c85238 PW |
1154 | return -EINVAL; |
1155 | ||
1156 | /* clocks must be on for this operation */ | |
1157 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
76e5589e BC |
1158 | pr_warning("omap_hwmod: %s: reset can only be entered from " |
1159 | "enabled state\n", oh->name); | |
63c85238 PW |
1160 | return -EINVAL; |
1161 | } | |
1162 | ||
96835af9 BC |
1163 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1164 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1165 | _enable_optional_clocks(oh); | |
1166 | ||
bd36179e | 1167 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1168 | |
1169 | v = oh->_sysc_cache; | |
96835af9 BC |
1170 | ret = _set_softreset(oh, &v); |
1171 | if (ret) | |
1172 | goto dis_opt_clks; | |
63c85238 PW |
1173 | _write_sysconfig(v, oh); |
1174 | ||
2cb06814 | 1175 | if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) |
cc7a1d2a | 1176 | omap_test_timeout((omap_hwmod_read(oh, |
2cb06814 BC |
1177 | oh->class->sysc->syss_offs) |
1178 | & SYSS_RESETDONE_MASK), | |
1179 | MAX_MODULE_SOFTRESET_WAIT, c); | |
1180 | else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) | |
cc7a1d2a | 1181 | omap_test_timeout(!(omap_hwmod_read(oh, |
2cb06814 BC |
1182 | oh->class->sysc->sysc_offs) |
1183 | & SYSC_TYPE2_SOFTRESET_MASK), | |
1184 | MAX_MODULE_SOFTRESET_WAIT, c); | |
63c85238 | 1185 | |
5365efbe | 1186 | if (c == MAX_MODULE_SOFTRESET_WAIT) |
76e5589e BC |
1187 | pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1188 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
63c85238 | 1189 | else |
5365efbe | 1190 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
63c85238 PW |
1191 | |
1192 | /* | |
1193 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1194 | * _wait_target_ready() or _reset() | |
1195 | */ | |
1196 | ||
96835af9 BC |
1197 | ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; |
1198 | ||
1199 | dis_opt_clks: | |
1200 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1201 | _disable_optional_clocks(oh); | |
1202 | ||
1203 | return ret; | |
63c85238 PW |
1204 | } |
1205 | ||
bd36179e PW |
1206 | /** |
1207 | * _reset - reset an omap_hwmod | |
1208 | * @oh: struct omap_hwmod * | |
1209 | * | |
1210 | * Resets an omap_hwmod @oh. The default software reset mechanism for | |
1211 | * most OMAP IP blocks is triggered via the OCP_SYSCONFIG.SOFTRESET | |
1212 | * bit. However, some hwmods cannot be reset via this method: some | |
1213 | * are not targets and therefore have no OCP header registers to | |
1214 | * access; others (like the IVA) have idiosyncratic reset sequences. | |
1215 | * So for these relatively rare cases, custom reset code can be | |
1216 | * supplied in the struct omap_hwmod_class .reset function pointer. | |
1217 | * Passes along the return value from either _reset() or the custom | |
1218 | * reset function - these must return -EINVAL if the hwmod cannot be | |
1219 | * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if | |
1220 | * the module did not reset in time, or 0 upon success. | |
1221 | */ | |
1222 | static int _reset(struct omap_hwmod *oh) | |
1223 | { | |
1224 | int ret; | |
1225 | ||
1226 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1227 | ||
1228 | ret = (oh->class->reset) ? oh->class->reset(oh) : _ocp_softreset(oh); | |
1229 | ||
1230 | return ret; | |
1231 | } | |
1232 | ||
63c85238 | 1233 | /** |
dc6d1cda | 1234 | * _enable - enable an omap_hwmod |
63c85238 PW |
1235 | * @oh: struct omap_hwmod * |
1236 | * | |
1237 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
1238 | * register target. Returns -EINVAL if the hwmod is in the wrong |
1239 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 1240 | */ |
dc6d1cda | 1241 | static int _enable(struct omap_hwmod *oh) |
63c85238 PW |
1242 | { |
1243 | int r; | |
1244 | ||
1245 | if (oh->_state != _HWMOD_STATE_INITIALIZED && | |
1246 | oh->_state != _HWMOD_STATE_IDLE && | |
1247 | oh->_state != _HWMOD_STATE_DISABLED) { | |
1248 | WARN(1, "omap_hwmod: %s: enabled state can only be entered " | |
1249 | "from initialized, idle, or disabled state\n", oh->name); | |
1250 | return -EINVAL; | |
1251 | } | |
1252 | ||
1253 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); | |
1254 | ||
8d9af88f | 1255 | /* Mux pins for device runtime if populated */ |
029268e4 TL |
1256 | if (oh->mux && (!oh->mux->enabled || |
1257 | ((oh->_state == _HWMOD_STATE_IDLE) && | |
1258 | oh->mux->pads_dynamic))) | |
8d9af88f | 1259 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); |
63c85238 PW |
1260 | |
1261 | _add_initiator_dep(oh, mpu_oh); | |
1262 | _enable_clocks(oh); | |
1263 | ||
31f62866 BC |
1264 | /* |
1265 | * If an IP contains only one HW reset line, then de-assert it in order | |
1266 | * to allow the module state transition. Otherwise the PRCM will return | |
1267 | * Intransition status, and the init will failed. | |
1268 | */ | |
1269 | if ((oh->_state == _HWMOD_STATE_INITIALIZED || | |
1270 | oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) | |
1271 | _deassert_hardreset(oh, oh->rst_lines[0].name); | |
1272 | ||
63c85238 | 1273 | r = _wait_target_ready(oh); |
9a23dfe1 | 1274 | if (!r) { |
63c85238 PW |
1275 | oh->_state = _HWMOD_STATE_ENABLED; |
1276 | ||
9a23dfe1 BC |
1277 | /* Access the sysconfig only if the target is ready */ |
1278 | if (oh->class->sysc) { | |
1279 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
1280 | _update_sysc_cache(oh); | |
74ff3a68 | 1281 | _enable_sysc(oh); |
9a23dfe1 BC |
1282 | } |
1283 | } else { | |
f2dd7e09 | 1284 | _disable_clocks(oh); |
9a23dfe1 BC |
1285 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", |
1286 | oh->name, r); | |
1287 | } | |
1288 | ||
63c85238 PW |
1289 | return r; |
1290 | } | |
1291 | ||
1292 | /** | |
dc6d1cda | 1293 | * _idle - idle an omap_hwmod |
63c85238 PW |
1294 | * @oh: struct omap_hwmod * |
1295 | * | |
1296 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
1297 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
1298 | * state or returns 0. | |
63c85238 | 1299 | */ |
dc6d1cda | 1300 | static int _idle(struct omap_hwmod *oh) |
63c85238 PW |
1301 | { |
1302 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
1303 | WARN(1, "omap_hwmod: %s: idle state can only be entered from " | |
1304 | "enabled state\n", oh->name); | |
1305 | return -EINVAL; | |
1306 | } | |
1307 | ||
1308 | pr_debug("omap_hwmod: %s: idling\n", oh->name); | |
1309 | ||
43b40992 | 1310 | if (oh->class->sysc) |
74ff3a68 | 1311 | _idle_sysc(oh); |
63c85238 PW |
1312 | _del_initiator_dep(oh, mpu_oh); |
1313 | _disable_clocks(oh); | |
1314 | ||
8d9af88f | 1315 | /* Mux pins for device idle if populated */ |
029268e4 | 1316 | if (oh->mux && oh->mux->pads_dynamic) |
8d9af88f TL |
1317 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); |
1318 | ||
63c85238 PW |
1319 | oh->_state = _HWMOD_STATE_IDLE; |
1320 | ||
1321 | return 0; | |
1322 | } | |
1323 | ||
9599217a KVA |
1324 | /** |
1325 | * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit | |
1326 | * @oh: struct omap_hwmod * | |
1327 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
1328 | * | |
1329 | * Sets the IP block's OCP autoidle bit in hardware, and updates our | |
1330 | * local copy. Intended to be used by drivers that require | |
1331 | * direct manipulation of the AUTOIDLE bits. | |
1332 | * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes | |
1333 | * along the return value from _set_module_autoidle(). | |
1334 | * | |
1335 | * Any users of this function should be scrutinized carefully. | |
1336 | */ | |
1337 | int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) | |
1338 | { | |
1339 | u32 v; | |
1340 | int retval = 0; | |
1341 | unsigned long flags; | |
1342 | ||
1343 | if (!oh || oh->_state != _HWMOD_STATE_ENABLED) | |
1344 | return -EINVAL; | |
1345 | ||
1346 | spin_lock_irqsave(&oh->_lock, flags); | |
1347 | ||
1348 | v = oh->_sysc_cache; | |
1349 | ||
1350 | retval = _set_module_autoidle(oh, autoidle, &v); | |
1351 | ||
1352 | if (!retval) | |
1353 | _write_sysconfig(v, oh); | |
1354 | ||
1355 | spin_unlock_irqrestore(&oh->_lock, flags); | |
1356 | ||
1357 | return retval; | |
1358 | } | |
1359 | ||
63c85238 PW |
1360 | /** |
1361 | * _shutdown - shutdown an omap_hwmod | |
1362 | * @oh: struct omap_hwmod * | |
1363 | * | |
1364 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
1365 | * used for the hwmod is removed or unloaded or if the driver is not | |
1366 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
1367 | * state or returns 0. | |
1368 | */ | |
1369 | static int _shutdown(struct omap_hwmod *oh) | |
1370 | { | |
e4dc8f50 PW |
1371 | int ret; |
1372 | u8 prev_state; | |
1373 | ||
63c85238 PW |
1374 | if (oh->_state != _HWMOD_STATE_IDLE && |
1375 | oh->_state != _HWMOD_STATE_ENABLED) { | |
1376 | WARN(1, "omap_hwmod: %s: disabled state can only be entered " | |
1377 | "from idle, or enabled state\n", oh->name); | |
1378 | return -EINVAL; | |
1379 | } | |
1380 | ||
1381 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); | |
1382 | ||
e4dc8f50 PW |
1383 | if (oh->class->pre_shutdown) { |
1384 | prev_state = oh->_state; | |
1385 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1386 | _enable(oh); |
e4dc8f50 PW |
1387 | ret = oh->class->pre_shutdown(oh); |
1388 | if (ret) { | |
1389 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1390 | _idle(oh); |
e4dc8f50 PW |
1391 | return ret; |
1392 | } | |
1393 | } | |
1394 | ||
6481c73c MV |
1395 | if (oh->class->sysc) { |
1396 | if (oh->_state == _HWMOD_STATE_IDLE) | |
1397 | _enable(oh); | |
74ff3a68 | 1398 | _shutdown_sysc(oh); |
6481c73c | 1399 | } |
3827f949 BC |
1400 | |
1401 | /* clocks and deps are already disabled in idle */ | |
1402 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
1403 | _del_initiator_dep(oh, mpu_oh); | |
1404 | /* XXX what about the other system initiators here? dma, dsp */ | |
1405 | _disable_clocks(oh); | |
1406 | } | |
63c85238 PW |
1407 | /* XXX Should this code also force-disable the optional clocks? */ |
1408 | ||
31f62866 BC |
1409 | /* |
1410 | * If an IP contains only one HW reset line, then assert it | |
1411 | * after disabling the clocks and before shutting down the IP. | |
1412 | */ | |
1413 | if (oh->rst_lines_cnt == 1) | |
1414 | _assert_hardreset(oh, oh->rst_lines[0].name); | |
1415 | ||
8d9af88f TL |
1416 | /* Mux pins to safe mode or use populated off mode values */ |
1417 | if (oh->mux) | |
1418 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); | |
63c85238 PW |
1419 | |
1420 | oh->_state = _HWMOD_STATE_DISABLED; | |
1421 | ||
1422 | return 0; | |
1423 | } | |
1424 | ||
63c85238 PW |
1425 | /** |
1426 | * _setup - do initial configuration of omap_hwmod | |
1427 | * @oh: struct omap_hwmod * | |
1428 | * | |
1429 | * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh | |
48d54f3f | 1430 | * OCP_SYSCONFIG register. Returns 0. |
63c85238 | 1431 | */ |
97d60162 | 1432 | static int _setup(struct omap_hwmod *oh, void *data) |
63c85238 | 1433 | { |
9a23dfe1 | 1434 | int i, r; |
2092e5cc | 1435 | u8 postsetup_state; |
97d60162 | 1436 | |
48d54f3f PW |
1437 | if (oh->_state != _HWMOD_STATE_CLKS_INITED) |
1438 | return 0; | |
1439 | ||
63c85238 PW |
1440 | /* Set iclk autoidle mode */ |
1441 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
1442 | for (i = 0; i < oh->slaves_cnt; i++) { |
1443 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
1444 | struct clk *c = os->_clk; |
1445 | ||
4d3ae5a9 | 1446 | if (!c) |
63c85238 PW |
1447 | continue; |
1448 | ||
1449 | if (os->flags & OCPIF_SWSUP_IDLE) { | |
1450 | /* XXX omap_iclk_deny_idle(c); */ | |
1451 | } else { | |
1452 | /* XXX omap_iclk_allow_idle(c); */ | |
1453 | clk_enable(c); | |
1454 | } | |
1455 | } | |
1456 | } | |
1457 | ||
1458 | oh->_state = _HWMOD_STATE_INITIALIZED; | |
1459 | ||
5365efbe BC |
1460 | /* |
1461 | * In the case of hwmod with hardreset that should not be | |
1462 | * de-assert at boot time, we have to keep the module | |
1463 | * initialized, because we cannot enable it properly with the | |
1464 | * reset asserted. Exit without warning because that behavior is | |
1465 | * expected. | |
1466 | */ | |
1467 | if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) | |
1468 | return 0; | |
1469 | ||
dc6d1cda | 1470 | r = _enable(oh); |
9a23dfe1 BC |
1471 | if (r) { |
1472 | pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", | |
1473 | oh->name, oh->_state); | |
1474 | return 0; | |
1475 | } | |
63c85238 | 1476 | |
b835d014 | 1477 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) { |
76e5589e BC |
1478 | _reset(oh); |
1479 | ||
b835d014 | 1480 | /* |
76e5589e | 1481 | * OCP_SYSCONFIG bits need to be reprogrammed after a softreset. |
dc6d1cda | 1482 | * The _enable() function should be split to |
76e5589e | 1483 | * avoid the rewrite of the OCP_SYSCONFIG register. |
b835d014 | 1484 | */ |
43b40992 | 1485 | if (oh->class->sysc) { |
b835d014 | 1486 | _update_sysc_cache(oh); |
74ff3a68 | 1487 | _enable_sysc(oh); |
b835d014 PW |
1488 | } |
1489 | } | |
63c85238 | 1490 | |
2092e5cc PW |
1491 | postsetup_state = oh->_postsetup_state; |
1492 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
1493 | postsetup_state = _HWMOD_STATE_ENABLED; | |
1494 | ||
1495 | /* | |
1496 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
1497 | * it should be set by the core code as a runtime flag during startup | |
1498 | */ | |
1499 | if ((oh->flags & HWMOD_INIT_NO_IDLE) && | |
1500 | (postsetup_state == _HWMOD_STATE_IDLE)) | |
1501 | postsetup_state = _HWMOD_STATE_ENABLED; | |
1502 | ||
1503 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1504 | _idle(oh); |
2092e5cc PW |
1505 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
1506 | _shutdown(oh); | |
1507 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
1508 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
1509 | oh->name, postsetup_state); | |
63c85238 PW |
1510 | |
1511 | return 0; | |
1512 | } | |
1513 | ||
63c85238 | 1514 | /** |
0102b627 | 1515 | * _register - register a struct omap_hwmod |
63c85238 PW |
1516 | * @oh: struct omap_hwmod * |
1517 | * | |
43b40992 PW |
1518 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
1519 | * already has been registered by the same name; -EINVAL if the | |
1520 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
1521 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
1522 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
1523 | * success. | |
63c85238 PW |
1524 | * |
1525 | * XXX The data should be copied into bootmem, so the original data | |
1526 | * should be marked __initdata and freed after init. This would allow | |
1527 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
1528 | * that the copy process would be relatively complex due to the large number | |
1529 | * of substructures. | |
1530 | */ | |
01592df9 | 1531 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 1532 | { |
569edd70 | 1533 | int ms_id; |
63c85238 | 1534 | |
43b40992 PW |
1535 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
1536 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
1537 | return -EINVAL; |
1538 | ||
63c85238 PW |
1539 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
1540 | ||
ce35b244 BC |
1541 | if (_lookup(oh->name)) |
1542 | return -EEXIST; | |
63c85238 PW |
1543 | |
1544 | ms_id = _find_mpu_port_index(oh); | |
e7c7d760 | 1545 | if (!IS_ERR_VALUE(ms_id)) |
63c85238 | 1546 | oh->_mpu_port_index = ms_id; |
e7c7d760 | 1547 | else |
63c85238 | 1548 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; |
63c85238 PW |
1549 | |
1550 | list_add_tail(&oh->node, &omap_hwmod_list); | |
1551 | ||
dc6d1cda | 1552 | spin_lock_init(&oh->_lock); |
2092e5cc | 1553 | |
63c85238 PW |
1554 | oh->_state = _HWMOD_STATE_REGISTERED; |
1555 | ||
569edd70 PW |
1556 | /* |
1557 | * XXX Rather than doing a strcmp(), this should test a flag | |
1558 | * set in the hwmod data, inserted by the autogenerator code. | |
1559 | */ | |
1560 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
1561 | mpu_oh = oh; | |
63c85238 | 1562 | |
569edd70 | 1563 | return 0; |
63c85238 PW |
1564 | } |
1565 | ||
0102b627 BC |
1566 | |
1567 | /* Public functions */ | |
1568 | ||
1569 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
1570 | { | |
1571 | if (oh->flags & HWMOD_16BIT_REG) | |
1572 | return __raw_readw(oh->_mpu_rt_va + reg_offs); | |
1573 | else | |
1574 | return __raw_readl(oh->_mpu_rt_va + reg_offs); | |
1575 | } | |
1576 | ||
1577 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
1578 | { | |
1579 | if (oh->flags & HWMOD_16BIT_REG) | |
1580 | __raw_writew(v, oh->_mpu_rt_va + reg_offs); | |
1581 | else | |
1582 | __raw_writel(v, oh->_mpu_rt_va + reg_offs); | |
1583 | } | |
1584 | ||
1585 | /** | |
1586 | * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode | |
1587 | * @oh: struct omap_hwmod * | |
1588 | * @idlemode: SIDLEMODE field bits (shifted to bit 0) | |
1589 | * | |
1590 | * Sets the IP block's OCP slave idlemode in hardware, and updates our | |
1591 | * local copy. Intended to be used by drivers that have some erratum | |
1592 | * that requires direct manipulation of the SIDLEMODE bits. Returns | |
1593 | * -EINVAL if @oh is null, or passes along the return value from | |
1594 | * _set_slave_idlemode(). | |
1595 | * | |
1596 | * XXX Does this function have any current users? If not, we should | |
1597 | * remove it; it is better to let the rest of the hwmod code handle this. | |
1598 | * Any users of this function should be scrutinized carefully. | |
1599 | */ | |
1600 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) | |
1601 | { | |
1602 | u32 v; | |
1603 | int retval = 0; | |
1604 | ||
1605 | if (!oh) | |
1606 | return -EINVAL; | |
1607 | ||
1608 | v = oh->_sysc_cache; | |
1609 | ||
1610 | retval = _set_slave_idlemode(oh, idlemode, &v); | |
1611 | if (!retval) | |
1612 | _write_sysconfig(v, oh); | |
1613 | ||
1614 | return retval; | |
1615 | } | |
1616 | ||
63c85238 PW |
1617 | /** |
1618 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
1619 | * @name: name of the omap_hwmod to look up | |
1620 | * | |
1621 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
1622 | * struct omap_hwmod *, or NULL upon error. | |
1623 | */ | |
1624 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
1625 | { | |
1626 | struct omap_hwmod *oh; | |
1627 | ||
1628 | if (!name) | |
1629 | return NULL; | |
1630 | ||
63c85238 | 1631 | oh = _lookup(name); |
63c85238 PW |
1632 | |
1633 | return oh; | |
1634 | } | |
1635 | ||
1636 | /** | |
1637 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
1638 | * @fn: pointer to a callback function | |
97d60162 | 1639 | * @data: void * data to pass to callback function |
63c85238 PW |
1640 | * |
1641 | * Call @fn for each registered omap_hwmod, passing @data to each | |
1642 | * function. @fn must return 0 for success or any other value for | |
1643 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
1644 | * will stop and the non-zero return value will be passed to the | |
1645 | * caller of omap_hwmod_for_each(). @fn is called with | |
1646 | * omap_hwmod_for_each() held. | |
1647 | */ | |
97d60162 PW |
1648 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
1649 | void *data) | |
63c85238 PW |
1650 | { |
1651 | struct omap_hwmod *temp_oh; | |
30ebad9d | 1652 | int ret = 0; |
63c85238 PW |
1653 | |
1654 | if (!fn) | |
1655 | return -EINVAL; | |
1656 | ||
63c85238 | 1657 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 1658 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
1659 | if (ret) |
1660 | break; | |
1661 | } | |
63c85238 PW |
1662 | |
1663 | return ret; | |
1664 | } | |
1665 | ||
63c85238 | 1666 | /** |
550c8092 | 1667 | * omap_hwmod_register - register an array of hwmods |
63c85238 PW |
1668 | * @ohs: pointer to an array of omap_hwmods to register |
1669 | * | |
1670 | * Intended to be called early in boot before the clock framework is | |
1671 | * initialized. If @ohs is not null, will register all omap_hwmods | |
550c8092 | 1672 | * listed in @ohs that are valid for this chip. Returns 0. |
63c85238 | 1673 | */ |
550c8092 | 1674 | int __init omap_hwmod_register(struct omap_hwmod **ohs) |
63c85238 | 1675 | { |
bac1a0f0 | 1676 | int r, i; |
63c85238 PW |
1677 | |
1678 | if (!ohs) | |
1679 | return 0; | |
1680 | ||
bac1a0f0 PW |
1681 | i = 0; |
1682 | do { | |
1683 | if (!omap_chip_is(ohs[i]->omap_chip)) | |
1684 | continue; | |
1685 | ||
1686 | r = _register(ohs[i]); | |
1687 | WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name, | |
1688 | r); | |
1689 | } while (ohs[++i]); | |
63c85238 PW |
1690 | |
1691 | return 0; | |
1692 | } | |
1693 | ||
e7c7d760 TL |
1694 | /* |
1695 | * _populate_mpu_rt_base - populate the virtual address for a hwmod | |
1696 | * | |
a2debdbd | 1697 | * Must be called only from omap_hwmod_setup_*() so ioremap works properly. |
e7c7d760 | 1698 | * Assumes the caller takes care of locking if needed. |
63c85238 | 1699 | */ |
e7c7d760 TL |
1700 | static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) |
1701 | { | |
48d54f3f PW |
1702 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1703 | return 0; | |
1704 | ||
e7c7d760 TL |
1705 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
1706 | return 0; | |
1707 | ||
1708 | oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); | |
e7c7d760 TL |
1709 | |
1710 | return 0; | |
1711 | } | |
1712 | ||
63c85238 | 1713 | /** |
a2debdbd PW |
1714 | * omap_hwmod_setup_one - set up a single hwmod |
1715 | * @oh_name: const char * name of the already-registered hwmod to set up | |
1716 | * | |
1717 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
1718 | * names to struct clk pointers for each registered omap_hwmod. Also | |
1719 | * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon | |
1720 | * success. | |
1721 | */ | |
1722 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
1723 | { |
1724 | struct omap_hwmod *oh; | |
1725 | int r; | |
1726 | ||
a2debdbd PW |
1727 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
1728 | ||
1729 | if (!mpu_oh) { | |
1730 | pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n", | |
1731 | oh_name, MPU_INITIATOR_NAME); | |
63c85238 | 1732 | return -EINVAL; |
a2debdbd | 1733 | } |
63c85238 | 1734 | |
a2debdbd PW |
1735 | oh = _lookup(oh_name); |
1736 | if (!oh) { | |
1737 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
1738 | return -EINVAL; | |
1739 | } | |
63c85238 | 1740 | |
a2debdbd PW |
1741 | if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) |
1742 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
63c85238 | 1743 | |
a2debdbd PW |
1744 | r = _populate_mpu_rt_base(oh, NULL); |
1745 | if (IS_ERR_VALUE(r)) { | |
1746 | WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name); | |
1747 | return -EINVAL; | |
1748 | } | |
1749 | ||
1750 | r = _init_clocks(oh, NULL); | |
1751 | if (IS_ERR_VALUE(r)) { | |
1752 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name); | |
1753 | return -EINVAL; | |
63c85238 PW |
1754 | } |
1755 | ||
a2debdbd PW |
1756 | _setup(oh, NULL); |
1757 | ||
63c85238 PW |
1758 | return 0; |
1759 | } | |
1760 | ||
1761 | /** | |
550c8092 | 1762 | * omap_hwmod_setup - do some post-clock framework initialization |
63c85238 PW |
1763 | * |
1764 | * Must be called after omap2_clk_init(). Resolves the struct clk names | |
1765 | * to struct clk pointers for each registered omap_hwmod. Also calls | |
a2debdbd | 1766 | * _setup() on each hwmod. Returns 0 upon success. |
63c85238 | 1767 | */ |
550c8092 | 1768 | static int __init omap_hwmod_setup_all(void) |
63c85238 PW |
1769 | { |
1770 | int r; | |
1771 | ||
569edd70 PW |
1772 | if (!mpu_oh) { |
1773 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
1774 | __func__, MPU_INITIATOR_NAME); | |
1775 | return -EINVAL; | |
1776 | } | |
1777 | ||
e7c7d760 | 1778 | r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); |
63c85238 | 1779 | |
97d60162 | 1780 | r = omap_hwmod_for_each(_init_clocks, NULL); |
a2debdbd PW |
1781 | WARN(IS_ERR_VALUE(r), |
1782 | "omap_hwmod: %s: _init_clocks failed\n", __func__); | |
63c85238 | 1783 | |
2092e5cc | 1784 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
1785 | |
1786 | return 0; | |
1787 | } | |
550c8092 | 1788 | core_initcall(omap_hwmod_setup_all); |
63c85238 | 1789 | |
63c85238 PW |
1790 | /** |
1791 | * omap_hwmod_enable - enable an omap_hwmod | |
1792 | * @oh: struct omap_hwmod * | |
1793 | * | |
74ff3a68 | 1794 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
1795 | * Returns -EINVAL on error or passes along the return value from _enable(). |
1796 | */ | |
1797 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
1798 | { | |
1799 | int r; | |
dc6d1cda | 1800 | unsigned long flags; |
63c85238 PW |
1801 | |
1802 | if (!oh) | |
1803 | return -EINVAL; | |
1804 | ||
dc6d1cda PW |
1805 | spin_lock_irqsave(&oh->_lock, flags); |
1806 | r = _enable(oh); | |
1807 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
1808 | |
1809 | return r; | |
1810 | } | |
1811 | ||
1812 | /** | |
1813 | * omap_hwmod_idle - idle an omap_hwmod | |
1814 | * @oh: struct omap_hwmod * | |
1815 | * | |
74ff3a68 | 1816 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
1817 | * Returns -EINVAL on error or passes along the return value from _idle(). |
1818 | */ | |
1819 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
1820 | { | |
dc6d1cda PW |
1821 | unsigned long flags; |
1822 | ||
63c85238 PW |
1823 | if (!oh) |
1824 | return -EINVAL; | |
1825 | ||
dc6d1cda PW |
1826 | spin_lock_irqsave(&oh->_lock, flags); |
1827 | _idle(oh); | |
1828 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
1829 | |
1830 | return 0; | |
1831 | } | |
1832 | ||
1833 | /** | |
1834 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
1835 | * @oh: struct omap_hwmod * | |
1836 | * | |
74ff3a68 | 1837 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
1838 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
1839 | * the return value from _shutdown(). | |
1840 | */ | |
1841 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
1842 | { | |
dc6d1cda PW |
1843 | unsigned long flags; |
1844 | ||
63c85238 PW |
1845 | if (!oh) |
1846 | return -EINVAL; | |
1847 | ||
dc6d1cda | 1848 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 1849 | _shutdown(oh); |
dc6d1cda | 1850 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
1851 | |
1852 | return 0; | |
1853 | } | |
1854 | ||
1855 | /** | |
1856 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
1857 | * @oh: struct omap_hwmod *oh | |
1858 | * | |
1859 | * Intended to be called by the omap_device code. | |
1860 | */ | |
1861 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
1862 | { | |
dc6d1cda PW |
1863 | unsigned long flags; |
1864 | ||
1865 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 1866 | _enable_clocks(oh); |
dc6d1cda | 1867 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
1868 | |
1869 | return 0; | |
1870 | } | |
1871 | ||
1872 | /** | |
1873 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
1874 | * @oh: struct omap_hwmod *oh | |
1875 | * | |
1876 | * Intended to be called by the omap_device code. | |
1877 | */ | |
1878 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
1879 | { | |
dc6d1cda PW |
1880 | unsigned long flags; |
1881 | ||
1882 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 1883 | _disable_clocks(oh); |
dc6d1cda | 1884 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
1885 | |
1886 | return 0; | |
1887 | } | |
1888 | ||
1889 | /** | |
1890 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
1891 | * @oh: struct omap_hwmod *oh | |
1892 | * | |
1893 | * Intended to be called by drivers and core code when all posted | |
1894 | * writes to a device must complete before continuing further | |
1895 | * execution (for example, after clearing some device IRQSTATUS | |
1896 | * register bits) | |
1897 | * | |
1898 | * XXX what about targets with multiple OCP threads? | |
1899 | */ | |
1900 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
1901 | { | |
1902 | BUG_ON(!oh); | |
1903 | ||
43b40992 | 1904 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
63c85238 PW |
1905 | WARN(1, "omap_device: %s: OCP barrier impossible due to " |
1906 | "device configuration\n", oh->name); | |
1907 | return; | |
1908 | } | |
1909 | ||
1910 | /* | |
1911 | * Forces posted writes to complete on the OCP thread handling | |
1912 | * register writes | |
1913 | */ | |
cc7a1d2a | 1914 | omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
1915 | } |
1916 | ||
1917 | /** | |
1918 | * omap_hwmod_reset - reset the hwmod | |
1919 | * @oh: struct omap_hwmod * | |
1920 | * | |
1921 | * Under some conditions, a driver may wish to reset the entire device. | |
1922 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 1923 | * the return value from _reset(). |
63c85238 PW |
1924 | */ |
1925 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
1926 | { | |
1927 | int r; | |
dc6d1cda | 1928 | unsigned long flags; |
63c85238 | 1929 | |
9b579114 | 1930 | if (!oh) |
63c85238 PW |
1931 | return -EINVAL; |
1932 | ||
dc6d1cda | 1933 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 1934 | r = _reset(oh); |
dc6d1cda | 1935 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
1936 | |
1937 | return r; | |
1938 | } | |
1939 | ||
1940 | /** | |
1941 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
1942 | * @oh: struct omap_hwmod * | |
1943 | * @res: pointer to the first element of an array of struct resource to fill | |
1944 | * | |
1945 | * Count the number of struct resource array elements necessary to | |
1946 | * contain omap_hwmod @oh resources. Intended to be called by code | |
1947 | * that registers omap_devices. Intended to be used to determine the | |
1948 | * size of a dynamically-allocated struct resource array, before | |
1949 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
1950 | * resource array elements needed. | |
1951 | * | |
1952 | * XXX This code is not optimized. It could attempt to merge adjacent | |
1953 | * resource IDs. | |
1954 | * | |
1955 | */ | |
1956 | int omap_hwmod_count_resources(struct omap_hwmod *oh) | |
1957 | { | |
1958 | int ret, i; | |
1959 | ||
9ee9fff9 | 1960 | ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt; |
63c85238 PW |
1961 | |
1962 | for (i = 0; i < oh->slaves_cnt; i++) | |
682fdc96 | 1963 | ret += oh->slaves[i]->addr_cnt; |
63c85238 PW |
1964 | |
1965 | return ret; | |
1966 | } | |
1967 | ||
1968 | /** | |
1969 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
1970 | * @oh: struct omap_hwmod * | |
1971 | * @res: pointer to the first element of an array of struct resource to fill | |
1972 | * | |
1973 | * Fill the struct resource array @res with resource data from the | |
1974 | * omap_hwmod @oh. Intended to be called by code that registers | |
1975 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
1976 | * number of array elements filled. | |
1977 | */ | |
1978 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
1979 | { | |
1980 | int i, j; | |
1981 | int r = 0; | |
1982 | ||
1983 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
1984 | ||
1985 | for (i = 0; i < oh->mpu_irqs_cnt; i++) { | |
718bfd76 PW |
1986 | (res + r)->name = (oh->mpu_irqs + i)->name; |
1987 | (res + r)->start = (oh->mpu_irqs + i)->irq; | |
1988 | (res + r)->end = (oh->mpu_irqs + i)->irq; | |
63c85238 PW |
1989 | (res + r)->flags = IORESOURCE_IRQ; |
1990 | r++; | |
1991 | } | |
1992 | ||
9ee9fff9 BC |
1993 | for (i = 0; i < oh->sdma_reqs_cnt; i++) { |
1994 | (res + r)->name = (oh->sdma_reqs + i)->name; | |
1995 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
1996 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
1997 | (res + r)->flags = IORESOURCE_DMA; |
1998 | r++; | |
1999 | } | |
2000 | ||
2001 | for (i = 0; i < oh->slaves_cnt; i++) { | |
2002 | struct omap_hwmod_ocp_if *os; | |
2003 | ||
682fdc96 | 2004 | os = oh->slaves[i]; |
63c85238 PW |
2005 | |
2006 | for (j = 0; j < os->addr_cnt; j++) { | |
cd503802 | 2007 | (res + r)->name = (os->addr + j)->name; |
63c85238 PW |
2008 | (res + r)->start = (os->addr + j)->pa_start; |
2009 | (res + r)->end = (os->addr + j)->pa_end; | |
2010 | (res + r)->flags = IORESOURCE_MEM; | |
2011 | r++; | |
2012 | } | |
2013 | } | |
2014 | ||
2015 | return r; | |
2016 | } | |
2017 | ||
2018 | /** | |
2019 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
2020 | * @oh: struct omap_hwmod * | |
2021 | * | |
2022 | * Return the powerdomain pointer associated with the OMAP module | |
2023 | * @oh's main clock. If @oh does not have a main clk, return the | |
2024 | * powerdomain associated with the interface clock associated with the | |
2025 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
2026 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
2027 | * success. | |
2028 | */ | |
2029 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
2030 | { | |
2031 | struct clk *c; | |
2032 | ||
2033 | if (!oh) | |
2034 | return NULL; | |
2035 | ||
2036 | if (oh->_clk) { | |
2037 | c = oh->_clk; | |
2038 | } else { | |
2039 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
2040 | return NULL; | |
2041 | c = oh->slaves[oh->_mpu_port_index]->_clk; | |
2042 | } | |
2043 | ||
d5647c18 TG |
2044 | if (!c->clkdm) |
2045 | return NULL; | |
2046 | ||
63c85238 PW |
2047 | return c->clkdm->pwrdm.ptr; |
2048 | ||
2049 | } | |
2050 | ||
db2a60bf PW |
2051 | /** |
2052 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
2053 | * @oh: struct omap_hwmod * | |
2054 | * | |
2055 | * Returns the virtual address corresponding to the beginning of the | |
2056 | * module's register target, in the address range that is intended to | |
2057 | * be used by the MPU. Returns the virtual address upon success or NULL | |
2058 | * upon error. | |
2059 | */ | |
2060 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
2061 | { | |
2062 | if (!oh) | |
2063 | return NULL; | |
2064 | ||
2065 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
2066 | return NULL; | |
2067 | ||
2068 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
2069 | return NULL; | |
2070 | ||
2071 | return oh->_mpu_rt_va; | |
2072 | } | |
2073 | ||
63c85238 PW |
2074 | /** |
2075 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
2076 | * @oh: struct omap_hwmod * | |
2077 | * @init_oh: struct omap_hwmod * (initiator) | |
2078 | * | |
2079 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
2080 | * Intended to be called by DSP/Bridge code via platform_data for the | |
2081 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
2082 | * code needs to add/del initiator dependencies dynamically | |
2083 | * before/after accessing a device. Returns the return value from | |
2084 | * _add_initiator_dep(). | |
2085 | * | |
2086 | * XXX Keep a usecount in the clockdomain code | |
2087 | */ | |
2088 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
2089 | struct omap_hwmod *init_oh) | |
2090 | { | |
2091 | return _add_initiator_dep(oh, init_oh); | |
2092 | } | |
2093 | ||
2094 | /* | |
2095 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
2096 | * for context save/restore operations? | |
2097 | */ | |
2098 | ||
2099 | /** | |
2100 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
2101 | * @oh: struct omap_hwmod * | |
2102 | * @init_oh: struct omap_hwmod * (initiator) | |
2103 | * | |
2104 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
2105 | * Intended to be called by DSP/Bridge code via platform_data for the | |
2106 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
2107 | * code needs to add/del initiator dependencies dynamically | |
2108 | * before/after accessing a device. Returns the return value from | |
2109 | * _del_initiator_dep(). | |
2110 | * | |
2111 | * XXX Keep a usecount in the clockdomain code | |
2112 | */ | |
2113 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
2114 | struct omap_hwmod *init_oh) | |
2115 | { | |
2116 | return _del_initiator_dep(oh, init_oh); | |
2117 | } | |
2118 | ||
63c85238 PW |
2119 | /** |
2120 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
2121 | * @oh: struct omap_hwmod * | |
2122 | * | |
2123 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2124 | * send wakeups to the PRCM. Eventually this should sets PRCM wakeup | |
2125 | * registers to cause the PRCM to receive wakeup events from the | |
2126 | * module. Does not set any wakeup routing registers beyond this | |
2127 | * point - if the module is to wake up any other module or subsystem, | |
2128 | * that must be set separately. Called by omap_device code. Returns | |
2129 | * -EINVAL on error or 0 upon success. | |
2130 | */ | |
2131 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
2132 | { | |
dc6d1cda | 2133 | unsigned long flags; |
5a7ddcbd | 2134 | u32 v; |
dc6d1cda | 2135 | |
43b40992 PW |
2136 | if (!oh->class->sysc || |
2137 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
2138 | return -EINVAL; |
2139 | ||
dc6d1cda | 2140 | spin_lock_irqsave(&oh->_lock, flags); |
5a7ddcbd KH |
2141 | v = oh->_sysc_cache; |
2142 | _enable_wakeup(oh, &v); | |
2143 | _write_sysconfig(v, oh); | |
dc6d1cda | 2144 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2145 | |
2146 | return 0; | |
2147 | } | |
2148 | ||
2149 | /** | |
2150 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
2151 | * @oh: struct omap_hwmod * | |
2152 | * | |
2153 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2154 | * from sending wakeups to the PRCM. Eventually this should clear | |
2155 | * PRCM wakeup registers to cause the PRCM to ignore wakeup events | |
2156 | * from the module. Does not set any wakeup routing registers beyond | |
2157 | * this point - if the module is to wake up any other module or | |
2158 | * subsystem, that must be set separately. Called by omap_device | |
2159 | * code. Returns -EINVAL on error or 0 upon success. | |
2160 | */ | |
2161 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
2162 | { | |
dc6d1cda | 2163 | unsigned long flags; |
5a7ddcbd | 2164 | u32 v; |
dc6d1cda | 2165 | |
43b40992 PW |
2166 | if (!oh->class->sysc || |
2167 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
2168 | return -EINVAL; |
2169 | ||
dc6d1cda | 2170 | spin_lock_irqsave(&oh->_lock, flags); |
5a7ddcbd KH |
2171 | v = oh->_sysc_cache; |
2172 | _disable_wakeup(oh, &v); | |
2173 | _write_sysconfig(v, oh); | |
dc6d1cda | 2174 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2175 | |
2176 | return 0; | |
2177 | } | |
43b40992 | 2178 | |
aee48e3c PW |
2179 | /** |
2180 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
2181 | * contained in the hwmod module. | |
2182 | * @oh: struct omap_hwmod * | |
2183 | * @name: name of the reset line to lookup and assert | |
2184 | * | |
2185 | * Some IP like dsp, ipu or iva contain processor that require | |
2186 | * an HW reset line to be assert / deassert in order to enable fully | |
2187 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
2188 | * yet supported on this OMAP; otherwise, passes along the return value | |
2189 | * from _assert_hardreset(). | |
2190 | */ | |
2191 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
2192 | { | |
2193 | int ret; | |
dc6d1cda | 2194 | unsigned long flags; |
aee48e3c PW |
2195 | |
2196 | if (!oh) | |
2197 | return -EINVAL; | |
2198 | ||
dc6d1cda | 2199 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 2200 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 2201 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
2202 | |
2203 | return ret; | |
2204 | } | |
2205 | ||
2206 | /** | |
2207 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
2208 | * contained in the hwmod module. | |
2209 | * @oh: struct omap_hwmod * | |
2210 | * @name: name of the reset line to look up and deassert | |
2211 | * | |
2212 | * Some IP like dsp, ipu or iva contain processor that require | |
2213 | * an HW reset line to be assert / deassert in order to enable fully | |
2214 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
2215 | * yet supported on this OMAP; otherwise, passes along the return value | |
2216 | * from _deassert_hardreset(). | |
2217 | */ | |
2218 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
2219 | { | |
2220 | int ret; | |
dc6d1cda | 2221 | unsigned long flags; |
aee48e3c PW |
2222 | |
2223 | if (!oh) | |
2224 | return -EINVAL; | |
2225 | ||
dc6d1cda | 2226 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 2227 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 2228 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
2229 | |
2230 | return ret; | |
2231 | } | |
2232 | ||
2233 | /** | |
2234 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
2235 | * contained in the hwmod module | |
2236 | * @oh: struct omap_hwmod * | |
2237 | * @name: name of the reset line to look up and read | |
2238 | * | |
2239 | * Return the current state of the hwmod @oh's reset line named @name: | |
2240 | * returns -EINVAL upon parameter error or if this operation | |
2241 | * is unsupported on the current OMAP; otherwise, passes along the return | |
2242 | * value from _read_hardreset(). | |
2243 | */ | |
2244 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
2245 | { | |
2246 | int ret; | |
dc6d1cda | 2247 | unsigned long flags; |
aee48e3c PW |
2248 | |
2249 | if (!oh) | |
2250 | return -EINVAL; | |
2251 | ||
dc6d1cda | 2252 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 2253 | ret = _read_hardreset(oh, name); |
dc6d1cda | 2254 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
2255 | |
2256 | return ret; | |
2257 | } | |
2258 | ||
2259 | ||
43b40992 PW |
2260 | /** |
2261 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
2262 | * @classname: struct omap_hwmod_class name to search for | |
2263 | * @fn: callback function pointer to call for each hwmod in class @classname | |
2264 | * @user: arbitrary context data to pass to the callback function | |
2265 | * | |
ce35b244 BC |
2266 | * For each omap_hwmod of class @classname, call @fn. |
2267 | * If the callback function returns something other than | |
43b40992 PW |
2268 | * zero, the iterator is terminated, and the callback function's return |
2269 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
2270 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
2271 | */ | |
2272 | int omap_hwmod_for_each_by_class(const char *classname, | |
2273 | int (*fn)(struct omap_hwmod *oh, | |
2274 | void *user), | |
2275 | void *user) | |
2276 | { | |
2277 | struct omap_hwmod *temp_oh; | |
2278 | int ret = 0; | |
2279 | ||
2280 | if (!classname || !fn) | |
2281 | return -EINVAL; | |
2282 | ||
2283 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
2284 | __func__, classname); | |
2285 | ||
43b40992 PW |
2286 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
2287 | if (!strcmp(temp_oh->class->name, classname)) { | |
2288 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
2289 | __func__, temp_oh->name); | |
2290 | ret = (*fn)(temp_oh, user); | |
2291 | if (ret) | |
2292 | break; | |
2293 | } | |
2294 | } | |
2295 | ||
43b40992 PW |
2296 | if (ret) |
2297 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
2298 | __func__, ret); | |
2299 | ||
2300 | return ret; | |
2301 | } | |
2302 | ||
2092e5cc PW |
2303 | /** |
2304 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
2305 | * @oh: struct omap_hwmod * | |
2306 | * @state: state that _setup() should leave the hwmod in | |
2307 | * | |
550c8092 | 2308 | * Sets the hwmod state that @oh will enter at the end of _setup() |
a2debdbd PW |
2309 | * (called by omap_hwmod_setup_*()). Only valid to call between |
2310 | * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns | |
550c8092 PW |
2311 | * 0 upon success or -EINVAL if there is a problem with the arguments |
2312 | * or if the hwmod is in the wrong state. | |
2092e5cc PW |
2313 | */ |
2314 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
2315 | { | |
2316 | int ret; | |
dc6d1cda | 2317 | unsigned long flags; |
2092e5cc PW |
2318 | |
2319 | if (!oh) | |
2320 | return -EINVAL; | |
2321 | ||
2322 | if (state != _HWMOD_STATE_DISABLED && | |
2323 | state != _HWMOD_STATE_ENABLED && | |
2324 | state != _HWMOD_STATE_IDLE) | |
2325 | return -EINVAL; | |
2326 | ||
dc6d1cda | 2327 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
2328 | |
2329 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
2330 | ret = -EINVAL; | |
2331 | goto ohsps_unlock; | |
2332 | } | |
2333 | ||
2334 | oh->_postsetup_state = state; | |
2335 | ret = 0; | |
2336 | ||
2337 | ohsps_unlock: | |
dc6d1cda | 2338 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
2339 | |
2340 | return ret; | |
2341 | } | |
c80705aa KH |
2342 | |
2343 | /** | |
2344 | * omap_hwmod_get_context_loss_count - get lost context count | |
2345 | * @oh: struct omap_hwmod * | |
2346 | * | |
2347 | * Query the powerdomain of of @oh to get the context loss | |
2348 | * count for this device. | |
2349 | * | |
2350 | * Returns the context loss count of the powerdomain assocated with @oh | |
2351 | * upon success, or zero if no powerdomain exists for @oh. | |
2352 | */ | |
2353 | u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) | |
2354 | { | |
2355 | struct powerdomain *pwrdm; | |
2356 | int ret = 0; | |
2357 | ||
2358 | pwrdm = omap_hwmod_get_pwrdm(oh); | |
2359 | if (pwrdm) | |
2360 | ret = pwrdm_get_context_loss_count(pwrdm); | |
2361 | ||
2362 | return ret; | |
2363 | } | |
43b01643 PW |
2364 | |
2365 | /** | |
2366 | * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup | |
2367 | * @oh: struct omap_hwmod * | |
2368 | * | |
2369 | * Prevent the hwmod @oh from being reset during the setup process. | |
2370 | * Intended for use by board-*.c files on boards with devices that | |
2371 | * cannot tolerate being reset. Must be called before the hwmod has | |
2372 | * been set up. Returns 0 upon success or negative error code upon | |
2373 | * failure. | |
2374 | */ | |
2375 | int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) | |
2376 | { | |
2377 | if (!oh) | |
2378 | return -EINVAL; | |
2379 | ||
2380 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
2381 | pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n", | |
2382 | oh->name); | |
2383 | return -EINVAL; | |
2384 | } | |
2385 | ||
2386 | oh->flags |= HWMOD_INIT_NO_RESET; | |
2387 | ||
2388 | return 0; | |
2389 | } |