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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, BenoƮt Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
75 | * | (__raw_{read,write}l, clk*) | | |
76 | * +-------------------------------+ | |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
f5dd3bb5 | 133 | #include <linux/clk-provider.h> |
63c85238 PW |
134 | #include <linux/delay.h> |
135 | #include <linux/err.h> | |
136 | #include <linux/list.h> | |
137 | #include <linux/mutex.h> | |
dc6d1cda | 138 | #include <linux/spinlock.h> |
abc2d545 | 139 | #include <linux/slab.h> |
2221b5cd | 140 | #include <linux/bootmem.h> |
63c85238 | 141 | |
a135eaae | 142 | #include "clock.h" |
2a296c8f | 143 | #include "omap_hwmod.h" |
63c85238 | 144 | |
dbc04161 TL |
145 | #include "soc.h" |
146 | #include "common.h" | |
147 | #include "clockdomain.h" | |
148 | #include "powerdomain.h" | |
ff4ae5d9 PW |
149 | #include "cm2xxx.h" |
150 | #include "cm3xxx.h" | |
d0f0631d | 151 | #include "cminst44xx.h" |
1688bf19 | 152 | #include "cm33xx.h" |
b13159af | 153 | #include "prm.h" |
139563ad | 154 | #include "prm3xxx.h" |
d198b514 | 155 | #include "prm44xx.h" |
1688bf19 | 156 | #include "prm33xx.h" |
eaac329d | 157 | #include "prminst44xx.h" |
8d9af88f | 158 | #include "mux.h" |
5165882a | 159 | #include "pm.h" |
63c85238 | 160 | |
63c85238 | 161 | /* Name of the OMAP hwmod for the MPU */ |
5c2c0296 | 162 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 | 163 | |
2221b5cd PW |
164 | /* |
165 | * Number of struct omap_hwmod_link records per struct | |
166 | * omap_hwmod_ocp_if record (master->slave and slave->master) | |
167 | */ | |
168 | #define LINKS_PER_OCP_IF 2 | |
169 | ||
9ebfd285 KH |
170 | /** |
171 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | |
172 | * @enable_module: function to enable a module (via MODULEMODE) | |
173 | * @disable_module: function to disable a module (via MODULEMODE) | |
174 | * | |
175 | * XXX Eventually this functionality will be hidden inside the PRM/CM | |
176 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | |
177 | * conditionals in this code. | |
178 | */ | |
179 | struct omap_hwmod_soc_ops { | |
180 | void (*enable_module)(struct omap_hwmod *oh); | |
181 | int (*disable_module)(struct omap_hwmod *oh); | |
8f6aa8ee | 182 | int (*wait_target_ready)(struct omap_hwmod *oh); |
b8249cf2 KH |
183 | int (*assert_hardreset)(struct omap_hwmod *oh, |
184 | struct omap_hwmod_rst_info *ohri); | |
185 | int (*deassert_hardreset)(struct omap_hwmod *oh, | |
186 | struct omap_hwmod_rst_info *ohri); | |
187 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | |
188 | struct omap_hwmod_rst_info *ohri); | |
0a179eaa | 189 | int (*init_clkdm)(struct omap_hwmod *oh); |
9ebfd285 KH |
190 | }; |
191 | ||
192 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | |
193 | static struct omap_hwmod_soc_ops soc_ops; | |
194 | ||
63c85238 PW |
195 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
196 | static LIST_HEAD(omap_hwmod_list); | |
197 | ||
63c85238 PW |
198 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
199 | static struct omap_hwmod *mpu_oh; | |
200 | ||
5165882a VB |
201 | /* io_chain_lock: used to serialize reconfigurations of the I/O chain */ |
202 | static DEFINE_SPINLOCK(io_chain_lock); | |
203 | ||
2221b5cd PW |
204 | /* |
205 | * linkspace: ptr to a buffer that struct omap_hwmod_link records are | |
206 | * allocated from - used to reduce the number of small memory | |
207 | * allocations, which has a significant impact on performance | |
208 | */ | |
209 | static struct omap_hwmod_link *linkspace; | |
210 | ||
211 | /* | |
212 | * free_ls, max_ls: array indexes into linkspace; representing the | |
213 | * next free struct omap_hwmod_link index, and the maximum number of | |
214 | * struct omap_hwmod_link records allocated (respectively) | |
215 | */ | |
216 | static unsigned short free_ls, max_ls, ls_supp; | |
63c85238 | 217 | |
9ebfd285 KH |
218 | /* inited: set to true once the hwmod code is initialized */ |
219 | static bool inited; | |
220 | ||
63c85238 PW |
221 | /* Private functions */ |
222 | ||
5d95dde7 | 223 | /** |
11cd4b94 | 224 | * _fetch_next_ocp_if - return the next OCP interface in a list |
2221b5cd | 225 | * @p: ptr to a ptr to the list_head inside the ocp_if to return |
11cd4b94 PW |
226 | * @i: pointer to the index of the element pointed to by @p in the list |
227 | * | |
228 | * Return a pointer to the struct omap_hwmod_ocp_if record | |
229 | * containing the struct list_head pointed to by @p, and increment | |
230 | * @p such that a future call to this routine will return the next | |
231 | * record. | |
5d95dde7 PW |
232 | */ |
233 | static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p, | |
5d95dde7 PW |
234 | int *i) |
235 | { | |
236 | struct omap_hwmod_ocp_if *oi; | |
237 | ||
11cd4b94 PW |
238 | oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if; |
239 | *p = (*p)->next; | |
2221b5cd | 240 | |
5d95dde7 PW |
241 | *i = *i + 1; |
242 | ||
243 | return oi; | |
244 | } | |
245 | ||
63c85238 PW |
246 | /** |
247 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
248 | * @oh: struct omap_hwmod * | |
249 | * | |
250 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
251 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
252 | * OCP_SYSCONFIG register or 0 upon success. | |
253 | */ | |
254 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
255 | { | |
43b40992 PW |
256 | if (!oh->class->sysc) { |
257 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
258 | return -EINVAL; |
259 | } | |
260 | ||
261 | /* XXX ensure module interface clock is up */ | |
262 | ||
cc7a1d2a | 263 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 264 | |
43b40992 | 265 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 266 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
267 | |
268 | return 0; | |
269 | } | |
270 | ||
271 | /** | |
272 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
273 | * @v: OCP_SYSCONFIG value to write | |
274 | * @oh: struct omap_hwmod * | |
275 | * | |
43b40992 PW |
276 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
277 | * one. No return value. | |
63c85238 PW |
278 | */ |
279 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
280 | { | |
43b40992 PW |
281 | if (!oh->class->sysc) { |
282 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
283 | return; |
284 | } | |
285 | ||
286 | /* XXX ensure module interface clock is up */ | |
287 | ||
233cbe5b RN |
288 | /* Module might have lost context, always update cache and register */ |
289 | oh->_sysc_cache = v; | |
290 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); | |
63c85238 PW |
291 | } |
292 | ||
293 | /** | |
294 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
295 | * @oh: struct omap_hwmod * | |
296 | * @standbymode: MIDLEMODE field bits | |
297 | * @v: pointer to register contents to modify | |
298 | * | |
299 | * Update the master standby mode bits in @v to be @standbymode for | |
300 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
301 | * upon error or 0 upon success. | |
302 | */ | |
303 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
304 | u32 *v) | |
305 | { | |
358f0e63 TG |
306 | u32 mstandby_mask; |
307 | u8 mstandby_shift; | |
308 | ||
43b40992 PW |
309 | if (!oh->class->sysc || |
310 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
311 | return -EINVAL; |
312 | ||
43b40992 PW |
313 | if (!oh->class->sysc->sysc_fields) { |
314 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
315 | return -EINVAL; |
316 | } | |
317 | ||
43b40992 | 318 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
319 | mstandby_mask = (0x3 << mstandby_shift); |
320 | ||
321 | *v &= ~mstandby_mask; | |
322 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
323 | |
324 | return 0; | |
325 | } | |
326 | ||
327 | /** | |
328 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
329 | * @oh: struct omap_hwmod * | |
330 | * @idlemode: SIDLEMODE field bits | |
331 | * @v: pointer to register contents to modify | |
332 | * | |
333 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
334 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
335 | * or 0 upon success. | |
336 | */ | |
337 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
338 | { | |
358f0e63 TG |
339 | u32 sidle_mask; |
340 | u8 sidle_shift; | |
341 | ||
43b40992 PW |
342 | if (!oh->class->sysc || |
343 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
344 | return -EINVAL; |
345 | ||
43b40992 PW |
346 | if (!oh->class->sysc->sysc_fields) { |
347 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
348 | return -EINVAL; |
349 | } | |
350 | ||
43b40992 | 351 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
352 | sidle_mask = (0x3 << sidle_shift); |
353 | ||
354 | *v &= ~sidle_mask; | |
355 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
356 | |
357 | return 0; | |
358 | } | |
359 | ||
360 | /** | |
361 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
362 | * @oh: struct omap_hwmod * | |
363 | * @clockact: CLOCKACTIVITY field bits | |
364 | * @v: pointer to register contents to modify | |
365 | * | |
366 | * Update the clockactivity mode bits in @v to be @clockact for the | |
367 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
368 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
369 | * success. | |
370 | */ | |
371 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
372 | { | |
358f0e63 TG |
373 | u32 clkact_mask; |
374 | u8 clkact_shift; | |
375 | ||
43b40992 PW |
376 | if (!oh->class->sysc || |
377 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
378 | return -EINVAL; |
379 | ||
43b40992 PW |
380 | if (!oh->class->sysc->sysc_fields) { |
381 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
382 | return -EINVAL; |
383 | } | |
384 | ||
43b40992 | 385 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
386 | clkact_mask = (0x3 << clkact_shift); |
387 | ||
388 | *v &= ~clkact_mask; | |
389 | *v |= clockact << clkact_shift; | |
63c85238 PW |
390 | |
391 | return 0; | |
392 | } | |
393 | ||
394 | /** | |
395 | * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
396 | * @oh: struct omap_hwmod * | |
397 | * @v: pointer to register contents to modify | |
398 | * | |
399 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
400 | * error or 0 upon success. | |
401 | */ | |
402 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
403 | { | |
358f0e63 TG |
404 | u32 softrst_mask; |
405 | ||
43b40992 PW |
406 | if (!oh->class->sysc || |
407 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
408 | return -EINVAL; |
409 | ||
43b40992 PW |
410 | if (!oh->class->sysc->sysc_fields) { |
411 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
412 | return -EINVAL; |
413 | } | |
414 | ||
43b40992 | 415 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
416 | |
417 | *v |= softrst_mask; | |
63c85238 PW |
418 | |
419 | return 0; | |
420 | } | |
421 | ||
6668546f KVA |
422 | /** |
423 | * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v | |
424 | * @oh: struct omap_hwmod * | |
425 | * | |
426 | * The DMADISABLE bit is a semi-automatic bit present in sysconfig register | |
427 | * of some modules. When the DMA must perform read/write accesses, the | |
428 | * DMADISABLE bit is cleared by the hardware. But when the DMA must stop | |
429 | * for power management, software must set the DMADISABLE bit back to 1. | |
430 | * | |
431 | * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon | |
432 | * error or 0 upon success. | |
433 | */ | |
434 | static int _set_dmadisable(struct omap_hwmod *oh) | |
435 | { | |
436 | u32 v; | |
437 | u32 dmadisable_mask; | |
438 | ||
439 | if (!oh->class->sysc || | |
440 | !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE)) | |
441 | return -EINVAL; | |
442 | ||
443 | if (!oh->class->sysc->sysc_fields) { | |
444 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
445 | return -EINVAL; | |
446 | } | |
447 | ||
448 | /* clocks must be on for this operation */ | |
449 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
450 | pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name); | |
451 | return -EINVAL; | |
452 | } | |
453 | ||
454 | pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name); | |
455 | ||
456 | v = oh->_sysc_cache; | |
457 | dmadisable_mask = | |
458 | (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift); | |
459 | v |= dmadisable_mask; | |
460 | _write_sysconfig(v, oh); | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
726072e5 PW |
465 | /** |
466 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
467 | * @oh: struct omap_hwmod * | |
468 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
469 | * @v: pointer to register contents to modify | |
470 | * | |
471 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
472 | * hwmod. The autoidle bit controls whether the module can gate | |
473 | * internal clocks automatically when it isn't doing anything; the | |
474 | * exact function of this bit varies on a per-module basis. This | |
475 | * function does not write to the hardware. Returns -EINVAL upon | |
476 | * error or 0 upon success. | |
477 | */ | |
478 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
479 | u32 *v) | |
480 | { | |
358f0e63 TG |
481 | u32 autoidle_mask; |
482 | u8 autoidle_shift; | |
483 | ||
43b40992 PW |
484 | if (!oh->class->sysc || |
485 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
486 | return -EINVAL; |
487 | ||
43b40992 PW |
488 | if (!oh->class->sysc->sysc_fields) { |
489 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
490 | return -EINVAL; |
491 | } | |
492 | ||
43b40992 | 493 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 494 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
495 | |
496 | *v &= ~autoidle_mask; | |
497 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
498 | |
499 | return 0; | |
500 | } | |
501 | ||
eceec009 G |
502 | /** |
503 | * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux | |
504 | * @oh: struct omap_hwmod * | |
505 | * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable | |
506 | * | |
507 | * Set or clear the I/O pad wakeup flag in the mux entries for the | |
508 | * hwmod @oh. This function changes the @oh->mux->pads_dynamic array | |
509 | * in memory. If the hwmod is currently idled, and the new idle | |
510 | * values don't match the previous ones, this function will also | |
511 | * update the SCM PADCTRL registers. Otherwise, if the hwmod is not | |
512 | * currently idled, this function won't touch the hardware: the new | |
513 | * mux settings are written to the SCM PADCTRL registers when the | |
514 | * hwmod is idled. No return value. | |
515 | */ | |
516 | static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake) | |
517 | { | |
518 | struct omap_device_pad *pad; | |
519 | bool change = false; | |
520 | u16 prev_idle; | |
521 | int j; | |
522 | ||
523 | if (!oh->mux || !oh->mux->enabled) | |
524 | return; | |
525 | ||
526 | for (j = 0; j < oh->mux->nr_pads_dynamic; j++) { | |
527 | pad = oh->mux->pads_dynamic[j]; | |
528 | ||
529 | if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP)) | |
530 | continue; | |
531 | ||
532 | prev_idle = pad->idle; | |
533 | ||
534 | if (set_wake) | |
535 | pad->idle |= OMAP_WAKEUP_EN; | |
536 | else | |
537 | pad->idle &= ~OMAP_WAKEUP_EN; | |
538 | ||
539 | if (prev_idle != pad->idle) | |
540 | change = true; | |
541 | } | |
542 | ||
543 | if (change && oh->_state == _HWMOD_STATE_IDLE) | |
544 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); | |
545 | } | |
546 | ||
63c85238 PW |
547 | /** |
548 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
549 | * @oh: struct omap_hwmod * | |
550 | * | |
551 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
552 | * upon error or 0 upon success. | |
553 | */ | |
5a7ddcbd | 554 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 555 | { |
43b40992 | 556 | if (!oh->class->sysc || |
86009eb3 | 557 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
558 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
559 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
560 | return -EINVAL; |
561 | ||
43b40992 PW |
562 | if (!oh->class->sysc->sysc_fields) { |
563 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
564 | return -EINVAL; |
565 | } | |
566 | ||
1fe74113 BC |
567 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
568 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 569 | |
86009eb3 BC |
570 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
571 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
572 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
573 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 574 | |
63c85238 PW |
575 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
576 | ||
577 | oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; | |
578 | ||
579 | return 0; | |
580 | } | |
581 | ||
582 | /** | |
583 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
584 | * @oh: struct omap_hwmod * | |
585 | * | |
586 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
587 | * upon error or 0 upon success. | |
588 | */ | |
5a7ddcbd | 589 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 590 | { |
43b40992 | 591 | if (!oh->class->sysc || |
86009eb3 | 592 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
593 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
594 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
595 | return -EINVAL; |
596 | ||
43b40992 PW |
597 | if (!oh->class->sysc->sysc_fields) { |
598 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
599 | return -EINVAL; |
600 | } | |
601 | ||
1fe74113 BC |
602 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
603 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 604 | |
86009eb3 BC |
605 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
606 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 | 607 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
561038f0 | 608 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v); |
86009eb3 | 609 | |
63c85238 PW |
610 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
611 | ||
612 | oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
f5dd3bb5 RN |
617 | static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) |
618 | { | |
c4a1ea2c RN |
619 | struct clk_hw_omap *clk; |
620 | ||
f5dd3bb5 RN |
621 | if (oh->clkdm) { |
622 | return oh->clkdm; | |
623 | } else if (oh->_clk) { | |
f5dd3bb5 RN |
624 | clk = to_clk_hw_omap(__clk_get_hw(oh->_clk)); |
625 | return clk->clkdm; | |
f5dd3bb5 RN |
626 | } |
627 | return NULL; | |
628 | } | |
629 | ||
63c85238 PW |
630 | /** |
631 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
632 | * @oh: struct omap_hwmod * | |
633 | * | |
634 | * Prevent the hardware module @oh from entering idle while the | |
635 | * hardare module initiator @init_oh is active. Useful when a module | |
636 | * will be accessed by a particular initiator (e.g., if a module will | |
637 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
638 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
639 | * mode. If the clockdomain is marked as not needing autodeps, return |
640 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
641 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
642 | */ |
643 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
644 | { | |
f5dd3bb5 RN |
645 | struct clockdomain *clkdm, *init_clkdm; |
646 | ||
647 | clkdm = _get_clkdm(oh); | |
648 | init_clkdm = _get_clkdm(init_oh); | |
649 | ||
650 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
651 | return -EINVAL; |
652 | ||
f5dd3bb5 | 653 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
654 | return 0; |
655 | ||
f5dd3bb5 | 656 | return clkdm_add_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
657 | } |
658 | ||
659 | /** | |
660 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
661 | * @oh: struct omap_hwmod * | |
662 | * | |
663 | * Allow the hardware module @oh to enter idle while the hardare | |
664 | * module initiator @init_oh is active. Useful when a module will not | |
665 | * be accessed by a particular initiator (e.g., if a module will not | |
666 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
667 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
668 | * mode. If the clockdomain is marked as not needing autodeps, return |
669 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
670 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
671 | */ |
672 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
673 | { | |
f5dd3bb5 RN |
674 | struct clockdomain *clkdm, *init_clkdm; |
675 | ||
676 | clkdm = _get_clkdm(oh); | |
677 | init_clkdm = _get_clkdm(init_oh); | |
678 | ||
679 | if (!clkdm || !init_clkdm) | |
63c85238 PW |
680 | return -EINVAL; |
681 | ||
f5dd3bb5 | 682 | if (clkdm && clkdm->flags & CLKDM_NO_AUTODEPS) |
570b54c7 PW |
683 | return 0; |
684 | ||
f5dd3bb5 | 685 | return clkdm_del_sleepdep(clkdm, init_clkdm); |
63c85238 PW |
686 | } |
687 | ||
688 | /** | |
689 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
690 | * @oh: struct omap_hwmod * | |
691 | * | |
692 | * Called from _init_clocks(). Populates the @oh _clk (main | |
693 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
694 | * success or -EINVAL on error. | |
695 | */ | |
696 | static int _init_main_clk(struct omap_hwmod *oh) | |
697 | { | |
63c85238 PW |
698 | int ret = 0; |
699 | ||
50ebdac2 | 700 | if (!oh->main_clk) |
63c85238 PW |
701 | return 0; |
702 | ||
6ea74cb9 RN |
703 | oh->_clk = clk_get(NULL, oh->main_clk); |
704 | if (IS_ERR(oh->_clk)) { | |
20383d82 BC |
705 | pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
706 | oh->name, oh->main_clk); | |
63403384 | 707 | return -EINVAL; |
dc75925d | 708 | } |
4d7cb45e RN |
709 | /* |
710 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
711 | * to do something meaningful. Today its just a no-op. | |
712 | * If clk_prepare() is used at some point to do things like | |
713 | * voltage scaling etc, then this would have to be moved to | |
714 | * some point where subsystems like i2c and pmic become | |
715 | * available. | |
716 | */ | |
717 | clk_prepare(oh->_clk); | |
63c85238 | 718 | |
f5dd3bb5 | 719 | if (!_get_clkdm(oh)) |
3bb05dbf | 720 | pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", |
5dcc3b97 | 721 | oh->name, oh->main_clk); |
81d7c6ff | 722 | |
63c85238 PW |
723 | return ret; |
724 | } | |
725 | ||
726 | /** | |
887adeac | 727 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
728 | * @oh: struct omap_hwmod * |
729 | * | |
730 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
731 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
732 | */ | |
733 | static int _init_interface_clks(struct omap_hwmod *oh) | |
734 | { | |
5d95dde7 | 735 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 736 | struct list_head *p; |
63c85238 | 737 | struct clk *c; |
5d95dde7 | 738 | int i = 0; |
63c85238 PW |
739 | int ret = 0; |
740 | ||
11cd4b94 | 741 | p = oh->slave_ports.next; |
2221b5cd | 742 | |
5d95dde7 | 743 | while (i < oh->slaves_cnt) { |
11cd4b94 | 744 | os = _fetch_next_ocp_if(&p, &i); |
50ebdac2 | 745 | if (!os->clk) |
63c85238 PW |
746 | continue; |
747 | ||
6ea74cb9 RN |
748 | c = clk_get(NULL, os->clk); |
749 | if (IS_ERR(c)) { | |
20383d82 BC |
750 | pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
751 | oh->name, os->clk); | |
63c85238 | 752 | ret = -EINVAL; |
dc75925d | 753 | } |
63c85238 | 754 | os->_clk = c; |
4d7cb45e RN |
755 | /* |
756 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
757 | * to do something meaningful. Today its just a no-op. | |
758 | * If clk_prepare() is used at some point to do things like | |
759 | * voltage scaling etc, then this would have to be moved to | |
760 | * some point where subsystems like i2c and pmic become | |
761 | * available. | |
762 | */ | |
763 | clk_prepare(os->_clk); | |
63c85238 PW |
764 | } |
765 | ||
766 | return ret; | |
767 | } | |
768 | ||
769 | /** | |
770 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
771 | * @oh: struct omap_hwmod * | |
772 | * | |
773 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
774 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
775 | */ | |
776 | static int _init_opt_clks(struct omap_hwmod *oh) | |
777 | { | |
778 | struct omap_hwmod_opt_clk *oc; | |
779 | struct clk *c; | |
780 | int i; | |
781 | int ret = 0; | |
782 | ||
783 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
6ea74cb9 RN |
784 | c = clk_get(NULL, oc->clk); |
785 | if (IS_ERR(c)) { | |
20383d82 BC |
786 | pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
787 | oh->name, oc->clk); | |
63c85238 | 788 | ret = -EINVAL; |
dc75925d | 789 | } |
63c85238 | 790 | oc->_clk = c; |
4d7cb45e RN |
791 | /* |
792 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
793 | * to do something meaningful. Today its just a no-op. | |
794 | * If clk_prepare() is used at some point to do things like | |
795 | * voltage scaling etc, then this would have to be moved to | |
796 | * some point where subsystems like i2c and pmic become | |
797 | * available. | |
798 | */ | |
799 | clk_prepare(oc->_clk); | |
63c85238 PW |
800 | } |
801 | ||
802 | return ret; | |
803 | } | |
804 | ||
805 | /** | |
806 | * _enable_clocks - enable hwmod main clock and interface clocks | |
807 | * @oh: struct omap_hwmod * | |
808 | * | |
809 | * Enables all clocks necessary for register reads and writes to succeed | |
810 | * on the hwmod @oh. Returns 0. | |
811 | */ | |
812 | static int _enable_clocks(struct omap_hwmod *oh) | |
813 | { | |
5d95dde7 | 814 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 815 | struct list_head *p; |
5d95dde7 | 816 | int i = 0; |
63c85238 PW |
817 | |
818 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
819 | ||
4d3ae5a9 | 820 | if (oh->_clk) |
63c85238 PW |
821 | clk_enable(oh->_clk); |
822 | ||
11cd4b94 | 823 | p = oh->slave_ports.next; |
2221b5cd | 824 | |
5d95dde7 | 825 | while (i < oh->slaves_cnt) { |
11cd4b94 | 826 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 827 | |
5d95dde7 PW |
828 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
829 | clk_enable(os->_clk); | |
63c85238 PW |
830 | } |
831 | ||
832 | /* The opt clocks are controlled by the device driver. */ | |
833 | ||
834 | return 0; | |
835 | } | |
836 | ||
837 | /** | |
838 | * _disable_clocks - disable hwmod main clock and interface clocks | |
839 | * @oh: struct omap_hwmod * | |
840 | * | |
841 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
842 | */ | |
843 | static int _disable_clocks(struct omap_hwmod *oh) | |
844 | { | |
5d95dde7 | 845 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 846 | struct list_head *p; |
5d95dde7 | 847 | int i = 0; |
63c85238 PW |
848 | |
849 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
850 | ||
4d3ae5a9 | 851 | if (oh->_clk) |
63c85238 PW |
852 | clk_disable(oh->_clk); |
853 | ||
11cd4b94 | 854 | p = oh->slave_ports.next; |
2221b5cd | 855 | |
5d95dde7 | 856 | while (i < oh->slaves_cnt) { |
11cd4b94 | 857 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 858 | |
5d95dde7 PW |
859 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
860 | clk_disable(os->_clk); | |
63c85238 PW |
861 | } |
862 | ||
863 | /* The opt clocks are controlled by the device driver. */ | |
864 | ||
865 | return 0; | |
866 | } | |
867 | ||
96835af9 BC |
868 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
869 | { | |
870 | struct omap_hwmod_opt_clk *oc; | |
871 | int i; | |
872 | ||
873 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
874 | ||
875 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
876 | if (oc->_clk) { | |
877 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
5dcc3b97 | 878 | __clk_get_name(oc->_clk)); |
96835af9 BC |
879 | clk_enable(oc->_clk); |
880 | } | |
881 | } | |
882 | ||
883 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
884 | { | |
885 | struct omap_hwmod_opt_clk *oc; | |
886 | int i; | |
887 | ||
888 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
889 | ||
890 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
891 | if (oc->_clk) { | |
892 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
5dcc3b97 | 893 | __clk_get_name(oc->_clk)); |
96835af9 BC |
894 | clk_disable(oc->_clk); |
895 | } | |
896 | } | |
897 | ||
45c38252 | 898 | /** |
3d9f0327 | 899 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
45c38252 BC |
900 | * @oh: struct omap_hwmod * |
901 | * | |
902 | * Enables the PRCM module mode related to the hwmod @oh. | |
903 | * No return value. | |
904 | */ | |
3d9f0327 | 905 | static void _omap4_enable_module(struct omap_hwmod *oh) |
45c38252 | 906 | { |
45c38252 BC |
907 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
908 | return; | |
909 | ||
3d9f0327 KH |
910 | pr_debug("omap_hwmod: %s: %s: %d\n", |
911 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
45c38252 BC |
912 | |
913 | omap4_cminst_module_enable(oh->prcm.omap4.modulemode, | |
914 | oh->clkdm->prcm_partition, | |
915 | oh->clkdm->cm_inst, | |
916 | oh->clkdm->clkdm_offs, | |
917 | oh->prcm.omap4.clkctrl_offs); | |
918 | } | |
919 | ||
1688bf19 VH |
920 | /** |
921 | * _am33xx_enable_module - enable CLKCTRL modulemode on AM33XX | |
922 | * @oh: struct omap_hwmod * | |
923 | * | |
924 | * Enables the PRCM module mode related to the hwmod @oh. | |
925 | * No return value. | |
926 | */ | |
927 | static void _am33xx_enable_module(struct omap_hwmod *oh) | |
928 | { | |
929 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
930 | return; | |
931 | ||
932 | pr_debug("omap_hwmod: %s: %s: %d\n", | |
933 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
934 | ||
935 | am33xx_cm_module_enable(oh->prcm.omap4.modulemode, oh->clkdm->cm_inst, | |
936 | oh->clkdm->clkdm_offs, | |
937 | oh->prcm.omap4.clkctrl_offs); | |
938 | } | |
939 | ||
45c38252 | 940 | /** |
bfc141e3 BC |
941 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
942 | * @oh: struct omap_hwmod * | |
943 | * | |
944 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
945 | * does not have an IDLEST bit or if the module successfully enters | |
946 | * slave idle; otherwise, pass along the return value of the | |
947 | * appropriate *_cm*_wait_module_idle() function. | |
948 | */ | |
949 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
950 | { | |
2b026d13 | 951 | if (!oh) |
bfc141e3 BC |
952 | return -EINVAL; |
953 | ||
2b026d13 | 954 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm) |
bfc141e3 BC |
955 | return 0; |
956 | ||
957 | if (oh->flags & HWMOD_NO_IDLEST) | |
958 | return 0; | |
959 | ||
960 | return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition, | |
961 | oh->clkdm->cm_inst, | |
962 | oh->clkdm->clkdm_offs, | |
963 | oh->prcm.omap4.clkctrl_offs); | |
964 | } | |
965 | ||
1688bf19 VH |
966 | /** |
967 | * _am33xx_wait_target_disable - wait for a module to be disabled on AM33XX | |
968 | * @oh: struct omap_hwmod * | |
969 | * | |
970 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
971 | * does not have an IDLEST bit or if the module successfully enters | |
972 | * slave idle; otherwise, pass along the return value of the | |
973 | * appropriate *_cm*_wait_module_idle() function. | |
974 | */ | |
975 | static int _am33xx_wait_target_disable(struct omap_hwmod *oh) | |
976 | { | |
977 | if (!oh) | |
978 | return -EINVAL; | |
979 | ||
980 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
981 | return 0; | |
982 | ||
983 | if (oh->flags & HWMOD_NO_IDLEST) | |
984 | return 0; | |
985 | ||
986 | return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst, | |
987 | oh->clkdm->clkdm_offs, | |
988 | oh->prcm.omap4.clkctrl_offs); | |
989 | } | |
990 | ||
212738a4 PW |
991 | /** |
992 | * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh | |
993 | * @oh: struct omap_hwmod *oh | |
994 | * | |
995 | * Count and return the number of MPU IRQs associated with the hwmod | |
996 | * @oh. Used to allocate struct resource data. Returns 0 if @oh is | |
997 | * NULL. | |
998 | */ | |
999 | static int _count_mpu_irqs(struct omap_hwmod *oh) | |
1000 | { | |
1001 | struct omap_hwmod_irq_info *ohii; | |
1002 | int i = 0; | |
1003 | ||
1004 | if (!oh || !oh->mpu_irqs) | |
1005 | return 0; | |
1006 | ||
1007 | do { | |
1008 | ohii = &oh->mpu_irqs[i++]; | |
1009 | } while (ohii->irq != -1); | |
1010 | ||
cc1b0765 | 1011 | return i-1; |
212738a4 PW |
1012 | } |
1013 | ||
bc614958 PW |
1014 | /** |
1015 | * _count_sdma_reqs - count the number of SDMA request lines associated with @oh | |
1016 | * @oh: struct omap_hwmod *oh | |
1017 | * | |
1018 | * Count and return the number of SDMA request lines associated with | |
1019 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1020 | * if @oh is NULL. | |
1021 | */ | |
1022 | static int _count_sdma_reqs(struct omap_hwmod *oh) | |
1023 | { | |
1024 | struct omap_hwmod_dma_info *ohdi; | |
1025 | int i = 0; | |
1026 | ||
1027 | if (!oh || !oh->sdma_reqs) | |
1028 | return 0; | |
1029 | ||
1030 | do { | |
1031 | ohdi = &oh->sdma_reqs[i++]; | |
1032 | } while (ohdi->dma_req != -1); | |
1033 | ||
cc1b0765 | 1034 | return i-1; |
bc614958 PW |
1035 | } |
1036 | ||
78183f3f PW |
1037 | /** |
1038 | * _count_ocp_if_addr_spaces - count the number of address space entries for @oh | |
1039 | * @oh: struct omap_hwmod *oh | |
1040 | * | |
1041 | * Count and return the number of address space ranges associated with | |
1042 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1043 | * if @oh is NULL. | |
1044 | */ | |
1045 | static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) | |
1046 | { | |
1047 | struct omap_hwmod_addr_space *mem; | |
1048 | int i = 0; | |
1049 | ||
1050 | if (!os || !os->addr) | |
1051 | return 0; | |
1052 | ||
1053 | do { | |
1054 | mem = &os->addr[i++]; | |
1055 | } while (mem->pa_start != mem->pa_end); | |
1056 | ||
cc1b0765 | 1057 | return i-1; |
78183f3f PW |
1058 | } |
1059 | ||
5e8370f1 PW |
1060 | /** |
1061 | * _get_mpu_irq_by_name - fetch MPU interrupt line number by name | |
1062 | * @oh: struct omap_hwmod * to operate on | |
1063 | * @name: pointer to the name of the MPU interrupt number to fetch (optional) | |
1064 | * @irq: pointer to an unsigned int to store the MPU IRQ number to | |
1065 | * | |
1066 | * Retrieve a MPU hardware IRQ line number named by @name associated | |
1067 | * with the IP block pointed to by @oh. The IRQ number will be filled | |
1068 | * into the address pointed to by @dma. When @name is non-null, the | |
1069 | * IRQ line number associated with the named entry will be returned. | |
1070 | * If @name is null, the first matching entry will be returned. Data | |
1071 | * order is not meaningful in hwmod data, so callers are strongly | |
1072 | * encouraged to use a non-null @name whenever possible to avoid | |
1073 | * unpredictable effects if hwmod data is later added that causes data | |
1074 | * ordering to change. Returns 0 upon success or a negative error | |
1075 | * code upon error. | |
1076 | */ | |
1077 | static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, | |
1078 | unsigned int *irq) | |
1079 | { | |
1080 | int i; | |
1081 | bool found = false; | |
1082 | ||
1083 | if (!oh->mpu_irqs) | |
1084 | return -ENOENT; | |
1085 | ||
1086 | i = 0; | |
1087 | while (oh->mpu_irqs[i].irq != -1) { | |
1088 | if (name == oh->mpu_irqs[i].name || | |
1089 | !strcmp(name, oh->mpu_irqs[i].name)) { | |
1090 | found = true; | |
1091 | break; | |
1092 | } | |
1093 | i++; | |
1094 | } | |
1095 | ||
1096 | if (!found) | |
1097 | return -ENOENT; | |
1098 | ||
1099 | *irq = oh->mpu_irqs[i].irq; | |
1100 | ||
1101 | return 0; | |
1102 | } | |
1103 | ||
1104 | /** | |
1105 | * _get_sdma_req_by_name - fetch SDMA request line ID by name | |
1106 | * @oh: struct omap_hwmod * to operate on | |
1107 | * @name: pointer to the name of the SDMA request line to fetch (optional) | |
1108 | * @dma: pointer to an unsigned int to store the request line ID to | |
1109 | * | |
1110 | * Retrieve an SDMA request line ID named by @name on the IP block | |
1111 | * pointed to by @oh. The ID will be filled into the address pointed | |
1112 | * to by @dma. When @name is non-null, the request line ID associated | |
1113 | * with the named entry will be returned. If @name is null, the first | |
1114 | * matching entry will be returned. Data order is not meaningful in | |
1115 | * hwmod data, so callers are strongly encouraged to use a non-null | |
1116 | * @name whenever possible to avoid unpredictable effects if hwmod | |
1117 | * data is later added that causes data ordering to change. Returns 0 | |
1118 | * upon success or a negative error code upon error. | |
1119 | */ | |
1120 | static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, | |
1121 | unsigned int *dma) | |
1122 | { | |
1123 | int i; | |
1124 | bool found = false; | |
1125 | ||
1126 | if (!oh->sdma_reqs) | |
1127 | return -ENOENT; | |
1128 | ||
1129 | i = 0; | |
1130 | while (oh->sdma_reqs[i].dma_req != -1) { | |
1131 | if (name == oh->sdma_reqs[i].name || | |
1132 | !strcmp(name, oh->sdma_reqs[i].name)) { | |
1133 | found = true; | |
1134 | break; | |
1135 | } | |
1136 | i++; | |
1137 | } | |
1138 | ||
1139 | if (!found) | |
1140 | return -ENOENT; | |
1141 | ||
1142 | *dma = oh->sdma_reqs[i].dma_req; | |
1143 | ||
1144 | return 0; | |
1145 | } | |
1146 | ||
1147 | /** | |
1148 | * _get_addr_space_by_name - fetch address space start & end by name | |
1149 | * @oh: struct omap_hwmod * to operate on | |
1150 | * @name: pointer to the name of the address space to fetch (optional) | |
1151 | * @pa_start: pointer to a u32 to store the starting address to | |
1152 | * @pa_end: pointer to a u32 to store the ending address to | |
1153 | * | |
1154 | * Retrieve address space start and end addresses for the IP block | |
1155 | * pointed to by @oh. The data will be filled into the addresses | |
1156 | * pointed to by @pa_start and @pa_end. When @name is non-null, the | |
1157 | * address space data associated with the named entry will be | |
1158 | * returned. If @name is null, the first matching entry will be | |
1159 | * returned. Data order is not meaningful in hwmod data, so callers | |
1160 | * are strongly encouraged to use a non-null @name whenever possible | |
1161 | * to avoid unpredictable effects if hwmod data is later added that | |
1162 | * causes data ordering to change. Returns 0 upon success or a | |
1163 | * negative error code upon error. | |
1164 | */ | |
1165 | static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, | |
1166 | u32 *pa_start, u32 *pa_end) | |
1167 | { | |
1168 | int i, j; | |
1169 | struct omap_hwmod_ocp_if *os; | |
2221b5cd | 1170 | struct list_head *p = NULL; |
5e8370f1 PW |
1171 | bool found = false; |
1172 | ||
11cd4b94 | 1173 | p = oh->slave_ports.next; |
2221b5cd | 1174 | |
5d95dde7 PW |
1175 | i = 0; |
1176 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 1177 | os = _fetch_next_ocp_if(&p, &i); |
5e8370f1 PW |
1178 | |
1179 | if (!os->addr) | |
1180 | return -ENOENT; | |
1181 | ||
1182 | j = 0; | |
1183 | while (os->addr[j].pa_start != os->addr[j].pa_end) { | |
1184 | if (name == os->addr[j].name || | |
1185 | !strcmp(name, os->addr[j].name)) { | |
1186 | found = true; | |
1187 | break; | |
1188 | } | |
1189 | j++; | |
1190 | } | |
1191 | ||
1192 | if (found) | |
1193 | break; | |
1194 | } | |
1195 | ||
1196 | if (!found) | |
1197 | return -ENOENT; | |
1198 | ||
1199 | *pa_start = os->addr[j].pa_start; | |
1200 | *pa_end = os->addr[j].pa_end; | |
1201 | ||
1202 | return 0; | |
1203 | } | |
1204 | ||
63c85238 | 1205 | /** |
24dbc213 | 1206 | * _save_mpu_port_index - find and save the index to @oh's MPU port |
63c85238 PW |
1207 | * @oh: struct omap_hwmod * |
1208 | * | |
24dbc213 PW |
1209 | * Determines the array index of the OCP slave port that the MPU uses |
1210 | * to address the device, and saves it into the struct omap_hwmod. | |
1211 | * Intended to be called during hwmod registration only. No return | |
1212 | * value. | |
63c85238 | 1213 | */ |
24dbc213 | 1214 | static void __init _save_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 1215 | { |
24dbc213 | 1216 | struct omap_hwmod_ocp_if *os = NULL; |
11cd4b94 | 1217 | struct list_head *p; |
5d95dde7 | 1218 | int i = 0; |
63c85238 | 1219 | |
5d95dde7 | 1220 | if (!oh) |
24dbc213 PW |
1221 | return; |
1222 | ||
1223 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
63c85238 | 1224 | |
11cd4b94 | 1225 | p = oh->slave_ports.next; |
2221b5cd | 1226 | |
5d95dde7 | 1227 | while (i < oh->slaves_cnt) { |
11cd4b94 | 1228 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 1229 | if (os->user & OCP_USER_MPU) { |
2221b5cd | 1230 | oh->_mpu_port = os; |
24dbc213 | 1231 | oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; |
63c85238 PW |
1232 | break; |
1233 | } | |
1234 | } | |
1235 | ||
24dbc213 | 1236 | return; |
63c85238 PW |
1237 | } |
1238 | ||
2d6141ba PW |
1239 | /** |
1240 | * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU | |
1241 | * @oh: struct omap_hwmod * | |
1242 | * | |
1243 | * Given a pointer to a struct omap_hwmod record @oh, return a pointer | |
1244 | * to the struct omap_hwmod_ocp_if record that is used by the MPU to | |
1245 | * communicate with the IP block. This interface need not be directly | |
1246 | * connected to the MPU (and almost certainly is not), but is directly | |
1247 | * connected to the IP block represented by @oh. Returns a pointer | |
1248 | * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon | |
1249 | * error or if there does not appear to be a path from the MPU to this | |
1250 | * IP block. | |
1251 | */ | |
1252 | static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) | |
1253 | { | |
1254 | if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) | |
1255 | return NULL; | |
1256 | ||
11cd4b94 | 1257 | return oh->_mpu_port; |
2d6141ba PW |
1258 | }; |
1259 | ||
63c85238 | 1260 | /** |
c9aafd23 | 1261 | * _find_mpu_rt_addr_space - return MPU register target address space for @oh |
63c85238 PW |
1262 | * @oh: struct omap_hwmod * |
1263 | * | |
c9aafd23 PW |
1264 | * Returns a pointer to the struct omap_hwmod_addr_space record representing |
1265 | * the register target MPU address space; or returns NULL upon error. | |
63c85238 | 1266 | */ |
c9aafd23 | 1267 | static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) |
63c85238 PW |
1268 | { |
1269 | struct omap_hwmod_ocp_if *os; | |
1270 | struct omap_hwmod_addr_space *mem; | |
c9aafd23 | 1271 | int found = 0, i = 0; |
63c85238 | 1272 | |
2d6141ba | 1273 | os = _find_mpu_rt_port(oh); |
24dbc213 | 1274 | if (!os || !os->addr) |
78183f3f PW |
1275 | return NULL; |
1276 | ||
1277 | do { | |
1278 | mem = &os->addr[i++]; | |
1279 | if (mem->flags & ADDR_TYPE_RT) | |
63c85238 | 1280 | found = 1; |
78183f3f | 1281 | } while (!found && mem->pa_start != mem->pa_end); |
63c85238 | 1282 | |
c9aafd23 | 1283 | return (found) ? mem : NULL; |
63c85238 PW |
1284 | } |
1285 | ||
1286 | /** | |
74ff3a68 | 1287 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
1288 | * @oh: struct omap_hwmod * |
1289 | * | |
006c7f18 PW |
1290 | * Ensure that the OCP_SYSCONFIG register for the IP block represented |
1291 | * by @oh is set to indicate to the PRCM that the IP block is active. | |
1292 | * Usually this means placing the module into smart-idle mode and | |
1293 | * smart-standby, but if there is a bug in the automatic idle handling | |
1294 | * for the IP block, it may need to be placed into the force-idle or | |
1295 | * no-idle variants of these modes. No return value. | |
63c85238 | 1296 | */ |
74ff3a68 | 1297 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 1298 | { |
43b40992 | 1299 | u8 idlemode, sf; |
63c85238 | 1300 | u32 v; |
006c7f18 | 1301 | bool clkdm_act; |
f5dd3bb5 | 1302 | struct clockdomain *clkdm; |
63c85238 | 1303 | |
43b40992 | 1304 | if (!oh->class->sysc) |
63c85238 PW |
1305 | return; |
1306 | ||
1307 | v = oh->_sysc_cache; | |
43b40992 | 1308 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1309 | |
f5dd3bb5 | 1310 | clkdm = _get_clkdm(oh); |
43b40992 | 1311 | if (sf & SYSC_HAS_SIDLEMODE) { |
f5dd3bb5 | 1312 | clkdm_act = (clkdm && clkdm->flags & CLKDM_ACTIVE_WITH_MPU); |
006c7f18 PW |
1313 | if (clkdm_act && !(oh->class->sysc->idlemodes & |
1314 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1315 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1316 | else | |
1317 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | |
1318 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
63c85238 PW |
1319 | _set_slave_idlemode(oh, idlemode, &v); |
1320 | } | |
1321 | ||
43b40992 | 1322 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1323 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1324 | idlemode = HWMOD_IDLEMODE_NO; | |
1325 | } else { | |
1326 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1327 | _enable_wakeup(oh, &v); | |
1328 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1329 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1330 | else | |
1331 | idlemode = HWMOD_IDLEMODE_SMART; | |
1332 | } | |
63c85238 PW |
1333 | _set_master_standbymode(oh, idlemode, &v); |
1334 | } | |
1335 | ||
a16b1f7f PW |
1336 | /* |
1337 | * XXX The clock framework should handle this, by | |
1338 | * calling into this code. But this must wait until the | |
1339 | * clock structures are tagged with omap_hwmod entries | |
1340 | */ | |
43b40992 PW |
1341 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1342 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
1343 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 | 1344 | |
9980ce53 RN |
1345 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1346 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
5a7ddcbd KH |
1347 | _enable_wakeup(oh, &v); |
1348 | ||
1349 | _write_sysconfig(v, oh); | |
78f26e87 HH |
1350 | |
1351 | /* | |
1352 | * Set the autoidle bit only after setting the smartidle bit | |
1353 | * Setting this will not have any impact on the other modules. | |
1354 | */ | |
1355 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1356 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1357 | 0 : 1; | |
1358 | _set_module_autoidle(oh, idlemode, &v); | |
1359 | _write_sysconfig(v, oh); | |
1360 | } | |
63c85238 PW |
1361 | } |
1362 | ||
1363 | /** | |
74ff3a68 | 1364 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1365 | * @oh: struct omap_hwmod * |
1366 | * | |
1367 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1368 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1369 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1370 | * configure it for smart-standby. No return value. | |
1371 | */ | |
74ff3a68 | 1372 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1373 | { |
43b40992 | 1374 | u8 idlemode, sf; |
63c85238 PW |
1375 | u32 v; |
1376 | ||
43b40992 | 1377 | if (!oh->class->sysc) |
63c85238 PW |
1378 | return; |
1379 | ||
1380 | v = oh->_sysc_cache; | |
43b40992 | 1381 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1382 | |
43b40992 | 1383 | if (sf & SYSC_HAS_SIDLEMODE) { |
006c7f18 PW |
1384 | /* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */ |
1385 | if (oh->flags & HWMOD_SWSUP_SIDLE || | |
1386 | !(oh->class->sysc->idlemodes & | |
1387 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1388 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1389 | else | |
1390 | idlemode = HWMOD_IDLEMODE_SMART; | |
63c85238 PW |
1391 | _set_slave_idlemode(oh, idlemode, &v); |
1392 | } | |
1393 | ||
43b40992 | 1394 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1395 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1396 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1397 | } else { | |
1398 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1399 | _enable_wakeup(oh, &v); | |
1400 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1401 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1402 | else | |
1403 | idlemode = HWMOD_IDLEMODE_SMART; | |
1404 | } | |
63c85238 PW |
1405 | _set_master_standbymode(oh, idlemode, &v); |
1406 | } | |
1407 | ||
86009eb3 BC |
1408 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1409 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
1410 | _enable_wakeup(oh, &v); | |
1411 | ||
63c85238 PW |
1412 | _write_sysconfig(v, oh); |
1413 | } | |
1414 | ||
1415 | /** | |
74ff3a68 | 1416 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1417 | * @oh: struct omap_hwmod * |
1418 | * | |
1419 | * Force the module into slave idle and master suspend. No return | |
1420 | * value. | |
1421 | */ | |
74ff3a68 | 1422 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1423 | { |
1424 | u32 v; | |
43b40992 | 1425 | u8 sf; |
63c85238 | 1426 | |
43b40992 | 1427 | if (!oh->class->sysc) |
63c85238 PW |
1428 | return; |
1429 | ||
1430 | v = oh->_sysc_cache; | |
43b40992 | 1431 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1432 | |
43b40992 | 1433 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1434 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1435 | ||
43b40992 | 1436 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1437 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1438 | ||
43b40992 | 1439 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1440 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1441 | |
1442 | _write_sysconfig(v, oh); | |
1443 | } | |
1444 | ||
1445 | /** | |
1446 | * _lookup - find an omap_hwmod by name | |
1447 | * @name: find an omap_hwmod by name | |
1448 | * | |
1449 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1450 | */ |
1451 | static struct omap_hwmod *_lookup(const char *name) | |
1452 | { | |
1453 | struct omap_hwmod *oh, *temp_oh; | |
1454 | ||
1455 | oh = NULL; | |
1456 | ||
1457 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1458 | if (!strcmp(name, temp_oh->name)) { | |
1459 | oh = temp_oh; | |
1460 | break; | |
1461 | } | |
1462 | } | |
1463 | ||
1464 | return oh; | |
1465 | } | |
868c157d | 1466 | |
6ae76997 BC |
1467 | /** |
1468 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1469 | * @oh: struct omap_hwmod * | |
1470 | * | |
1471 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1472 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
868c157d | 1473 | * Return -EINVAL if the clkdm_name lookup failed. |
6ae76997 BC |
1474 | */ |
1475 | static int _init_clkdm(struct omap_hwmod *oh) | |
1476 | { | |
3bb05dbf PW |
1477 | if (!oh->clkdm_name) { |
1478 | pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name); | |
6ae76997 | 1479 | return 0; |
3bb05dbf | 1480 | } |
6ae76997 | 1481 | |
6ae76997 BC |
1482 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
1483 | if (!oh->clkdm) { | |
1484 | pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", | |
1485 | oh->name, oh->clkdm_name); | |
1486 | return -EINVAL; | |
1487 | } | |
1488 | ||
1489 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1490 | oh->name, oh->clkdm_name); | |
1491 | ||
1492 | return 0; | |
1493 | } | |
63c85238 PW |
1494 | |
1495 | /** | |
6ae76997 BC |
1496 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1497 | * well the clockdomain. | |
63c85238 | 1498 | * @oh: struct omap_hwmod * |
97d60162 | 1499 | * @data: not used; pass NULL |
63c85238 | 1500 | * |
a2debdbd | 1501 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1502 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1503 | * success, or a negative error code on failure. | |
63c85238 | 1504 | */ |
97d60162 | 1505 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
1506 | { |
1507 | int ret = 0; | |
1508 | ||
48d54f3f PW |
1509 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1510 | return 0; | |
63c85238 PW |
1511 | |
1512 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1513 | ||
b797be1d VH |
1514 | if (soc_ops.init_clkdm) |
1515 | ret |= soc_ops.init_clkdm(oh); | |
1516 | ||
63c85238 PW |
1517 | ret |= _init_main_clk(oh); |
1518 | ret |= _init_interface_clks(oh); | |
1519 | ret |= _init_opt_clks(oh); | |
1520 | ||
f5c1f84b BC |
1521 | if (!ret) |
1522 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a BC |
1523 | else |
1524 | pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name); | |
63c85238 | 1525 | |
09c35f2f | 1526 | return ret; |
63c85238 PW |
1527 | } |
1528 | ||
5365efbe | 1529 | /** |
cc1226e7 | 1530 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1531 | * @oh: struct omap_hwmod * |
1532 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1533 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1534 | * |
1535 | * Return the bit position of the reset line that match the | |
1536 | * input name. Return -ENOENT if not found. | |
1537 | */ | |
a032d33b PW |
1538 | static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1539 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1540 | { |
1541 | int i; | |
1542 | ||
1543 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1544 | const char *rst_line = oh->rst_lines[i].name; | |
1545 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1546 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1547 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1548 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1549 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1550 | ohri->st_shift); | |
5365efbe | 1551 | |
cc1226e7 | 1552 | return 0; |
5365efbe BC |
1553 | } |
1554 | } | |
1555 | ||
1556 | return -ENOENT; | |
1557 | } | |
1558 | ||
1559 | /** | |
1560 | * _assert_hardreset - assert the HW reset line of submodules | |
1561 | * contained in the hwmod module. | |
1562 | * @oh: struct omap_hwmod * | |
1563 | * @name: name of the reset line to lookup and assert | |
1564 | * | |
b8249cf2 KH |
1565 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1566 | * reset line to be assert / deassert in order to enable fully the IP. | |
1567 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1568 | * asserting the hardreset line on the currently-booted SoC, or passes | |
1569 | * along the return value from _lookup_hardreset() or the SoC's | |
1570 | * assert_hardreset code. | |
5365efbe BC |
1571 | */ |
1572 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1573 | { | |
cc1226e7 | 1574 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1575 | int ret = -EINVAL; |
5365efbe BC |
1576 | |
1577 | if (!oh) | |
1578 | return -EINVAL; | |
1579 | ||
b8249cf2 KH |
1580 | if (!soc_ops.assert_hardreset) |
1581 | return -ENOSYS; | |
1582 | ||
cc1226e7 | 1583 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1584 | if (ret < 0) |
cc1226e7 | 1585 | return ret; |
5365efbe | 1586 | |
b8249cf2 KH |
1587 | ret = soc_ops.assert_hardreset(oh, &ohri); |
1588 | ||
1589 | return ret; | |
5365efbe BC |
1590 | } |
1591 | ||
1592 | /** | |
1593 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1594 | * in the hwmod module. | |
1595 | * @oh: struct omap_hwmod * | |
1596 | * @name: name of the reset line to look up and deassert | |
1597 | * | |
b8249cf2 KH |
1598 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1599 | * reset line to be assert / deassert in order to enable fully the IP. | |
1600 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1601 | * deasserting the hardreset line on the currently-booted SoC, or passes | |
1602 | * along the return value from _lookup_hardreset() or the SoC's | |
1603 | * deassert_hardreset code. | |
5365efbe BC |
1604 | */ |
1605 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1606 | { | |
cc1226e7 | 1607 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1608 | int ret = -EINVAL; |
e8e96dff | 1609 | int hwsup = 0; |
5365efbe BC |
1610 | |
1611 | if (!oh) | |
1612 | return -EINVAL; | |
1613 | ||
b8249cf2 KH |
1614 | if (!soc_ops.deassert_hardreset) |
1615 | return -ENOSYS; | |
1616 | ||
cc1226e7 | 1617 | ret = _lookup_hardreset(oh, name, &ohri); |
1618 | if (IS_ERR_VALUE(ret)) | |
1619 | return ret; | |
5365efbe | 1620 | |
e8e96dff ORL |
1621 | if (oh->clkdm) { |
1622 | /* | |
1623 | * A clockdomain must be in SW_SUP otherwise reset | |
1624 | * might not be completed. The clockdomain can be set | |
1625 | * in HW_AUTO only when the module become ready. | |
1626 | */ | |
1627 | hwsup = clkdm_in_hwsup(oh->clkdm); | |
1628 | ret = clkdm_hwmod_enable(oh->clkdm, oh); | |
1629 | if (ret) { | |
1630 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1631 | oh->name, oh->clkdm->name, ret); | |
1632 | return ret; | |
1633 | } | |
1634 | } | |
1635 | ||
1636 | _enable_clocks(oh); | |
1637 | if (soc_ops.enable_module) | |
1638 | soc_ops.enable_module(oh); | |
1639 | ||
b8249cf2 | 1640 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
e8e96dff ORL |
1641 | |
1642 | if (soc_ops.disable_module) | |
1643 | soc_ops.disable_module(oh); | |
1644 | _disable_clocks(oh); | |
1645 | ||
cc1226e7 | 1646 | if (ret == -EBUSY) |
5365efbe BC |
1647 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); |
1648 | ||
e8e96dff ORL |
1649 | if (!ret) { |
1650 | /* | |
1651 | * Set the clockdomain to HW_AUTO, assuming that the | |
1652 | * previous state was HW_AUTO. | |
1653 | */ | |
1654 | if (oh->clkdm && hwsup) | |
1655 | clkdm_allow_idle(oh->clkdm); | |
1656 | } else { | |
1657 | if (oh->clkdm) | |
1658 | clkdm_hwmod_disable(oh->clkdm, oh); | |
1659 | } | |
1660 | ||
cc1226e7 | 1661 | return ret; |
5365efbe BC |
1662 | } |
1663 | ||
1664 | /** | |
1665 | * _read_hardreset - read the HW reset line state of submodules | |
1666 | * contained in the hwmod module | |
1667 | * @oh: struct omap_hwmod * | |
1668 | * @name: name of the reset line to look up and read | |
1669 | * | |
b8249cf2 KH |
1670 | * Return the state of the reset line. Returns -EINVAL if @oh is |
1671 | * null, -ENOSYS if we have no way of reading the hardreset line | |
1672 | * status on the currently-booted SoC, or passes along the return | |
1673 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | |
1674 | * code. | |
5365efbe BC |
1675 | */ |
1676 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1677 | { | |
cc1226e7 | 1678 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1679 | int ret = -EINVAL; |
5365efbe BC |
1680 | |
1681 | if (!oh) | |
1682 | return -EINVAL; | |
1683 | ||
b8249cf2 KH |
1684 | if (!soc_ops.is_hardreset_asserted) |
1685 | return -ENOSYS; | |
1686 | ||
cc1226e7 | 1687 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1688 | if (ret < 0) |
cc1226e7 | 1689 | return ret; |
5365efbe | 1690 | |
b8249cf2 | 1691 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
5365efbe BC |
1692 | } |
1693 | ||
747834ab | 1694 | /** |
eb05f691 | 1695 | * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset |
747834ab PW |
1696 | * @oh: struct omap_hwmod * |
1697 | * | |
eb05f691 ORL |
1698 | * If all hardreset lines associated with @oh are asserted, then return true. |
1699 | * Otherwise, if part of @oh is out hardreset or if no hardreset lines | |
1700 | * associated with @oh are asserted, then return false. | |
747834ab | 1701 | * This function is used to avoid executing some parts of the IP block |
eb05f691 | 1702 | * enable/disable sequence if its hardreset line is set. |
747834ab | 1703 | */ |
eb05f691 | 1704 | static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh) |
747834ab | 1705 | { |
eb05f691 | 1706 | int i, rst_cnt = 0; |
747834ab PW |
1707 | |
1708 | if (oh->rst_lines_cnt == 0) | |
1709 | return false; | |
1710 | ||
1711 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1712 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
eb05f691 ORL |
1713 | rst_cnt++; |
1714 | ||
1715 | if (oh->rst_lines_cnt == rst_cnt) | |
1716 | return true; | |
747834ab PW |
1717 | |
1718 | return false; | |
1719 | } | |
1720 | ||
e9332b6e PW |
1721 | /** |
1722 | * _are_any_hardreset_lines_asserted - return true if any part of @oh is | |
1723 | * hard-reset | |
1724 | * @oh: struct omap_hwmod * | |
1725 | * | |
1726 | * If any hardreset lines associated with @oh are asserted, then | |
1727 | * return true. Otherwise, if no hardreset lines associated with @oh | |
1728 | * are asserted, or if @oh has no hardreset lines, then return false. | |
1729 | * This function is used to avoid executing some parts of the IP block | |
1730 | * enable/disable sequence if any hardreset line is set. | |
1731 | */ | |
1732 | static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) | |
1733 | { | |
1734 | int rst_cnt = 0; | |
1735 | int i; | |
1736 | ||
1737 | for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++) | |
1738 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
1739 | rst_cnt++; | |
1740 | ||
1741 | return (rst_cnt) ? true : false; | |
1742 | } | |
1743 | ||
747834ab PW |
1744 | /** |
1745 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
1746 | * @oh: struct omap_hwmod * | |
1747 | * | |
1748 | * Disable the PRCM module mode related to the hwmod @oh. | |
1749 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1750 | */ | |
1751 | static int _omap4_disable_module(struct omap_hwmod *oh) | |
1752 | { | |
1753 | int v; | |
1754 | ||
747834ab PW |
1755 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
1756 | return -EINVAL; | |
1757 | ||
eb05f691 ORL |
1758 | /* |
1759 | * Since integration code might still be doing something, only | |
1760 | * disable if all lines are under hardreset. | |
1761 | */ | |
e9332b6e | 1762 | if (_are_any_hardreset_lines_asserted(oh)) |
eb05f691 ORL |
1763 | return 0; |
1764 | ||
747834ab PW |
1765 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); |
1766 | ||
1767 | omap4_cminst_module_disable(oh->clkdm->prcm_partition, | |
1768 | oh->clkdm->cm_inst, | |
1769 | oh->clkdm->clkdm_offs, | |
1770 | oh->prcm.omap4.clkctrl_offs); | |
1771 | ||
747834ab PW |
1772 | v = _omap4_wait_target_disable(oh); |
1773 | if (v) | |
1774 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1775 | oh->name); | |
1776 | ||
1777 | return 0; | |
1778 | } | |
1779 | ||
1688bf19 VH |
1780 | /** |
1781 | * _am33xx_disable_module - enable CLKCTRL modulemode on AM33XX | |
1782 | * @oh: struct omap_hwmod * | |
1783 | * | |
1784 | * Disable the PRCM module mode related to the hwmod @oh. | |
1785 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1786 | */ | |
1787 | static int _am33xx_disable_module(struct omap_hwmod *oh) | |
1788 | { | |
1789 | int v; | |
1790 | ||
1791 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
1792 | return -EINVAL; | |
1793 | ||
1794 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); | |
1795 | ||
e9332b6e PW |
1796 | if (_are_any_hardreset_lines_asserted(oh)) |
1797 | return 0; | |
1798 | ||
1688bf19 VH |
1799 | am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs, |
1800 | oh->prcm.omap4.clkctrl_offs); | |
1801 | ||
1688bf19 VH |
1802 | v = _am33xx_wait_target_disable(oh); |
1803 | if (v) | |
1804 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1805 | oh->name); | |
1806 | ||
1807 | return 0; | |
1808 | } | |
1809 | ||
63c85238 | 1810 | /** |
bd36179e | 1811 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1812 | * @oh: struct omap_hwmod * |
1813 | * | |
1814 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1815 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1816 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1817 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1818 | * |
1819 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1820 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1821 | * use the SYSCONFIG softreset bit to provide the status. |
1822 | * | |
bd36179e PW |
1823 | * Note that some IP like McBSP do have reset control but don't have |
1824 | * reset status. | |
63c85238 | 1825 | */ |
bd36179e | 1826 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1827 | { |
387ca5bf | 1828 | u32 v, softrst_mask; |
6f8b7ff5 | 1829 | int c = 0; |
96835af9 | 1830 | int ret = 0; |
63c85238 | 1831 | |
43b40992 | 1832 | if (!oh->class->sysc || |
2cb06814 | 1833 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1834 | return -ENOENT; |
63c85238 PW |
1835 | |
1836 | /* clocks must be on for this operation */ | |
1837 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
7852ec05 PW |
1838 | pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n", |
1839 | oh->name); | |
63c85238 PW |
1840 | return -EINVAL; |
1841 | } | |
1842 | ||
96835af9 BC |
1843 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1844 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1845 | _enable_optional_clocks(oh); | |
1846 | ||
bd36179e | 1847 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1848 | |
1849 | v = oh->_sysc_cache; | |
96835af9 BC |
1850 | ret = _set_softreset(oh, &v); |
1851 | if (ret) | |
1852 | goto dis_opt_clks; | |
63c85238 PW |
1853 | _write_sysconfig(v, oh); |
1854 | ||
d99de7f5 FGL |
1855 | if (oh->class->sysc->srst_udelay) |
1856 | udelay(oh->class->sysc->srst_udelay); | |
1857 | ||
2cb06814 | 1858 | if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) |
cc7a1d2a | 1859 | omap_test_timeout((omap_hwmod_read(oh, |
2cb06814 BC |
1860 | oh->class->sysc->syss_offs) |
1861 | & SYSS_RESETDONE_MASK), | |
1862 | MAX_MODULE_SOFTRESET_WAIT, c); | |
387ca5bf RN |
1863 | else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { |
1864 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | |
cc7a1d2a | 1865 | omap_test_timeout(!(omap_hwmod_read(oh, |
2cb06814 | 1866 | oh->class->sysc->sysc_offs) |
387ca5bf | 1867 | & softrst_mask), |
2cb06814 | 1868 | MAX_MODULE_SOFTRESET_WAIT, c); |
387ca5bf | 1869 | } |
63c85238 | 1870 | |
5365efbe | 1871 | if (c == MAX_MODULE_SOFTRESET_WAIT) |
76e5589e BC |
1872 | pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1873 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
63c85238 | 1874 | else |
5365efbe | 1875 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
63c85238 PW |
1876 | |
1877 | /* | |
1878 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1879 | * _wait_target_ready() or _reset() | |
1880 | */ | |
1881 | ||
96835af9 BC |
1882 | ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; |
1883 | ||
1884 | dis_opt_clks: | |
1885 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1886 | _disable_optional_clocks(oh); | |
1887 | ||
1888 | return ret; | |
63c85238 PW |
1889 | } |
1890 | ||
bd36179e PW |
1891 | /** |
1892 | * _reset - reset an omap_hwmod | |
1893 | * @oh: struct omap_hwmod * | |
1894 | * | |
30e105c0 PW |
1895 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1896 | * function pointer defined, then call it to reset the IP block, and | |
1897 | * pass along its return value to the caller. Otherwise, if the IP | |
1898 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1899 | * associated with it, call a function to reset the IP block via that | |
1900 | * method, and pass along the return value to the caller. Finally, if | |
1901 | * the IP block has some hardreset lines associated with it, assert | |
1902 | * all of those, but do _not_ deassert them. (This is because driver | |
1903 | * authors have expressed an apparent requirement to control the | |
1904 | * deassertion of the hardreset lines themselves.) | |
1905 | * | |
1906 | * The default software reset mechanism for most OMAP IP blocks is | |
1907 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1908 | * hwmods cannot be reset via this method. Some are not targets and | |
1909 | * therefore have no OCP header registers to access. Others (like the | |
1910 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
1911 | * rare cases, custom reset code can be supplied in the struct | |
6668546f KVA |
1912 | * omap_hwmod_class .reset function pointer. |
1913 | * | |
1914 | * _set_dmadisable() is called to set the DMADISABLE bit so that it | |
1915 | * does not prevent idling of the system. This is necessary for cases | |
1916 | * where ROMCODE/BOOTLOADER uses dma and transfers control to the | |
1917 | * kernel without disabling dma. | |
1918 | * | |
1919 | * Passes along the return value from either _ocp_softreset() or the | |
1920 | * custom reset function - these must return -EINVAL if the hwmod | |
1921 | * cannot be reset this way or if the hwmod is in the wrong state, | |
1922 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
bd36179e PW |
1923 | */ |
1924 | static int _reset(struct omap_hwmod *oh) | |
1925 | { | |
30e105c0 | 1926 | int i, r; |
bd36179e PW |
1927 | |
1928 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1929 | ||
30e105c0 PW |
1930 | if (oh->class->reset) { |
1931 | r = oh->class->reset(oh); | |
1932 | } else { | |
1933 | if (oh->rst_lines_cnt > 0) { | |
1934 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1935 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
1936 | return 0; | |
1937 | } else { | |
1938 | r = _ocp_softreset(oh); | |
1939 | if (r == -ENOENT) | |
1940 | r = 0; | |
1941 | } | |
1942 | } | |
1943 | ||
6668546f KVA |
1944 | _set_dmadisable(oh); |
1945 | ||
9c8b0ec7 | 1946 | /* |
30e105c0 PW |
1947 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
1948 | * softreset. The _enable() function should be split to avoid | |
1949 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 1950 | */ |
2800852a RN |
1951 | if (oh->class->sysc) { |
1952 | _update_sysc_cache(oh); | |
1953 | _enable_sysc(oh); | |
1954 | } | |
1955 | ||
30e105c0 | 1956 | return r; |
bd36179e PW |
1957 | } |
1958 | ||
5165882a VB |
1959 | /** |
1960 | * _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain | |
1961 | * | |
1962 | * Call the appropriate PRM function to clear any logged I/O chain | |
1963 | * wakeups and to reconfigure the chain. This apparently needs to be | |
1964 | * done upon every mux change. Since hwmods can be concurrently | |
1965 | * enabled and idled, hold a spinlock around the I/O chain | |
1966 | * reconfiguration sequence. No return value. | |
1967 | * | |
1968 | * XXX When the PRM code is moved to drivers, this function can be removed, | |
1969 | * as the PRM infrastructure should abstract this. | |
1970 | */ | |
1971 | static void _reconfigure_io_chain(void) | |
1972 | { | |
1973 | unsigned long flags; | |
1974 | ||
1975 | spin_lock_irqsave(&io_chain_lock, flags); | |
1976 | ||
1977 | if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl()) | |
1978 | omap3xxx_prm_reconfigure_io_chain(); | |
1979 | else if (cpu_is_omap44xx()) | |
1980 | omap44xx_prm_reconfigure_io_chain(); | |
1981 | ||
1982 | spin_unlock_irqrestore(&io_chain_lock, flags); | |
1983 | } | |
1984 | ||
63c85238 | 1985 | /** |
dc6d1cda | 1986 | * _enable - enable an omap_hwmod |
63c85238 PW |
1987 | * @oh: struct omap_hwmod * |
1988 | * | |
1989 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
1990 | * register target. Returns -EINVAL if the hwmod is in the wrong |
1991 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 1992 | */ |
dc6d1cda | 1993 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 1994 | { |
747834ab | 1995 | int r; |
665d0013 | 1996 | int hwsup = 0; |
63c85238 | 1997 | |
34617e2a BC |
1998 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
1999 | ||
aacf0941 | 2000 | /* |
64813c3f PW |
2001 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled |
2002 | * state at init. Now that someone is really trying to enable | |
2003 | * them, just ensure that the hwmod mux is set. | |
aacf0941 RN |
2004 | */ |
2005 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
2006 | /* | |
2007 | * If the caller has mux data populated, do the mux'ing | |
2008 | * which wouldn't have been done as part of the _enable() | |
2009 | * done during setup. | |
2010 | */ | |
2011 | if (oh->mux) | |
2012 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
2013 | ||
2014 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; | |
2015 | return 0; | |
2016 | } | |
2017 | ||
63c85238 PW |
2018 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
2019 | oh->_state != _HWMOD_STATE_IDLE && | |
2020 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
2021 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
2022 | oh->name); | |
63c85238 PW |
2023 | return -EINVAL; |
2024 | } | |
2025 | ||
31f62866 | 2026 | /* |
eb05f691 | 2027 | * If an IP block contains HW reset lines and all of them are |
747834ab PW |
2028 | * asserted, we let integration code associated with that |
2029 | * block handle the enable. We've received very little | |
2030 | * information on what those driver authors need, and until | |
2031 | * detailed information is provided and the driver code is | |
2032 | * posted to the public lists, this is probably the best we | |
2033 | * can do. | |
31f62866 | 2034 | */ |
eb05f691 | 2035 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab | 2036 | return 0; |
63c85238 | 2037 | |
665d0013 RN |
2038 | /* Mux pins for device runtime if populated */ |
2039 | if (oh->mux && (!oh->mux->enabled || | |
2040 | ((oh->_state == _HWMOD_STATE_IDLE) && | |
5165882a | 2041 | oh->mux->pads_dynamic))) { |
665d0013 | 2042 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); |
5165882a VB |
2043 | _reconfigure_io_chain(); |
2044 | } | |
665d0013 RN |
2045 | |
2046 | _add_initiator_dep(oh, mpu_oh); | |
34617e2a | 2047 | |
665d0013 RN |
2048 | if (oh->clkdm) { |
2049 | /* | |
2050 | * A clockdomain must be in SW_SUP before enabling | |
2051 | * completely the module. The clockdomain can be set | |
2052 | * in HW_AUTO only when the module become ready. | |
2053 | */ | |
b71c7217 PW |
2054 | hwsup = clkdm_in_hwsup(oh->clkdm) && |
2055 | !clkdm_missing_idle_reporting(oh->clkdm); | |
665d0013 RN |
2056 | r = clkdm_hwmod_enable(oh->clkdm, oh); |
2057 | if (r) { | |
2058 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
2059 | oh->name, oh->clkdm->name, r); | |
2060 | return r; | |
2061 | } | |
34617e2a | 2062 | } |
665d0013 RN |
2063 | |
2064 | _enable_clocks(oh); | |
9ebfd285 KH |
2065 | if (soc_ops.enable_module) |
2066 | soc_ops.enable_module(oh); | |
34617e2a | 2067 | |
8f6aa8ee KH |
2068 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
2069 | -EINVAL; | |
665d0013 RN |
2070 | if (!r) { |
2071 | /* | |
2072 | * Set the clockdomain to HW_AUTO only if the target is ready, | |
2073 | * assuming that the previous state was HW_AUTO | |
2074 | */ | |
2075 | if (oh->clkdm && hwsup) | |
2076 | clkdm_allow_idle(oh->clkdm); | |
2077 | ||
2078 | oh->_state = _HWMOD_STATE_ENABLED; | |
2079 | ||
2080 | /* Access the sysconfig only if the target is ready */ | |
2081 | if (oh->class->sysc) { | |
2082 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
2083 | _update_sysc_cache(oh); | |
2084 | _enable_sysc(oh); | |
2085 | } | |
2086 | } else { | |
2577a4a6 PW |
2087 | if (soc_ops.disable_module) |
2088 | soc_ops.disable_module(oh); | |
665d0013 RN |
2089 | _disable_clocks(oh); |
2090 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | |
2091 | oh->name, r); | |
34617e2a | 2092 | |
665d0013 RN |
2093 | if (oh->clkdm) |
2094 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
2095 | } |
2096 | ||
63c85238 PW |
2097 | return r; |
2098 | } | |
2099 | ||
2100 | /** | |
dc6d1cda | 2101 | * _idle - idle an omap_hwmod |
63c85238 PW |
2102 | * @oh: struct omap_hwmod * |
2103 | * | |
2104 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
2105 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
2106 | * state or returns 0. | |
63c85238 | 2107 | */ |
dc6d1cda | 2108 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 2109 | { |
34617e2a BC |
2110 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
2111 | ||
63c85238 | 2112 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
2113 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
2114 | oh->name); | |
63c85238 PW |
2115 | return -EINVAL; |
2116 | } | |
2117 | ||
eb05f691 | 2118 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab PW |
2119 | return 0; |
2120 | ||
43b40992 | 2121 | if (oh->class->sysc) |
74ff3a68 | 2122 | _idle_sysc(oh); |
63c85238 | 2123 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 | 2124 | |
9ebfd285 KH |
2125 | if (soc_ops.disable_module) |
2126 | soc_ops.disable_module(oh); | |
bfc141e3 | 2127 | |
45c38252 BC |
2128 | /* |
2129 | * The module must be in idle mode before disabling any parents | |
2130 | * clocks. Otherwise, the parent clock might be disabled before | |
2131 | * the module transition is done, and thus will prevent the | |
2132 | * transition to complete properly. | |
2133 | */ | |
2134 | _disable_clocks(oh); | |
665d0013 RN |
2135 | if (oh->clkdm) |
2136 | clkdm_hwmod_disable(oh->clkdm, oh); | |
63c85238 | 2137 | |
8d9af88f | 2138 | /* Mux pins for device idle if populated */ |
5165882a | 2139 | if (oh->mux && oh->mux->pads_dynamic) { |
8d9af88f | 2140 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); |
5165882a VB |
2141 | _reconfigure_io_chain(); |
2142 | } | |
8d9af88f | 2143 | |
63c85238 PW |
2144 | oh->_state = _HWMOD_STATE_IDLE; |
2145 | ||
2146 | return 0; | |
2147 | } | |
2148 | ||
9599217a KVA |
2149 | /** |
2150 | * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit | |
2151 | * @oh: struct omap_hwmod * | |
2152 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
2153 | * | |
2154 | * Sets the IP block's OCP autoidle bit in hardware, and updates our | |
2155 | * local copy. Intended to be used by drivers that require | |
2156 | * direct manipulation of the AUTOIDLE bits. | |
2157 | * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes | |
2158 | * along the return value from _set_module_autoidle(). | |
2159 | * | |
2160 | * Any users of this function should be scrutinized carefully. | |
2161 | */ | |
2162 | int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) | |
2163 | { | |
2164 | u32 v; | |
2165 | int retval = 0; | |
2166 | unsigned long flags; | |
2167 | ||
2168 | if (!oh || oh->_state != _HWMOD_STATE_ENABLED) | |
2169 | return -EINVAL; | |
2170 | ||
2171 | spin_lock_irqsave(&oh->_lock, flags); | |
2172 | ||
2173 | v = oh->_sysc_cache; | |
2174 | ||
2175 | retval = _set_module_autoidle(oh, autoidle, &v); | |
2176 | ||
2177 | if (!retval) | |
2178 | _write_sysconfig(v, oh); | |
2179 | ||
2180 | spin_unlock_irqrestore(&oh->_lock, flags); | |
2181 | ||
2182 | return retval; | |
2183 | } | |
2184 | ||
63c85238 PW |
2185 | /** |
2186 | * _shutdown - shutdown an omap_hwmod | |
2187 | * @oh: struct omap_hwmod * | |
2188 | * | |
2189 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
2190 | * used for the hwmod is removed or unloaded or if the driver is not | |
2191 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
2192 | * state or returns 0. | |
2193 | */ | |
2194 | static int _shutdown(struct omap_hwmod *oh) | |
2195 | { | |
9c8b0ec7 | 2196 | int ret, i; |
e4dc8f50 PW |
2197 | u8 prev_state; |
2198 | ||
63c85238 PW |
2199 | if (oh->_state != _HWMOD_STATE_IDLE && |
2200 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
2201 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
2202 | oh->name); | |
63c85238 PW |
2203 | return -EINVAL; |
2204 | } | |
2205 | ||
eb05f691 | 2206 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab PW |
2207 | return 0; |
2208 | ||
63c85238 PW |
2209 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); |
2210 | ||
e4dc8f50 PW |
2211 | if (oh->class->pre_shutdown) { |
2212 | prev_state = oh->_state; | |
2213 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2214 | _enable(oh); |
e4dc8f50 PW |
2215 | ret = oh->class->pre_shutdown(oh); |
2216 | if (ret) { | |
2217 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2218 | _idle(oh); |
e4dc8f50 PW |
2219 | return ret; |
2220 | } | |
2221 | } | |
2222 | ||
6481c73c MV |
2223 | if (oh->class->sysc) { |
2224 | if (oh->_state == _HWMOD_STATE_IDLE) | |
2225 | _enable(oh); | |
74ff3a68 | 2226 | _shutdown_sysc(oh); |
6481c73c | 2227 | } |
5365efbe | 2228 | |
3827f949 BC |
2229 | /* clocks and deps are already disabled in idle */ |
2230 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
2231 | _del_initiator_dep(oh, mpu_oh); | |
2232 | /* XXX what about the other system initiators here? dma, dsp */ | |
9ebfd285 KH |
2233 | if (soc_ops.disable_module) |
2234 | soc_ops.disable_module(oh); | |
45c38252 | 2235 | _disable_clocks(oh); |
665d0013 RN |
2236 | if (oh->clkdm) |
2237 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 2238 | } |
63c85238 PW |
2239 | /* XXX Should this code also force-disable the optional clocks? */ |
2240 | ||
9c8b0ec7 PW |
2241 | for (i = 0; i < oh->rst_lines_cnt; i++) |
2242 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 2243 | |
8d9af88f TL |
2244 | /* Mux pins to safe mode or use populated off mode values */ |
2245 | if (oh->mux) | |
2246 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); | |
63c85238 PW |
2247 | |
2248 | oh->_state = _HWMOD_STATE_DISABLED; | |
2249 | ||
2250 | return 0; | |
2251 | } | |
2252 | ||
381d033a PW |
2253 | /** |
2254 | * _init_mpu_rt_base - populate the virtual address for a hwmod | |
2255 | * @oh: struct omap_hwmod * to locate the virtual address | |
2256 | * | |
2257 | * Cache the virtual address used by the MPU to access this IP block's | |
2258 | * registers. This address is needed early so the OCP registers that | |
2259 | * are part of the device's address space can be ioremapped properly. | |
2260 | * No return value. | |
2261 | */ | |
2262 | static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) | |
2263 | { | |
c9aafd23 PW |
2264 | struct omap_hwmod_addr_space *mem; |
2265 | void __iomem *va_start; | |
2266 | ||
2267 | if (!oh) | |
2268 | return; | |
2269 | ||
2221b5cd PW |
2270 | _save_mpu_port_index(oh); |
2271 | ||
381d033a PW |
2272 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
2273 | return; | |
2274 | ||
c9aafd23 PW |
2275 | mem = _find_mpu_rt_addr_space(oh); |
2276 | if (!mem) { | |
2277 | pr_debug("omap_hwmod: %s: no MPU register target found\n", | |
2278 | oh->name); | |
2279 | return; | |
2280 | } | |
2281 | ||
2282 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
2283 | if (!va_start) { | |
2284 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
2285 | return; | |
2286 | } | |
2287 | ||
2288 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | |
2289 | oh->name, va_start); | |
2290 | ||
2291 | oh->_mpu_rt_va = va_start; | |
381d033a PW |
2292 | } |
2293 | ||
2294 | /** | |
2295 | * _init - initialize internal data for the hwmod @oh | |
2296 | * @oh: struct omap_hwmod * | |
2297 | * @n: (unused) | |
2298 | * | |
2299 | * Look up the clocks and the address space used by the MPU to access | |
2300 | * registers belonging to the hwmod @oh. @oh must already be | |
2301 | * registered at this point. This is the first of two phases for | |
2302 | * hwmod initialization. Code called here does not touch any hardware | |
2303 | * registers, it simply prepares internal data structures. Returns 0 | |
2304 | * upon success or if the hwmod isn't registered, or -EINVAL upon | |
2305 | * failure. | |
2306 | */ | |
2307 | static int __init _init(struct omap_hwmod *oh, void *data) | |
2308 | { | |
2309 | int r; | |
2310 | ||
2311 | if (oh->_state != _HWMOD_STATE_REGISTERED) | |
2312 | return 0; | |
2313 | ||
2314 | _init_mpu_rt_base(oh, NULL); | |
2315 | ||
2316 | r = _init_clocks(oh, NULL); | |
2317 | if (IS_ERR_VALUE(r)) { | |
2318 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); | |
2319 | return -EINVAL; | |
2320 | } | |
2321 | ||
2322 | oh->_state = _HWMOD_STATE_INITIALIZED; | |
2323 | ||
2324 | return 0; | |
2325 | } | |
2326 | ||
63c85238 | 2327 | /** |
64813c3f | 2328 | * _setup_iclk_autoidle - configure an IP block's interface clocks |
63c85238 PW |
2329 | * @oh: struct omap_hwmod * |
2330 | * | |
64813c3f PW |
2331 | * Set up the module's interface clocks. XXX This function is still mostly |
2332 | * a stub; implementing this properly requires iclk autoidle usecounting in | |
2333 | * the clock code. No return value. | |
63c85238 | 2334 | */ |
64813c3f | 2335 | static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) |
63c85238 | 2336 | { |
5d95dde7 | 2337 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 2338 | struct list_head *p; |
5d95dde7 | 2339 | int i = 0; |
381d033a | 2340 | if (oh->_state != _HWMOD_STATE_INITIALIZED) |
64813c3f | 2341 | return; |
48d54f3f | 2342 | |
11cd4b94 | 2343 | p = oh->slave_ports.next; |
63c85238 | 2344 | |
5d95dde7 | 2345 | while (i < oh->slaves_cnt) { |
11cd4b94 | 2346 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 | 2347 | if (!os->_clk) |
64813c3f | 2348 | continue; |
63c85238 | 2349 | |
64813c3f PW |
2350 | if (os->flags & OCPIF_SWSUP_IDLE) { |
2351 | /* XXX omap_iclk_deny_idle(c); */ | |
2352 | } else { | |
2353 | /* XXX omap_iclk_allow_idle(c); */ | |
5d95dde7 | 2354 | clk_enable(os->_clk); |
63c85238 PW |
2355 | } |
2356 | } | |
2357 | ||
64813c3f PW |
2358 | return; |
2359 | } | |
2360 | ||
2361 | /** | |
2362 | * _setup_reset - reset an IP block during the setup process | |
2363 | * @oh: struct omap_hwmod * | |
2364 | * | |
2365 | * Reset the IP block corresponding to the hwmod @oh during the setup | |
2366 | * process. The IP block is first enabled so it can be successfully | |
2367 | * reset. Returns 0 upon success or a negative error code upon | |
2368 | * failure. | |
2369 | */ | |
2370 | static int __init _setup_reset(struct omap_hwmod *oh) | |
2371 | { | |
2372 | int r; | |
2373 | ||
2374 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2375 | return -EINVAL; | |
63c85238 | 2376 | |
747834ab PW |
2377 | if (oh->rst_lines_cnt == 0) { |
2378 | r = _enable(oh); | |
2379 | if (r) { | |
2380 | pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", | |
2381 | oh->name, oh->_state); | |
2382 | return -EINVAL; | |
2383 | } | |
9a23dfe1 | 2384 | } |
63c85238 | 2385 | |
2800852a | 2386 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
64813c3f PW |
2387 | r = _reset(oh); |
2388 | ||
2389 | return r; | |
2390 | } | |
2391 | ||
2392 | /** | |
2393 | * _setup_postsetup - transition to the appropriate state after _setup | |
2394 | * @oh: struct omap_hwmod * | |
2395 | * | |
2396 | * Place an IP block represented by @oh into a "post-setup" state -- | |
2397 | * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that | |
2398 | * this function is called at the end of _setup().) The postsetup | |
2399 | * state for an IP block can be changed by calling | |
2400 | * omap_hwmod_enter_postsetup_state() early in the boot process, | |
2401 | * before one of the omap_hwmod_setup*() functions are called for the | |
2402 | * IP block. | |
2403 | * | |
2404 | * The IP block stays in this state until a PM runtime-based driver is | |
2405 | * loaded for that IP block. A post-setup state of IDLE is | |
2406 | * appropriate for almost all IP blocks with runtime PM-enabled | |
2407 | * drivers, since those drivers are able to enable the IP block. A | |
2408 | * post-setup state of ENABLED is appropriate for kernels with PM | |
2409 | * runtime disabled. The DISABLED state is appropriate for unusual IP | |
2410 | * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers | |
2411 | * included, since the WDTIMER starts running on reset and will reset | |
2412 | * the MPU if left active. | |
2413 | * | |
2414 | * This post-setup mechanism is deprecated. Once all of the OMAP | |
2415 | * drivers have been converted to use PM runtime, and all of the IP | |
2416 | * block data and interconnect data is available to the hwmod code, it | |
2417 | * should be possible to replace this mechanism with a "lazy reset" | |
2418 | * arrangement. In a "lazy reset" setup, each IP block is enabled | |
2419 | * when the driver first probes, then all remaining IP blocks without | |
2420 | * drivers are either shut down or enabled after the drivers have | |
2421 | * loaded. However, this cannot take place until the above | |
2422 | * preconditions have been met, since otherwise the late reset code | |
2423 | * has no way of knowing which IP blocks are in use by drivers, and | |
2424 | * which ones are unused. | |
2425 | * | |
2426 | * No return value. | |
2427 | */ | |
2428 | static void __init _setup_postsetup(struct omap_hwmod *oh) | |
2429 | { | |
2430 | u8 postsetup_state; | |
2431 | ||
2432 | if (oh->rst_lines_cnt > 0) | |
2433 | return; | |
76e5589e | 2434 | |
2092e5cc PW |
2435 | postsetup_state = oh->_postsetup_state; |
2436 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
2437 | postsetup_state = _HWMOD_STATE_ENABLED; | |
2438 | ||
2439 | /* | |
2440 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
2441 | * it should be set by the core code as a runtime flag during startup | |
2442 | */ | |
2443 | if ((oh->flags & HWMOD_INIT_NO_IDLE) && | |
aacf0941 RN |
2444 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
2445 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 2446 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 2447 | } |
2092e5cc PW |
2448 | |
2449 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2450 | _idle(oh); |
2092e5cc PW |
2451 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
2452 | _shutdown(oh); | |
2453 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2454 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2455 | oh->name, postsetup_state); | |
63c85238 | 2456 | |
64813c3f PW |
2457 | return; |
2458 | } | |
2459 | ||
2460 | /** | |
2461 | * _setup - prepare IP block hardware for use | |
2462 | * @oh: struct omap_hwmod * | |
2463 | * @n: (unused, pass NULL) | |
2464 | * | |
2465 | * Configure the IP block represented by @oh. This may include | |
2466 | * enabling the IP block, resetting it, and placing it into a | |
2467 | * post-setup state, depending on the type of IP block and applicable | |
2468 | * flags. IP blocks are reset to prevent any previous configuration | |
2469 | * by the bootloader or previous operating system from interfering | |
2470 | * with power management or other parts of the system. The reset can | |
2471 | * be avoided; see omap_hwmod_no_setup_reset(). This is the second of | |
2472 | * two phases for hwmod initialization. Code called here generally | |
2473 | * affects the IP block hardware, or system integration hardware | |
2474 | * associated with the IP block. Returns 0. | |
2475 | */ | |
2476 | static int __init _setup(struct omap_hwmod *oh, void *data) | |
2477 | { | |
2478 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2479 | return 0; | |
2480 | ||
2481 | _setup_iclk_autoidle(oh); | |
2482 | ||
2483 | if (!_setup_reset(oh)) | |
2484 | _setup_postsetup(oh); | |
2485 | ||
63c85238 PW |
2486 | return 0; |
2487 | } | |
2488 | ||
63c85238 | 2489 | /** |
0102b627 | 2490 | * _register - register a struct omap_hwmod |
63c85238 PW |
2491 | * @oh: struct omap_hwmod * |
2492 | * | |
43b40992 PW |
2493 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
2494 | * already has been registered by the same name; -EINVAL if the | |
2495 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
2496 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
2497 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
2498 | * success. | |
63c85238 PW |
2499 | * |
2500 | * XXX The data should be copied into bootmem, so the original data | |
2501 | * should be marked __initdata and freed after init. This would allow | |
2502 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
2503 | * that the copy process would be relatively complex due to the large number | |
2504 | * of substructures. | |
2505 | */ | |
01592df9 | 2506 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 2507 | { |
43b40992 PW |
2508 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
2509 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
2510 | return -EINVAL; |
2511 | ||
63c85238 PW |
2512 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
2513 | ||
ce35b244 BC |
2514 | if (_lookup(oh->name)) |
2515 | return -EEXIST; | |
63c85238 | 2516 | |
63c85238 PW |
2517 | list_add_tail(&oh->node, &omap_hwmod_list); |
2518 | ||
2221b5cd PW |
2519 | INIT_LIST_HEAD(&oh->master_ports); |
2520 | INIT_LIST_HEAD(&oh->slave_ports); | |
dc6d1cda | 2521 | spin_lock_init(&oh->_lock); |
2092e5cc | 2522 | |
63c85238 PW |
2523 | oh->_state = _HWMOD_STATE_REGISTERED; |
2524 | ||
569edd70 PW |
2525 | /* |
2526 | * XXX Rather than doing a strcmp(), this should test a flag | |
2527 | * set in the hwmod data, inserted by the autogenerator code. | |
2528 | */ | |
2529 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
2530 | mpu_oh = oh; | |
63c85238 | 2531 | |
569edd70 | 2532 | return 0; |
63c85238 PW |
2533 | } |
2534 | ||
2221b5cd PW |
2535 | /** |
2536 | * _alloc_links - return allocated memory for hwmod links | |
2537 | * @ml: pointer to a struct omap_hwmod_link * for the master link | |
2538 | * @sl: pointer to a struct omap_hwmod_link * for the slave link | |
2539 | * | |
2540 | * Return pointers to two struct omap_hwmod_link records, via the | |
2541 | * addresses pointed to by @ml and @sl. Will first attempt to return | |
2542 | * memory allocated as part of a large initial block, but if that has | |
2543 | * been exhausted, will allocate memory itself. Since ideally this | |
2544 | * second allocation path will never occur, the number of these | |
2545 | * 'supplemental' allocations will be logged when debugging is | |
2546 | * enabled. Returns 0. | |
2547 | */ | |
2548 | static int __init _alloc_links(struct omap_hwmod_link **ml, | |
2549 | struct omap_hwmod_link **sl) | |
2550 | { | |
2551 | unsigned int sz; | |
2552 | ||
2553 | if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) { | |
2554 | *ml = &linkspace[free_ls++]; | |
2555 | *sl = &linkspace[free_ls++]; | |
2556 | return 0; | |
2557 | } | |
2558 | ||
2559 | sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; | |
2560 | ||
2561 | *sl = NULL; | |
2562 | *ml = alloc_bootmem(sz); | |
2563 | ||
2564 | memset(*ml, 0, sz); | |
2565 | ||
2566 | *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); | |
2567 | ||
2568 | ls_supp++; | |
2569 | pr_debug("omap_hwmod: supplemental link allocations needed: %d\n", | |
2570 | ls_supp * LINKS_PER_OCP_IF); | |
2571 | ||
2572 | return 0; | |
2573 | }; | |
2574 | ||
2575 | /** | |
2576 | * _add_link - add an interconnect between two IP blocks | |
2577 | * @oi: pointer to a struct omap_hwmod_ocp_if record | |
2578 | * | |
2579 | * Add struct omap_hwmod_link records connecting the master IP block | |
2580 | * specified in @oi->master to @oi, and connecting the slave IP block | |
2581 | * specified in @oi->slave to @oi. This code is assumed to run before | |
2582 | * preemption or SMP has been enabled, thus avoiding the need for | |
2583 | * locking in this code. Changes to this assumption will require | |
2584 | * additional locking. Returns 0. | |
2585 | */ | |
2586 | static int __init _add_link(struct omap_hwmod_ocp_if *oi) | |
2587 | { | |
2588 | struct omap_hwmod_link *ml, *sl; | |
2589 | ||
2590 | pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, | |
2591 | oi->slave->name); | |
2592 | ||
2593 | _alloc_links(&ml, &sl); | |
2594 | ||
2595 | ml->ocp_if = oi; | |
2596 | INIT_LIST_HEAD(&ml->node); | |
2597 | list_add(&ml->node, &oi->master->master_ports); | |
2598 | oi->master->masters_cnt++; | |
2599 | ||
2600 | sl->ocp_if = oi; | |
2601 | INIT_LIST_HEAD(&sl->node); | |
2602 | list_add(&sl->node, &oi->slave->slave_ports); | |
2603 | oi->slave->slaves_cnt++; | |
2604 | ||
2605 | return 0; | |
2606 | } | |
2607 | ||
2608 | /** | |
2609 | * _register_link - register a struct omap_hwmod_ocp_if | |
2610 | * @oi: struct omap_hwmod_ocp_if * | |
2611 | * | |
2612 | * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it | |
2613 | * has already been registered; -EINVAL if @oi is NULL or if the | |
2614 | * record pointed to by @oi is missing required fields; or 0 upon | |
2615 | * success. | |
2616 | * | |
2617 | * XXX The data should be copied into bootmem, so the original data | |
2618 | * should be marked __initdata and freed after init. This would allow | |
2619 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. | |
2620 | */ | |
2621 | static int __init _register_link(struct omap_hwmod_ocp_if *oi) | |
2622 | { | |
2623 | if (!oi || !oi->master || !oi->slave || !oi->user) | |
2624 | return -EINVAL; | |
2625 | ||
2626 | if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) | |
2627 | return -EEXIST; | |
2628 | ||
2629 | pr_debug("omap_hwmod: registering link from %s to %s\n", | |
2630 | oi->master->name, oi->slave->name); | |
2631 | ||
2632 | /* | |
2633 | * Register the connected hwmods, if they haven't been | |
2634 | * registered already | |
2635 | */ | |
2636 | if (oi->master->_state != _HWMOD_STATE_REGISTERED) | |
2637 | _register(oi->master); | |
2638 | ||
2639 | if (oi->slave->_state != _HWMOD_STATE_REGISTERED) | |
2640 | _register(oi->slave); | |
2641 | ||
2642 | _add_link(oi); | |
2643 | ||
2644 | oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; | |
2645 | ||
2646 | return 0; | |
2647 | } | |
2648 | ||
2649 | /** | |
2650 | * _alloc_linkspace - allocate large block of hwmod links | |
2651 | * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count | |
2652 | * | |
2653 | * Allocate a large block of struct omap_hwmod_link records. This | |
2654 | * improves boot time significantly by avoiding the need to allocate | |
2655 | * individual records one by one. If the number of records to | |
2656 | * allocate in the block hasn't been manually specified, this function | |
2657 | * will count the number of struct omap_hwmod_ocp_if records in @ois | |
2658 | * and use that to determine the allocation size. For SoC families | |
2659 | * that require multiple list registrations, such as OMAP3xxx, this | |
2660 | * estimation process isn't optimal, so manual estimation is advised | |
2661 | * in those cases. Returns -EEXIST if the allocation has already occurred | |
2662 | * or 0 upon success. | |
2663 | */ | |
2664 | static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) | |
2665 | { | |
2666 | unsigned int i = 0; | |
2667 | unsigned int sz; | |
2668 | ||
2669 | if (linkspace) { | |
2670 | WARN(1, "linkspace already allocated\n"); | |
2671 | return -EEXIST; | |
2672 | } | |
2673 | ||
2674 | if (max_ls == 0) | |
2675 | while (ois[i++]) | |
2676 | max_ls += LINKS_PER_OCP_IF; | |
2677 | ||
2678 | sz = sizeof(struct omap_hwmod_link) * max_ls; | |
2679 | ||
2680 | pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", | |
2681 | __func__, sz, max_ls); | |
2682 | ||
2683 | linkspace = alloc_bootmem(sz); | |
2684 | ||
2685 | memset(linkspace, 0, sz); | |
2686 | ||
2687 | return 0; | |
2688 | } | |
0102b627 | 2689 | |
8f6aa8ee KH |
2690 | /* Static functions intended only for use in soc_ops field function pointers */ |
2691 | ||
2692 | /** | |
ff4ae5d9 | 2693 | * _omap2xxx_wait_target_ready - wait for a module to leave slave idle |
8f6aa8ee KH |
2694 | * @oh: struct omap_hwmod * |
2695 | * | |
2696 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2697 | * does not have an IDLEST bit or if the module successfully leaves | |
2698 | * slave idle; otherwise, pass along the return value of the | |
2699 | * appropriate *_cm*_wait_module_ready() function. | |
2700 | */ | |
ff4ae5d9 | 2701 | static int _omap2xxx_wait_target_ready(struct omap_hwmod *oh) |
8f6aa8ee KH |
2702 | { |
2703 | if (!oh) | |
2704 | return -EINVAL; | |
2705 | ||
2706 | if (oh->flags & HWMOD_NO_IDLEST) | |
2707 | return 0; | |
2708 | ||
2709 | if (!_find_mpu_rt_port(oh)) | |
2710 | return 0; | |
2711 | ||
2712 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2713 | ||
ff4ae5d9 PW |
2714 | return omap2xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs, |
2715 | oh->prcm.omap2.idlest_reg_id, | |
2716 | oh->prcm.omap2.idlest_idle_bit); | |
2717 | } | |
2718 | ||
2719 | /** | |
2720 | * _omap3xxx_wait_target_ready - wait for a module to leave slave idle | |
2721 | * @oh: struct omap_hwmod * | |
2722 | * | |
2723 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2724 | * does not have an IDLEST bit or if the module successfully leaves | |
2725 | * slave idle; otherwise, pass along the return value of the | |
2726 | * appropriate *_cm*_wait_module_ready() function. | |
2727 | */ | |
2728 | static int _omap3xxx_wait_target_ready(struct omap_hwmod *oh) | |
2729 | { | |
2730 | if (!oh) | |
2731 | return -EINVAL; | |
2732 | ||
2733 | if (oh->flags & HWMOD_NO_IDLEST) | |
2734 | return 0; | |
2735 | ||
2736 | if (!_find_mpu_rt_port(oh)) | |
2737 | return 0; | |
2738 | ||
2739 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2740 | ||
2741 | return omap3xxx_cm_wait_module_ready(oh->prcm.omap2.module_offs, | |
2742 | oh->prcm.omap2.idlest_reg_id, | |
2743 | oh->prcm.omap2.idlest_idle_bit); | |
8f6aa8ee KH |
2744 | } |
2745 | ||
2746 | /** | |
2747 | * _omap4_wait_target_ready - wait for a module to leave slave idle | |
2748 | * @oh: struct omap_hwmod * | |
2749 | * | |
2750 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2751 | * does not have an IDLEST bit or if the module successfully leaves | |
2752 | * slave idle; otherwise, pass along the return value of the | |
2753 | * appropriate *_cm*_wait_module_ready() function. | |
2754 | */ | |
2755 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | |
2756 | { | |
2b026d13 | 2757 | if (!oh) |
8f6aa8ee KH |
2758 | return -EINVAL; |
2759 | ||
2b026d13 | 2760 | if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm) |
8f6aa8ee KH |
2761 | return 0; |
2762 | ||
2763 | if (!_find_mpu_rt_port(oh)) | |
2764 | return 0; | |
2765 | ||
2766 | /* XXX check module SIDLEMODE, hardreset status */ | |
2767 | ||
2768 | return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, | |
2769 | oh->clkdm->cm_inst, | |
2770 | oh->clkdm->clkdm_offs, | |
2771 | oh->prcm.omap4.clkctrl_offs); | |
2772 | } | |
2773 | ||
1688bf19 VH |
2774 | /** |
2775 | * _am33xx_wait_target_ready - wait for a module to leave slave idle | |
2776 | * @oh: struct omap_hwmod * | |
2777 | * | |
2778 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2779 | * does not have an IDLEST bit or if the module successfully leaves | |
2780 | * slave idle; otherwise, pass along the return value of the | |
2781 | * appropriate *_cm*_wait_module_ready() function. | |
2782 | */ | |
2783 | static int _am33xx_wait_target_ready(struct omap_hwmod *oh) | |
2784 | { | |
2785 | if (!oh || !oh->clkdm) | |
2786 | return -EINVAL; | |
2787 | ||
2788 | if (oh->flags & HWMOD_NO_IDLEST) | |
2789 | return 0; | |
2790 | ||
2791 | if (!_find_mpu_rt_port(oh)) | |
2792 | return 0; | |
2793 | ||
2794 | /* XXX check module SIDLEMODE, hardreset status */ | |
2795 | ||
2796 | return am33xx_cm_wait_module_ready(oh->clkdm->cm_inst, | |
2797 | oh->clkdm->clkdm_offs, | |
2798 | oh->prcm.omap4.clkctrl_offs); | |
2799 | } | |
2800 | ||
b8249cf2 KH |
2801 | /** |
2802 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2803 | * @oh: struct omap_hwmod * to assert hardreset | |
2804 | * @ohri: hardreset line data | |
2805 | * | |
2806 | * Call omap2_prm_assert_hardreset() with parameters extracted from | |
2807 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2808 | * use as an soc_ops function pointer. Passes along the return value | |
2809 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | |
2810 | * for removal when the PRM code is moved into drivers/. | |
2811 | */ | |
2812 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | |
2813 | struct omap_hwmod_rst_info *ohri) | |
2814 | { | |
2815 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | |
2816 | ohri->rst_shift); | |
2817 | } | |
2818 | ||
2819 | /** | |
2820 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2821 | * @oh: struct omap_hwmod * to deassert hardreset | |
2822 | * @ohri: hardreset line data | |
2823 | * | |
2824 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | |
2825 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2826 | * use as an soc_ops function pointer. Passes along the return value | |
2827 | * from omap2_prm_deassert_hardreset(). XXX This function is | |
2828 | * scheduled for removal when the PRM code is moved into drivers/. | |
2829 | */ | |
2830 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | |
2831 | struct omap_hwmod_rst_info *ohri) | |
2832 | { | |
2833 | return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | |
2834 | ohri->rst_shift, | |
2835 | ohri->st_shift); | |
2836 | } | |
2837 | ||
2838 | /** | |
2839 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | |
2840 | * @oh: struct omap_hwmod * to test hardreset | |
2841 | * @ohri: hardreset line data | |
2842 | * | |
2843 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | |
2844 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2845 | * intended for use as an soc_ops function pointer. Passes along the | |
2846 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | |
2847 | * function is scheduled for removal when the PRM code is moved into | |
2848 | * drivers/. | |
2849 | */ | |
2850 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | |
2851 | struct omap_hwmod_rst_info *ohri) | |
2852 | { | |
2853 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | |
2854 | ohri->st_shift); | |
2855 | } | |
2856 | ||
2857 | /** | |
2858 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2859 | * @oh: struct omap_hwmod * to assert hardreset | |
2860 | * @ohri: hardreset line data | |
2861 | * | |
2862 | * Call omap4_prminst_assert_hardreset() with parameters extracted | |
2863 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2864 | * intended for use as an soc_ops function pointer. Passes along the | |
2865 | * return value from omap4_prminst_assert_hardreset(). XXX This | |
2866 | * function is scheduled for removal when the PRM code is moved into | |
2867 | * drivers/. | |
2868 | */ | |
2869 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | |
2870 | struct omap_hwmod_rst_info *ohri) | |
b8249cf2 | 2871 | { |
07b3a139 PW |
2872 | if (!oh->clkdm) |
2873 | return -EINVAL; | |
2874 | ||
b8249cf2 KH |
2875 | return omap4_prminst_assert_hardreset(ohri->rst_shift, |
2876 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2877 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2878 | oh->prcm.omap4.rstctrl_offs); | |
2879 | } | |
2880 | ||
2881 | /** | |
2882 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2883 | * @oh: struct omap_hwmod * to deassert hardreset | |
2884 | * @ohri: hardreset line data | |
2885 | * | |
2886 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | |
2887 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2888 | * intended for use as an soc_ops function pointer. Passes along the | |
2889 | * return value from omap4_prminst_deassert_hardreset(). XXX This | |
2890 | * function is scheduled for removal when the PRM code is moved into | |
2891 | * drivers/. | |
2892 | */ | |
2893 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | |
2894 | struct omap_hwmod_rst_info *ohri) | |
2895 | { | |
07b3a139 PW |
2896 | if (!oh->clkdm) |
2897 | return -EINVAL; | |
2898 | ||
b8249cf2 KH |
2899 | if (ohri->st_shift) |
2900 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
2901 | oh->name, ohri->name); | |
2902 | return omap4_prminst_deassert_hardreset(ohri->rst_shift, | |
2903 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2904 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2905 | oh->prcm.omap4.rstctrl_offs); | |
2906 | } | |
2907 | ||
2908 | /** | |
2909 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | |
2910 | * @oh: struct omap_hwmod * to test hardreset | |
2911 | * @ohri: hardreset line data | |
2912 | * | |
2913 | * Call omap4_prminst_is_hardreset_asserted() with parameters | |
2914 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
2915 | * Only intended for use as an soc_ops function pointer. Passes along | |
2916 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | |
2917 | * This function is scheduled for removal when the PRM code is moved | |
2918 | * into drivers/. | |
2919 | */ | |
2920 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | |
2921 | struct omap_hwmod_rst_info *ohri) | |
2922 | { | |
07b3a139 PW |
2923 | if (!oh->clkdm) |
2924 | return -EINVAL; | |
2925 | ||
b8249cf2 KH |
2926 | return omap4_prminst_is_hardreset_asserted(ohri->rst_shift, |
2927 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2928 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2929 | oh->prcm.omap4.rstctrl_offs); | |
2930 | } | |
2931 | ||
1688bf19 VH |
2932 | /** |
2933 | * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
2934 | * @oh: struct omap_hwmod * to assert hardreset | |
2935 | * @ohri: hardreset line data | |
2936 | * | |
2937 | * Call am33xx_prminst_assert_hardreset() with parameters extracted | |
2938 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2939 | * intended for use as an soc_ops function pointer. Passes along the | |
2940 | * return value from am33xx_prminst_assert_hardreset(). XXX This | |
2941 | * function is scheduled for removal when the PRM code is moved into | |
2942 | * drivers/. | |
2943 | */ | |
2944 | static int _am33xx_assert_hardreset(struct omap_hwmod *oh, | |
2945 | struct omap_hwmod_rst_info *ohri) | |
2946 | ||
2947 | { | |
2948 | return am33xx_prm_assert_hardreset(ohri->rst_shift, | |
2949 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2950 | oh->prcm.omap4.rstctrl_offs); | |
2951 | } | |
2952 | ||
2953 | /** | |
2954 | * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
2955 | * @oh: struct omap_hwmod * to deassert hardreset | |
2956 | * @ohri: hardreset line data | |
2957 | * | |
2958 | * Call am33xx_prminst_deassert_hardreset() with parameters extracted | |
2959 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2960 | * intended for use as an soc_ops function pointer. Passes along the | |
2961 | * return value from am33xx_prminst_deassert_hardreset(). XXX This | |
2962 | * function is scheduled for removal when the PRM code is moved into | |
2963 | * drivers/. | |
2964 | */ | |
2965 | static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, | |
2966 | struct omap_hwmod_rst_info *ohri) | |
2967 | { | |
2968 | if (ohri->st_shift) | |
2969 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
2970 | oh->name, ohri->name); | |
2971 | ||
2972 | return am33xx_prm_deassert_hardreset(ohri->rst_shift, | |
2973 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2974 | oh->prcm.omap4.rstctrl_offs, | |
2975 | oh->prcm.omap4.rstst_offs); | |
2976 | } | |
2977 | ||
2978 | /** | |
2979 | * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args | |
2980 | * @oh: struct omap_hwmod * to test hardreset | |
2981 | * @ohri: hardreset line data | |
2982 | * | |
2983 | * Call am33xx_prminst_is_hardreset_asserted() with parameters | |
2984 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
2985 | * Only intended for use as an soc_ops function pointer. Passes along | |
2986 | * the return value from am33xx_prminst_is_hardreset_asserted(). XXX | |
2987 | * This function is scheduled for removal when the PRM code is moved | |
2988 | * into drivers/. | |
2989 | */ | |
2990 | static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh, | |
2991 | struct omap_hwmod_rst_info *ohri) | |
2992 | { | |
2993 | return am33xx_prm_is_hardreset_asserted(ohri->rst_shift, | |
2994 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2995 | oh->prcm.omap4.rstctrl_offs); | |
2996 | } | |
2997 | ||
0102b627 BC |
2998 | /* Public functions */ |
2999 | ||
3000 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
3001 | { | |
3002 | if (oh->flags & HWMOD_16BIT_REG) | |
3003 | return __raw_readw(oh->_mpu_rt_va + reg_offs); | |
3004 | else | |
3005 | return __raw_readl(oh->_mpu_rt_va + reg_offs); | |
3006 | } | |
3007 | ||
3008 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
3009 | { | |
3010 | if (oh->flags & HWMOD_16BIT_REG) | |
3011 | __raw_writew(v, oh->_mpu_rt_va + reg_offs); | |
3012 | else | |
3013 | __raw_writel(v, oh->_mpu_rt_va + reg_offs); | |
3014 | } | |
3015 | ||
6d3c55fd A |
3016 | /** |
3017 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
3018 | * @oh: struct omap_hwmod * | |
3019 | * | |
3020 | * This is a public function exposed to drivers. Some drivers may need to do | |
3021 | * some settings before and after resetting the device. Those drivers after | |
3022 | * doing the necessary settings could use this function to start a reset by | |
3023 | * setting the SYSCONFIG.SOFTRESET bit. | |
3024 | */ | |
3025 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
3026 | { | |
3c55c1ba PW |
3027 | u32 v; |
3028 | int ret; | |
3029 | ||
3030 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
3031 | return -EINVAL; |
3032 | ||
3c55c1ba PW |
3033 | v = oh->_sysc_cache; |
3034 | ret = _set_softreset(oh, &v); | |
3035 | if (ret) | |
3036 | goto error; | |
3037 | _write_sysconfig(v, oh); | |
3038 | ||
3039 | error: | |
3040 | return ret; | |
6d3c55fd A |
3041 | } |
3042 | ||
0102b627 BC |
3043 | /** |
3044 | * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode | |
3045 | * @oh: struct omap_hwmod * | |
3046 | * @idlemode: SIDLEMODE field bits (shifted to bit 0) | |
3047 | * | |
3048 | * Sets the IP block's OCP slave idlemode in hardware, and updates our | |
3049 | * local copy. Intended to be used by drivers that have some erratum | |
3050 | * that requires direct manipulation of the SIDLEMODE bits. Returns | |
3051 | * -EINVAL if @oh is null, or passes along the return value from | |
3052 | * _set_slave_idlemode(). | |
3053 | * | |
3054 | * XXX Does this function have any current users? If not, we should | |
3055 | * remove it; it is better to let the rest of the hwmod code handle this. | |
3056 | * Any users of this function should be scrutinized carefully. | |
3057 | */ | |
3058 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) | |
3059 | { | |
3060 | u32 v; | |
3061 | int retval = 0; | |
3062 | ||
3063 | if (!oh) | |
3064 | return -EINVAL; | |
3065 | ||
3066 | v = oh->_sysc_cache; | |
3067 | ||
3068 | retval = _set_slave_idlemode(oh, idlemode, &v); | |
3069 | if (!retval) | |
3070 | _write_sysconfig(v, oh); | |
3071 | ||
3072 | return retval; | |
3073 | } | |
3074 | ||
63c85238 PW |
3075 | /** |
3076 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
3077 | * @name: name of the omap_hwmod to look up | |
3078 | * | |
3079 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
3080 | * struct omap_hwmod *, or NULL upon error. | |
3081 | */ | |
3082 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
3083 | { | |
3084 | struct omap_hwmod *oh; | |
3085 | ||
3086 | if (!name) | |
3087 | return NULL; | |
3088 | ||
63c85238 | 3089 | oh = _lookup(name); |
63c85238 PW |
3090 | |
3091 | return oh; | |
3092 | } | |
3093 | ||
3094 | /** | |
3095 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
3096 | * @fn: pointer to a callback function | |
97d60162 | 3097 | * @data: void * data to pass to callback function |
63c85238 PW |
3098 | * |
3099 | * Call @fn for each registered omap_hwmod, passing @data to each | |
3100 | * function. @fn must return 0 for success or any other value for | |
3101 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
3102 | * will stop and the non-zero return value will be passed to the | |
3103 | * caller of omap_hwmod_for_each(). @fn is called with | |
3104 | * omap_hwmod_for_each() held. | |
3105 | */ | |
97d60162 PW |
3106 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
3107 | void *data) | |
63c85238 PW |
3108 | { |
3109 | struct omap_hwmod *temp_oh; | |
30ebad9d | 3110 | int ret = 0; |
63c85238 PW |
3111 | |
3112 | if (!fn) | |
3113 | return -EINVAL; | |
3114 | ||
63c85238 | 3115 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 3116 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
3117 | if (ret) |
3118 | break; | |
3119 | } | |
63c85238 PW |
3120 | |
3121 | return ret; | |
3122 | } | |
3123 | ||
2221b5cd PW |
3124 | /** |
3125 | * omap_hwmod_register_links - register an array of hwmod links | |
3126 | * @ois: pointer to an array of omap_hwmod_ocp_if to register | |
3127 | * | |
3128 | * Intended to be called early in boot before the clock framework is | |
3129 | * initialized. If @ois is not null, will register all omap_hwmods | |
9ebfd285 KH |
3130 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
3131 | * omap_hwmod_init() hasn't been called before calling this function, | |
3132 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | |
3133 | * success. | |
2221b5cd PW |
3134 | */ |
3135 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | |
3136 | { | |
3137 | int r, i; | |
3138 | ||
9ebfd285 KH |
3139 | if (!inited) |
3140 | return -EINVAL; | |
3141 | ||
2221b5cd PW |
3142 | if (!ois) |
3143 | return 0; | |
3144 | ||
2221b5cd PW |
3145 | if (!linkspace) { |
3146 | if (_alloc_linkspace(ois)) { | |
3147 | pr_err("omap_hwmod: could not allocate link space\n"); | |
3148 | return -ENOMEM; | |
3149 | } | |
3150 | } | |
3151 | ||
3152 | i = 0; | |
3153 | do { | |
3154 | r = _register_link(ois[i]); | |
3155 | WARN(r && r != -EEXIST, | |
3156 | "omap_hwmod: _register_link(%s -> %s) returned %d\n", | |
3157 | ois[i]->master->name, ois[i]->slave->name, r); | |
3158 | } while (ois[++i]); | |
3159 | ||
3160 | return 0; | |
3161 | } | |
3162 | ||
381d033a PW |
3163 | /** |
3164 | * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up | |
3165 | * @oh: pointer to the hwmod currently being set up (usually not the MPU) | |
3166 | * | |
3167 | * If the hwmod data corresponding to the MPU subsystem IP block | |
3168 | * hasn't been initialized and set up yet, do so now. This must be | |
3169 | * done first since sleep dependencies may be added from other hwmods | |
3170 | * to the MPU. Intended to be called only by omap_hwmod_setup*(). No | |
3171 | * return value. | |
63c85238 | 3172 | */ |
381d033a | 3173 | static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) |
e7c7d760 | 3174 | { |
381d033a PW |
3175 | if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) |
3176 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
3177 | __func__, MPU_INITIATOR_NAME); | |
3178 | else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) | |
3179 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
e7c7d760 TL |
3180 | } |
3181 | ||
63c85238 | 3182 | /** |
a2debdbd PW |
3183 | * omap_hwmod_setup_one - set up a single hwmod |
3184 | * @oh_name: const char * name of the already-registered hwmod to set up | |
3185 | * | |
381d033a PW |
3186 | * Initialize and set up a single hwmod. Intended to be used for a |
3187 | * small number of early devices, such as the timer IP blocks used for | |
3188 | * the scheduler clock. Must be called after omap2_clk_init(). | |
3189 | * Resolves the struct clk names to struct clk pointers for each | |
3190 | * registered omap_hwmod. Also calls _setup() on each hwmod. Returns | |
3191 | * -EINVAL upon error or 0 upon success. | |
a2debdbd PW |
3192 | */ |
3193 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
3194 | { |
3195 | struct omap_hwmod *oh; | |
63c85238 | 3196 | |
a2debdbd PW |
3197 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
3198 | ||
a2debdbd PW |
3199 | oh = _lookup(oh_name); |
3200 | if (!oh) { | |
3201 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
3202 | return -EINVAL; | |
3203 | } | |
63c85238 | 3204 | |
381d033a | 3205 | _ensure_mpu_hwmod_is_setup(oh); |
63c85238 | 3206 | |
381d033a | 3207 | _init(oh, NULL); |
a2debdbd PW |
3208 | _setup(oh, NULL); |
3209 | ||
63c85238 PW |
3210 | return 0; |
3211 | } | |
3212 | ||
3213 | /** | |
381d033a | 3214 | * omap_hwmod_setup_all - set up all registered IP blocks |
63c85238 | 3215 | * |
381d033a PW |
3216 | * Initialize and set up all IP blocks registered with the hwmod code. |
3217 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
3218 | * names to struct clk pointers for each registered omap_hwmod. Also | |
3219 | * calls _setup() on each hwmod. Returns 0 upon success. | |
63c85238 | 3220 | */ |
550c8092 | 3221 | static int __init omap_hwmod_setup_all(void) |
63c85238 | 3222 | { |
381d033a | 3223 | _ensure_mpu_hwmod_is_setup(NULL); |
63c85238 | 3224 | |
381d033a | 3225 | omap_hwmod_for_each(_init, NULL); |
2092e5cc | 3226 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
3227 | |
3228 | return 0; | |
3229 | } | |
550c8092 | 3230 | core_initcall(omap_hwmod_setup_all); |
63c85238 | 3231 | |
63c85238 PW |
3232 | /** |
3233 | * omap_hwmod_enable - enable an omap_hwmod | |
3234 | * @oh: struct omap_hwmod * | |
3235 | * | |
74ff3a68 | 3236 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
3237 | * Returns -EINVAL on error or passes along the return value from _enable(). |
3238 | */ | |
3239 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
3240 | { | |
3241 | int r; | |
dc6d1cda | 3242 | unsigned long flags; |
63c85238 PW |
3243 | |
3244 | if (!oh) | |
3245 | return -EINVAL; | |
3246 | ||
dc6d1cda PW |
3247 | spin_lock_irqsave(&oh->_lock, flags); |
3248 | r = _enable(oh); | |
3249 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3250 | |
3251 | return r; | |
3252 | } | |
3253 | ||
3254 | /** | |
3255 | * omap_hwmod_idle - idle an omap_hwmod | |
3256 | * @oh: struct omap_hwmod * | |
3257 | * | |
74ff3a68 | 3258 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
3259 | * Returns -EINVAL on error or passes along the return value from _idle(). |
3260 | */ | |
3261 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
3262 | { | |
dc6d1cda PW |
3263 | unsigned long flags; |
3264 | ||
63c85238 PW |
3265 | if (!oh) |
3266 | return -EINVAL; | |
3267 | ||
dc6d1cda PW |
3268 | spin_lock_irqsave(&oh->_lock, flags); |
3269 | _idle(oh); | |
3270 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3271 | |
3272 | return 0; | |
3273 | } | |
3274 | ||
3275 | /** | |
3276 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
3277 | * @oh: struct omap_hwmod * | |
3278 | * | |
74ff3a68 | 3279 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
3280 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
3281 | * the return value from _shutdown(). | |
3282 | */ | |
3283 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
3284 | { | |
dc6d1cda PW |
3285 | unsigned long flags; |
3286 | ||
63c85238 PW |
3287 | if (!oh) |
3288 | return -EINVAL; | |
3289 | ||
dc6d1cda | 3290 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3291 | _shutdown(oh); |
dc6d1cda | 3292 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3293 | |
3294 | return 0; | |
3295 | } | |
3296 | ||
3297 | /** | |
3298 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
3299 | * @oh: struct omap_hwmod *oh | |
3300 | * | |
3301 | * Intended to be called by the omap_device code. | |
3302 | */ | |
3303 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
3304 | { | |
dc6d1cda PW |
3305 | unsigned long flags; |
3306 | ||
3307 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 3308 | _enable_clocks(oh); |
dc6d1cda | 3309 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3310 | |
3311 | return 0; | |
3312 | } | |
3313 | ||
3314 | /** | |
3315 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
3316 | * @oh: struct omap_hwmod *oh | |
3317 | * | |
3318 | * Intended to be called by the omap_device code. | |
3319 | */ | |
3320 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
3321 | { | |
dc6d1cda PW |
3322 | unsigned long flags; |
3323 | ||
3324 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 3325 | _disable_clocks(oh); |
dc6d1cda | 3326 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3327 | |
3328 | return 0; | |
3329 | } | |
3330 | ||
3331 | /** | |
3332 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
3333 | * @oh: struct omap_hwmod *oh | |
3334 | * | |
3335 | * Intended to be called by drivers and core code when all posted | |
3336 | * writes to a device must complete before continuing further | |
3337 | * execution (for example, after clearing some device IRQSTATUS | |
3338 | * register bits) | |
3339 | * | |
3340 | * XXX what about targets with multiple OCP threads? | |
3341 | */ | |
3342 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
3343 | { | |
3344 | BUG_ON(!oh); | |
3345 | ||
43b40992 | 3346 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
4f8a428d RK |
3347 | WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n", |
3348 | oh->name); | |
63c85238 PW |
3349 | return; |
3350 | } | |
3351 | ||
3352 | /* | |
3353 | * Forces posted writes to complete on the OCP thread handling | |
3354 | * register writes | |
3355 | */ | |
cc7a1d2a | 3356 | omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
3357 | } |
3358 | ||
3359 | /** | |
3360 | * omap_hwmod_reset - reset the hwmod | |
3361 | * @oh: struct omap_hwmod * | |
3362 | * | |
3363 | * Under some conditions, a driver may wish to reset the entire device. | |
3364 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 3365 | * the return value from _reset(). |
63c85238 PW |
3366 | */ |
3367 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
3368 | { | |
3369 | int r; | |
dc6d1cda | 3370 | unsigned long flags; |
63c85238 | 3371 | |
9b579114 | 3372 | if (!oh) |
63c85238 PW |
3373 | return -EINVAL; |
3374 | ||
dc6d1cda | 3375 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3376 | r = _reset(oh); |
dc6d1cda | 3377 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3378 | |
3379 | return r; | |
3380 | } | |
3381 | ||
5e8370f1 PW |
3382 | /* |
3383 | * IP block data retrieval functions | |
3384 | */ | |
3385 | ||
63c85238 PW |
3386 | /** |
3387 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
3388 | * @oh: struct omap_hwmod * | |
3389 | * @res: pointer to the first element of an array of struct resource to fill | |
3390 | * | |
3391 | * Count the number of struct resource array elements necessary to | |
3392 | * contain omap_hwmod @oh resources. Intended to be called by code | |
3393 | * that registers omap_devices. Intended to be used to determine the | |
3394 | * size of a dynamically-allocated struct resource array, before | |
3395 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
3396 | * resource array elements needed. | |
3397 | * | |
3398 | * XXX This code is not optimized. It could attempt to merge adjacent | |
3399 | * resource IDs. | |
3400 | * | |
3401 | */ | |
3402 | int omap_hwmod_count_resources(struct omap_hwmod *oh) | |
3403 | { | |
5d95dde7 | 3404 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3405 | struct list_head *p; |
5d95dde7 PW |
3406 | int ret; |
3407 | int i = 0; | |
63c85238 | 3408 | |
bc614958 | 3409 | ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); |
63c85238 | 3410 | |
11cd4b94 | 3411 | p = oh->slave_ports.next; |
2221b5cd | 3412 | |
5d95dde7 | 3413 | while (i < oh->slaves_cnt) { |
11cd4b94 | 3414 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 PW |
3415 | ret += _count_ocp_if_addr_spaces(os); |
3416 | } | |
63c85238 PW |
3417 | |
3418 | return ret; | |
3419 | } | |
3420 | ||
3421 | /** | |
3422 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
3423 | * @oh: struct omap_hwmod * | |
3424 | * @res: pointer to the first element of an array of struct resource to fill | |
3425 | * | |
3426 | * Fill the struct resource array @res with resource data from the | |
3427 | * omap_hwmod @oh. Intended to be called by code that registers | |
3428 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3429 | * number of array elements filled. | |
3430 | */ | |
3431 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
3432 | { | |
5d95dde7 | 3433 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3434 | struct list_head *p; |
5d95dde7 | 3435 | int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; |
63c85238 PW |
3436 | int r = 0; |
3437 | ||
3438 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
3439 | ||
212738a4 PW |
3440 | mpu_irqs_cnt = _count_mpu_irqs(oh); |
3441 | for (i = 0; i < mpu_irqs_cnt; i++) { | |
718bfd76 PW |
3442 | (res + r)->name = (oh->mpu_irqs + i)->name; |
3443 | (res + r)->start = (oh->mpu_irqs + i)->irq; | |
3444 | (res + r)->end = (oh->mpu_irqs + i)->irq; | |
63c85238 PW |
3445 | (res + r)->flags = IORESOURCE_IRQ; |
3446 | r++; | |
3447 | } | |
3448 | ||
bc614958 PW |
3449 | sdma_reqs_cnt = _count_sdma_reqs(oh); |
3450 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
9ee9fff9 BC |
3451 | (res + r)->name = (oh->sdma_reqs + i)->name; |
3452 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3453 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
3454 | (res + r)->flags = IORESOURCE_DMA; |
3455 | r++; | |
3456 | } | |
3457 | ||
11cd4b94 | 3458 | p = oh->slave_ports.next; |
2221b5cd | 3459 | |
5d95dde7 PW |
3460 | i = 0; |
3461 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 3462 | os = _fetch_next_ocp_if(&p, &i); |
78183f3f | 3463 | addr_cnt = _count_ocp_if_addr_spaces(os); |
63c85238 | 3464 | |
78183f3f | 3465 | for (j = 0; j < addr_cnt; j++) { |
cd503802 | 3466 | (res + r)->name = (os->addr + j)->name; |
63c85238 PW |
3467 | (res + r)->start = (os->addr + j)->pa_start; |
3468 | (res + r)->end = (os->addr + j)->pa_end; | |
3469 | (res + r)->flags = IORESOURCE_MEM; | |
3470 | r++; | |
3471 | } | |
3472 | } | |
3473 | ||
3474 | return r; | |
3475 | } | |
3476 | ||
b82b04e8 VH |
3477 | /** |
3478 | * omap_hwmod_fill_dma_resources - fill struct resource array with dma data | |
3479 | * @oh: struct omap_hwmod * | |
3480 | * @res: pointer to the array of struct resource to fill | |
3481 | * | |
3482 | * Fill the struct resource array @res with dma resource data from the | |
3483 | * omap_hwmod @oh. Intended to be called by code that registers | |
3484 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3485 | * number of array elements filled. | |
3486 | */ | |
3487 | int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res) | |
3488 | { | |
3489 | int i, sdma_reqs_cnt; | |
3490 | int r = 0; | |
3491 | ||
3492 | sdma_reqs_cnt = _count_sdma_reqs(oh); | |
3493 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
3494 | (res + r)->name = (oh->sdma_reqs + i)->name; | |
3495 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3496 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
3497 | (res + r)->flags = IORESOURCE_DMA; | |
3498 | r++; | |
3499 | } | |
3500 | ||
3501 | return r; | |
3502 | } | |
3503 | ||
5e8370f1 PW |
3504 | /** |
3505 | * omap_hwmod_get_resource_byname - fetch IP block integration data by name | |
3506 | * @oh: struct omap_hwmod * to operate on | |
3507 | * @type: one of the IORESOURCE_* constants from include/linux/ioport.h | |
3508 | * @name: pointer to the name of the data to fetch (optional) | |
3509 | * @rsrc: pointer to a struct resource, allocated by the caller | |
3510 | * | |
3511 | * Retrieve MPU IRQ, SDMA request line, or address space start/end | |
3512 | * data for the IP block pointed to by @oh. The data will be filled | |
3513 | * into a struct resource record pointed to by @rsrc. The struct | |
3514 | * resource must be allocated by the caller. When @name is non-null, | |
3515 | * the data associated with the matching entry in the IRQ/SDMA/address | |
3516 | * space hwmod data arrays will be returned. If @name is null, the | |
3517 | * first array entry will be returned. Data order is not meaningful | |
3518 | * in hwmod data, so callers are strongly encouraged to use a non-null | |
3519 | * @name whenever possible to avoid unpredictable effects if hwmod | |
3520 | * data is later added that causes data ordering to change. This | |
3521 | * function is only intended for use by OMAP core code. Device | |
3522 | * drivers should not call this function - the appropriate bus-related | |
3523 | * data accessor functions should be used instead. Returns 0 upon | |
3524 | * success or a negative error code upon error. | |
3525 | */ | |
3526 | int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, | |
3527 | const char *name, struct resource *rsrc) | |
3528 | { | |
3529 | int r; | |
3530 | unsigned int irq, dma; | |
3531 | u32 pa_start, pa_end; | |
3532 | ||
3533 | if (!oh || !rsrc) | |
3534 | return -EINVAL; | |
3535 | ||
3536 | if (type == IORESOURCE_IRQ) { | |
3537 | r = _get_mpu_irq_by_name(oh, name, &irq); | |
3538 | if (r) | |
3539 | return r; | |
3540 | ||
3541 | rsrc->start = irq; | |
3542 | rsrc->end = irq; | |
3543 | } else if (type == IORESOURCE_DMA) { | |
3544 | r = _get_sdma_req_by_name(oh, name, &dma); | |
3545 | if (r) | |
3546 | return r; | |
3547 | ||
3548 | rsrc->start = dma; | |
3549 | rsrc->end = dma; | |
3550 | } else if (type == IORESOURCE_MEM) { | |
3551 | r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); | |
3552 | if (r) | |
3553 | return r; | |
3554 | ||
3555 | rsrc->start = pa_start; | |
3556 | rsrc->end = pa_end; | |
3557 | } else { | |
3558 | return -EINVAL; | |
3559 | } | |
3560 | ||
3561 | rsrc->flags = type; | |
3562 | rsrc->name = name; | |
3563 | ||
3564 | return 0; | |
3565 | } | |
3566 | ||
63c85238 PW |
3567 | /** |
3568 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
3569 | * @oh: struct omap_hwmod * | |
3570 | * | |
3571 | * Return the powerdomain pointer associated with the OMAP module | |
3572 | * @oh's main clock. If @oh does not have a main clk, return the | |
3573 | * powerdomain associated with the interface clock associated with the | |
3574 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
3575 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
3576 | * success. | |
3577 | */ | |
3578 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
3579 | { | |
3580 | struct clk *c; | |
2d6141ba | 3581 | struct omap_hwmod_ocp_if *oi; |
f5dd3bb5 | 3582 | struct clockdomain *clkdm; |
f5dd3bb5 | 3583 | struct clk_hw_omap *clk; |
63c85238 PW |
3584 | |
3585 | if (!oh) | |
3586 | return NULL; | |
3587 | ||
f5dd3bb5 RN |
3588 | if (oh->clkdm) |
3589 | return oh->clkdm->pwrdm.ptr; | |
3590 | ||
63c85238 PW |
3591 | if (oh->_clk) { |
3592 | c = oh->_clk; | |
3593 | } else { | |
2d6141ba PW |
3594 | oi = _find_mpu_rt_port(oh); |
3595 | if (!oi) | |
63c85238 | 3596 | return NULL; |
2d6141ba | 3597 | c = oi->_clk; |
63c85238 PW |
3598 | } |
3599 | ||
f5dd3bb5 RN |
3600 | clk = to_clk_hw_omap(__clk_get_hw(c)); |
3601 | clkdm = clk->clkdm; | |
f5dd3bb5 | 3602 | if (!clkdm) |
d5647c18 TG |
3603 | return NULL; |
3604 | ||
f5dd3bb5 | 3605 | return clkdm->pwrdm.ptr; |
63c85238 PW |
3606 | } |
3607 | ||
db2a60bf PW |
3608 | /** |
3609 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
3610 | * @oh: struct omap_hwmod * | |
3611 | * | |
3612 | * Returns the virtual address corresponding to the beginning of the | |
3613 | * module's register target, in the address range that is intended to | |
3614 | * be used by the MPU. Returns the virtual address upon success or NULL | |
3615 | * upon error. | |
3616 | */ | |
3617 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
3618 | { | |
3619 | if (!oh) | |
3620 | return NULL; | |
3621 | ||
3622 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
3623 | return NULL; | |
3624 | ||
3625 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
3626 | return NULL; | |
3627 | ||
3628 | return oh->_mpu_rt_va; | |
3629 | } | |
3630 | ||
63c85238 PW |
3631 | /** |
3632 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
3633 | * @oh: struct omap_hwmod * | |
3634 | * @init_oh: struct omap_hwmod * (initiator) | |
3635 | * | |
3636 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
3637 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3638 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3639 | * code needs to add/del initiator dependencies dynamically | |
3640 | * before/after accessing a device. Returns the return value from | |
3641 | * _add_initiator_dep(). | |
3642 | * | |
3643 | * XXX Keep a usecount in the clockdomain code | |
3644 | */ | |
3645 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
3646 | struct omap_hwmod *init_oh) | |
3647 | { | |
3648 | return _add_initiator_dep(oh, init_oh); | |
3649 | } | |
3650 | ||
3651 | /* | |
3652 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
3653 | * for context save/restore operations? | |
3654 | */ | |
3655 | ||
3656 | /** | |
3657 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
3658 | * @oh: struct omap_hwmod * | |
3659 | * @init_oh: struct omap_hwmod * (initiator) | |
3660 | * | |
3661 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
3662 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3663 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3664 | * code needs to add/del initiator dependencies dynamically | |
3665 | * before/after accessing a device. Returns the return value from | |
3666 | * _del_initiator_dep(). | |
3667 | * | |
3668 | * XXX Keep a usecount in the clockdomain code | |
3669 | */ | |
3670 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
3671 | struct omap_hwmod *init_oh) | |
3672 | { | |
3673 | return _del_initiator_dep(oh, init_oh); | |
3674 | } | |
3675 | ||
63c85238 PW |
3676 | /** |
3677 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
3678 | * @oh: struct omap_hwmod * | |
3679 | * | |
3680 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
3681 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
3682 | * this IP block if it has dynamic mux entries. Eventually this | |
3683 | * should set PRCM wakeup registers to cause the PRCM to receive | |
3684 | * wakeup events from the module. Does not set any wakeup routing | |
3685 | * registers beyond this point - if the module is to wake up any other | |
3686 | * module or subsystem, that must be set separately. Called by | |
3687 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3688 | */ |
3689 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
3690 | { | |
dc6d1cda | 3691 | unsigned long flags; |
5a7ddcbd | 3692 | u32 v; |
dc6d1cda | 3693 | |
dc6d1cda | 3694 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3695 | |
3696 | if (oh->class->sysc && | |
3697 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3698 | v = oh->_sysc_cache; | |
3699 | _enable_wakeup(oh, &v); | |
3700 | _write_sysconfig(v, oh); | |
3701 | } | |
3702 | ||
eceec009 | 3703 | _set_idle_ioring_wakeup(oh, true); |
dc6d1cda | 3704 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3705 | |
3706 | return 0; | |
3707 | } | |
3708 | ||
3709 | /** | |
3710 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
3711 | * @oh: struct omap_hwmod * | |
3712 | * | |
3713 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
3714 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
3715 | * events for this IP block if it has dynamic mux entries. Eventually | |
3716 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
3717 | * wakeup events from the module. Does not set any wakeup routing | |
3718 | * registers beyond this point - if the module is to wake up any other | |
3719 | * module or subsystem, that must be set separately. Called by | |
3720 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3721 | */ |
3722 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
3723 | { | |
dc6d1cda | 3724 | unsigned long flags; |
5a7ddcbd | 3725 | u32 v; |
dc6d1cda | 3726 | |
dc6d1cda | 3727 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3728 | |
3729 | if (oh->class->sysc && | |
3730 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3731 | v = oh->_sysc_cache; | |
3732 | _disable_wakeup(oh, &v); | |
3733 | _write_sysconfig(v, oh); | |
3734 | } | |
3735 | ||
eceec009 | 3736 | _set_idle_ioring_wakeup(oh, false); |
dc6d1cda | 3737 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3738 | |
3739 | return 0; | |
3740 | } | |
43b40992 | 3741 | |
aee48e3c PW |
3742 | /** |
3743 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
3744 | * contained in the hwmod module. | |
3745 | * @oh: struct omap_hwmod * | |
3746 | * @name: name of the reset line to lookup and assert | |
3747 | * | |
3748 | * Some IP like dsp, ipu or iva contain processor that require | |
3749 | * an HW reset line to be assert / deassert in order to enable fully | |
3750 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3751 | * yet supported on this OMAP; otherwise, passes along the return value | |
3752 | * from _assert_hardreset(). | |
3753 | */ | |
3754 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
3755 | { | |
3756 | int ret; | |
dc6d1cda | 3757 | unsigned long flags; |
aee48e3c PW |
3758 | |
3759 | if (!oh) | |
3760 | return -EINVAL; | |
3761 | ||
dc6d1cda | 3762 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3763 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 3764 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3765 | |
3766 | return ret; | |
3767 | } | |
3768 | ||
3769 | /** | |
3770 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
3771 | * contained in the hwmod module. | |
3772 | * @oh: struct omap_hwmod * | |
3773 | * @name: name of the reset line to look up and deassert | |
3774 | * | |
3775 | * Some IP like dsp, ipu or iva contain processor that require | |
3776 | * an HW reset line to be assert / deassert in order to enable fully | |
3777 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3778 | * yet supported on this OMAP; otherwise, passes along the return value | |
3779 | * from _deassert_hardreset(). | |
3780 | */ | |
3781 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
3782 | { | |
3783 | int ret; | |
dc6d1cda | 3784 | unsigned long flags; |
aee48e3c PW |
3785 | |
3786 | if (!oh) | |
3787 | return -EINVAL; | |
3788 | ||
dc6d1cda | 3789 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3790 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 3791 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3792 | |
3793 | return ret; | |
3794 | } | |
3795 | ||
3796 | /** | |
3797 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
3798 | * contained in the hwmod module | |
3799 | * @oh: struct omap_hwmod * | |
3800 | * @name: name of the reset line to look up and read | |
3801 | * | |
3802 | * Return the current state of the hwmod @oh's reset line named @name: | |
3803 | * returns -EINVAL upon parameter error or if this operation | |
3804 | * is unsupported on the current OMAP; otherwise, passes along the return | |
3805 | * value from _read_hardreset(). | |
3806 | */ | |
3807 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
3808 | { | |
3809 | int ret; | |
dc6d1cda | 3810 | unsigned long flags; |
aee48e3c PW |
3811 | |
3812 | if (!oh) | |
3813 | return -EINVAL; | |
3814 | ||
dc6d1cda | 3815 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3816 | ret = _read_hardreset(oh, name); |
dc6d1cda | 3817 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3818 | |
3819 | return ret; | |
3820 | } | |
3821 | ||
3822 | ||
43b40992 PW |
3823 | /** |
3824 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
3825 | * @classname: struct omap_hwmod_class name to search for | |
3826 | * @fn: callback function pointer to call for each hwmod in class @classname | |
3827 | * @user: arbitrary context data to pass to the callback function | |
3828 | * | |
ce35b244 BC |
3829 | * For each omap_hwmod of class @classname, call @fn. |
3830 | * If the callback function returns something other than | |
43b40992 PW |
3831 | * zero, the iterator is terminated, and the callback function's return |
3832 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
3833 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
3834 | */ | |
3835 | int omap_hwmod_for_each_by_class(const char *classname, | |
3836 | int (*fn)(struct omap_hwmod *oh, | |
3837 | void *user), | |
3838 | void *user) | |
3839 | { | |
3840 | struct omap_hwmod *temp_oh; | |
3841 | int ret = 0; | |
3842 | ||
3843 | if (!classname || !fn) | |
3844 | return -EINVAL; | |
3845 | ||
3846 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
3847 | __func__, classname); | |
3848 | ||
43b40992 PW |
3849 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
3850 | if (!strcmp(temp_oh->class->name, classname)) { | |
3851 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
3852 | __func__, temp_oh->name); | |
3853 | ret = (*fn)(temp_oh, user); | |
3854 | if (ret) | |
3855 | break; | |
3856 | } | |
3857 | } | |
3858 | ||
43b40992 PW |
3859 | if (ret) |
3860 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
3861 | __func__, ret); | |
3862 | ||
3863 | return ret; | |
3864 | } | |
3865 | ||
2092e5cc PW |
3866 | /** |
3867 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
3868 | * @oh: struct omap_hwmod * | |
3869 | * @state: state that _setup() should leave the hwmod in | |
3870 | * | |
550c8092 | 3871 | * Sets the hwmod state that @oh will enter at the end of _setup() |
64813c3f PW |
3872 | * (called by omap_hwmod_setup_*()). See also the documentation |
3873 | * for _setup_postsetup(), above. Returns 0 upon success or | |
3874 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
3875 | * in the wrong state. | |
2092e5cc PW |
3876 | */ |
3877 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
3878 | { | |
3879 | int ret; | |
dc6d1cda | 3880 | unsigned long flags; |
2092e5cc PW |
3881 | |
3882 | if (!oh) | |
3883 | return -EINVAL; | |
3884 | ||
3885 | if (state != _HWMOD_STATE_DISABLED && | |
3886 | state != _HWMOD_STATE_ENABLED && | |
3887 | state != _HWMOD_STATE_IDLE) | |
3888 | return -EINVAL; | |
3889 | ||
dc6d1cda | 3890 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
3891 | |
3892 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3893 | ret = -EINVAL; | |
3894 | goto ohsps_unlock; | |
3895 | } | |
3896 | ||
3897 | oh->_postsetup_state = state; | |
3898 | ret = 0; | |
3899 | ||
3900 | ohsps_unlock: | |
dc6d1cda | 3901 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
3902 | |
3903 | return ret; | |
3904 | } | |
c80705aa KH |
3905 | |
3906 | /** | |
3907 | * omap_hwmod_get_context_loss_count - get lost context count | |
3908 | * @oh: struct omap_hwmod * | |
3909 | * | |
3910 | * Query the powerdomain of of @oh to get the context loss | |
3911 | * count for this device. | |
3912 | * | |
3913 | * Returns the context loss count of the powerdomain assocated with @oh | |
3914 | * upon success, or zero if no powerdomain exists for @oh. | |
3915 | */ | |
fc013873 | 3916 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
3917 | { |
3918 | struct powerdomain *pwrdm; | |
3919 | int ret = 0; | |
3920 | ||
3921 | pwrdm = omap_hwmod_get_pwrdm(oh); | |
3922 | if (pwrdm) | |
3923 | ret = pwrdm_get_context_loss_count(pwrdm); | |
3924 | ||
3925 | return ret; | |
3926 | } | |
43b01643 PW |
3927 | |
3928 | /** | |
3929 | * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup | |
3930 | * @oh: struct omap_hwmod * | |
3931 | * | |
3932 | * Prevent the hwmod @oh from being reset during the setup process. | |
3933 | * Intended for use by board-*.c files on boards with devices that | |
3934 | * cannot tolerate being reset. Must be called before the hwmod has | |
3935 | * been set up. Returns 0 upon success or negative error code upon | |
3936 | * failure. | |
3937 | */ | |
3938 | int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) | |
3939 | { | |
3940 | if (!oh) | |
3941 | return -EINVAL; | |
3942 | ||
3943 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3944 | pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n", | |
3945 | oh->name); | |
3946 | return -EINVAL; | |
3947 | } | |
3948 | ||
3949 | oh->flags |= HWMOD_INIT_NO_RESET; | |
3950 | ||
3951 | return 0; | |
3952 | } | |
abc2d545 TK |
3953 | |
3954 | /** | |
3955 | * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ | |
3956 | * @oh: struct omap_hwmod * containing hwmod mux entries | |
3957 | * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup | |
3958 | * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup | |
3959 | * | |
3960 | * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux | |
3961 | * entry number @pad_idx for the hwmod @oh, trigger the interrupt | |
3962 | * service routine for the hwmod's mpu_irqs array index @irq_idx. If | |
3963 | * this function is not called for a given pad_idx, then the ISR | |
3964 | * associated with @oh's first MPU IRQ will be triggered when an I/O | |
3965 | * pad wakeup occurs on that pad. Note that @pad_idx is the index of | |
3966 | * the _dynamic or wakeup_ entry: if there are other entries not | |
3967 | * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these | |
3968 | * entries are NOT COUNTED in the dynamic pad index. This function | |
3969 | * must be called separately for each pad that requires its interrupt | |
3970 | * to be re-routed this way. Returns -EINVAL if there is an argument | |
3971 | * problem or if @oh does not have hwmod mux entries or MPU IRQs; | |
3972 | * returns -ENOMEM if memory cannot be allocated; or 0 upon success. | |
3973 | * | |
3974 | * XXX This function interface is fragile. Rather than using array | |
3975 | * indexes, which are subject to unpredictable change, it should be | |
3976 | * using hwmod IRQ names, and some other stable key for the hwmod mux | |
3977 | * pad records. | |
3978 | */ | |
3979 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) | |
3980 | { | |
3981 | int nr_irqs; | |
3982 | ||
3983 | might_sleep(); | |
3984 | ||
3985 | if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 || | |
3986 | pad_idx >= oh->mux->nr_pads_dynamic) | |
3987 | return -EINVAL; | |
3988 | ||
3989 | /* Check the number of available mpu_irqs */ | |
3990 | for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++) | |
3991 | ; | |
3992 | ||
3993 | if (irq_idx >= nr_irqs) | |
3994 | return -EINVAL; | |
3995 | ||
3996 | if (!oh->mux->irqs) { | |
3997 | /* XXX What frees this? */ | |
3998 | oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic, | |
3999 | GFP_KERNEL); | |
4000 | if (!oh->mux->irqs) | |
4001 | return -ENOMEM; | |
4002 | } | |
4003 | oh->mux->irqs[pad_idx] = irq_idx; | |
4004 | ||
4005 | return 0; | |
4006 | } | |
9ebfd285 KH |
4007 | |
4008 | /** | |
4009 | * omap_hwmod_init - initialize the hwmod code | |
4010 | * | |
4011 | * Sets up some function pointers needed by the hwmod code to operate on the | |
4012 | * currently-booted SoC. Intended to be called once during kernel init | |
4013 | * before any hwmods are registered. No return value. | |
4014 | */ | |
4015 | void __init omap_hwmod_init(void) | |
4016 | { | |
ff4ae5d9 PW |
4017 | if (cpu_is_omap24xx()) { |
4018 | soc_ops.wait_target_ready = _omap2xxx_wait_target_ready; | |
4019 | soc_ops.assert_hardreset = _omap2_assert_hardreset; | |
4020 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
4021 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
4022 | } else if (cpu_is_omap34xx()) { | |
4023 | soc_ops.wait_target_ready = _omap3xxx_wait_target_ready; | |
b8249cf2 KH |
4024 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
4025 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
4026 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
05e152c7 | 4027 | } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { |
9ebfd285 KH |
4028 | soc_ops.enable_module = _omap4_enable_module; |
4029 | soc_ops.disable_module = _omap4_disable_module; | |
8f6aa8ee | 4030 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
b8249cf2 KH |
4031 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
4032 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | |
4033 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | |
0a179eaa | 4034 | soc_ops.init_clkdm = _init_clkdm; |
1688bf19 VH |
4035 | } else if (soc_is_am33xx()) { |
4036 | soc_ops.enable_module = _am33xx_enable_module; | |
4037 | soc_ops.disable_module = _am33xx_disable_module; | |
4038 | soc_ops.wait_target_ready = _am33xx_wait_target_ready; | |
4039 | soc_ops.assert_hardreset = _am33xx_assert_hardreset; | |
4040 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; | |
4041 | soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; | |
4042 | soc_ops.init_clkdm = _init_clkdm; | |
8f6aa8ee KH |
4043 | } else { |
4044 | WARN(1, "omap_hwmod: unknown SoC type\n"); | |
9ebfd285 KH |
4045 | } |
4046 | ||
4047 | inited = true; | |
4048 | } | |
68c9a95e TL |
4049 | |
4050 | /** | |
4051 | * omap_hwmod_get_main_clk - get pointer to main clock name | |
4052 | * @oh: struct omap_hwmod * | |
4053 | * | |
4054 | * Returns the main clock name assocated with @oh upon success, | |
4055 | * or NULL if @oh is NULL. | |
4056 | */ | |
4057 | const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) | |
4058 | { | |
4059 | if (!oh) | |
4060 | return NULL; | |
4061 | ||
4062 | return oh->main_clk; | |
4063 | } |