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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, Benoît Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
75 | * | (__raw_{read,write}l, clk*) | | |
76 | * +-------------------------------+ | |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
133 | #include <linux/clk.h> | |
134 | #include <linux/delay.h> | |
135 | #include <linux/err.h> | |
136 | #include <linux/list.h> | |
137 | #include <linux/mutex.h> | |
dc6d1cda | 138 | #include <linux/spinlock.h> |
abc2d545 | 139 | #include <linux/slab.h> |
2221b5cd | 140 | #include <linux/bootmem.h> |
63c85238 | 141 | |
ce491cf8 TL |
142 | #include <plat/clock.h> |
143 | #include <plat/omap_hwmod.h> | |
5365efbe | 144 | #include <plat/prcm.h> |
63c85238 | 145 | |
dbc04161 TL |
146 | #include "soc.h" |
147 | #include "common.h" | |
148 | #include "clockdomain.h" | |
149 | #include "powerdomain.h" | |
59fb659b | 150 | #include "cm2xxx_3xxx.h" |
d0f0631d | 151 | #include "cminst44xx.h" |
1688bf19 | 152 | #include "cm33xx.h" |
59fb659b | 153 | #include "prm2xxx_3xxx.h" |
d198b514 | 154 | #include "prm44xx.h" |
1688bf19 | 155 | #include "prm33xx.h" |
eaac329d | 156 | #include "prminst44xx.h" |
8d9af88f | 157 | #include "mux.h" |
5165882a | 158 | #include "pm.h" |
63c85238 | 159 | |
5365efbe BC |
160 | /* Maximum microseconds to wait for OMAP module to softreset */ |
161 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | |
63c85238 PW |
162 | |
163 | /* Name of the OMAP hwmod for the MPU */ | |
5c2c0296 | 164 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 | 165 | |
2221b5cd PW |
166 | /* |
167 | * Number of struct omap_hwmod_link records per struct | |
168 | * omap_hwmod_ocp_if record (master->slave and slave->master) | |
169 | */ | |
170 | #define LINKS_PER_OCP_IF 2 | |
171 | ||
9ebfd285 KH |
172 | /** |
173 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | |
174 | * @enable_module: function to enable a module (via MODULEMODE) | |
175 | * @disable_module: function to disable a module (via MODULEMODE) | |
176 | * | |
177 | * XXX Eventually this functionality will be hidden inside the PRM/CM | |
178 | * device drivers. Until then, this should avoid huge blocks of cpu_is_*() | |
179 | * conditionals in this code. | |
180 | */ | |
181 | struct omap_hwmod_soc_ops { | |
182 | void (*enable_module)(struct omap_hwmod *oh); | |
183 | int (*disable_module)(struct omap_hwmod *oh); | |
8f6aa8ee | 184 | int (*wait_target_ready)(struct omap_hwmod *oh); |
b8249cf2 KH |
185 | int (*assert_hardreset)(struct omap_hwmod *oh, |
186 | struct omap_hwmod_rst_info *ohri); | |
187 | int (*deassert_hardreset)(struct omap_hwmod *oh, | |
188 | struct omap_hwmod_rst_info *ohri); | |
189 | int (*is_hardreset_asserted)(struct omap_hwmod *oh, | |
190 | struct omap_hwmod_rst_info *ohri); | |
0a179eaa | 191 | int (*init_clkdm)(struct omap_hwmod *oh); |
9ebfd285 KH |
192 | }; |
193 | ||
194 | /* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */ | |
195 | static struct omap_hwmod_soc_ops soc_ops; | |
196 | ||
63c85238 PW |
197 | /* omap_hwmod_list contains all registered struct omap_hwmods */ |
198 | static LIST_HEAD(omap_hwmod_list); | |
199 | ||
63c85238 PW |
200 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
201 | static struct omap_hwmod *mpu_oh; | |
202 | ||
5165882a VB |
203 | /* io_chain_lock: used to serialize reconfigurations of the I/O chain */ |
204 | static DEFINE_SPINLOCK(io_chain_lock); | |
205 | ||
2221b5cd PW |
206 | /* |
207 | * linkspace: ptr to a buffer that struct omap_hwmod_link records are | |
208 | * allocated from - used to reduce the number of small memory | |
209 | * allocations, which has a significant impact on performance | |
210 | */ | |
211 | static struct omap_hwmod_link *linkspace; | |
212 | ||
213 | /* | |
214 | * free_ls, max_ls: array indexes into linkspace; representing the | |
215 | * next free struct omap_hwmod_link index, and the maximum number of | |
216 | * struct omap_hwmod_link records allocated (respectively) | |
217 | */ | |
218 | static unsigned short free_ls, max_ls, ls_supp; | |
63c85238 | 219 | |
9ebfd285 KH |
220 | /* inited: set to true once the hwmod code is initialized */ |
221 | static bool inited; | |
222 | ||
63c85238 PW |
223 | /* Private functions */ |
224 | ||
5d95dde7 | 225 | /** |
11cd4b94 | 226 | * _fetch_next_ocp_if - return the next OCP interface in a list |
2221b5cd | 227 | * @p: ptr to a ptr to the list_head inside the ocp_if to return |
11cd4b94 PW |
228 | * @i: pointer to the index of the element pointed to by @p in the list |
229 | * | |
230 | * Return a pointer to the struct omap_hwmod_ocp_if record | |
231 | * containing the struct list_head pointed to by @p, and increment | |
232 | * @p such that a future call to this routine will return the next | |
233 | * record. | |
5d95dde7 PW |
234 | */ |
235 | static struct omap_hwmod_ocp_if *_fetch_next_ocp_if(struct list_head **p, | |
5d95dde7 PW |
236 | int *i) |
237 | { | |
238 | struct omap_hwmod_ocp_if *oi; | |
239 | ||
11cd4b94 PW |
240 | oi = list_entry(*p, struct omap_hwmod_link, node)->ocp_if; |
241 | *p = (*p)->next; | |
2221b5cd | 242 | |
5d95dde7 PW |
243 | *i = *i + 1; |
244 | ||
245 | return oi; | |
246 | } | |
247 | ||
63c85238 PW |
248 | /** |
249 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
250 | * @oh: struct omap_hwmod * | |
251 | * | |
252 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
253 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
254 | * OCP_SYSCONFIG register or 0 upon success. | |
255 | */ | |
256 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
257 | { | |
43b40992 PW |
258 | if (!oh->class->sysc) { |
259 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
260 | return -EINVAL; |
261 | } | |
262 | ||
263 | /* XXX ensure module interface clock is up */ | |
264 | ||
cc7a1d2a | 265 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 266 | |
43b40992 | 267 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 268 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
269 | |
270 | return 0; | |
271 | } | |
272 | ||
273 | /** | |
274 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
275 | * @v: OCP_SYSCONFIG value to write | |
276 | * @oh: struct omap_hwmod * | |
277 | * | |
43b40992 PW |
278 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
279 | * one. No return value. | |
63c85238 PW |
280 | */ |
281 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
282 | { | |
43b40992 PW |
283 | if (!oh->class->sysc) { |
284 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
285 | return; |
286 | } | |
287 | ||
288 | /* XXX ensure module interface clock is up */ | |
289 | ||
233cbe5b RN |
290 | /* Module might have lost context, always update cache and register */ |
291 | oh->_sysc_cache = v; | |
292 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); | |
63c85238 PW |
293 | } |
294 | ||
295 | /** | |
296 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
297 | * @oh: struct omap_hwmod * | |
298 | * @standbymode: MIDLEMODE field bits | |
299 | * @v: pointer to register contents to modify | |
300 | * | |
301 | * Update the master standby mode bits in @v to be @standbymode for | |
302 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
303 | * upon error or 0 upon success. | |
304 | */ | |
305 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
306 | u32 *v) | |
307 | { | |
358f0e63 TG |
308 | u32 mstandby_mask; |
309 | u8 mstandby_shift; | |
310 | ||
43b40992 PW |
311 | if (!oh->class->sysc || |
312 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
313 | return -EINVAL; |
314 | ||
43b40992 PW |
315 | if (!oh->class->sysc->sysc_fields) { |
316 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
317 | return -EINVAL; |
318 | } | |
319 | ||
43b40992 | 320 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
321 | mstandby_mask = (0x3 << mstandby_shift); |
322 | ||
323 | *v &= ~mstandby_mask; | |
324 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
325 | |
326 | return 0; | |
327 | } | |
328 | ||
329 | /** | |
330 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
331 | * @oh: struct omap_hwmod * | |
332 | * @idlemode: SIDLEMODE field bits | |
333 | * @v: pointer to register contents to modify | |
334 | * | |
335 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
336 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
337 | * or 0 upon success. | |
338 | */ | |
339 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
340 | { | |
358f0e63 TG |
341 | u32 sidle_mask; |
342 | u8 sidle_shift; | |
343 | ||
43b40992 PW |
344 | if (!oh->class->sysc || |
345 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
346 | return -EINVAL; |
347 | ||
43b40992 PW |
348 | if (!oh->class->sysc->sysc_fields) { |
349 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
350 | return -EINVAL; |
351 | } | |
352 | ||
43b40992 | 353 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
354 | sidle_mask = (0x3 << sidle_shift); |
355 | ||
356 | *v &= ~sidle_mask; | |
357 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
358 | |
359 | return 0; | |
360 | } | |
361 | ||
362 | /** | |
363 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
364 | * @oh: struct omap_hwmod * | |
365 | * @clockact: CLOCKACTIVITY field bits | |
366 | * @v: pointer to register contents to modify | |
367 | * | |
368 | * Update the clockactivity mode bits in @v to be @clockact for the | |
369 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
370 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
371 | * success. | |
372 | */ | |
373 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
374 | { | |
358f0e63 TG |
375 | u32 clkact_mask; |
376 | u8 clkact_shift; | |
377 | ||
43b40992 PW |
378 | if (!oh->class->sysc || |
379 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
380 | return -EINVAL; |
381 | ||
43b40992 PW |
382 | if (!oh->class->sysc->sysc_fields) { |
383 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
384 | return -EINVAL; |
385 | } | |
386 | ||
43b40992 | 387 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
388 | clkact_mask = (0x3 << clkact_shift); |
389 | ||
390 | *v &= ~clkact_mask; | |
391 | *v |= clockact << clkact_shift; | |
63c85238 PW |
392 | |
393 | return 0; | |
394 | } | |
395 | ||
396 | /** | |
397 | * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
398 | * @oh: struct omap_hwmod * | |
399 | * @v: pointer to register contents to modify | |
400 | * | |
401 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
402 | * error or 0 upon success. | |
403 | */ | |
404 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
405 | { | |
358f0e63 TG |
406 | u32 softrst_mask; |
407 | ||
43b40992 PW |
408 | if (!oh->class->sysc || |
409 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
410 | return -EINVAL; |
411 | ||
43b40992 PW |
412 | if (!oh->class->sysc->sysc_fields) { |
413 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
414 | return -EINVAL; |
415 | } | |
416 | ||
43b40992 | 417 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
418 | |
419 | *v |= softrst_mask; | |
63c85238 PW |
420 | |
421 | return 0; | |
422 | } | |
423 | ||
613ad0e9 TK |
424 | /** |
425 | * _wait_softreset_complete - wait for an OCP softreset to complete | |
426 | * @oh: struct omap_hwmod * to wait on | |
427 | * | |
428 | * Wait until the IP block represented by @oh reports that its OCP | |
429 | * softreset is complete. This can be triggered by software (see | |
430 | * _ocp_softreset()) or by hardware upon returning from off-mode (one | |
431 | * example is HSMMC). Waits for up to MAX_MODULE_SOFTRESET_WAIT | |
432 | * microseconds. Returns the number of microseconds waited. | |
433 | */ | |
434 | static int _wait_softreset_complete(struct omap_hwmod *oh) | |
435 | { | |
436 | struct omap_hwmod_class_sysconfig *sysc; | |
437 | u32 softrst_mask; | |
438 | int c = 0; | |
439 | ||
440 | sysc = oh->class->sysc; | |
441 | ||
442 | if (sysc->sysc_flags & SYSS_HAS_RESET_STATUS) | |
443 | omap_test_timeout((omap_hwmod_read(oh, sysc->syss_offs) | |
444 | & SYSS_RESETDONE_MASK), | |
445 | MAX_MODULE_SOFTRESET_WAIT, c); | |
446 | else if (sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { | |
447 | softrst_mask = (0x1 << sysc->sysc_fields->srst_shift); | |
448 | omap_test_timeout(!(omap_hwmod_read(oh, sysc->sysc_offs) | |
449 | & softrst_mask), | |
450 | MAX_MODULE_SOFTRESET_WAIT, c); | |
451 | } | |
452 | ||
453 | return c; | |
454 | } | |
455 | ||
6668546f KVA |
456 | /** |
457 | * _set_dmadisable: set OCP_SYSCONFIG.DMADISABLE bit in @v | |
458 | * @oh: struct omap_hwmod * | |
459 | * | |
460 | * The DMADISABLE bit is a semi-automatic bit present in sysconfig register | |
461 | * of some modules. When the DMA must perform read/write accesses, the | |
462 | * DMADISABLE bit is cleared by the hardware. But when the DMA must stop | |
463 | * for power management, software must set the DMADISABLE bit back to 1. | |
464 | * | |
465 | * Set the DMADISABLE bit in @v for hwmod @oh. Returns -EINVAL upon | |
466 | * error or 0 upon success. | |
467 | */ | |
468 | static int _set_dmadisable(struct omap_hwmod *oh) | |
469 | { | |
470 | u32 v; | |
471 | u32 dmadisable_mask; | |
472 | ||
473 | if (!oh->class->sysc || | |
474 | !(oh->class->sysc->sysc_flags & SYSC_HAS_DMADISABLE)) | |
475 | return -EINVAL; | |
476 | ||
477 | if (!oh->class->sysc->sysc_fields) { | |
478 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
479 | return -EINVAL; | |
480 | } | |
481 | ||
482 | /* clocks must be on for this operation */ | |
483 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
484 | pr_warn("omap_hwmod: %s: dma can be disabled only from enabled state\n", oh->name); | |
485 | return -EINVAL; | |
486 | } | |
487 | ||
488 | pr_debug("omap_hwmod: %s: setting DMADISABLE\n", oh->name); | |
489 | ||
490 | v = oh->_sysc_cache; | |
491 | dmadisable_mask = | |
492 | (0x1 << oh->class->sysc->sysc_fields->dmadisable_shift); | |
493 | v |= dmadisable_mask; | |
494 | _write_sysconfig(v, oh); | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
726072e5 PW |
499 | /** |
500 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
501 | * @oh: struct omap_hwmod * | |
502 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
503 | * @v: pointer to register contents to modify | |
504 | * | |
505 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
506 | * hwmod. The autoidle bit controls whether the module can gate | |
507 | * internal clocks automatically when it isn't doing anything; the | |
508 | * exact function of this bit varies on a per-module basis. This | |
509 | * function does not write to the hardware. Returns -EINVAL upon | |
510 | * error or 0 upon success. | |
511 | */ | |
512 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
513 | u32 *v) | |
514 | { | |
358f0e63 TG |
515 | u32 autoidle_mask; |
516 | u8 autoidle_shift; | |
517 | ||
43b40992 PW |
518 | if (!oh->class->sysc || |
519 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
520 | return -EINVAL; |
521 | ||
43b40992 PW |
522 | if (!oh->class->sysc->sysc_fields) { |
523 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
524 | return -EINVAL; |
525 | } | |
526 | ||
43b40992 | 527 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 528 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
529 | |
530 | *v &= ~autoidle_mask; | |
531 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
532 | |
533 | return 0; | |
534 | } | |
535 | ||
eceec009 G |
536 | /** |
537 | * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux | |
538 | * @oh: struct omap_hwmod * | |
539 | * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable | |
540 | * | |
541 | * Set or clear the I/O pad wakeup flag in the mux entries for the | |
542 | * hwmod @oh. This function changes the @oh->mux->pads_dynamic array | |
543 | * in memory. If the hwmod is currently idled, and the new idle | |
544 | * values don't match the previous ones, this function will also | |
545 | * update the SCM PADCTRL registers. Otherwise, if the hwmod is not | |
546 | * currently idled, this function won't touch the hardware: the new | |
547 | * mux settings are written to the SCM PADCTRL registers when the | |
548 | * hwmod is idled. No return value. | |
549 | */ | |
550 | static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake) | |
551 | { | |
552 | struct omap_device_pad *pad; | |
553 | bool change = false; | |
554 | u16 prev_idle; | |
555 | int j; | |
556 | ||
557 | if (!oh->mux || !oh->mux->enabled) | |
558 | return; | |
559 | ||
560 | for (j = 0; j < oh->mux->nr_pads_dynamic; j++) { | |
561 | pad = oh->mux->pads_dynamic[j]; | |
562 | ||
563 | if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP)) | |
564 | continue; | |
565 | ||
566 | prev_idle = pad->idle; | |
567 | ||
568 | if (set_wake) | |
569 | pad->idle |= OMAP_WAKEUP_EN; | |
570 | else | |
571 | pad->idle &= ~OMAP_WAKEUP_EN; | |
572 | ||
573 | if (prev_idle != pad->idle) | |
574 | change = true; | |
575 | } | |
576 | ||
577 | if (change && oh->_state == _HWMOD_STATE_IDLE) | |
578 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); | |
579 | } | |
580 | ||
63c85238 PW |
581 | /** |
582 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
583 | * @oh: struct omap_hwmod * | |
584 | * | |
585 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
586 | * upon error or 0 upon success. | |
587 | */ | |
5a7ddcbd | 588 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 589 | { |
43b40992 | 590 | if (!oh->class->sysc || |
86009eb3 | 591 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
592 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
593 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
594 | return -EINVAL; |
595 | ||
43b40992 PW |
596 | if (!oh->class->sysc->sysc_fields) { |
597 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
598 | return -EINVAL; |
599 | } | |
600 | ||
1fe74113 BC |
601 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
602 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 603 | |
86009eb3 BC |
604 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
605 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
606 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
607 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 608 | |
63c85238 PW |
609 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
610 | ||
611 | oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
616 | /** | |
617 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
618 | * @oh: struct omap_hwmod * | |
619 | * | |
620 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
621 | * upon error or 0 upon success. | |
622 | */ | |
5a7ddcbd | 623 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 624 | { |
43b40992 | 625 | if (!oh->class->sysc || |
86009eb3 | 626 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
627 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
628 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
629 | return -EINVAL; |
630 | ||
43b40992 PW |
631 | if (!oh->class->sysc->sysc_fields) { |
632 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
633 | return -EINVAL; |
634 | } | |
635 | ||
1fe74113 BC |
636 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
637 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 638 | |
86009eb3 BC |
639 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
640 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 | 641 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
561038f0 | 642 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART, v); |
86009eb3 | 643 | |
63c85238 PW |
644 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
645 | ||
646 | oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | /** | |
652 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
653 | * @oh: struct omap_hwmod * | |
654 | * | |
655 | * Prevent the hardware module @oh from entering idle while the | |
656 | * hardare module initiator @init_oh is active. Useful when a module | |
657 | * will be accessed by a particular initiator (e.g., if a module will | |
658 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
659 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
660 | * mode. If the clockdomain is marked as not needing autodeps, return |
661 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
662 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
663 | */ |
664 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
665 | { | |
666 | if (!oh->_clk) | |
667 | return -EINVAL; | |
668 | ||
570b54c7 PW |
669 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
670 | return 0; | |
671 | ||
55ed9694 | 672 | return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
673 | } |
674 | ||
675 | /** | |
676 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
677 | * @oh: struct omap_hwmod * | |
678 | * | |
679 | * Allow the hardware module @oh to enter idle while the hardare | |
680 | * module initiator @init_oh is active. Useful when a module will not | |
681 | * be accessed by a particular initiator (e.g., if a module will not | |
682 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
683 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
684 | * mode. If the clockdomain is marked as not needing autodeps, return |
685 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
686 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
687 | */ |
688 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
689 | { | |
690 | if (!oh->_clk) | |
691 | return -EINVAL; | |
692 | ||
570b54c7 PW |
693 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
694 | return 0; | |
695 | ||
55ed9694 | 696 | return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
697 | } |
698 | ||
699 | /** | |
700 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
701 | * @oh: struct omap_hwmod * | |
702 | * | |
703 | * Called from _init_clocks(). Populates the @oh _clk (main | |
704 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
705 | * success or -EINVAL on error. | |
706 | */ | |
707 | static int _init_main_clk(struct omap_hwmod *oh) | |
708 | { | |
63c85238 PW |
709 | int ret = 0; |
710 | ||
50ebdac2 | 711 | if (!oh->main_clk) |
63c85238 PW |
712 | return 0; |
713 | ||
6ea74cb9 RN |
714 | oh->_clk = clk_get(NULL, oh->main_clk); |
715 | if (IS_ERR(oh->_clk)) { | |
20383d82 BC |
716 | pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
717 | oh->name, oh->main_clk); | |
63403384 | 718 | return -EINVAL; |
dc75925d | 719 | } |
4d7cb45e RN |
720 | /* |
721 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
722 | * to do something meaningful. Today its just a no-op. | |
723 | * If clk_prepare() is used at some point to do things like | |
724 | * voltage scaling etc, then this would have to be moved to | |
725 | * some point where subsystems like i2c and pmic become | |
726 | * available. | |
727 | */ | |
728 | clk_prepare(oh->_clk); | |
63c85238 | 729 | |
63403384 | 730 | if (!oh->_clk->clkdm) |
3bb05dbf | 731 | pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n", |
5dcc3b97 | 732 | oh->name, oh->main_clk); |
81d7c6ff | 733 | |
63c85238 PW |
734 | return ret; |
735 | } | |
736 | ||
737 | /** | |
887adeac | 738 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
739 | * @oh: struct omap_hwmod * |
740 | * | |
741 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
742 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
743 | */ | |
744 | static int _init_interface_clks(struct omap_hwmod *oh) | |
745 | { | |
5d95dde7 | 746 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 747 | struct list_head *p; |
63c85238 | 748 | struct clk *c; |
5d95dde7 | 749 | int i = 0; |
63c85238 PW |
750 | int ret = 0; |
751 | ||
11cd4b94 | 752 | p = oh->slave_ports.next; |
2221b5cd | 753 | |
5d95dde7 | 754 | while (i < oh->slaves_cnt) { |
11cd4b94 | 755 | os = _fetch_next_ocp_if(&p, &i); |
50ebdac2 | 756 | if (!os->clk) |
63c85238 PW |
757 | continue; |
758 | ||
6ea74cb9 RN |
759 | c = clk_get(NULL, os->clk); |
760 | if (IS_ERR(c)) { | |
20383d82 BC |
761 | pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
762 | oh->name, os->clk); | |
63c85238 | 763 | ret = -EINVAL; |
dc75925d | 764 | } |
63c85238 | 765 | os->_clk = c; |
4d7cb45e RN |
766 | /* |
767 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
768 | * to do something meaningful. Today its just a no-op. | |
769 | * If clk_prepare() is used at some point to do things like | |
770 | * voltage scaling etc, then this would have to be moved to | |
771 | * some point where subsystems like i2c and pmic become | |
772 | * available. | |
773 | */ | |
774 | clk_prepare(os->_clk); | |
63c85238 PW |
775 | } |
776 | ||
777 | return ret; | |
778 | } | |
779 | ||
780 | /** | |
781 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
782 | * @oh: struct omap_hwmod * | |
783 | * | |
784 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
785 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
786 | */ | |
787 | static int _init_opt_clks(struct omap_hwmod *oh) | |
788 | { | |
789 | struct omap_hwmod_opt_clk *oc; | |
790 | struct clk *c; | |
791 | int i; | |
792 | int ret = 0; | |
793 | ||
794 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
6ea74cb9 RN |
795 | c = clk_get(NULL, oc->clk); |
796 | if (IS_ERR(c)) { | |
20383d82 BC |
797 | pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
798 | oh->name, oc->clk); | |
63c85238 | 799 | ret = -EINVAL; |
dc75925d | 800 | } |
63c85238 | 801 | oc->_clk = c; |
4d7cb45e RN |
802 | /* |
803 | * HACK: This needs a re-visit once clk_prepare() is implemented | |
804 | * to do something meaningful. Today its just a no-op. | |
805 | * If clk_prepare() is used at some point to do things like | |
806 | * voltage scaling etc, then this would have to be moved to | |
807 | * some point where subsystems like i2c and pmic become | |
808 | * available. | |
809 | */ | |
810 | clk_prepare(oc->_clk); | |
63c85238 PW |
811 | } |
812 | ||
813 | return ret; | |
814 | } | |
815 | ||
816 | /** | |
817 | * _enable_clocks - enable hwmod main clock and interface clocks | |
818 | * @oh: struct omap_hwmod * | |
819 | * | |
820 | * Enables all clocks necessary for register reads and writes to succeed | |
821 | * on the hwmod @oh. Returns 0. | |
822 | */ | |
823 | static int _enable_clocks(struct omap_hwmod *oh) | |
824 | { | |
5d95dde7 | 825 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 826 | struct list_head *p; |
5d95dde7 | 827 | int i = 0; |
63c85238 PW |
828 | |
829 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
830 | ||
4d3ae5a9 | 831 | if (oh->_clk) |
63c85238 PW |
832 | clk_enable(oh->_clk); |
833 | ||
11cd4b94 | 834 | p = oh->slave_ports.next; |
2221b5cd | 835 | |
5d95dde7 | 836 | while (i < oh->slaves_cnt) { |
11cd4b94 | 837 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 838 | |
5d95dde7 PW |
839 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
840 | clk_enable(os->_clk); | |
63c85238 PW |
841 | } |
842 | ||
843 | /* The opt clocks are controlled by the device driver. */ | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
848 | /** | |
849 | * _disable_clocks - disable hwmod main clock and interface clocks | |
850 | * @oh: struct omap_hwmod * | |
851 | * | |
852 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
853 | */ | |
854 | static int _disable_clocks(struct omap_hwmod *oh) | |
855 | { | |
5d95dde7 | 856 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 857 | struct list_head *p; |
5d95dde7 | 858 | int i = 0; |
63c85238 PW |
859 | |
860 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
861 | ||
4d3ae5a9 | 862 | if (oh->_clk) |
63c85238 PW |
863 | clk_disable(oh->_clk); |
864 | ||
11cd4b94 | 865 | p = oh->slave_ports.next; |
2221b5cd | 866 | |
5d95dde7 | 867 | while (i < oh->slaves_cnt) { |
11cd4b94 | 868 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 869 | |
5d95dde7 PW |
870 | if (os->_clk && (os->flags & OCPIF_SWSUP_IDLE)) |
871 | clk_disable(os->_clk); | |
63c85238 PW |
872 | } |
873 | ||
874 | /* The opt clocks are controlled by the device driver. */ | |
875 | ||
876 | return 0; | |
877 | } | |
878 | ||
96835af9 BC |
879 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
880 | { | |
881 | struct omap_hwmod_opt_clk *oc; | |
882 | int i; | |
883 | ||
884 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
885 | ||
886 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
887 | if (oc->_clk) { | |
888 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
5dcc3b97 | 889 | __clk_get_name(oc->_clk)); |
96835af9 BC |
890 | clk_enable(oc->_clk); |
891 | } | |
892 | } | |
893 | ||
894 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
895 | { | |
896 | struct omap_hwmod_opt_clk *oc; | |
897 | int i; | |
898 | ||
899 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
900 | ||
901 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
902 | if (oc->_clk) { | |
903 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
5dcc3b97 | 904 | __clk_get_name(oc->_clk)); |
96835af9 BC |
905 | clk_disable(oc->_clk); |
906 | } | |
907 | } | |
908 | ||
45c38252 | 909 | /** |
3d9f0327 | 910 | * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4 |
45c38252 BC |
911 | * @oh: struct omap_hwmod * |
912 | * | |
913 | * Enables the PRCM module mode related to the hwmod @oh. | |
914 | * No return value. | |
915 | */ | |
3d9f0327 | 916 | static void _omap4_enable_module(struct omap_hwmod *oh) |
45c38252 | 917 | { |
45c38252 BC |
918 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
919 | return; | |
920 | ||
3d9f0327 KH |
921 | pr_debug("omap_hwmod: %s: %s: %d\n", |
922 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
45c38252 BC |
923 | |
924 | omap4_cminst_module_enable(oh->prcm.omap4.modulemode, | |
925 | oh->clkdm->prcm_partition, | |
926 | oh->clkdm->cm_inst, | |
927 | oh->clkdm->clkdm_offs, | |
928 | oh->prcm.omap4.clkctrl_offs); | |
929 | } | |
930 | ||
1688bf19 VH |
931 | /** |
932 | * _am33xx_enable_module - enable CLKCTRL modulemode on AM33XX | |
933 | * @oh: struct omap_hwmod * | |
934 | * | |
935 | * Enables the PRCM module mode related to the hwmod @oh. | |
936 | * No return value. | |
937 | */ | |
938 | static void _am33xx_enable_module(struct omap_hwmod *oh) | |
939 | { | |
940 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
941 | return; | |
942 | ||
943 | pr_debug("omap_hwmod: %s: %s: %d\n", | |
944 | oh->name, __func__, oh->prcm.omap4.modulemode); | |
945 | ||
946 | am33xx_cm_module_enable(oh->prcm.omap4.modulemode, oh->clkdm->cm_inst, | |
947 | oh->clkdm->clkdm_offs, | |
948 | oh->prcm.omap4.clkctrl_offs); | |
949 | } | |
950 | ||
45c38252 | 951 | /** |
bfc141e3 BC |
952 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
953 | * @oh: struct omap_hwmod * | |
954 | * | |
955 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
956 | * does not have an IDLEST bit or if the module successfully enters | |
957 | * slave idle; otherwise, pass along the return value of the | |
958 | * appropriate *_cm*_wait_module_idle() function. | |
959 | */ | |
960 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
961 | { | |
2b026d13 | 962 | if (!oh) |
bfc141e3 BC |
963 | return -EINVAL; |
964 | ||
2b026d13 | 965 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm) |
bfc141e3 BC |
966 | return 0; |
967 | ||
968 | if (oh->flags & HWMOD_NO_IDLEST) | |
969 | return 0; | |
970 | ||
971 | return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition, | |
972 | oh->clkdm->cm_inst, | |
973 | oh->clkdm->clkdm_offs, | |
974 | oh->prcm.omap4.clkctrl_offs); | |
975 | } | |
976 | ||
1688bf19 VH |
977 | /** |
978 | * _am33xx_wait_target_disable - wait for a module to be disabled on AM33XX | |
979 | * @oh: struct omap_hwmod * | |
980 | * | |
981 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
982 | * does not have an IDLEST bit or if the module successfully enters | |
983 | * slave idle; otherwise, pass along the return value of the | |
984 | * appropriate *_cm*_wait_module_idle() function. | |
985 | */ | |
986 | static int _am33xx_wait_target_disable(struct omap_hwmod *oh) | |
987 | { | |
988 | if (!oh) | |
989 | return -EINVAL; | |
990 | ||
991 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
992 | return 0; | |
993 | ||
994 | if (oh->flags & HWMOD_NO_IDLEST) | |
995 | return 0; | |
996 | ||
997 | return am33xx_cm_wait_module_idle(oh->clkdm->cm_inst, | |
998 | oh->clkdm->clkdm_offs, | |
999 | oh->prcm.omap4.clkctrl_offs); | |
1000 | } | |
1001 | ||
212738a4 PW |
1002 | /** |
1003 | * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh | |
1004 | * @oh: struct omap_hwmod *oh | |
1005 | * | |
1006 | * Count and return the number of MPU IRQs associated with the hwmod | |
1007 | * @oh. Used to allocate struct resource data. Returns 0 if @oh is | |
1008 | * NULL. | |
1009 | */ | |
1010 | static int _count_mpu_irqs(struct omap_hwmod *oh) | |
1011 | { | |
1012 | struct omap_hwmod_irq_info *ohii; | |
1013 | int i = 0; | |
1014 | ||
1015 | if (!oh || !oh->mpu_irqs) | |
1016 | return 0; | |
1017 | ||
1018 | do { | |
1019 | ohii = &oh->mpu_irqs[i++]; | |
1020 | } while (ohii->irq != -1); | |
1021 | ||
cc1b0765 | 1022 | return i-1; |
212738a4 PW |
1023 | } |
1024 | ||
bc614958 PW |
1025 | /** |
1026 | * _count_sdma_reqs - count the number of SDMA request lines associated with @oh | |
1027 | * @oh: struct omap_hwmod *oh | |
1028 | * | |
1029 | * Count and return the number of SDMA request lines associated with | |
1030 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1031 | * if @oh is NULL. | |
1032 | */ | |
1033 | static int _count_sdma_reqs(struct omap_hwmod *oh) | |
1034 | { | |
1035 | struct omap_hwmod_dma_info *ohdi; | |
1036 | int i = 0; | |
1037 | ||
1038 | if (!oh || !oh->sdma_reqs) | |
1039 | return 0; | |
1040 | ||
1041 | do { | |
1042 | ohdi = &oh->sdma_reqs[i++]; | |
1043 | } while (ohdi->dma_req != -1); | |
1044 | ||
cc1b0765 | 1045 | return i-1; |
bc614958 PW |
1046 | } |
1047 | ||
78183f3f PW |
1048 | /** |
1049 | * _count_ocp_if_addr_spaces - count the number of address space entries for @oh | |
1050 | * @oh: struct omap_hwmod *oh | |
1051 | * | |
1052 | * Count and return the number of address space ranges associated with | |
1053 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
1054 | * if @oh is NULL. | |
1055 | */ | |
1056 | static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) | |
1057 | { | |
1058 | struct omap_hwmod_addr_space *mem; | |
1059 | int i = 0; | |
1060 | ||
1061 | if (!os || !os->addr) | |
1062 | return 0; | |
1063 | ||
1064 | do { | |
1065 | mem = &os->addr[i++]; | |
1066 | } while (mem->pa_start != mem->pa_end); | |
1067 | ||
cc1b0765 | 1068 | return i-1; |
78183f3f PW |
1069 | } |
1070 | ||
5e8370f1 PW |
1071 | /** |
1072 | * _get_mpu_irq_by_name - fetch MPU interrupt line number by name | |
1073 | * @oh: struct omap_hwmod * to operate on | |
1074 | * @name: pointer to the name of the MPU interrupt number to fetch (optional) | |
1075 | * @irq: pointer to an unsigned int to store the MPU IRQ number to | |
1076 | * | |
1077 | * Retrieve a MPU hardware IRQ line number named by @name associated | |
1078 | * with the IP block pointed to by @oh. The IRQ number will be filled | |
1079 | * into the address pointed to by @dma. When @name is non-null, the | |
1080 | * IRQ line number associated with the named entry will be returned. | |
1081 | * If @name is null, the first matching entry will be returned. Data | |
1082 | * order is not meaningful in hwmod data, so callers are strongly | |
1083 | * encouraged to use a non-null @name whenever possible to avoid | |
1084 | * unpredictable effects if hwmod data is later added that causes data | |
1085 | * ordering to change. Returns 0 upon success or a negative error | |
1086 | * code upon error. | |
1087 | */ | |
1088 | static int _get_mpu_irq_by_name(struct omap_hwmod *oh, const char *name, | |
1089 | unsigned int *irq) | |
1090 | { | |
1091 | int i; | |
1092 | bool found = false; | |
1093 | ||
1094 | if (!oh->mpu_irqs) | |
1095 | return -ENOENT; | |
1096 | ||
1097 | i = 0; | |
1098 | while (oh->mpu_irqs[i].irq != -1) { | |
1099 | if (name == oh->mpu_irqs[i].name || | |
1100 | !strcmp(name, oh->mpu_irqs[i].name)) { | |
1101 | found = true; | |
1102 | break; | |
1103 | } | |
1104 | i++; | |
1105 | } | |
1106 | ||
1107 | if (!found) | |
1108 | return -ENOENT; | |
1109 | ||
1110 | *irq = oh->mpu_irqs[i].irq; | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | /** | |
1116 | * _get_sdma_req_by_name - fetch SDMA request line ID by name | |
1117 | * @oh: struct omap_hwmod * to operate on | |
1118 | * @name: pointer to the name of the SDMA request line to fetch (optional) | |
1119 | * @dma: pointer to an unsigned int to store the request line ID to | |
1120 | * | |
1121 | * Retrieve an SDMA request line ID named by @name on the IP block | |
1122 | * pointed to by @oh. The ID will be filled into the address pointed | |
1123 | * to by @dma. When @name is non-null, the request line ID associated | |
1124 | * with the named entry will be returned. If @name is null, the first | |
1125 | * matching entry will be returned. Data order is not meaningful in | |
1126 | * hwmod data, so callers are strongly encouraged to use a non-null | |
1127 | * @name whenever possible to avoid unpredictable effects if hwmod | |
1128 | * data is later added that causes data ordering to change. Returns 0 | |
1129 | * upon success or a negative error code upon error. | |
1130 | */ | |
1131 | static int _get_sdma_req_by_name(struct omap_hwmod *oh, const char *name, | |
1132 | unsigned int *dma) | |
1133 | { | |
1134 | int i; | |
1135 | bool found = false; | |
1136 | ||
1137 | if (!oh->sdma_reqs) | |
1138 | return -ENOENT; | |
1139 | ||
1140 | i = 0; | |
1141 | while (oh->sdma_reqs[i].dma_req != -1) { | |
1142 | if (name == oh->sdma_reqs[i].name || | |
1143 | !strcmp(name, oh->sdma_reqs[i].name)) { | |
1144 | found = true; | |
1145 | break; | |
1146 | } | |
1147 | i++; | |
1148 | } | |
1149 | ||
1150 | if (!found) | |
1151 | return -ENOENT; | |
1152 | ||
1153 | *dma = oh->sdma_reqs[i].dma_req; | |
1154 | ||
1155 | return 0; | |
1156 | } | |
1157 | ||
1158 | /** | |
1159 | * _get_addr_space_by_name - fetch address space start & end by name | |
1160 | * @oh: struct omap_hwmod * to operate on | |
1161 | * @name: pointer to the name of the address space to fetch (optional) | |
1162 | * @pa_start: pointer to a u32 to store the starting address to | |
1163 | * @pa_end: pointer to a u32 to store the ending address to | |
1164 | * | |
1165 | * Retrieve address space start and end addresses for the IP block | |
1166 | * pointed to by @oh. The data will be filled into the addresses | |
1167 | * pointed to by @pa_start and @pa_end. When @name is non-null, the | |
1168 | * address space data associated with the named entry will be | |
1169 | * returned. If @name is null, the first matching entry will be | |
1170 | * returned. Data order is not meaningful in hwmod data, so callers | |
1171 | * are strongly encouraged to use a non-null @name whenever possible | |
1172 | * to avoid unpredictable effects if hwmod data is later added that | |
1173 | * causes data ordering to change. Returns 0 upon success or a | |
1174 | * negative error code upon error. | |
1175 | */ | |
1176 | static int _get_addr_space_by_name(struct omap_hwmod *oh, const char *name, | |
1177 | u32 *pa_start, u32 *pa_end) | |
1178 | { | |
1179 | int i, j; | |
1180 | struct omap_hwmod_ocp_if *os; | |
2221b5cd | 1181 | struct list_head *p = NULL; |
5e8370f1 PW |
1182 | bool found = false; |
1183 | ||
11cd4b94 | 1184 | p = oh->slave_ports.next; |
2221b5cd | 1185 | |
5d95dde7 PW |
1186 | i = 0; |
1187 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 1188 | os = _fetch_next_ocp_if(&p, &i); |
5e8370f1 PW |
1189 | |
1190 | if (!os->addr) | |
1191 | return -ENOENT; | |
1192 | ||
1193 | j = 0; | |
1194 | while (os->addr[j].pa_start != os->addr[j].pa_end) { | |
1195 | if (name == os->addr[j].name || | |
1196 | !strcmp(name, os->addr[j].name)) { | |
1197 | found = true; | |
1198 | break; | |
1199 | } | |
1200 | j++; | |
1201 | } | |
1202 | ||
1203 | if (found) | |
1204 | break; | |
1205 | } | |
1206 | ||
1207 | if (!found) | |
1208 | return -ENOENT; | |
1209 | ||
1210 | *pa_start = os->addr[j].pa_start; | |
1211 | *pa_end = os->addr[j].pa_end; | |
1212 | ||
1213 | return 0; | |
1214 | } | |
1215 | ||
63c85238 | 1216 | /** |
24dbc213 | 1217 | * _save_mpu_port_index - find and save the index to @oh's MPU port |
63c85238 PW |
1218 | * @oh: struct omap_hwmod * |
1219 | * | |
24dbc213 PW |
1220 | * Determines the array index of the OCP slave port that the MPU uses |
1221 | * to address the device, and saves it into the struct omap_hwmod. | |
1222 | * Intended to be called during hwmod registration only. No return | |
1223 | * value. | |
63c85238 | 1224 | */ |
24dbc213 | 1225 | static void __init _save_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 1226 | { |
24dbc213 | 1227 | struct omap_hwmod_ocp_if *os = NULL; |
11cd4b94 | 1228 | struct list_head *p; |
5d95dde7 | 1229 | int i = 0; |
63c85238 | 1230 | |
5d95dde7 | 1231 | if (!oh) |
24dbc213 PW |
1232 | return; |
1233 | ||
1234 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
63c85238 | 1235 | |
11cd4b94 | 1236 | p = oh->slave_ports.next; |
2221b5cd | 1237 | |
5d95dde7 | 1238 | while (i < oh->slaves_cnt) { |
11cd4b94 | 1239 | os = _fetch_next_ocp_if(&p, &i); |
63c85238 | 1240 | if (os->user & OCP_USER_MPU) { |
2221b5cd | 1241 | oh->_mpu_port = os; |
24dbc213 | 1242 | oh->_int_flags &= ~_HWMOD_NO_MPU_PORT; |
63c85238 PW |
1243 | break; |
1244 | } | |
1245 | } | |
1246 | ||
24dbc213 | 1247 | return; |
63c85238 PW |
1248 | } |
1249 | ||
2d6141ba PW |
1250 | /** |
1251 | * _find_mpu_rt_port - return omap_hwmod_ocp_if accessible by the MPU | |
1252 | * @oh: struct omap_hwmod * | |
1253 | * | |
1254 | * Given a pointer to a struct omap_hwmod record @oh, return a pointer | |
1255 | * to the struct omap_hwmod_ocp_if record that is used by the MPU to | |
1256 | * communicate with the IP block. This interface need not be directly | |
1257 | * connected to the MPU (and almost certainly is not), but is directly | |
1258 | * connected to the IP block represented by @oh. Returns a pointer | |
1259 | * to the struct omap_hwmod_ocp_if * upon success, or returns NULL upon | |
1260 | * error or if there does not appear to be a path from the MPU to this | |
1261 | * IP block. | |
1262 | */ | |
1263 | static struct omap_hwmod_ocp_if *_find_mpu_rt_port(struct omap_hwmod *oh) | |
1264 | { | |
1265 | if (!oh || oh->_int_flags & _HWMOD_NO_MPU_PORT || oh->slaves_cnt == 0) | |
1266 | return NULL; | |
1267 | ||
11cd4b94 | 1268 | return oh->_mpu_port; |
2d6141ba PW |
1269 | }; |
1270 | ||
63c85238 | 1271 | /** |
c9aafd23 | 1272 | * _find_mpu_rt_addr_space - return MPU register target address space for @oh |
63c85238 PW |
1273 | * @oh: struct omap_hwmod * |
1274 | * | |
c9aafd23 PW |
1275 | * Returns a pointer to the struct omap_hwmod_addr_space record representing |
1276 | * the register target MPU address space; or returns NULL upon error. | |
63c85238 | 1277 | */ |
c9aafd23 | 1278 | static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap_hwmod *oh) |
63c85238 PW |
1279 | { |
1280 | struct omap_hwmod_ocp_if *os; | |
1281 | struct omap_hwmod_addr_space *mem; | |
c9aafd23 | 1282 | int found = 0, i = 0; |
63c85238 | 1283 | |
2d6141ba | 1284 | os = _find_mpu_rt_port(oh); |
24dbc213 | 1285 | if (!os || !os->addr) |
78183f3f PW |
1286 | return NULL; |
1287 | ||
1288 | do { | |
1289 | mem = &os->addr[i++]; | |
1290 | if (mem->flags & ADDR_TYPE_RT) | |
63c85238 | 1291 | found = 1; |
78183f3f | 1292 | } while (!found && mem->pa_start != mem->pa_end); |
63c85238 | 1293 | |
c9aafd23 | 1294 | return (found) ? mem : NULL; |
63c85238 PW |
1295 | } |
1296 | ||
1297 | /** | |
74ff3a68 | 1298 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
1299 | * @oh: struct omap_hwmod * |
1300 | * | |
006c7f18 PW |
1301 | * Ensure that the OCP_SYSCONFIG register for the IP block represented |
1302 | * by @oh is set to indicate to the PRCM that the IP block is active. | |
1303 | * Usually this means placing the module into smart-idle mode and | |
1304 | * smart-standby, but if there is a bug in the automatic idle handling | |
1305 | * for the IP block, it may need to be placed into the force-idle or | |
1306 | * no-idle variants of these modes. No return value. | |
63c85238 | 1307 | */ |
74ff3a68 | 1308 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 1309 | { |
43b40992 | 1310 | u8 idlemode, sf; |
63c85238 | 1311 | u32 v; |
006c7f18 | 1312 | bool clkdm_act; |
63c85238 | 1313 | |
43b40992 | 1314 | if (!oh->class->sysc) |
63c85238 PW |
1315 | return; |
1316 | ||
613ad0e9 TK |
1317 | /* |
1318 | * Wait until reset has completed, this is needed as the IP | |
1319 | * block is reset automatically by hardware in some cases | |
1320 | * (off-mode for example), and the drivers require the | |
1321 | * IP to be ready when they access it | |
1322 | */ | |
1323 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1324 | _enable_optional_clocks(oh); | |
1325 | _wait_softreset_complete(oh); | |
1326 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1327 | _disable_optional_clocks(oh); | |
1328 | ||
63c85238 | 1329 | v = oh->_sysc_cache; |
43b40992 | 1330 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1331 | |
43b40992 | 1332 | if (sf & SYSC_HAS_SIDLEMODE) { |
006c7f18 PW |
1333 | clkdm_act = ((oh->clkdm && |
1334 | oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) || | |
1335 | (oh->_clk && oh->_clk->clkdm && | |
1336 | oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU)); | |
1337 | if (clkdm_act && !(oh->class->sysc->idlemodes & | |
1338 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1339 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1340 | else | |
1341 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? | |
1342 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
63c85238 PW |
1343 | _set_slave_idlemode(oh, idlemode, &v); |
1344 | } | |
1345 | ||
43b40992 | 1346 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1347 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1348 | idlemode = HWMOD_IDLEMODE_NO; | |
1349 | } else { | |
1350 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1351 | _enable_wakeup(oh, &v); | |
1352 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1353 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1354 | else | |
1355 | idlemode = HWMOD_IDLEMODE_SMART; | |
1356 | } | |
63c85238 PW |
1357 | _set_master_standbymode(oh, idlemode, &v); |
1358 | } | |
1359 | ||
a16b1f7f PW |
1360 | /* |
1361 | * XXX The clock framework should handle this, by | |
1362 | * calling into this code. But this must wait until the | |
1363 | * clock structures are tagged with omap_hwmod entries | |
1364 | */ | |
43b40992 PW |
1365 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1366 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
1367 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 | 1368 | |
9980ce53 RN |
1369 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1370 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
5a7ddcbd KH |
1371 | _enable_wakeup(oh, &v); |
1372 | ||
1373 | _write_sysconfig(v, oh); | |
78f26e87 HH |
1374 | |
1375 | /* | |
1376 | * Set the autoidle bit only after setting the smartidle bit | |
1377 | * Setting this will not have any impact on the other modules. | |
1378 | */ | |
1379 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1380 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1381 | 0 : 1; | |
1382 | _set_module_autoidle(oh, idlemode, &v); | |
1383 | _write_sysconfig(v, oh); | |
1384 | } | |
63c85238 PW |
1385 | } |
1386 | ||
1387 | /** | |
74ff3a68 | 1388 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1389 | * @oh: struct omap_hwmod * |
1390 | * | |
1391 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1392 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1393 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1394 | * configure it for smart-standby. No return value. | |
1395 | */ | |
74ff3a68 | 1396 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1397 | { |
43b40992 | 1398 | u8 idlemode, sf; |
63c85238 PW |
1399 | u32 v; |
1400 | ||
43b40992 | 1401 | if (!oh->class->sysc) |
63c85238 PW |
1402 | return; |
1403 | ||
1404 | v = oh->_sysc_cache; | |
43b40992 | 1405 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1406 | |
43b40992 | 1407 | if (sf & SYSC_HAS_SIDLEMODE) { |
006c7f18 PW |
1408 | /* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */ |
1409 | if (oh->flags & HWMOD_SWSUP_SIDLE || | |
1410 | !(oh->class->sysc->idlemodes & | |
1411 | (SIDLE_SMART | SIDLE_SMART_WKUP))) | |
1412 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1413 | else | |
1414 | idlemode = HWMOD_IDLEMODE_SMART; | |
63c85238 PW |
1415 | _set_slave_idlemode(oh, idlemode, &v); |
1416 | } | |
1417 | ||
43b40992 | 1418 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1419 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1420 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1421 | } else { | |
1422 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1423 | _enable_wakeup(oh, &v); | |
1424 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1425 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1426 | else | |
1427 | idlemode = HWMOD_IDLEMODE_SMART; | |
1428 | } | |
63c85238 PW |
1429 | _set_master_standbymode(oh, idlemode, &v); |
1430 | } | |
1431 | ||
86009eb3 BC |
1432 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1433 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
1434 | _enable_wakeup(oh, &v); | |
1435 | ||
63c85238 PW |
1436 | _write_sysconfig(v, oh); |
1437 | } | |
1438 | ||
1439 | /** | |
74ff3a68 | 1440 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1441 | * @oh: struct omap_hwmod * |
1442 | * | |
1443 | * Force the module into slave idle and master suspend. No return | |
1444 | * value. | |
1445 | */ | |
74ff3a68 | 1446 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1447 | { |
1448 | u32 v; | |
43b40992 | 1449 | u8 sf; |
63c85238 | 1450 | |
43b40992 | 1451 | if (!oh->class->sysc) |
63c85238 PW |
1452 | return; |
1453 | ||
1454 | v = oh->_sysc_cache; | |
43b40992 | 1455 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1456 | |
43b40992 | 1457 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1458 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1459 | ||
43b40992 | 1460 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1461 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1462 | ||
43b40992 | 1463 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1464 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1465 | |
1466 | _write_sysconfig(v, oh); | |
1467 | } | |
1468 | ||
1469 | /** | |
1470 | * _lookup - find an omap_hwmod by name | |
1471 | * @name: find an omap_hwmod by name | |
1472 | * | |
1473 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1474 | */ |
1475 | static struct omap_hwmod *_lookup(const char *name) | |
1476 | { | |
1477 | struct omap_hwmod *oh, *temp_oh; | |
1478 | ||
1479 | oh = NULL; | |
1480 | ||
1481 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1482 | if (!strcmp(name, temp_oh->name)) { | |
1483 | oh = temp_oh; | |
1484 | break; | |
1485 | } | |
1486 | } | |
1487 | ||
1488 | return oh; | |
1489 | } | |
868c157d | 1490 | |
6ae76997 BC |
1491 | /** |
1492 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1493 | * @oh: struct omap_hwmod * | |
1494 | * | |
1495 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1496 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
868c157d | 1497 | * Return -EINVAL if the clkdm_name lookup failed. |
6ae76997 BC |
1498 | */ |
1499 | static int _init_clkdm(struct omap_hwmod *oh) | |
1500 | { | |
3bb05dbf PW |
1501 | if (!oh->clkdm_name) { |
1502 | pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name); | |
6ae76997 | 1503 | return 0; |
3bb05dbf | 1504 | } |
6ae76997 | 1505 | |
6ae76997 BC |
1506 | oh->clkdm = clkdm_lookup(oh->clkdm_name); |
1507 | if (!oh->clkdm) { | |
1508 | pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", | |
1509 | oh->name, oh->clkdm_name); | |
1510 | return -EINVAL; | |
1511 | } | |
1512 | ||
1513 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1514 | oh->name, oh->clkdm_name); | |
1515 | ||
1516 | return 0; | |
1517 | } | |
63c85238 PW |
1518 | |
1519 | /** | |
6ae76997 BC |
1520 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1521 | * well the clockdomain. | |
63c85238 | 1522 | * @oh: struct omap_hwmod * |
97d60162 | 1523 | * @data: not used; pass NULL |
63c85238 | 1524 | * |
a2debdbd | 1525 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1526 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1527 | * success, or a negative error code on failure. | |
63c85238 | 1528 | */ |
97d60162 | 1529 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
1530 | { |
1531 | int ret = 0; | |
1532 | ||
48d54f3f PW |
1533 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1534 | return 0; | |
63c85238 PW |
1535 | |
1536 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1537 | ||
1538 | ret |= _init_main_clk(oh); | |
1539 | ret |= _init_interface_clks(oh); | |
1540 | ret |= _init_opt_clks(oh); | |
0a179eaa KH |
1541 | if (soc_ops.init_clkdm) |
1542 | ret |= soc_ops.init_clkdm(oh); | |
63c85238 | 1543 | |
f5c1f84b BC |
1544 | if (!ret) |
1545 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a BC |
1546 | else |
1547 | pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name); | |
63c85238 | 1548 | |
09c35f2f | 1549 | return ret; |
63c85238 PW |
1550 | } |
1551 | ||
5365efbe | 1552 | /** |
cc1226e7 | 1553 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1554 | * @oh: struct omap_hwmod * |
1555 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1556 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1557 | * |
1558 | * Return the bit position of the reset line that match the | |
1559 | * input name. Return -ENOENT if not found. | |
1560 | */ | |
a032d33b PW |
1561 | static int _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1562 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1563 | { |
1564 | int i; | |
1565 | ||
1566 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1567 | const char *rst_line = oh->rst_lines[i].name; | |
1568 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1569 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1570 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1571 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1572 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1573 | ohri->st_shift); | |
5365efbe | 1574 | |
cc1226e7 | 1575 | return 0; |
5365efbe BC |
1576 | } |
1577 | } | |
1578 | ||
1579 | return -ENOENT; | |
1580 | } | |
1581 | ||
1582 | /** | |
1583 | * _assert_hardreset - assert the HW reset line of submodules | |
1584 | * contained in the hwmod module. | |
1585 | * @oh: struct omap_hwmod * | |
1586 | * @name: name of the reset line to lookup and assert | |
1587 | * | |
b8249cf2 KH |
1588 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1589 | * reset line to be assert / deassert in order to enable fully the IP. | |
1590 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1591 | * asserting the hardreset line on the currently-booted SoC, or passes | |
1592 | * along the return value from _lookup_hardreset() or the SoC's | |
1593 | * assert_hardreset code. | |
5365efbe BC |
1594 | */ |
1595 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1596 | { | |
cc1226e7 | 1597 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1598 | int ret = -EINVAL; |
5365efbe BC |
1599 | |
1600 | if (!oh) | |
1601 | return -EINVAL; | |
1602 | ||
b8249cf2 KH |
1603 | if (!soc_ops.assert_hardreset) |
1604 | return -ENOSYS; | |
1605 | ||
cc1226e7 | 1606 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1607 | if (ret < 0) |
cc1226e7 | 1608 | return ret; |
5365efbe | 1609 | |
b8249cf2 KH |
1610 | ret = soc_ops.assert_hardreset(oh, &ohri); |
1611 | ||
1612 | return ret; | |
5365efbe BC |
1613 | } |
1614 | ||
1615 | /** | |
1616 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1617 | * in the hwmod module. | |
1618 | * @oh: struct omap_hwmod * | |
1619 | * @name: name of the reset line to look up and deassert | |
1620 | * | |
b8249cf2 KH |
1621 | * Some IP like dsp, ipu or iva contain processor that require an HW |
1622 | * reset line to be assert / deassert in order to enable fully the IP. | |
1623 | * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of | |
1624 | * deasserting the hardreset line on the currently-booted SoC, or passes | |
1625 | * along the return value from _lookup_hardreset() or the SoC's | |
1626 | * deassert_hardreset code. | |
5365efbe BC |
1627 | */ |
1628 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1629 | { | |
cc1226e7 | 1630 | struct omap_hwmod_rst_info ohri; |
b8249cf2 | 1631 | int ret = -EINVAL; |
e8e96dff | 1632 | int hwsup = 0; |
5365efbe BC |
1633 | |
1634 | if (!oh) | |
1635 | return -EINVAL; | |
1636 | ||
b8249cf2 KH |
1637 | if (!soc_ops.deassert_hardreset) |
1638 | return -ENOSYS; | |
1639 | ||
cc1226e7 | 1640 | ret = _lookup_hardreset(oh, name, &ohri); |
1641 | if (IS_ERR_VALUE(ret)) | |
1642 | return ret; | |
5365efbe | 1643 | |
e8e96dff ORL |
1644 | if (oh->clkdm) { |
1645 | /* | |
1646 | * A clockdomain must be in SW_SUP otherwise reset | |
1647 | * might not be completed. The clockdomain can be set | |
1648 | * in HW_AUTO only when the module become ready. | |
1649 | */ | |
1650 | hwsup = clkdm_in_hwsup(oh->clkdm); | |
1651 | ret = clkdm_hwmod_enable(oh->clkdm, oh); | |
1652 | if (ret) { | |
1653 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1654 | oh->name, oh->clkdm->name, ret); | |
1655 | return ret; | |
1656 | } | |
1657 | } | |
1658 | ||
1659 | _enable_clocks(oh); | |
1660 | if (soc_ops.enable_module) | |
1661 | soc_ops.enable_module(oh); | |
1662 | ||
b8249cf2 | 1663 | ret = soc_ops.deassert_hardreset(oh, &ohri); |
e8e96dff ORL |
1664 | |
1665 | if (soc_ops.disable_module) | |
1666 | soc_ops.disable_module(oh); | |
1667 | _disable_clocks(oh); | |
1668 | ||
cc1226e7 | 1669 | if (ret == -EBUSY) |
5365efbe BC |
1670 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); |
1671 | ||
e8e96dff ORL |
1672 | if (!ret) { |
1673 | /* | |
1674 | * Set the clockdomain to HW_AUTO, assuming that the | |
1675 | * previous state was HW_AUTO. | |
1676 | */ | |
1677 | if (oh->clkdm && hwsup) | |
1678 | clkdm_allow_idle(oh->clkdm); | |
1679 | } else { | |
1680 | if (oh->clkdm) | |
1681 | clkdm_hwmod_disable(oh->clkdm, oh); | |
1682 | } | |
1683 | ||
cc1226e7 | 1684 | return ret; |
5365efbe BC |
1685 | } |
1686 | ||
1687 | /** | |
1688 | * _read_hardreset - read the HW reset line state of submodules | |
1689 | * contained in the hwmod module | |
1690 | * @oh: struct omap_hwmod * | |
1691 | * @name: name of the reset line to look up and read | |
1692 | * | |
b8249cf2 KH |
1693 | * Return the state of the reset line. Returns -EINVAL if @oh is |
1694 | * null, -ENOSYS if we have no way of reading the hardreset line | |
1695 | * status on the currently-booted SoC, or passes along the return | |
1696 | * value from _lookup_hardreset() or the SoC's is_hardreset_asserted | |
1697 | * code. | |
5365efbe BC |
1698 | */ |
1699 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1700 | { | |
cc1226e7 | 1701 | struct omap_hwmod_rst_info ohri; |
a032d33b | 1702 | int ret = -EINVAL; |
5365efbe BC |
1703 | |
1704 | if (!oh) | |
1705 | return -EINVAL; | |
1706 | ||
b8249cf2 KH |
1707 | if (!soc_ops.is_hardreset_asserted) |
1708 | return -ENOSYS; | |
1709 | ||
cc1226e7 | 1710 | ret = _lookup_hardreset(oh, name, &ohri); |
a032d33b | 1711 | if (ret < 0) |
cc1226e7 | 1712 | return ret; |
5365efbe | 1713 | |
b8249cf2 | 1714 | return soc_ops.is_hardreset_asserted(oh, &ohri); |
5365efbe BC |
1715 | } |
1716 | ||
747834ab | 1717 | /** |
eb05f691 | 1718 | * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset |
747834ab PW |
1719 | * @oh: struct omap_hwmod * |
1720 | * | |
eb05f691 ORL |
1721 | * If all hardreset lines associated with @oh are asserted, then return true. |
1722 | * Otherwise, if part of @oh is out hardreset or if no hardreset lines | |
1723 | * associated with @oh are asserted, then return false. | |
747834ab | 1724 | * This function is used to avoid executing some parts of the IP block |
eb05f691 | 1725 | * enable/disable sequence if its hardreset line is set. |
747834ab | 1726 | */ |
eb05f691 | 1727 | static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh) |
747834ab | 1728 | { |
eb05f691 | 1729 | int i, rst_cnt = 0; |
747834ab PW |
1730 | |
1731 | if (oh->rst_lines_cnt == 0) | |
1732 | return false; | |
1733 | ||
1734 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1735 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
eb05f691 ORL |
1736 | rst_cnt++; |
1737 | ||
1738 | if (oh->rst_lines_cnt == rst_cnt) | |
1739 | return true; | |
747834ab PW |
1740 | |
1741 | return false; | |
1742 | } | |
1743 | ||
e9332b6e PW |
1744 | /** |
1745 | * _are_any_hardreset_lines_asserted - return true if any part of @oh is | |
1746 | * hard-reset | |
1747 | * @oh: struct omap_hwmod * | |
1748 | * | |
1749 | * If any hardreset lines associated with @oh are asserted, then | |
1750 | * return true. Otherwise, if no hardreset lines associated with @oh | |
1751 | * are asserted, or if @oh has no hardreset lines, then return false. | |
1752 | * This function is used to avoid executing some parts of the IP block | |
1753 | * enable/disable sequence if any hardreset line is set. | |
1754 | */ | |
1755 | static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh) | |
1756 | { | |
1757 | int rst_cnt = 0; | |
1758 | int i; | |
1759 | ||
1760 | for (i = 0; i < oh->rst_lines_cnt && rst_cnt == 0; i++) | |
1761 | if (_read_hardreset(oh, oh->rst_lines[i].name) > 0) | |
1762 | rst_cnt++; | |
1763 | ||
1764 | return (rst_cnt) ? true : false; | |
1765 | } | |
1766 | ||
747834ab PW |
1767 | /** |
1768 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
1769 | * @oh: struct omap_hwmod * | |
1770 | * | |
1771 | * Disable the PRCM module mode related to the hwmod @oh. | |
1772 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1773 | */ | |
1774 | static int _omap4_disable_module(struct omap_hwmod *oh) | |
1775 | { | |
1776 | int v; | |
1777 | ||
747834ab PW |
1778 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) |
1779 | return -EINVAL; | |
1780 | ||
eb05f691 ORL |
1781 | /* |
1782 | * Since integration code might still be doing something, only | |
1783 | * disable if all lines are under hardreset. | |
1784 | */ | |
e9332b6e | 1785 | if (_are_any_hardreset_lines_asserted(oh)) |
eb05f691 ORL |
1786 | return 0; |
1787 | ||
747834ab PW |
1788 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); |
1789 | ||
1790 | omap4_cminst_module_disable(oh->clkdm->prcm_partition, | |
1791 | oh->clkdm->cm_inst, | |
1792 | oh->clkdm->clkdm_offs, | |
1793 | oh->prcm.omap4.clkctrl_offs); | |
1794 | ||
747834ab PW |
1795 | v = _omap4_wait_target_disable(oh); |
1796 | if (v) | |
1797 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1798 | oh->name); | |
1799 | ||
1800 | return 0; | |
1801 | } | |
1802 | ||
1688bf19 VH |
1803 | /** |
1804 | * _am33xx_disable_module - enable CLKCTRL modulemode on AM33XX | |
1805 | * @oh: struct omap_hwmod * | |
1806 | * | |
1807 | * Disable the PRCM module mode related to the hwmod @oh. | |
1808 | * Return EINVAL if the modulemode is not supported and 0 in case of success. | |
1809 | */ | |
1810 | static int _am33xx_disable_module(struct omap_hwmod *oh) | |
1811 | { | |
1812 | int v; | |
1813 | ||
1814 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
1815 | return -EINVAL; | |
1816 | ||
1817 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); | |
1818 | ||
e9332b6e PW |
1819 | if (_are_any_hardreset_lines_asserted(oh)) |
1820 | return 0; | |
1821 | ||
1688bf19 VH |
1822 | am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs, |
1823 | oh->prcm.omap4.clkctrl_offs); | |
1824 | ||
1688bf19 VH |
1825 | v = _am33xx_wait_target_disable(oh); |
1826 | if (v) | |
1827 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
1828 | oh->name); | |
1829 | ||
1830 | return 0; | |
1831 | } | |
1832 | ||
63c85238 | 1833 | /** |
bd36179e | 1834 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1835 | * @oh: struct omap_hwmod * |
1836 | * | |
1837 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1838 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1839 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1840 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1841 | * |
1842 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1843 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1844 | * use the SYSCONFIG softreset bit to provide the status. |
1845 | * | |
bd36179e PW |
1846 | * Note that some IP like McBSP do have reset control but don't have |
1847 | * reset status. | |
63c85238 | 1848 | */ |
bd36179e | 1849 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1850 | { |
613ad0e9 | 1851 | u32 v; |
6f8b7ff5 | 1852 | int c = 0; |
96835af9 | 1853 | int ret = 0; |
63c85238 | 1854 | |
43b40992 | 1855 | if (!oh->class->sysc || |
2cb06814 | 1856 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1857 | return -ENOENT; |
63c85238 PW |
1858 | |
1859 | /* clocks must be on for this operation */ | |
1860 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
7852ec05 PW |
1861 | pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n", |
1862 | oh->name); | |
63c85238 PW |
1863 | return -EINVAL; |
1864 | } | |
1865 | ||
96835af9 BC |
1866 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1867 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1868 | _enable_optional_clocks(oh); | |
1869 | ||
bd36179e | 1870 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1871 | |
1872 | v = oh->_sysc_cache; | |
96835af9 BC |
1873 | ret = _set_softreset(oh, &v); |
1874 | if (ret) | |
1875 | goto dis_opt_clks; | |
63c85238 PW |
1876 | _write_sysconfig(v, oh); |
1877 | ||
d99de7f5 FGL |
1878 | if (oh->class->sysc->srst_udelay) |
1879 | udelay(oh->class->sysc->srst_udelay); | |
1880 | ||
613ad0e9 | 1881 | c = _wait_softreset_complete(oh); |
5365efbe | 1882 | if (c == MAX_MODULE_SOFTRESET_WAIT) |
76e5589e BC |
1883 | pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1884 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
63c85238 | 1885 | else |
5365efbe | 1886 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
63c85238 PW |
1887 | |
1888 | /* | |
1889 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1890 | * _wait_target_ready() or _reset() | |
1891 | */ | |
1892 | ||
96835af9 BC |
1893 | ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; |
1894 | ||
1895 | dis_opt_clks: | |
1896 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1897 | _disable_optional_clocks(oh); | |
1898 | ||
1899 | return ret; | |
63c85238 PW |
1900 | } |
1901 | ||
bd36179e PW |
1902 | /** |
1903 | * _reset - reset an omap_hwmod | |
1904 | * @oh: struct omap_hwmod * | |
1905 | * | |
30e105c0 PW |
1906 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1907 | * function pointer defined, then call it to reset the IP block, and | |
1908 | * pass along its return value to the caller. Otherwise, if the IP | |
1909 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1910 | * associated with it, call a function to reset the IP block via that | |
1911 | * method, and pass along the return value to the caller. Finally, if | |
1912 | * the IP block has some hardreset lines associated with it, assert | |
1913 | * all of those, but do _not_ deassert them. (This is because driver | |
1914 | * authors have expressed an apparent requirement to control the | |
1915 | * deassertion of the hardreset lines themselves.) | |
1916 | * | |
1917 | * The default software reset mechanism for most OMAP IP blocks is | |
1918 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1919 | * hwmods cannot be reset via this method. Some are not targets and | |
1920 | * therefore have no OCP header registers to access. Others (like the | |
1921 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
1922 | * rare cases, custom reset code can be supplied in the struct | |
6668546f KVA |
1923 | * omap_hwmod_class .reset function pointer. |
1924 | * | |
1925 | * _set_dmadisable() is called to set the DMADISABLE bit so that it | |
1926 | * does not prevent idling of the system. This is necessary for cases | |
1927 | * where ROMCODE/BOOTLOADER uses dma and transfers control to the | |
1928 | * kernel without disabling dma. | |
1929 | * | |
1930 | * Passes along the return value from either _ocp_softreset() or the | |
1931 | * custom reset function - these must return -EINVAL if the hwmod | |
1932 | * cannot be reset this way or if the hwmod is in the wrong state, | |
1933 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
bd36179e PW |
1934 | */ |
1935 | static int _reset(struct omap_hwmod *oh) | |
1936 | { | |
30e105c0 | 1937 | int i, r; |
bd36179e PW |
1938 | |
1939 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1940 | ||
30e105c0 PW |
1941 | if (oh->class->reset) { |
1942 | r = oh->class->reset(oh); | |
1943 | } else { | |
1944 | if (oh->rst_lines_cnt > 0) { | |
1945 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1946 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
1947 | return 0; | |
1948 | } else { | |
1949 | r = _ocp_softreset(oh); | |
1950 | if (r == -ENOENT) | |
1951 | r = 0; | |
1952 | } | |
1953 | } | |
1954 | ||
6668546f KVA |
1955 | _set_dmadisable(oh); |
1956 | ||
9c8b0ec7 | 1957 | /* |
30e105c0 PW |
1958 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
1959 | * softreset. The _enable() function should be split to avoid | |
1960 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 1961 | */ |
2800852a RN |
1962 | if (oh->class->sysc) { |
1963 | _update_sysc_cache(oh); | |
1964 | _enable_sysc(oh); | |
1965 | } | |
1966 | ||
30e105c0 | 1967 | return r; |
bd36179e PW |
1968 | } |
1969 | ||
5165882a VB |
1970 | /** |
1971 | * _reconfigure_io_chain - clear any I/O chain wakeups and reconfigure chain | |
1972 | * | |
1973 | * Call the appropriate PRM function to clear any logged I/O chain | |
1974 | * wakeups and to reconfigure the chain. This apparently needs to be | |
1975 | * done upon every mux change. Since hwmods can be concurrently | |
1976 | * enabled and idled, hold a spinlock around the I/O chain | |
1977 | * reconfiguration sequence. No return value. | |
1978 | * | |
1979 | * XXX When the PRM code is moved to drivers, this function can be removed, | |
1980 | * as the PRM infrastructure should abstract this. | |
1981 | */ | |
1982 | static void _reconfigure_io_chain(void) | |
1983 | { | |
1984 | unsigned long flags; | |
1985 | ||
1986 | spin_lock_irqsave(&io_chain_lock, flags); | |
1987 | ||
1988 | if (cpu_is_omap34xx() && omap3_has_io_chain_ctrl()) | |
1989 | omap3xxx_prm_reconfigure_io_chain(); | |
1990 | else if (cpu_is_omap44xx()) | |
1991 | omap44xx_prm_reconfigure_io_chain(); | |
1992 | ||
1993 | spin_unlock_irqrestore(&io_chain_lock, flags); | |
1994 | } | |
1995 | ||
63c85238 | 1996 | /** |
dc6d1cda | 1997 | * _enable - enable an omap_hwmod |
63c85238 PW |
1998 | * @oh: struct omap_hwmod * |
1999 | * | |
2000 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
2001 | * register target. Returns -EINVAL if the hwmod is in the wrong |
2002 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 2003 | */ |
dc6d1cda | 2004 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 2005 | { |
747834ab | 2006 | int r; |
665d0013 | 2007 | int hwsup = 0; |
63c85238 | 2008 | |
34617e2a BC |
2009 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
2010 | ||
aacf0941 | 2011 | /* |
64813c3f PW |
2012 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left in enabled |
2013 | * state at init. Now that someone is really trying to enable | |
2014 | * them, just ensure that the hwmod mux is set. | |
aacf0941 RN |
2015 | */ |
2016 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
2017 | /* | |
2018 | * If the caller has mux data populated, do the mux'ing | |
2019 | * which wouldn't have been done as part of the _enable() | |
2020 | * done during setup. | |
2021 | */ | |
2022 | if (oh->mux) | |
2023 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
2024 | ||
2025 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; | |
2026 | return 0; | |
2027 | } | |
2028 | ||
63c85238 PW |
2029 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
2030 | oh->_state != _HWMOD_STATE_IDLE && | |
2031 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
2032 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
2033 | oh->name); | |
63c85238 PW |
2034 | return -EINVAL; |
2035 | } | |
2036 | ||
31f62866 | 2037 | /* |
eb05f691 | 2038 | * If an IP block contains HW reset lines and all of them are |
747834ab PW |
2039 | * asserted, we let integration code associated with that |
2040 | * block handle the enable. We've received very little | |
2041 | * information on what those driver authors need, and until | |
2042 | * detailed information is provided and the driver code is | |
2043 | * posted to the public lists, this is probably the best we | |
2044 | * can do. | |
31f62866 | 2045 | */ |
eb05f691 | 2046 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab | 2047 | return 0; |
63c85238 | 2048 | |
665d0013 RN |
2049 | /* Mux pins for device runtime if populated */ |
2050 | if (oh->mux && (!oh->mux->enabled || | |
2051 | ((oh->_state == _HWMOD_STATE_IDLE) && | |
5165882a | 2052 | oh->mux->pads_dynamic))) { |
665d0013 | 2053 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); |
5165882a VB |
2054 | _reconfigure_io_chain(); |
2055 | } | |
665d0013 RN |
2056 | |
2057 | _add_initiator_dep(oh, mpu_oh); | |
34617e2a | 2058 | |
665d0013 RN |
2059 | if (oh->clkdm) { |
2060 | /* | |
2061 | * A clockdomain must be in SW_SUP before enabling | |
2062 | * completely the module. The clockdomain can be set | |
2063 | * in HW_AUTO only when the module become ready. | |
2064 | */ | |
b71c7217 PW |
2065 | hwsup = clkdm_in_hwsup(oh->clkdm) && |
2066 | !clkdm_missing_idle_reporting(oh->clkdm); | |
665d0013 RN |
2067 | r = clkdm_hwmod_enable(oh->clkdm, oh); |
2068 | if (r) { | |
2069 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
2070 | oh->name, oh->clkdm->name, r); | |
2071 | return r; | |
2072 | } | |
34617e2a | 2073 | } |
665d0013 RN |
2074 | |
2075 | _enable_clocks(oh); | |
9ebfd285 KH |
2076 | if (soc_ops.enable_module) |
2077 | soc_ops.enable_module(oh); | |
34617e2a | 2078 | |
8f6aa8ee KH |
2079 | r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) : |
2080 | -EINVAL; | |
665d0013 RN |
2081 | if (!r) { |
2082 | /* | |
2083 | * Set the clockdomain to HW_AUTO only if the target is ready, | |
2084 | * assuming that the previous state was HW_AUTO | |
2085 | */ | |
2086 | if (oh->clkdm && hwsup) | |
2087 | clkdm_allow_idle(oh->clkdm); | |
2088 | ||
2089 | oh->_state = _HWMOD_STATE_ENABLED; | |
2090 | ||
2091 | /* Access the sysconfig only if the target is ready */ | |
2092 | if (oh->class->sysc) { | |
2093 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
2094 | _update_sysc_cache(oh); | |
2095 | _enable_sysc(oh); | |
2096 | } | |
2097 | } else { | |
471a009b | 2098 | _omap4_disable_module(oh); |
665d0013 RN |
2099 | _disable_clocks(oh); |
2100 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | |
2101 | oh->name, r); | |
34617e2a | 2102 | |
665d0013 RN |
2103 | if (oh->clkdm) |
2104 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
2105 | } |
2106 | ||
63c85238 PW |
2107 | return r; |
2108 | } | |
2109 | ||
2110 | /** | |
dc6d1cda | 2111 | * _idle - idle an omap_hwmod |
63c85238 PW |
2112 | * @oh: struct omap_hwmod * |
2113 | * | |
2114 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
2115 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
2116 | * state or returns 0. | |
63c85238 | 2117 | */ |
dc6d1cda | 2118 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 2119 | { |
34617e2a BC |
2120 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
2121 | ||
63c85238 | 2122 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
2123 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
2124 | oh->name); | |
63c85238 PW |
2125 | return -EINVAL; |
2126 | } | |
2127 | ||
eb05f691 | 2128 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab PW |
2129 | return 0; |
2130 | ||
43b40992 | 2131 | if (oh->class->sysc) |
74ff3a68 | 2132 | _idle_sysc(oh); |
63c85238 | 2133 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 | 2134 | |
9ebfd285 KH |
2135 | if (soc_ops.disable_module) |
2136 | soc_ops.disable_module(oh); | |
bfc141e3 | 2137 | |
45c38252 BC |
2138 | /* |
2139 | * The module must be in idle mode before disabling any parents | |
2140 | * clocks. Otherwise, the parent clock might be disabled before | |
2141 | * the module transition is done, and thus will prevent the | |
2142 | * transition to complete properly. | |
2143 | */ | |
2144 | _disable_clocks(oh); | |
665d0013 RN |
2145 | if (oh->clkdm) |
2146 | clkdm_hwmod_disable(oh->clkdm, oh); | |
63c85238 | 2147 | |
8d9af88f | 2148 | /* Mux pins for device idle if populated */ |
5165882a | 2149 | if (oh->mux && oh->mux->pads_dynamic) { |
8d9af88f | 2150 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); |
5165882a VB |
2151 | _reconfigure_io_chain(); |
2152 | } | |
8d9af88f | 2153 | |
63c85238 PW |
2154 | oh->_state = _HWMOD_STATE_IDLE; |
2155 | ||
2156 | return 0; | |
2157 | } | |
2158 | ||
9599217a KVA |
2159 | /** |
2160 | * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit | |
2161 | * @oh: struct omap_hwmod * | |
2162 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
2163 | * | |
2164 | * Sets the IP block's OCP autoidle bit in hardware, and updates our | |
2165 | * local copy. Intended to be used by drivers that require | |
2166 | * direct manipulation of the AUTOIDLE bits. | |
2167 | * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes | |
2168 | * along the return value from _set_module_autoidle(). | |
2169 | * | |
2170 | * Any users of this function should be scrutinized carefully. | |
2171 | */ | |
2172 | int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) | |
2173 | { | |
2174 | u32 v; | |
2175 | int retval = 0; | |
2176 | unsigned long flags; | |
2177 | ||
2178 | if (!oh || oh->_state != _HWMOD_STATE_ENABLED) | |
2179 | return -EINVAL; | |
2180 | ||
2181 | spin_lock_irqsave(&oh->_lock, flags); | |
2182 | ||
2183 | v = oh->_sysc_cache; | |
2184 | ||
2185 | retval = _set_module_autoidle(oh, autoidle, &v); | |
2186 | ||
2187 | if (!retval) | |
2188 | _write_sysconfig(v, oh); | |
2189 | ||
2190 | spin_unlock_irqrestore(&oh->_lock, flags); | |
2191 | ||
2192 | return retval; | |
2193 | } | |
2194 | ||
63c85238 PW |
2195 | /** |
2196 | * _shutdown - shutdown an omap_hwmod | |
2197 | * @oh: struct omap_hwmod * | |
2198 | * | |
2199 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
2200 | * used for the hwmod is removed or unloaded or if the driver is not | |
2201 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
2202 | * state or returns 0. | |
2203 | */ | |
2204 | static int _shutdown(struct omap_hwmod *oh) | |
2205 | { | |
9c8b0ec7 | 2206 | int ret, i; |
e4dc8f50 PW |
2207 | u8 prev_state; |
2208 | ||
63c85238 PW |
2209 | if (oh->_state != _HWMOD_STATE_IDLE && |
2210 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
2211 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
2212 | oh->name); | |
63c85238 PW |
2213 | return -EINVAL; |
2214 | } | |
2215 | ||
eb05f691 | 2216 | if (_are_all_hardreset_lines_asserted(oh)) |
747834ab PW |
2217 | return 0; |
2218 | ||
63c85238 PW |
2219 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); |
2220 | ||
e4dc8f50 PW |
2221 | if (oh->class->pre_shutdown) { |
2222 | prev_state = oh->_state; | |
2223 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2224 | _enable(oh); |
e4dc8f50 PW |
2225 | ret = oh->class->pre_shutdown(oh); |
2226 | if (ret) { | |
2227 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2228 | _idle(oh); |
e4dc8f50 PW |
2229 | return ret; |
2230 | } | |
2231 | } | |
2232 | ||
6481c73c MV |
2233 | if (oh->class->sysc) { |
2234 | if (oh->_state == _HWMOD_STATE_IDLE) | |
2235 | _enable(oh); | |
74ff3a68 | 2236 | _shutdown_sysc(oh); |
6481c73c | 2237 | } |
5365efbe | 2238 | |
3827f949 BC |
2239 | /* clocks and deps are already disabled in idle */ |
2240 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
2241 | _del_initiator_dep(oh, mpu_oh); | |
2242 | /* XXX what about the other system initiators here? dma, dsp */ | |
9ebfd285 KH |
2243 | if (soc_ops.disable_module) |
2244 | soc_ops.disable_module(oh); | |
45c38252 | 2245 | _disable_clocks(oh); |
665d0013 RN |
2246 | if (oh->clkdm) |
2247 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 2248 | } |
63c85238 PW |
2249 | /* XXX Should this code also force-disable the optional clocks? */ |
2250 | ||
9c8b0ec7 PW |
2251 | for (i = 0; i < oh->rst_lines_cnt; i++) |
2252 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 2253 | |
8d9af88f TL |
2254 | /* Mux pins to safe mode or use populated off mode values */ |
2255 | if (oh->mux) | |
2256 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); | |
63c85238 PW |
2257 | |
2258 | oh->_state = _HWMOD_STATE_DISABLED; | |
2259 | ||
2260 | return 0; | |
2261 | } | |
2262 | ||
381d033a PW |
2263 | /** |
2264 | * _init_mpu_rt_base - populate the virtual address for a hwmod | |
2265 | * @oh: struct omap_hwmod * to locate the virtual address | |
2266 | * | |
2267 | * Cache the virtual address used by the MPU to access this IP block's | |
2268 | * registers. This address is needed early so the OCP registers that | |
2269 | * are part of the device's address space can be ioremapped properly. | |
2270 | * No return value. | |
2271 | */ | |
2272 | static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data) | |
2273 | { | |
c9aafd23 PW |
2274 | struct omap_hwmod_addr_space *mem; |
2275 | void __iomem *va_start; | |
2276 | ||
2277 | if (!oh) | |
2278 | return; | |
2279 | ||
2221b5cd PW |
2280 | _save_mpu_port_index(oh); |
2281 | ||
381d033a PW |
2282 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
2283 | return; | |
2284 | ||
c9aafd23 PW |
2285 | mem = _find_mpu_rt_addr_space(oh); |
2286 | if (!mem) { | |
2287 | pr_debug("omap_hwmod: %s: no MPU register target found\n", | |
2288 | oh->name); | |
2289 | return; | |
2290 | } | |
2291 | ||
2292 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
2293 | if (!va_start) { | |
2294 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
2295 | return; | |
2296 | } | |
2297 | ||
2298 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", | |
2299 | oh->name, va_start); | |
2300 | ||
2301 | oh->_mpu_rt_va = va_start; | |
381d033a PW |
2302 | } |
2303 | ||
2304 | /** | |
2305 | * _init - initialize internal data for the hwmod @oh | |
2306 | * @oh: struct omap_hwmod * | |
2307 | * @n: (unused) | |
2308 | * | |
2309 | * Look up the clocks and the address space used by the MPU to access | |
2310 | * registers belonging to the hwmod @oh. @oh must already be | |
2311 | * registered at this point. This is the first of two phases for | |
2312 | * hwmod initialization. Code called here does not touch any hardware | |
2313 | * registers, it simply prepares internal data structures. Returns 0 | |
2314 | * upon success or if the hwmod isn't registered, or -EINVAL upon | |
2315 | * failure. | |
2316 | */ | |
2317 | static int __init _init(struct omap_hwmod *oh, void *data) | |
2318 | { | |
2319 | int r; | |
2320 | ||
2321 | if (oh->_state != _HWMOD_STATE_REGISTERED) | |
2322 | return 0; | |
2323 | ||
2324 | _init_mpu_rt_base(oh, NULL); | |
2325 | ||
2326 | r = _init_clocks(oh, NULL); | |
2327 | if (IS_ERR_VALUE(r)) { | |
2328 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name); | |
2329 | return -EINVAL; | |
2330 | } | |
2331 | ||
2332 | oh->_state = _HWMOD_STATE_INITIALIZED; | |
2333 | ||
2334 | return 0; | |
2335 | } | |
2336 | ||
63c85238 | 2337 | /** |
64813c3f | 2338 | * _setup_iclk_autoidle - configure an IP block's interface clocks |
63c85238 PW |
2339 | * @oh: struct omap_hwmod * |
2340 | * | |
64813c3f PW |
2341 | * Set up the module's interface clocks. XXX This function is still mostly |
2342 | * a stub; implementing this properly requires iclk autoidle usecounting in | |
2343 | * the clock code. No return value. | |
63c85238 | 2344 | */ |
64813c3f | 2345 | static void __init _setup_iclk_autoidle(struct omap_hwmod *oh) |
63c85238 | 2346 | { |
5d95dde7 | 2347 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 2348 | struct list_head *p; |
5d95dde7 | 2349 | int i = 0; |
381d033a | 2350 | if (oh->_state != _HWMOD_STATE_INITIALIZED) |
64813c3f | 2351 | return; |
48d54f3f | 2352 | |
11cd4b94 | 2353 | p = oh->slave_ports.next; |
63c85238 | 2354 | |
5d95dde7 | 2355 | while (i < oh->slaves_cnt) { |
11cd4b94 | 2356 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 | 2357 | if (!os->_clk) |
64813c3f | 2358 | continue; |
63c85238 | 2359 | |
64813c3f PW |
2360 | if (os->flags & OCPIF_SWSUP_IDLE) { |
2361 | /* XXX omap_iclk_deny_idle(c); */ | |
2362 | } else { | |
2363 | /* XXX omap_iclk_allow_idle(c); */ | |
5d95dde7 | 2364 | clk_enable(os->_clk); |
63c85238 PW |
2365 | } |
2366 | } | |
2367 | ||
64813c3f PW |
2368 | return; |
2369 | } | |
2370 | ||
2371 | /** | |
2372 | * _setup_reset - reset an IP block during the setup process | |
2373 | * @oh: struct omap_hwmod * | |
2374 | * | |
2375 | * Reset the IP block corresponding to the hwmod @oh during the setup | |
2376 | * process. The IP block is first enabled so it can be successfully | |
2377 | * reset. Returns 0 upon success or a negative error code upon | |
2378 | * failure. | |
2379 | */ | |
2380 | static int __init _setup_reset(struct omap_hwmod *oh) | |
2381 | { | |
2382 | int r; | |
2383 | ||
2384 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2385 | return -EINVAL; | |
63c85238 | 2386 | |
747834ab PW |
2387 | if (oh->rst_lines_cnt == 0) { |
2388 | r = _enable(oh); | |
2389 | if (r) { | |
2390 | pr_warning("omap_hwmod: %s: cannot be enabled for reset (%d)\n", | |
2391 | oh->name, oh->_state); | |
2392 | return -EINVAL; | |
2393 | } | |
9a23dfe1 | 2394 | } |
63c85238 | 2395 | |
2800852a | 2396 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
64813c3f PW |
2397 | r = _reset(oh); |
2398 | ||
2399 | return r; | |
2400 | } | |
2401 | ||
2402 | /** | |
2403 | * _setup_postsetup - transition to the appropriate state after _setup | |
2404 | * @oh: struct omap_hwmod * | |
2405 | * | |
2406 | * Place an IP block represented by @oh into a "post-setup" state -- | |
2407 | * either IDLE, ENABLED, or DISABLED. ("post-setup" simply means that | |
2408 | * this function is called at the end of _setup().) The postsetup | |
2409 | * state for an IP block can be changed by calling | |
2410 | * omap_hwmod_enter_postsetup_state() early in the boot process, | |
2411 | * before one of the omap_hwmod_setup*() functions are called for the | |
2412 | * IP block. | |
2413 | * | |
2414 | * The IP block stays in this state until a PM runtime-based driver is | |
2415 | * loaded for that IP block. A post-setup state of IDLE is | |
2416 | * appropriate for almost all IP blocks with runtime PM-enabled | |
2417 | * drivers, since those drivers are able to enable the IP block. A | |
2418 | * post-setup state of ENABLED is appropriate for kernels with PM | |
2419 | * runtime disabled. The DISABLED state is appropriate for unusual IP | |
2420 | * blocks such as the MPU WDTIMER on kernels without WDTIMER drivers | |
2421 | * included, since the WDTIMER starts running on reset and will reset | |
2422 | * the MPU if left active. | |
2423 | * | |
2424 | * This post-setup mechanism is deprecated. Once all of the OMAP | |
2425 | * drivers have been converted to use PM runtime, and all of the IP | |
2426 | * block data and interconnect data is available to the hwmod code, it | |
2427 | * should be possible to replace this mechanism with a "lazy reset" | |
2428 | * arrangement. In a "lazy reset" setup, each IP block is enabled | |
2429 | * when the driver first probes, then all remaining IP blocks without | |
2430 | * drivers are either shut down or enabled after the drivers have | |
2431 | * loaded. However, this cannot take place until the above | |
2432 | * preconditions have been met, since otherwise the late reset code | |
2433 | * has no way of knowing which IP blocks are in use by drivers, and | |
2434 | * which ones are unused. | |
2435 | * | |
2436 | * No return value. | |
2437 | */ | |
2438 | static void __init _setup_postsetup(struct omap_hwmod *oh) | |
2439 | { | |
2440 | u8 postsetup_state; | |
2441 | ||
2442 | if (oh->rst_lines_cnt > 0) | |
2443 | return; | |
76e5589e | 2444 | |
2092e5cc PW |
2445 | postsetup_state = oh->_postsetup_state; |
2446 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
2447 | postsetup_state = _HWMOD_STATE_ENABLED; | |
2448 | ||
2449 | /* | |
2450 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
2451 | * it should be set by the core code as a runtime flag during startup | |
2452 | */ | |
2453 | if ((oh->flags & HWMOD_INIT_NO_IDLE) && | |
aacf0941 RN |
2454 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
2455 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 2456 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 2457 | } |
2092e5cc PW |
2458 | |
2459 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 2460 | _idle(oh); |
2092e5cc PW |
2461 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
2462 | _shutdown(oh); | |
2463 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
2464 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
2465 | oh->name, postsetup_state); | |
63c85238 | 2466 | |
64813c3f PW |
2467 | return; |
2468 | } | |
2469 | ||
2470 | /** | |
2471 | * _setup - prepare IP block hardware for use | |
2472 | * @oh: struct omap_hwmod * | |
2473 | * @n: (unused, pass NULL) | |
2474 | * | |
2475 | * Configure the IP block represented by @oh. This may include | |
2476 | * enabling the IP block, resetting it, and placing it into a | |
2477 | * post-setup state, depending on the type of IP block and applicable | |
2478 | * flags. IP blocks are reset to prevent any previous configuration | |
2479 | * by the bootloader or previous operating system from interfering | |
2480 | * with power management or other parts of the system. The reset can | |
2481 | * be avoided; see omap_hwmod_no_setup_reset(). This is the second of | |
2482 | * two phases for hwmod initialization. Code called here generally | |
2483 | * affects the IP block hardware, or system integration hardware | |
2484 | * associated with the IP block. Returns 0. | |
2485 | */ | |
2486 | static int __init _setup(struct omap_hwmod *oh, void *data) | |
2487 | { | |
2488 | if (oh->_state != _HWMOD_STATE_INITIALIZED) | |
2489 | return 0; | |
2490 | ||
2491 | _setup_iclk_autoidle(oh); | |
2492 | ||
2493 | if (!_setup_reset(oh)) | |
2494 | _setup_postsetup(oh); | |
2495 | ||
63c85238 PW |
2496 | return 0; |
2497 | } | |
2498 | ||
63c85238 | 2499 | /** |
0102b627 | 2500 | * _register - register a struct omap_hwmod |
63c85238 PW |
2501 | * @oh: struct omap_hwmod * |
2502 | * | |
43b40992 PW |
2503 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
2504 | * already has been registered by the same name; -EINVAL if the | |
2505 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
2506 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
2507 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
2508 | * success. | |
63c85238 PW |
2509 | * |
2510 | * XXX The data should be copied into bootmem, so the original data | |
2511 | * should be marked __initdata and freed after init. This would allow | |
2512 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
2513 | * that the copy process would be relatively complex due to the large number | |
2514 | * of substructures. | |
2515 | */ | |
01592df9 | 2516 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 2517 | { |
43b40992 PW |
2518 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
2519 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
2520 | return -EINVAL; |
2521 | ||
63c85238 PW |
2522 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
2523 | ||
ce35b244 BC |
2524 | if (_lookup(oh->name)) |
2525 | return -EEXIST; | |
63c85238 | 2526 | |
63c85238 PW |
2527 | list_add_tail(&oh->node, &omap_hwmod_list); |
2528 | ||
2221b5cd PW |
2529 | INIT_LIST_HEAD(&oh->master_ports); |
2530 | INIT_LIST_HEAD(&oh->slave_ports); | |
dc6d1cda | 2531 | spin_lock_init(&oh->_lock); |
2092e5cc | 2532 | |
63c85238 PW |
2533 | oh->_state = _HWMOD_STATE_REGISTERED; |
2534 | ||
569edd70 PW |
2535 | /* |
2536 | * XXX Rather than doing a strcmp(), this should test a flag | |
2537 | * set in the hwmod data, inserted by the autogenerator code. | |
2538 | */ | |
2539 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
2540 | mpu_oh = oh; | |
63c85238 | 2541 | |
569edd70 | 2542 | return 0; |
63c85238 PW |
2543 | } |
2544 | ||
2221b5cd PW |
2545 | /** |
2546 | * _alloc_links - return allocated memory for hwmod links | |
2547 | * @ml: pointer to a struct omap_hwmod_link * for the master link | |
2548 | * @sl: pointer to a struct omap_hwmod_link * for the slave link | |
2549 | * | |
2550 | * Return pointers to two struct omap_hwmod_link records, via the | |
2551 | * addresses pointed to by @ml and @sl. Will first attempt to return | |
2552 | * memory allocated as part of a large initial block, but if that has | |
2553 | * been exhausted, will allocate memory itself. Since ideally this | |
2554 | * second allocation path will never occur, the number of these | |
2555 | * 'supplemental' allocations will be logged when debugging is | |
2556 | * enabled. Returns 0. | |
2557 | */ | |
2558 | static int __init _alloc_links(struct omap_hwmod_link **ml, | |
2559 | struct omap_hwmod_link **sl) | |
2560 | { | |
2561 | unsigned int sz; | |
2562 | ||
2563 | if ((free_ls + LINKS_PER_OCP_IF) <= max_ls) { | |
2564 | *ml = &linkspace[free_ls++]; | |
2565 | *sl = &linkspace[free_ls++]; | |
2566 | return 0; | |
2567 | } | |
2568 | ||
2569 | sz = sizeof(struct omap_hwmod_link) * LINKS_PER_OCP_IF; | |
2570 | ||
2571 | *sl = NULL; | |
2572 | *ml = alloc_bootmem(sz); | |
2573 | ||
2574 | memset(*ml, 0, sz); | |
2575 | ||
2576 | *sl = (void *)(*ml) + sizeof(struct omap_hwmod_link); | |
2577 | ||
2578 | ls_supp++; | |
2579 | pr_debug("omap_hwmod: supplemental link allocations needed: %d\n", | |
2580 | ls_supp * LINKS_PER_OCP_IF); | |
2581 | ||
2582 | return 0; | |
2583 | }; | |
2584 | ||
2585 | /** | |
2586 | * _add_link - add an interconnect between two IP blocks | |
2587 | * @oi: pointer to a struct omap_hwmod_ocp_if record | |
2588 | * | |
2589 | * Add struct omap_hwmod_link records connecting the master IP block | |
2590 | * specified in @oi->master to @oi, and connecting the slave IP block | |
2591 | * specified in @oi->slave to @oi. This code is assumed to run before | |
2592 | * preemption or SMP has been enabled, thus avoiding the need for | |
2593 | * locking in this code. Changes to this assumption will require | |
2594 | * additional locking. Returns 0. | |
2595 | */ | |
2596 | static int __init _add_link(struct omap_hwmod_ocp_if *oi) | |
2597 | { | |
2598 | struct omap_hwmod_link *ml, *sl; | |
2599 | ||
2600 | pr_debug("omap_hwmod: %s -> %s: adding link\n", oi->master->name, | |
2601 | oi->slave->name); | |
2602 | ||
2603 | _alloc_links(&ml, &sl); | |
2604 | ||
2605 | ml->ocp_if = oi; | |
2606 | INIT_LIST_HEAD(&ml->node); | |
2607 | list_add(&ml->node, &oi->master->master_ports); | |
2608 | oi->master->masters_cnt++; | |
2609 | ||
2610 | sl->ocp_if = oi; | |
2611 | INIT_LIST_HEAD(&sl->node); | |
2612 | list_add(&sl->node, &oi->slave->slave_ports); | |
2613 | oi->slave->slaves_cnt++; | |
2614 | ||
2615 | return 0; | |
2616 | } | |
2617 | ||
2618 | /** | |
2619 | * _register_link - register a struct omap_hwmod_ocp_if | |
2620 | * @oi: struct omap_hwmod_ocp_if * | |
2621 | * | |
2622 | * Registers the omap_hwmod_ocp_if record @oi. Returns -EEXIST if it | |
2623 | * has already been registered; -EINVAL if @oi is NULL or if the | |
2624 | * record pointed to by @oi is missing required fields; or 0 upon | |
2625 | * success. | |
2626 | * | |
2627 | * XXX The data should be copied into bootmem, so the original data | |
2628 | * should be marked __initdata and freed after init. This would allow | |
2629 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. | |
2630 | */ | |
2631 | static int __init _register_link(struct omap_hwmod_ocp_if *oi) | |
2632 | { | |
2633 | if (!oi || !oi->master || !oi->slave || !oi->user) | |
2634 | return -EINVAL; | |
2635 | ||
2636 | if (oi->_int_flags & _OCPIF_INT_FLAGS_REGISTERED) | |
2637 | return -EEXIST; | |
2638 | ||
2639 | pr_debug("omap_hwmod: registering link from %s to %s\n", | |
2640 | oi->master->name, oi->slave->name); | |
2641 | ||
2642 | /* | |
2643 | * Register the connected hwmods, if they haven't been | |
2644 | * registered already | |
2645 | */ | |
2646 | if (oi->master->_state != _HWMOD_STATE_REGISTERED) | |
2647 | _register(oi->master); | |
2648 | ||
2649 | if (oi->slave->_state != _HWMOD_STATE_REGISTERED) | |
2650 | _register(oi->slave); | |
2651 | ||
2652 | _add_link(oi); | |
2653 | ||
2654 | oi->_int_flags |= _OCPIF_INT_FLAGS_REGISTERED; | |
2655 | ||
2656 | return 0; | |
2657 | } | |
2658 | ||
2659 | /** | |
2660 | * _alloc_linkspace - allocate large block of hwmod links | |
2661 | * @ois: pointer to an array of struct omap_hwmod_ocp_if records to count | |
2662 | * | |
2663 | * Allocate a large block of struct omap_hwmod_link records. This | |
2664 | * improves boot time significantly by avoiding the need to allocate | |
2665 | * individual records one by one. If the number of records to | |
2666 | * allocate in the block hasn't been manually specified, this function | |
2667 | * will count the number of struct omap_hwmod_ocp_if records in @ois | |
2668 | * and use that to determine the allocation size. For SoC families | |
2669 | * that require multiple list registrations, such as OMAP3xxx, this | |
2670 | * estimation process isn't optimal, so manual estimation is advised | |
2671 | * in those cases. Returns -EEXIST if the allocation has already occurred | |
2672 | * or 0 upon success. | |
2673 | */ | |
2674 | static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois) | |
2675 | { | |
2676 | unsigned int i = 0; | |
2677 | unsigned int sz; | |
2678 | ||
2679 | if (linkspace) { | |
2680 | WARN(1, "linkspace already allocated\n"); | |
2681 | return -EEXIST; | |
2682 | } | |
2683 | ||
2684 | if (max_ls == 0) | |
2685 | while (ois[i++]) | |
2686 | max_ls += LINKS_PER_OCP_IF; | |
2687 | ||
2688 | sz = sizeof(struct omap_hwmod_link) * max_ls; | |
2689 | ||
2690 | pr_debug("omap_hwmod: %s: allocating %d byte linkspace (%d links)\n", | |
2691 | __func__, sz, max_ls); | |
2692 | ||
2693 | linkspace = alloc_bootmem(sz); | |
2694 | ||
2695 | memset(linkspace, 0, sz); | |
2696 | ||
2697 | return 0; | |
2698 | } | |
0102b627 | 2699 | |
8f6aa8ee KH |
2700 | /* Static functions intended only for use in soc_ops field function pointers */ |
2701 | ||
2702 | /** | |
2703 | * _omap2_wait_target_ready - wait for a module to leave slave idle | |
2704 | * @oh: struct omap_hwmod * | |
2705 | * | |
2706 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2707 | * does not have an IDLEST bit or if the module successfully leaves | |
2708 | * slave idle; otherwise, pass along the return value of the | |
2709 | * appropriate *_cm*_wait_module_ready() function. | |
2710 | */ | |
2711 | static int _omap2_wait_target_ready(struct omap_hwmod *oh) | |
2712 | { | |
2713 | if (!oh) | |
2714 | return -EINVAL; | |
2715 | ||
2716 | if (oh->flags & HWMOD_NO_IDLEST) | |
2717 | return 0; | |
2718 | ||
2719 | if (!_find_mpu_rt_port(oh)) | |
2720 | return 0; | |
2721 | ||
2722 | /* XXX check module SIDLEMODE, hardreset status, enabled clocks */ | |
2723 | ||
2724 | return omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, | |
2725 | oh->prcm.omap2.idlest_reg_id, | |
2726 | oh->prcm.omap2.idlest_idle_bit); | |
2727 | } | |
2728 | ||
2729 | /** | |
2730 | * _omap4_wait_target_ready - wait for a module to leave slave idle | |
2731 | * @oh: struct omap_hwmod * | |
2732 | * | |
2733 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2734 | * does not have an IDLEST bit or if the module successfully leaves | |
2735 | * slave idle; otherwise, pass along the return value of the | |
2736 | * appropriate *_cm*_wait_module_ready() function. | |
2737 | */ | |
2738 | static int _omap4_wait_target_ready(struct omap_hwmod *oh) | |
2739 | { | |
2b026d13 | 2740 | if (!oh) |
8f6aa8ee KH |
2741 | return -EINVAL; |
2742 | ||
2b026d13 | 2743 | if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm) |
8f6aa8ee KH |
2744 | return 0; |
2745 | ||
2746 | if (!_find_mpu_rt_port(oh)) | |
2747 | return 0; | |
2748 | ||
2749 | /* XXX check module SIDLEMODE, hardreset status */ | |
2750 | ||
2751 | return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, | |
2752 | oh->clkdm->cm_inst, | |
2753 | oh->clkdm->clkdm_offs, | |
2754 | oh->prcm.omap4.clkctrl_offs); | |
2755 | } | |
2756 | ||
1688bf19 VH |
2757 | /** |
2758 | * _am33xx_wait_target_ready - wait for a module to leave slave idle | |
2759 | * @oh: struct omap_hwmod * | |
2760 | * | |
2761 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
2762 | * does not have an IDLEST bit or if the module successfully leaves | |
2763 | * slave idle; otherwise, pass along the return value of the | |
2764 | * appropriate *_cm*_wait_module_ready() function. | |
2765 | */ | |
2766 | static int _am33xx_wait_target_ready(struct omap_hwmod *oh) | |
2767 | { | |
2768 | if (!oh || !oh->clkdm) | |
2769 | return -EINVAL; | |
2770 | ||
2771 | if (oh->flags & HWMOD_NO_IDLEST) | |
2772 | return 0; | |
2773 | ||
2774 | if (!_find_mpu_rt_port(oh)) | |
2775 | return 0; | |
2776 | ||
2777 | /* XXX check module SIDLEMODE, hardreset status */ | |
2778 | ||
2779 | return am33xx_cm_wait_module_ready(oh->clkdm->cm_inst, | |
2780 | oh->clkdm->clkdm_offs, | |
2781 | oh->prcm.omap4.clkctrl_offs); | |
2782 | } | |
2783 | ||
b8249cf2 KH |
2784 | /** |
2785 | * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2786 | * @oh: struct omap_hwmod * to assert hardreset | |
2787 | * @ohri: hardreset line data | |
2788 | * | |
2789 | * Call omap2_prm_assert_hardreset() with parameters extracted from | |
2790 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2791 | * use as an soc_ops function pointer. Passes along the return value | |
2792 | * from omap2_prm_assert_hardreset(). XXX This function is scheduled | |
2793 | * for removal when the PRM code is moved into drivers/. | |
2794 | */ | |
2795 | static int _omap2_assert_hardreset(struct omap_hwmod *oh, | |
2796 | struct omap_hwmod_rst_info *ohri) | |
2797 | { | |
2798 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | |
2799 | ohri->rst_shift); | |
2800 | } | |
2801 | ||
2802 | /** | |
2803 | * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args | |
2804 | * @oh: struct omap_hwmod * to deassert hardreset | |
2805 | * @ohri: hardreset line data | |
2806 | * | |
2807 | * Call omap2_prm_deassert_hardreset() with parameters extracted from | |
2808 | * the hwmod @oh and the hardreset line data @ohri. Only intended for | |
2809 | * use as an soc_ops function pointer. Passes along the return value | |
2810 | * from omap2_prm_deassert_hardreset(). XXX This function is | |
2811 | * scheduled for removal when the PRM code is moved into drivers/. | |
2812 | */ | |
2813 | static int _omap2_deassert_hardreset(struct omap_hwmod *oh, | |
2814 | struct omap_hwmod_rst_info *ohri) | |
2815 | { | |
2816 | return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | |
2817 | ohri->rst_shift, | |
2818 | ohri->st_shift); | |
2819 | } | |
2820 | ||
2821 | /** | |
2822 | * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args | |
2823 | * @oh: struct omap_hwmod * to test hardreset | |
2824 | * @ohri: hardreset line data | |
2825 | * | |
2826 | * Call omap2_prm_is_hardreset_asserted() with parameters extracted | |
2827 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2828 | * intended for use as an soc_ops function pointer. Passes along the | |
2829 | * return value from omap2_prm_is_hardreset_asserted(). XXX This | |
2830 | * function is scheduled for removal when the PRM code is moved into | |
2831 | * drivers/. | |
2832 | */ | |
2833 | static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh, | |
2834 | struct omap_hwmod_rst_info *ohri) | |
2835 | { | |
2836 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | |
2837 | ohri->st_shift); | |
2838 | } | |
2839 | ||
2840 | /** | |
2841 | * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2842 | * @oh: struct omap_hwmod * to assert hardreset | |
2843 | * @ohri: hardreset line data | |
2844 | * | |
2845 | * Call omap4_prminst_assert_hardreset() with parameters extracted | |
2846 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2847 | * intended for use as an soc_ops function pointer. Passes along the | |
2848 | * return value from omap4_prminst_assert_hardreset(). XXX This | |
2849 | * function is scheduled for removal when the PRM code is moved into | |
2850 | * drivers/. | |
2851 | */ | |
2852 | static int _omap4_assert_hardreset(struct omap_hwmod *oh, | |
2853 | struct omap_hwmod_rst_info *ohri) | |
b8249cf2 | 2854 | { |
07b3a139 PW |
2855 | if (!oh->clkdm) |
2856 | return -EINVAL; | |
2857 | ||
b8249cf2 KH |
2858 | return omap4_prminst_assert_hardreset(ohri->rst_shift, |
2859 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2860 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2861 | oh->prcm.omap4.rstctrl_offs); | |
2862 | } | |
2863 | ||
2864 | /** | |
2865 | * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args | |
2866 | * @oh: struct omap_hwmod * to deassert hardreset | |
2867 | * @ohri: hardreset line data | |
2868 | * | |
2869 | * Call omap4_prminst_deassert_hardreset() with parameters extracted | |
2870 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2871 | * intended for use as an soc_ops function pointer. Passes along the | |
2872 | * return value from omap4_prminst_deassert_hardreset(). XXX This | |
2873 | * function is scheduled for removal when the PRM code is moved into | |
2874 | * drivers/. | |
2875 | */ | |
2876 | static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | |
2877 | struct omap_hwmod_rst_info *ohri) | |
2878 | { | |
07b3a139 PW |
2879 | if (!oh->clkdm) |
2880 | return -EINVAL; | |
2881 | ||
b8249cf2 KH |
2882 | if (ohri->st_shift) |
2883 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
2884 | oh->name, ohri->name); | |
2885 | return omap4_prminst_deassert_hardreset(ohri->rst_shift, | |
2886 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2887 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2888 | oh->prcm.omap4.rstctrl_offs); | |
2889 | } | |
2890 | ||
2891 | /** | |
2892 | * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args | |
2893 | * @oh: struct omap_hwmod * to test hardreset | |
2894 | * @ohri: hardreset line data | |
2895 | * | |
2896 | * Call omap4_prminst_is_hardreset_asserted() with parameters | |
2897 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
2898 | * Only intended for use as an soc_ops function pointer. Passes along | |
2899 | * the return value from omap4_prminst_is_hardreset_asserted(). XXX | |
2900 | * This function is scheduled for removal when the PRM code is moved | |
2901 | * into drivers/. | |
2902 | */ | |
2903 | static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | |
2904 | struct omap_hwmod_rst_info *ohri) | |
2905 | { | |
07b3a139 PW |
2906 | if (!oh->clkdm) |
2907 | return -EINVAL; | |
2908 | ||
b8249cf2 KH |
2909 | return omap4_prminst_is_hardreset_asserted(ohri->rst_shift, |
2910 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
2911 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2912 | oh->prcm.omap4.rstctrl_offs); | |
2913 | } | |
2914 | ||
1688bf19 VH |
2915 | /** |
2916 | * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
2917 | * @oh: struct omap_hwmod * to assert hardreset | |
2918 | * @ohri: hardreset line data | |
2919 | * | |
2920 | * Call am33xx_prminst_assert_hardreset() with parameters extracted | |
2921 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2922 | * intended for use as an soc_ops function pointer. Passes along the | |
2923 | * return value from am33xx_prminst_assert_hardreset(). XXX This | |
2924 | * function is scheduled for removal when the PRM code is moved into | |
2925 | * drivers/. | |
2926 | */ | |
2927 | static int _am33xx_assert_hardreset(struct omap_hwmod *oh, | |
2928 | struct omap_hwmod_rst_info *ohri) | |
2929 | ||
2930 | { | |
2931 | return am33xx_prm_assert_hardreset(ohri->rst_shift, | |
2932 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2933 | oh->prcm.omap4.rstctrl_offs); | |
2934 | } | |
2935 | ||
2936 | /** | |
2937 | * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args | |
2938 | * @oh: struct omap_hwmod * to deassert hardreset | |
2939 | * @ohri: hardreset line data | |
2940 | * | |
2941 | * Call am33xx_prminst_deassert_hardreset() with parameters extracted | |
2942 | * from the hwmod @oh and the hardreset line data @ohri. Only | |
2943 | * intended for use as an soc_ops function pointer. Passes along the | |
2944 | * return value from am33xx_prminst_deassert_hardreset(). XXX This | |
2945 | * function is scheduled for removal when the PRM code is moved into | |
2946 | * drivers/. | |
2947 | */ | |
2948 | static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, | |
2949 | struct omap_hwmod_rst_info *ohri) | |
2950 | { | |
2951 | if (ohri->st_shift) | |
2952 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
2953 | oh->name, ohri->name); | |
2954 | ||
2955 | return am33xx_prm_deassert_hardreset(ohri->rst_shift, | |
2956 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2957 | oh->prcm.omap4.rstctrl_offs, | |
2958 | oh->prcm.omap4.rstst_offs); | |
2959 | } | |
2960 | ||
2961 | /** | |
2962 | * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args | |
2963 | * @oh: struct omap_hwmod * to test hardreset | |
2964 | * @ohri: hardreset line data | |
2965 | * | |
2966 | * Call am33xx_prminst_is_hardreset_asserted() with parameters | |
2967 | * extracted from the hwmod @oh and the hardreset line data @ohri. | |
2968 | * Only intended for use as an soc_ops function pointer. Passes along | |
2969 | * the return value from am33xx_prminst_is_hardreset_asserted(). XXX | |
2970 | * This function is scheduled for removal when the PRM code is moved | |
2971 | * into drivers/. | |
2972 | */ | |
2973 | static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh, | |
2974 | struct omap_hwmod_rst_info *ohri) | |
2975 | { | |
2976 | return am33xx_prm_is_hardreset_asserted(ohri->rst_shift, | |
2977 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
2978 | oh->prcm.omap4.rstctrl_offs); | |
2979 | } | |
2980 | ||
0102b627 BC |
2981 | /* Public functions */ |
2982 | ||
2983 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
2984 | { | |
2985 | if (oh->flags & HWMOD_16BIT_REG) | |
2986 | return __raw_readw(oh->_mpu_rt_va + reg_offs); | |
2987 | else | |
2988 | return __raw_readl(oh->_mpu_rt_va + reg_offs); | |
2989 | } | |
2990 | ||
2991 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
2992 | { | |
2993 | if (oh->flags & HWMOD_16BIT_REG) | |
2994 | __raw_writew(v, oh->_mpu_rt_va + reg_offs); | |
2995 | else | |
2996 | __raw_writel(v, oh->_mpu_rt_va + reg_offs); | |
2997 | } | |
2998 | ||
6d3c55fd A |
2999 | /** |
3000 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
3001 | * @oh: struct omap_hwmod * | |
3002 | * | |
3003 | * This is a public function exposed to drivers. Some drivers may need to do | |
3004 | * some settings before and after resetting the device. Those drivers after | |
3005 | * doing the necessary settings could use this function to start a reset by | |
3006 | * setting the SYSCONFIG.SOFTRESET bit. | |
3007 | */ | |
3008 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
3009 | { | |
3c55c1ba PW |
3010 | u32 v; |
3011 | int ret; | |
3012 | ||
3013 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
3014 | return -EINVAL; |
3015 | ||
3c55c1ba PW |
3016 | v = oh->_sysc_cache; |
3017 | ret = _set_softreset(oh, &v); | |
3018 | if (ret) | |
3019 | goto error; | |
3020 | _write_sysconfig(v, oh); | |
3021 | ||
3022 | error: | |
3023 | return ret; | |
6d3c55fd A |
3024 | } |
3025 | ||
0102b627 BC |
3026 | /** |
3027 | * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode | |
3028 | * @oh: struct omap_hwmod * | |
3029 | * @idlemode: SIDLEMODE field bits (shifted to bit 0) | |
3030 | * | |
3031 | * Sets the IP block's OCP slave idlemode in hardware, and updates our | |
3032 | * local copy. Intended to be used by drivers that have some erratum | |
3033 | * that requires direct manipulation of the SIDLEMODE bits. Returns | |
3034 | * -EINVAL if @oh is null, or passes along the return value from | |
3035 | * _set_slave_idlemode(). | |
3036 | * | |
3037 | * XXX Does this function have any current users? If not, we should | |
3038 | * remove it; it is better to let the rest of the hwmod code handle this. | |
3039 | * Any users of this function should be scrutinized carefully. | |
3040 | */ | |
3041 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) | |
3042 | { | |
3043 | u32 v; | |
3044 | int retval = 0; | |
3045 | ||
3046 | if (!oh) | |
3047 | return -EINVAL; | |
3048 | ||
3049 | v = oh->_sysc_cache; | |
3050 | ||
3051 | retval = _set_slave_idlemode(oh, idlemode, &v); | |
3052 | if (!retval) | |
3053 | _write_sysconfig(v, oh); | |
3054 | ||
3055 | return retval; | |
3056 | } | |
3057 | ||
63c85238 PW |
3058 | /** |
3059 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
3060 | * @name: name of the omap_hwmod to look up | |
3061 | * | |
3062 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
3063 | * struct omap_hwmod *, or NULL upon error. | |
3064 | */ | |
3065 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
3066 | { | |
3067 | struct omap_hwmod *oh; | |
3068 | ||
3069 | if (!name) | |
3070 | return NULL; | |
3071 | ||
63c85238 | 3072 | oh = _lookup(name); |
63c85238 PW |
3073 | |
3074 | return oh; | |
3075 | } | |
3076 | ||
3077 | /** | |
3078 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
3079 | * @fn: pointer to a callback function | |
97d60162 | 3080 | * @data: void * data to pass to callback function |
63c85238 PW |
3081 | * |
3082 | * Call @fn for each registered omap_hwmod, passing @data to each | |
3083 | * function. @fn must return 0 for success or any other value for | |
3084 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
3085 | * will stop and the non-zero return value will be passed to the | |
3086 | * caller of omap_hwmod_for_each(). @fn is called with | |
3087 | * omap_hwmod_for_each() held. | |
3088 | */ | |
97d60162 PW |
3089 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
3090 | void *data) | |
63c85238 PW |
3091 | { |
3092 | struct omap_hwmod *temp_oh; | |
30ebad9d | 3093 | int ret = 0; |
63c85238 PW |
3094 | |
3095 | if (!fn) | |
3096 | return -EINVAL; | |
3097 | ||
63c85238 | 3098 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 3099 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
3100 | if (ret) |
3101 | break; | |
3102 | } | |
63c85238 PW |
3103 | |
3104 | return ret; | |
3105 | } | |
3106 | ||
2221b5cd PW |
3107 | /** |
3108 | * omap_hwmod_register_links - register an array of hwmod links | |
3109 | * @ois: pointer to an array of omap_hwmod_ocp_if to register | |
3110 | * | |
3111 | * Intended to be called early in boot before the clock framework is | |
3112 | * initialized. If @ois is not null, will register all omap_hwmods | |
9ebfd285 KH |
3113 | * listed in @ois that are valid for this chip. Returns -EINVAL if |
3114 | * omap_hwmod_init() hasn't been called before calling this function, | |
3115 | * -ENOMEM if the link memory area can't be allocated, or 0 upon | |
3116 | * success. | |
2221b5cd PW |
3117 | */ |
3118 | int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois) | |
3119 | { | |
3120 | int r, i; | |
3121 | ||
9ebfd285 KH |
3122 | if (!inited) |
3123 | return -EINVAL; | |
3124 | ||
2221b5cd PW |
3125 | if (!ois) |
3126 | return 0; | |
3127 | ||
2221b5cd PW |
3128 | if (!linkspace) { |
3129 | if (_alloc_linkspace(ois)) { | |
3130 | pr_err("omap_hwmod: could not allocate link space\n"); | |
3131 | return -ENOMEM; | |
3132 | } | |
3133 | } | |
3134 | ||
3135 | i = 0; | |
3136 | do { | |
3137 | r = _register_link(ois[i]); | |
3138 | WARN(r && r != -EEXIST, | |
3139 | "omap_hwmod: _register_link(%s -> %s) returned %d\n", | |
3140 | ois[i]->master->name, ois[i]->slave->name, r); | |
3141 | } while (ois[++i]); | |
3142 | ||
3143 | return 0; | |
3144 | } | |
3145 | ||
381d033a PW |
3146 | /** |
3147 | * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up | |
3148 | * @oh: pointer to the hwmod currently being set up (usually not the MPU) | |
3149 | * | |
3150 | * If the hwmod data corresponding to the MPU subsystem IP block | |
3151 | * hasn't been initialized and set up yet, do so now. This must be | |
3152 | * done first since sleep dependencies may be added from other hwmods | |
3153 | * to the MPU. Intended to be called only by omap_hwmod_setup*(). No | |
3154 | * return value. | |
63c85238 | 3155 | */ |
381d033a | 3156 | static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh) |
e7c7d760 | 3157 | { |
381d033a PW |
3158 | if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN) |
3159 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
3160 | __func__, MPU_INITIATOR_NAME); | |
3161 | else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) | |
3162 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
e7c7d760 TL |
3163 | } |
3164 | ||
63c85238 | 3165 | /** |
a2debdbd PW |
3166 | * omap_hwmod_setup_one - set up a single hwmod |
3167 | * @oh_name: const char * name of the already-registered hwmod to set up | |
3168 | * | |
381d033a PW |
3169 | * Initialize and set up a single hwmod. Intended to be used for a |
3170 | * small number of early devices, such as the timer IP blocks used for | |
3171 | * the scheduler clock. Must be called after omap2_clk_init(). | |
3172 | * Resolves the struct clk names to struct clk pointers for each | |
3173 | * registered omap_hwmod. Also calls _setup() on each hwmod. Returns | |
3174 | * -EINVAL upon error or 0 upon success. | |
a2debdbd PW |
3175 | */ |
3176 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
3177 | { |
3178 | struct omap_hwmod *oh; | |
63c85238 | 3179 | |
a2debdbd PW |
3180 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
3181 | ||
a2debdbd PW |
3182 | oh = _lookup(oh_name); |
3183 | if (!oh) { | |
3184 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
3185 | return -EINVAL; | |
3186 | } | |
63c85238 | 3187 | |
381d033a | 3188 | _ensure_mpu_hwmod_is_setup(oh); |
63c85238 | 3189 | |
381d033a | 3190 | _init(oh, NULL); |
a2debdbd PW |
3191 | _setup(oh, NULL); |
3192 | ||
63c85238 PW |
3193 | return 0; |
3194 | } | |
3195 | ||
3196 | /** | |
381d033a | 3197 | * omap_hwmod_setup_all - set up all registered IP blocks |
63c85238 | 3198 | * |
381d033a PW |
3199 | * Initialize and set up all IP blocks registered with the hwmod code. |
3200 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
3201 | * names to struct clk pointers for each registered omap_hwmod. Also | |
3202 | * calls _setup() on each hwmod. Returns 0 upon success. | |
63c85238 | 3203 | */ |
550c8092 | 3204 | static int __init omap_hwmod_setup_all(void) |
63c85238 | 3205 | { |
381d033a | 3206 | _ensure_mpu_hwmod_is_setup(NULL); |
63c85238 | 3207 | |
381d033a | 3208 | omap_hwmod_for_each(_init, NULL); |
2092e5cc | 3209 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
3210 | |
3211 | return 0; | |
3212 | } | |
550c8092 | 3213 | core_initcall(omap_hwmod_setup_all); |
63c85238 | 3214 | |
63c85238 PW |
3215 | /** |
3216 | * omap_hwmod_enable - enable an omap_hwmod | |
3217 | * @oh: struct omap_hwmod * | |
3218 | * | |
74ff3a68 | 3219 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
3220 | * Returns -EINVAL on error or passes along the return value from _enable(). |
3221 | */ | |
3222 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
3223 | { | |
3224 | int r; | |
dc6d1cda | 3225 | unsigned long flags; |
63c85238 PW |
3226 | |
3227 | if (!oh) | |
3228 | return -EINVAL; | |
3229 | ||
dc6d1cda PW |
3230 | spin_lock_irqsave(&oh->_lock, flags); |
3231 | r = _enable(oh); | |
3232 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3233 | |
3234 | return r; | |
3235 | } | |
3236 | ||
3237 | /** | |
3238 | * omap_hwmod_idle - idle an omap_hwmod | |
3239 | * @oh: struct omap_hwmod * | |
3240 | * | |
74ff3a68 | 3241 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
3242 | * Returns -EINVAL on error or passes along the return value from _idle(). |
3243 | */ | |
3244 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
3245 | { | |
dc6d1cda PW |
3246 | unsigned long flags; |
3247 | ||
63c85238 PW |
3248 | if (!oh) |
3249 | return -EINVAL; | |
3250 | ||
dc6d1cda PW |
3251 | spin_lock_irqsave(&oh->_lock, flags); |
3252 | _idle(oh); | |
3253 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
3254 | |
3255 | return 0; | |
3256 | } | |
3257 | ||
3258 | /** | |
3259 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
3260 | * @oh: struct omap_hwmod * | |
3261 | * | |
74ff3a68 | 3262 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
3263 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
3264 | * the return value from _shutdown(). | |
3265 | */ | |
3266 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
3267 | { | |
dc6d1cda PW |
3268 | unsigned long flags; |
3269 | ||
63c85238 PW |
3270 | if (!oh) |
3271 | return -EINVAL; | |
3272 | ||
dc6d1cda | 3273 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3274 | _shutdown(oh); |
dc6d1cda | 3275 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3276 | |
3277 | return 0; | |
3278 | } | |
3279 | ||
3280 | /** | |
3281 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
3282 | * @oh: struct omap_hwmod *oh | |
3283 | * | |
3284 | * Intended to be called by the omap_device code. | |
3285 | */ | |
3286 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
3287 | { | |
dc6d1cda PW |
3288 | unsigned long flags; |
3289 | ||
3290 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 3291 | _enable_clocks(oh); |
dc6d1cda | 3292 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3293 | |
3294 | return 0; | |
3295 | } | |
3296 | ||
3297 | /** | |
3298 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
3299 | * @oh: struct omap_hwmod *oh | |
3300 | * | |
3301 | * Intended to be called by the omap_device code. | |
3302 | */ | |
3303 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
3304 | { | |
dc6d1cda PW |
3305 | unsigned long flags; |
3306 | ||
3307 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 3308 | _disable_clocks(oh); |
dc6d1cda | 3309 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3310 | |
3311 | return 0; | |
3312 | } | |
3313 | ||
3314 | /** | |
3315 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
3316 | * @oh: struct omap_hwmod *oh | |
3317 | * | |
3318 | * Intended to be called by drivers and core code when all posted | |
3319 | * writes to a device must complete before continuing further | |
3320 | * execution (for example, after clearing some device IRQSTATUS | |
3321 | * register bits) | |
3322 | * | |
3323 | * XXX what about targets with multiple OCP threads? | |
3324 | */ | |
3325 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
3326 | { | |
3327 | BUG_ON(!oh); | |
3328 | ||
43b40992 | 3329 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
4f8a428d RK |
3330 | WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n", |
3331 | oh->name); | |
63c85238 PW |
3332 | return; |
3333 | } | |
3334 | ||
3335 | /* | |
3336 | * Forces posted writes to complete on the OCP thread handling | |
3337 | * register writes | |
3338 | */ | |
cc7a1d2a | 3339 | omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
3340 | } |
3341 | ||
3342 | /** | |
3343 | * omap_hwmod_reset - reset the hwmod | |
3344 | * @oh: struct omap_hwmod * | |
3345 | * | |
3346 | * Under some conditions, a driver may wish to reset the entire device. | |
3347 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 3348 | * the return value from _reset(). |
63c85238 PW |
3349 | */ |
3350 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
3351 | { | |
3352 | int r; | |
dc6d1cda | 3353 | unsigned long flags; |
63c85238 | 3354 | |
9b579114 | 3355 | if (!oh) |
63c85238 PW |
3356 | return -EINVAL; |
3357 | ||
dc6d1cda | 3358 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 3359 | r = _reset(oh); |
dc6d1cda | 3360 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3361 | |
3362 | return r; | |
3363 | } | |
3364 | ||
5e8370f1 PW |
3365 | /* |
3366 | * IP block data retrieval functions | |
3367 | */ | |
3368 | ||
63c85238 PW |
3369 | /** |
3370 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
3371 | * @oh: struct omap_hwmod * | |
3372 | * @res: pointer to the first element of an array of struct resource to fill | |
3373 | * | |
3374 | * Count the number of struct resource array elements necessary to | |
3375 | * contain omap_hwmod @oh resources. Intended to be called by code | |
3376 | * that registers omap_devices. Intended to be used to determine the | |
3377 | * size of a dynamically-allocated struct resource array, before | |
3378 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
3379 | * resource array elements needed. | |
3380 | * | |
3381 | * XXX This code is not optimized. It could attempt to merge adjacent | |
3382 | * resource IDs. | |
3383 | * | |
3384 | */ | |
3385 | int omap_hwmod_count_resources(struct omap_hwmod *oh) | |
3386 | { | |
5d95dde7 | 3387 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3388 | struct list_head *p; |
5d95dde7 PW |
3389 | int ret; |
3390 | int i = 0; | |
63c85238 | 3391 | |
bc614958 | 3392 | ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); |
63c85238 | 3393 | |
11cd4b94 | 3394 | p = oh->slave_ports.next; |
2221b5cd | 3395 | |
5d95dde7 | 3396 | while (i < oh->slaves_cnt) { |
11cd4b94 | 3397 | os = _fetch_next_ocp_if(&p, &i); |
5d95dde7 PW |
3398 | ret += _count_ocp_if_addr_spaces(os); |
3399 | } | |
63c85238 PW |
3400 | |
3401 | return ret; | |
3402 | } | |
3403 | ||
3404 | /** | |
3405 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
3406 | * @oh: struct omap_hwmod * | |
3407 | * @res: pointer to the first element of an array of struct resource to fill | |
3408 | * | |
3409 | * Fill the struct resource array @res with resource data from the | |
3410 | * omap_hwmod @oh. Intended to be called by code that registers | |
3411 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3412 | * number of array elements filled. | |
3413 | */ | |
3414 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
3415 | { | |
5d95dde7 | 3416 | struct omap_hwmod_ocp_if *os; |
11cd4b94 | 3417 | struct list_head *p; |
5d95dde7 | 3418 | int i, j, mpu_irqs_cnt, sdma_reqs_cnt, addr_cnt; |
63c85238 PW |
3419 | int r = 0; |
3420 | ||
3421 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
3422 | ||
212738a4 PW |
3423 | mpu_irqs_cnt = _count_mpu_irqs(oh); |
3424 | for (i = 0; i < mpu_irqs_cnt; i++) { | |
718bfd76 PW |
3425 | (res + r)->name = (oh->mpu_irqs + i)->name; |
3426 | (res + r)->start = (oh->mpu_irqs + i)->irq; | |
3427 | (res + r)->end = (oh->mpu_irqs + i)->irq; | |
63c85238 PW |
3428 | (res + r)->flags = IORESOURCE_IRQ; |
3429 | r++; | |
3430 | } | |
3431 | ||
bc614958 PW |
3432 | sdma_reqs_cnt = _count_sdma_reqs(oh); |
3433 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
9ee9fff9 BC |
3434 | (res + r)->name = (oh->sdma_reqs + i)->name; |
3435 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3436 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
3437 | (res + r)->flags = IORESOURCE_DMA; |
3438 | r++; | |
3439 | } | |
3440 | ||
11cd4b94 | 3441 | p = oh->slave_ports.next; |
2221b5cd | 3442 | |
5d95dde7 PW |
3443 | i = 0; |
3444 | while (i < oh->slaves_cnt) { | |
11cd4b94 | 3445 | os = _fetch_next_ocp_if(&p, &i); |
78183f3f | 3446 | addr_cnt = _count_ocp_if_addr_spaces(os); |
63c85238 | 3447 | |
78183f3f | 3448 | for (j = 0; j < addr_cnt; j++) { |
cd503802 | 3449 | (res + r)->name = (os->addr + j)->name; |
63c85238 PW |
3450 | (res + r)->start = (os->addr + j)->pa_start; |
3451 | (res + r)->end = (os->addr + j)->pa_end; | |
3452 | (res + r)->flags = IORESOURCE_MEM; | |
3453 | r++; | |
3454 | } | |
3455 | } | |
3456 | ||
3457 | return r; | |
3458 | } | |
3459 | ||
b82b04e8 VH |
3460 | /** |
3461 | * omap_hwmod_fill_dma_resources - fill struct resource array with dma data | |
3462 | * @oh: struct omap_hwmod * | |
3463 | * @res: pointer to the array of struct resource to fill | |
3464 | * | |
3465 | * Fill the struct resource array @res with dma resource data from the | |
3466 | * omap_hwmod @oh. Intended to be called by code that registers | |
3467 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
3468 | * number of array elements filled. | |
3469 | */ | |
3470 | int omap_hwmod_fill_dma_resources(struct omap_hwmod *oh, struct resource *res) | |
3471 | { | |
3472 | int i, sdma_reqs_cnt; | |
3473 | int r = 0; | |
3474 | ||
3475 | sdma_reqs_cnt = _count_sdma_reqs(oh); | |
3476 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
3477 | (res + r)->name = (oh->sdma_reqs + i)->name; | |
3478 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
3479 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
3480 | (res + r)->flags = IORESOURCE_DMA; | |
3481 | r++; | |
3482 | } | |
3483 | ||
3484 | return r; | |
3485 | } | |
3486 | ||
5e8370f1 PW |
3487 | /** |
3488 | * omap_hwmod_get_resource_byname - fetch IP block integration data by name | |
3489 | * @oh: struct omap_hwmod * to operate on | |
3490 | * @type: one of the IORESOURCE_* constants from include/linux/ioport.h | |
3491 | * @name: pointer to the name of the data to fetch (optional) | |
3492 | * @rsrc: pointer to a struct resource, allocated by the caller | |
3493 | * | |
3494 | * Retrieve MPU IRQ, SDMA request line, or address space start/end | |
3495 | * data for the IP block pointed to by @oh. The data will be filled | |
3496 | * into a struct resource record pointed to by @rsrc. The struct | |
3497 | * resource must be allocated by the caller. When @name is non-null, | |
3498 | * the data associated with the matching entry in the IRQ/SDMA/address | |
3499 | * space hwmod data arrays will be returned. If @name is null, the | |
3500 | * first array entry will be returned. Data order is not meaningful | |
3501 | * in hwmod data, so callers are strongly encouraged to use a non-null | |
3502 | * @name whenever possible to avoid unpredictable effects if hwmod | |
3503 | * data is later added that causes data ordering to change. This | |
3504 | * function is only intended for use by OMAP core code. Device | |
3505 | * drivers should not call this function - the appropriate bus-related | |
3506 | * data accessor functions should be used instead. Returns 0 upon | |
3507 | * success or a negative error code upon error. | |
3508 | */ | |
3509 | int omap_hwmod_get_resource_byname(struct omap_hwmod *oh, unsigned int type, | |
3510 | const char *name, struct resource *rsrc) | |
3511 | { | |
3512 | int r; | |
3513 | unsigned int irq, dma; | |
3514 | u32 pa_start, pa_end; | |
3515 | ||
3516 | if (!oh || !rsrc) | |
3517 | return -EINVAL; | |
3518 | ||
3519 | if (type == IORESOURCE_IRQ) { | |
3520 | r = _get_mpu_irq_by_name(oh, name, &irq); | |
3521 | if (r) | |
3522 | return r; | |
3523 | ||
3524 | rsrc->start = irq; | |
3525 | rsrc->end = irq; | |
3526 | } else if (type == IORESOURCE_DMA) { | |
3527 | r = _get_sdma_req_by_name(oh, name, &dma); | |
3528 | if (r) | |
3529 | return r; | |
3530 | ||
3531 | rsrc->start = dma; | |
3532 | rsrc->end = dma; | |
3533 | } else if (type == IORESOURCE_MEM) { | |
3534 | r = _get_addr_space_by_name(oh, name, &pa_start, &pa_end); | |
3535 | if (r) | |
3536 | return r; | |
3537 | ||
3538 | rsrc->start = pa_start; | |
3539 | rsrc->end = pa_end; | |
3540 | } else { | |
3541 | return -EINVAL; | |
3542 | } | |
3543 | ||
3544 | rsrc->flags = type; | |
3545 | rsrc->name = name; | |
3546 | ||
3547 | return 0; | |
3548 | } | |
3549 | ||
63c85238 PW |
3550 | /** |
3551 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
3552 | * @oh: struct omap_hwmod * | |
3553 | * | |
3554 | * Return the powerdomain pointer associated with the OMAP module | |
3555 | * @oh's main clock. If @oh does not have a main clk, return the | |
3556 | * powerdomain associated with the interface clock associated with the | |
3557 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
3558 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
3559 | * success. | |
3560 | */ | |
3561 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
3562 | { | |
3563 | struct clk *c; | |
2d6141ba | 3564 | struct omap_hwmod_ocp_if *oi; |
63c85238 PW |
3565 | |
3566 | if (!oh) | |
3567 | return NULL; | |
3568 | ||
3569 | if (oh->_clk) { | |
3570 | c = oh->_clk; | |
3571 | } else { | |
2d6141ba PW |
3572 | oi = _find_mpu_rt_port(oh); |
3573 | if (!oi) | |
63c85238 | 3574 | return NULL; |
2d6141ba | 3575 | c = oi->_clk; |
63c85238 PW |
3576 | } |
3577 | ||
d5647c18 TG |
3578 | if (!c->clkdm) |
3579 | return NULL; | |
3580 | ||
63c85238 PW |
3581 | return c->clkdm->pwrdm.ptr; |
3582 | ||
3583 | } | |
3584 | ||
db2a60bf PW |
3585 | /** |
3586 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
3587 | * @oh: struct omap_hwmod * | |
3588 | * | |
3589 | * Returns the virtual address corresponding to the beginning of the | |
3590 | * module's register target, in the address range that is intended to | |
3591 | * be used by the MPU. Returns the virtual address upon success or NULL | |
3592 | * upon error. | |
3593 | */ | |
3594 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
3595 | { | |
3596 | if (!oh) | |
3597 | return NULL; | |
3598 | ||
3599 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
3600 | return NULL; | |
3601 | ||
3602 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
3603 | return NULL; | |
3604 | ||
3605 | return oh->_mpu_rt_va; | |
3606 | } | |
3607 | ||
63c85238 PW |
3608 | /** |
3609 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
3610 | * @oh: struct omap_hwmod * | |
3611 | * @init_oh: struct omap_hwmod * (initiator) | |
3612 | * | |
3613 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
3614 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3615 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3616 | * code needs to add/del initiator dependencies dynamically | |
3617 | * before/after accessing a device. Returns the return value from | |
3618 | * _add_initiator_dep(). | |
3619 | * | |
3620 | * XXX Keep a usecount in the clockdomain code | |
3621 | */ | |
3622 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
3623 | struct omap_hwmod *init_oh) | |
3624 | { | |
3625 | return _add_initiator_dep(oh, init_oh); | |
3626 | } | |
3627 | ||
3628 | /* | |
3629 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
3630 | * for context save/restore operations? | |
3631 | */ | |
3632 | ||
3633 | /** | |
3634 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
3635 | * @oh: struct omap_hwmod * | |
3636 | * @init_oh: struct omap_hwmod * (initiator) | |
3637 | * | |
3638 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
3639 | * Intended to be called by DSP/Bridge code via platform_data for the | |
3640 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
3641 | * code needs to add/del initiator dependencies dynamically | |
3642 | * before/after accessing a device. Returns the return value from | |
3643 | * _del_initiator_dep(). | |
3644 | * | |
3645 | * XXX Keep a usecount in the clockdomain code | |
3646 | */ | |
3647 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
3648 | struct omap_hwmod *init_oh) | |
3649 | { | |
3650 | return _del_initiator_dep(oh, init_oh); | |
3651 | } | |
3652 | ||
63c85238 PW |
3653 | /** |
3654 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
3655 | * @oh: struct omap_hwmod * | |
3656 | * | |
3657 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
3658 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
3659 | * this IP block if it has dynamic mux entries. Eventually this | |
3660 | * should set PRCM wakeup registers to cause the PRCM to receive | |
3661 | * wakeup events from the module. Does not set any wakeup routing | |
3662 | * registers beyond this point - if the module is to wake up any other | |
3663 | * module or subsystem, that must be set separately. Called by | |
3664 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3665 | */ |
3666 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
3667 | { | |
dc6d1cda | 3668 | unsigned long flags; |
5a7ddcbd | 3669 | u32 v; |
dc6d1cda | 3670 | |
dc6d1cda | 3671 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3672 | |
3673 | if (oh->class->sysc && | |
3674 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3675 | v = oh->_sysc_cache; | |
3676 | _enable_wakeup(oh, &v); | |
3677 | _write_sysconfig(v, oh); | |
3678 | } | |
3679 | ||
eceec009 | 3680 | _set_idle_ioring_wakeup(oh, true); |
dc6d1cda | 3681 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3682 | |
3683 | return 0; | |
3684 | } | |
3685 | ||
3686 | /** | |
3687 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
3688 | * @oh: struct omap_hwmod * | |
3689 | * | |
3690 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
3691 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
3692 | * events for this IP block if it has dynamic mux entries. Eventually | |
3693 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
3694 | * wakeup events from the module. Does not set any wakeup routing | |
3695 | * registers beyond this point - if the module is to wake up any other | |
3696 | * module or subsystem, that must be set separately. Called by | |
3697 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
3698 | */ |
3699 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
3700 | { | |
dc6d1cda | 3701 | unsigned long flags; |
5a7ddcbd | 3702 | u32 v; |
dc6d1cda | 3703 | |
dc6d1cda | 3704 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
3705 | |
3706 | if (oh->class->sysc && | |
3707 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
3708 | v = oh->_sysc_cache; | |
3709 | _disable_wakeup(oh, &v); | |
3710 | _write_sysconfig(v, oh); | |
3711 | } | |
3712 | ||
eceec009 | 3713 | _set_idle_ioring_wakeup(oh, false); |
dc6d1cda | 3714 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
3715 | |
3716 | return 0; | |
3717 | } | |
43b40992 | 3718 | |
aee48e3c PW |
3719 | /** |
3720 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
3721 | * contained in the hwmod module. | |
3722 | * @oh: struct omap_hwmod * | |
3723 | * @name: name of the reset line to lookup and assert | |
3724 | * | |
3725 | * Some IP like dsp, ipu or iva contain processor that require | |
3726 | * an HW reset line to be assert / deassert in order to enable fully | |
3727 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3728 | * yet supported on this OMAP; otherwise, passes along the return value | |
3729 | * from _assert_hardreset(). | |
3730 | */ | |
3731 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
3732 | { | |
3733 | int ret; | |
dc6d1cda | 3734 | unsigned long flags; |
aee48e3c PW |
3735 | |
3736 | if (!oh) | |
3737 | return -EINVAL; | |
3738 | ||
dc6d1cda | 3739 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3740 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 3741 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3742 | |
3743 | return ret; | |
3744 | } | |
3745 | ||
3746 | /** | |
3747 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
3748 | * contained in the hwmod module. | |
3749 | * @oh: struct omap_hwmod * | |
3750 | * @name: name of the reset line to look up and deassert | |
3751 | * | |
3752 | * Some IP like dsp, ipu or iva contain processor that require | |
3753 | * an HW reset line to be assert / deassert in order to enable fully | |
3754 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
3755 | * yet supported on this OMAP; otherwise, passes along the return value | |
3756 | * from _deassert_hardreset(). | |
3757 | */ | |
3758 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
3759 | { | |
3760 | int ret; | |
dc6d1cda | 3761 | unsigned long flags; |
aee48e3c PW |
3762 | |
3763 | if (!oh) | |
3764 | return -EINVAL; | |
3765 | ||
dc6d1cda | 3766 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3767 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 3768 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3769 | |
3770 | return ret; | |
3771 | } | |
3772 | ||
3773 | /** | |
3774 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
3775 | * contained in the hwmod module | |
3776 | * @oh: struct omap_hwmod * | |
3777 | * @name: name of the reset line to look up and read | |
3778 | * | |
3779 | * Return the current state of the hwmod @oh's reset line named @name: | |
3780 | * returns -EINVAL upon parameter error or if this operation | |
3781 | * is unsupported on the current OMAP; otherwise, passes along the return | |
3782 | * value from _read_hardreset(). | |
3783 | */ | |
3784 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
3785 | { | |
3786 | int ret; | |
dc6d1cda | 3787 | unsigned long flags; |
aee48e3c PW |
3788 | |
3789 | if (!oh) | |
3790 | return -EINVAL; | |
3791 | ||
dc6d1cda | 3792 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 3793 | ret = _read_hardreset(oh, name); |
dc6d1cda | 3794 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
3795 | |
3796 | return ret; | |
3797 | } | |
3798 | ||
3799 | ||
43b40992 PW |
3800 | /** |
3801 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
3802 | * @classname: struct omap_hwmod_class name to search for | |
3803 | * @fn: callback function pointer to call for each hwmod in class @classname | |
3804 | * @user: arbitrary context data to pass to the callback function | |
3805 | * | |
ce35b244 BC |
3806 | * For each omap_hwmod of class @classname, call @fn. |
3807 | * If the callback function returns something other than | |
43b40992 PW |
3808 | * zero, the iterator is terminated, and the callback function's return |
3809 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
3810 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
3811 | */ | |
3812 | int omap_hwmod_for_each_by_class(const char *classname, | |
3813 | int (*fn)(struct omap_hwmod *oh, | |
3814 | void *user), | |
3815 | void *user) | |
3816 | { | |
3817 | struct omap_hwmod *temp_oh; | |
3818 | int ret = 0; | |
3819 | ||
3820 | if (!classname || !fn) | |
3821 | return -EINVAL; | |
3822 | ||
3823 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
3824 | __func__, classname); | |
3825 | ||
43b40992 PW |
3826 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
3827 | if (!strcmp(temp_oh->class->name, classname)) { | |
3828 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
3829 | __func__, temp_oh->name); | |
3830 | ret = (*fn)(temp_oh, user); | |
3831 | if (ret) | |
3832 | break; | |
3833 | } | |
3834 | } | |
3835 | ||
43b40992 PW |
3836 | if (ret) |
3837 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
3838 | __func__, ret); | |
3839 | ||
3840 | return ret; | |
3841 | } | |
3842 | ||
2092e5cc PW |
3843 | /** |
3844 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
3845 | * @oh: struct omap_hwmod * | |
3846 | * @state: state that _setup() should leave the hwmod in | |
3847 | * | |
550c8092 | 3848 | * Sets the hwmod state that @oh will enter at the end of _setup() |
64813c3f PW |
3849 | * (called by omap_hwmod_setup_*()). See also the documentation |
3850 | * for _setup_postsetup(), above. Returns 0 upon success or | |
3851 | * -EINVAL if there is a problem with the arguments or if the hwmod is | |
3852 | * in the wrong state. | |
2092e5cc PW |
3853 | */ |
3854 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
3855 | { | |
3856 | int ret; | |
dc6d1cda | 3857 | unsigned long flags; |
2092e5cc PW |
3858 | |
3859 | if (!oh) | |
3860 | return -EINVAL; | |
3861 | ||
3862 | if (state != _HWMOD_STATE_DISABLED && | |
3863 | state != _HWMOD_STATE_ENABLED && | |
3864 | state != _HWMOD_STATE_IDLE) | |
3865 | return -EINVAL; | |
3866 | ||
dc6d1cda | 3867 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
3868 | |
3869 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3870 | ret = -EINVAL; | |
3871 | goto ohsps_unlock; | |
3872 | } | |
3873 | ||
3874 | oh->_postsetup_state = state; | |
3875 | ret = 0; | |
3876 | ||
3877 | ohsps_unlock: | |
dc6d1cda | 3878 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
3879 | |
3880 | return ret; | |
3881 | } | |
c80705aa KH |
3882 | |
3883 | /** | |
3884 | * omap_hwmod_get_context_loss_count - get lost context count | |
3885 | * @oh: struct omap_hwmod * | |
3886 | * | |
3887 | * Query the powerdomain of of @oh to get the context loss | |
3888 | * count for this device. | |
3889 | * | |
3890 | * Returns the context loss count of the powerdomain assocated with @oh | |
3891 | * upon success, or zero if no powerdomain exists for @oh. | |
3892 | */ | |
fc013873 | 3893 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
3894 | { |
3895 | struct powerdomain *pwrdm; | |
3896 | int ret = 0; | |
3897 | ||
3898 | pwrdm = omap_hwmod_get_pwrdm(oh); | |
3899 | if (pwrdm) | |
3900 | ret = pwrdm_get_context_loss_count(pwrdm); | |
3901 | ||
3902 | return ret; | |
3903 | } | |
43b01643 PW |
3904 | |
3905 | /** | |
3906 | * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup | |
3907 | * @oh: struct omap_hwmod * | |
3908 | * | |
3909 | * Prevent the hwmod @oh from being reset during the setup process. | |
3910 | * Intended for use by board-*.c files on boards with devices that | |
3911 | * cannot tolerate being reset. Must be called before the hwmod has | |
3912 | * been set up. Returns 0 upon success or negative error code upon | |
3913 | * failure. | |
3914 | */ | |
3915 | int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) | |
3916 | { | |
3917 | if (!oh) | |
3918 | return -EINVAL; | |
3919 | ||
3920 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
3921 | pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n", | |
3922 | oh->name); | |
3923 | return -EINVAL; | |
3924 | } | |
3925 | ||
3926 | oh->flags |= HWMOD_INIT_NO_RESET; | |
3927 | ||
3928 | return 0; | |
3929 | } | |
abc2d545 TK |
3930 | |
3931 | /** | |
3932 | * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ | |
3933 | * @oh: struct omap_hwmod * containing hwmod mux entries | |
3934 | * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup | |
3935 | * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup | |
3936 | * | |
3937 | * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux | |
3938 | * entry number @pad_idx for the hwmod @oh, trigger the interrupt | |
3939 | * service routine for the hwmod's mpu_irqs array index @irq_idx. If | |
3940 | * this function is not called for a given pad_idx, then the ISR | |
3941 | * associated with @oh's first MPU IRQ will be triggered when an I/O | |
3942 | * pad wakeup occurs on that pad. Note that @pad_idx is the index of | |
3943 | * the _dynamic or wakeup_ entry: if there are other entries not | |
3944 | * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these | |
3945 | * entries are NOT COUNTED in the dynamic pad index. This function | |
3946 | * must be called separately for each pad that requires its interrupt | |
3947 | * to be re-routed this way. Returns -EINVAL if there is an argument | |
3948 | * problem or if @oh does not have hwmod mux entries or MPU IRQs; | |
3949 | * returns -ENOMEM if memory cannot be allocated; or 0 upon success. | |
3950 | * | |
3951 | * XXX This function interface is fragile. Rather than using array | |
3952 | * indexes, which are subject to unpredictable change, it should be | |
3953 | * using hwmod IRQ names, and some other stable key for the hwmod mux | |
3954 | * pad records. | |
3955 | */ | |
3956 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) | |
3957 | { | |
3958 | int nr_irqs; | |
3959 | ||
3960 | might_sleep(); | |
3961 | ||
3962 | if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 || | |
3963 | pad_idx >= oh->mux->nr_pads_dynamic) | |
3964 | return -EINVAL; | |
3965 | ||
3966 | /* Check the number of available mpu_irqs */ | |
3967 | for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++) | |
3968 | ; | |
3969 | ||
3970 | if (irq_idx >= nr_irqs) | |
3971 | return -EINVAL; | |
3972 | ||
3973 | if (!oh->mux->irqs) { | |
3974 | /* XXX What frees this? */ | |
3975 | oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic, | |
3976 | GFP_KERNEL); | |
3977 | if (!oh->mux->irqs) | |
3978 | return -ENOMEM; | |
3979 | } | |
3980 | oh->mux->irqs[pad_idx] = irq_idx; | |
3981 | ||
3982 | return 0; | |
3983 | } | |
9ebfd285 KH |
3984 | |
3985 | /** | |
3986 | * omap_hwmod_init - initialize the hwmod code | |
3987 | * | |
3988 | * Sets up some function pointers needed by the hwmod code to operate on the | |
3989 | * currently-booted SoC. Intended to be called once during kernel init | |
3990 | * before any hwmods are registered. No return value. | |
3991 | */ | |
3992 | void __init omap_hwmod_init(void) | |
3993 | { | |
8f6aa8ee KH |
3994 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
3995 | soc_ops.wait_target_ready = _omap2_wait_target_ready; | |
b8249cf2 KH |
3996 | soc_ops.assert_hardreset = _omap2_assert_hardreset; |
3997 | soc_ops.deassert_hardreset = _omap2_deassert_hardreset; | |
3998 | soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; | |
05e152c7 | 3999 | } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { |
9ebfd285 KH |
4000 | soc_ops.enable_module = _omap4_enable_module; |
4001 | soc_ops.disable_module = _omap4_disable_module; | |
8f6aa8ee | 4002 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
b8249cf2 KH |
4003 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
4004 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | |
4005 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | |
0a179eaa | 4006 | soc_ops.init_clkdm = _init_clkdm; |
1688bf19 VH |
4007 | } else if (soc_is_am33xx()) { |
4008 | soc_ops.enable_module = _am33xx_enable_module; | |
4009 | soc_ops.disable_module = _am33xx_disable_module; | |
4010 | soc_ops.wait_target_ready = _am33xx_wait_target_ready; | |
4011 | soc_ops.assert_hardreset = _am33xx_assert_hardreset; | |
4012 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; | |
4013 | soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; | |
4014 | soc_ops.init_clkdm = _init_clkdm; | |
8f6aa8ee KH |
4015 | } else { |
4016 | WARN(1, "omap_hwmod: unknown SoC type\n"); | |
9ebfd285 KH |
4017 | } |
4018 | ||
4019 | inited = true; | |
4020 | } | |
68c9a95e TL |
4021 | |
4022 | /** | |
4023 | * omap_hwmod_get_main_clk - get pointer to main clock name | |
4024 | * @oh: struct omap_hwmod * | |
4025 | * | |
4026 | * Returns the main clock name assocated with @oh upon success, | |
4027 | * or NULL if @oh is NULL. | |
4028 | */ | |
4029 | const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh) | |
4030 | { | |
4031 | if (!oh) | |
4032 | return NULL; | |
4033 | ||
4034 | return oh->main_clk; | |
4035 | } |