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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
db2a60bf | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
63c85238 | 5 | * |
4788da26 PW |
6 | * Paul Walmsley, Benoît Cousson, Kevin Hilman |
7 | * | |
8 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
9 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
10 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
74ff3a68 PW |
16 | * Introduction |
17 | * ------------ | |
18 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
19 | * IP blocks connected by interconnects. The IP blocks include | |
20 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
21 | * etc. Some of these devices, like the DSP, are created by TI; | |
22 | * others, like the SGX, largely originate from external vendors. In | |
23 | * TI's documentation, on-chip devices are referred to as "OMAP | |
24 | * modules." Some of these IP blocks are identical across several | |
25 | * OMAP versions. Others are revised frequently. | |
63c85238 | 26 | * |
74ff3a68 PW |
27 | * These OMAP modules are tied together by various interconnects. |
28 | * Most of the address and data flow between modules is via OCP-based | |
29 | * interconnects such as the L3 and L4 buses; but there are other | |
30 | * interconnects that distribute the hardware clock tree, handle idle | |
31 | * and reset signaling, supply power, and connect the modules to | |
32 | * various pads or balls on the OMAP package. | |
33 | * | |
34 | * OMAP hwmod provides a consistent way to describe the on-chip | |
35 | * hardware blocks and their integration into the rest of the chip. | |
36 | * This description can be automatically generated from the TI | |
37 | * hardware database. OMAP hwmod provides a standard, consistent API | |
38 | * to reset, enable, idle, and disable these hardware blocks. And | |
39 | * hwmod provides a way for other core code, such as the Linux device | |
40 | * code or the OMAP power management and address space mapping code, | |
41 | * to query the hardware database. | |
42 | * | |
43 | * Using hwmod | |
44 | * ----------- | |
45 | * Drivers won't call hwmod functions directly. That is done by the | |
46 | * omap_device code, and in rare occasions, by custom integration code | |
47 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
48 | * build a struct platform_device using omap_hwmod data, and that is | |
49 | * currently how hwmod data is communicated to drivers and to the | |
50 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
51 | * indirectly, via pm_runtime*() functions. | |
52 | * | |
53 | * From a layering perspective, here is where the OMAP hwmod code | |
54 | * fits into the kernel software stack: | |
55 | * | |
56 | * +-------------------------------+ | |
57 | * | Device driver code | | |
58 | * | (e.g., drivers/) | | |
59 | * +-------------------------------+ | |
60 | * | Linux driver model | | |
61 | * | (platform_device / | | |
62 | * | platform_driver data/code) | | |
63 | * +-------------------------------+ | |
64 | * | OMAP core-driver integration | | |
65 | * |(arch/arm/mach-omap2/devices.c)| | |
66 | * +-------------------------------+ | |
67 | * | omap_device code | | |
68 | * | (../plat-omap/omap_device.c) | | |
69 | * +-------------------------------+ | |
70 | * ----> | omap_hwmod code/data | <----- | |
71 | * | (../mach-omap2/omap_hwmod*) | | |
72 | * +-------------------------------+ | |
73 | * | OMAP clock/PRCM/register fns | | |
74 | * | (__raw_{read,write}l, clk*) | | |
75 | * +-------------------------------+ | |
76 | * | |
77 | * Device drivers should not contain any OMAP-specific code or data in | |
78 | * them. They should only contain code to operate the IP block that | |
79 | * the driver is responsible for. This is because these IP blocks can | |
80 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
81 | * other manufacturers; and drivers should be reusable across other | |
82 | * platforms. | |
83 | * | |
84 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
85 | * devices upon boot. The goal here is for the kernel to be | |
86 | * completely self-reliant and independent from bootloaders. This is | |
87 | * to ensure a repeatable configuration, both to ensure consistent | |
88 | * runtime behavior, and to make it easier for others to reproduce | |
89 | * bugs. | |
90 | * | |
91 | * OMAP module activity states | |
92 | * --------------------------- | |
93 | * The hwmod code considers modules to be in one of several activity | |
94 | * states. IP blocks start out in an UNKNOWN state, then once they | |
95 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
96 | * Once their clock names are resolved to clock pointers, the module | |
97 | * enters the CLKS_INITED state; and finally, once the module has been | |
98 | * reset and the integration registers programmed, the INITIALIZED state | |
99 | * is entered. The hwmod code will then place the module into either | |
100 | * the IDLE state to save power, or in the case of a critical system | |
101 | * module, the ENABLED state. | |
102 | * | |
103 | * OMAP core integration code can then call omap_hwmod*() functions | |
104 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
105 | * states, as needed. This is done during both the PM idle loop, and | |
106 | * in the OMAP core integration code's implementation of the PM runtime | |
107 | * functions. | |
108 | * | |
109 | * References | |
110 | * ---------- | |
111 | * This is a partial list. | |
63c85238 PW |
112 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
113 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
114 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
115 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
116 | * - Open Core Protocol Specification 2.2 | |
117 | * | |
118 | * To do: | |
119 | * - pin mux handling | |
120 | * - handle IO mapping | |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
133 | #include <linux/clk.h> | |
134 | #include <linux/delay.h> | |
135 | #include <linux/err.h> | |
136 | #include <linux/list.h> | |
137 | #include <linux/mutex.h> | |
63c85238 | 138 | |
6f8b7ff5 | 139 | #include <plat/common.h> |
ce491cf8 TL |
140 | #include <plat/cpu.h> |
141 | #include <plat/clockdomain.h> | |
142 | #include <plat/powerdomain.h> | |
143 | #include <plat/clock.h> | |
144 | #include <plat/omap_hwmod.h> | |
5365efbe | 145 | #include <plat/prcm.h> |
63c85238 PW |
146 | |
147 | #include "cm.h" | |
5365efbe | 148 | #include "prm.h" |
63c85238 | 149 | |
5365efbe BC |
150 | /* Maximum microseconds to wait for OMAP module to softreset */ |
151 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | |
63c85238 PW |
152 | |
153 | /* Name of the OMAP hwmod for the MPU */ | |
5c2c0296 | 154 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 PW |
155 | |
156 | /* omap_hwmod_list contains all registered struct omap_hwmods */ | |
157 | static LIST_HEAD(omap_hwmod_list); | |
158 | ||
159 | static DEFINE_MUTEX(omap_hwmod_mutex); | |
160 | ||
161 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ | |
162 | static struct omap_hwmod *mpu_oh; | |
163 | ||
164 | /* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */ | |
165 | static u8 inited; | |
166 | ||
167 | ||
168 | /* Private functions */ | |
169 | ||
170 | /** | |
171 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
172 | * @oh: struct omap_hwmod * | |
173 | * | |
174 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
175 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
176 | * OCP_SYSCONFIG register or 0 upon success. | |
177 | */ | |
178 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
179 | { | |
43b40992 PW |
180 | if (!oh->class->sysc) { |
181 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
182 | return -EINVAL; |
183 | } | |
184 | ||
185 | /* XXX ensure module interface clock is up */ | |
186 | ||
cc7a1d2a | 187 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 188 | |
43b40992 | 189 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 190 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
191 | |
192 | return 0; | |
193 | } | |
194 | ||
195 | /** | |
196 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
197 | * @v: OCP_SYSCONFIG value to write | |
198 | * @oh: struct omap_hwmod * | |
199 | * | |
43b40992 PW |
200 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
201 | * one. No return value. | |
63c85238 PW |
202 | */ |
203 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
204 | { | |
43b40992 PW |
205 | if (!oh->class->sysc) { |
206 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
207 | return; |
208 | } | |
209 | ||
210 | /* XXX ensure module interface clock is up */ | |
211 | ||
212 | if (oh->_sysc_cache != v) { | |
213 | oh->_sysc_cache = v; | |
cc7a1d2a | 214 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
215 | } |
216 | } | |
217 | ||
218 | /** | |
219 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
220 | * @oh: struct omap_hwmod * | |
221 | * @standbymode: MIDLEMODE field bits | |
222 | * @v: pointer to register contents to modify | |
223 | * | |
224 | * Update the master standby mode bits in @v to be @standbymode for | |
225 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
226 | * upon error or 0 upon success. | |
227 | */ | |
228 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
229 | u32 *v) | |
230 | { | |
358f0e63 TG |
231 | u32 mstandby_mask; |
232 | u8 mstandby_shift; | |
233 | ||
43b40992 PW |
234 | if (!oh->class->sysc || |
235 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
236 | return -EINVAL; |
237 | ||
43b40992 PW |
238 | if (!oh->class->sysc->sysc_fields) { |
239 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
240 | return -EINVAL; |
241 | } | |
242 | ||
43b40992 | 243 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
244 | mstandby_mask = (0x3 << mstandby_shift); |
245 | ||
246 | *v &= ~mstandby_mask; | |
247 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
248 | |
249 | return 0; | |
250 | } | |
251 | ||
252 | /** | |
253 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
254 | * @oh: struct omap_hwmod * | |
255 | * @idlemode: SIDLEMODE field bits | |
256 | * @v: pointer to register contents to modify | |
257 | * | |
258 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
259 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
260 | * or 0 upon success. | |
261 | */ | |
262 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
263 | { | |
358f0e63 TG |
264 | u32 sidle_mask; |
265 | u8 sidle_shift; | |
266 | ||
43b40992 PW |
267 | if (!oh->class->sysc || |
268 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
269 | return -EINVAL; |
270 | ||
43b40992 PW |
271 | if (!oh->class->sysc->sysc_fields) { |
272 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
273 | return -EINVAL; |
274 | } | |
275 | ||
43b40992 | 276 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
277 | sidle_mask = (0x3 << sidle_shift); |
278 | ||
279 | *v &= ~sidle_mask; | |
280 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
281 | |
282 | return 0; | |
283 | } | |
284 | ||
285 | /** | |
286 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
287 | * @oh: struct omap_hwmod * | |
288 | * @clockact: CLOCKACTIVITY field bits | |
289 | * @v: pointer to register contents to modify | |
290 | * | |
291 | * Update the clockactivity mode bits in @v to be @clockact for the | |
292 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
293 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
294 | * success. | |
295 | */ | |
296 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
297 | { | |
358f0e63 TG |
298 | u32 clkact_mask; |
299 | u8 clkact_shift; | |
300 | ||
43b40992 PW |
301 | if (!oh->class->sysc || |
302 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
303 | return -EINVAL; |
304 | ||
43b40992 PW |
305 | if (!oh->class->sysc->sysc_fields) { |
306 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
307 | return -EINVAL; |
308 | } | |
309 | ||
43b40992 | 310 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
311 | clkact_mask = (0x3 << clkact_shift); |
312 | ||
313 | *v &= ~clkact_mask; | |
314 | *v |= clockact << clkact_shift; | |
63c85238 PW |
315 | |
316 | return 0; | |
317 | } | |
318 | ||
319 | /** | |
320 | * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
321 | * @oh: struct omap_hwmod * | |
322 | * @v: pointer to register contents to modify | |
323 | * | |
324 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
325 | * error or 0 upon success. | |
326 | */ | |
327 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
328 | { | |
358f0e63 TG |
329 | u32 softrst_mask; |
330 | ||
43b40992 PW |
331 | if (!oh->class->sysc || |
332 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
333 | return -EINVAL; |
334 | ||
43b40992 PW |
335 | if (!oh->class->sysc->sysc_fields) { |
336 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
337 | return -EINVAL; |
338 | } | |
339 | ||
43b40992 | 340 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
341 | |
342 | *v |= softrst_mask; | |
63c85238 PW |
343 | |
344 | return 0; | |
345 | } | |
346 | ||
726072e5 PW |
347 | /** |
348 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
349 | * @oh: struct omap_hwmod * | |
350 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
351 | * @v: pointer to register contents to modify | |
352 | * | |
353 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
354 | * hwmod. The autoidle bit controls whether the module can gate | |
355 | * internal clocks automatically when it isn't doing anything; the | |
356 | * exact function of this bit varies on a per-module basis. This | |
357 | * function does not write to the hardware. Returns -EINVAL upon | |
358 | * error or 0 upon success. | |
359 | */ | |
360 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
361 | u32 *v) | |
362 | { | |
358f0e63 TG |
363 | u32 autoidle_mask; |
364 | u8 autoidle_shift; | |
365 | ||
43b40992 PW |
366 | if (!oh->class->sysc || |
367 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
368 | return -EINVAL; |
369 | ||
43b40992 PW |
370 | if (!oh->class->sysc->sysc_fields) { |
371 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
372 | return -EINVAL; |
373 | } | |
374 | ||
43b40992 | 375 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
358f0e63 TG |
376 | autoidle_mask = (0x3 << autoidle_shift); |
377 | ||
378 | *v &= ~autoidle_mask; | |
379 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
380 | |
381 | return 0; | |
382 | } | |
383 | ||
63c85238 PW |
384 | /** |
385 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
386 | * @oh: struct omap_hwmod * | |
387 | * | |
388 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
389 | * upon error or 0 upon success. | |
390 | */ | |
391 | static int _enable_wakeup(struct omap_hwmod *oh) | |
392 | { | |
358f0e63 | 393 | u32 v, wakeup_mask; |
63c85238 | 394 | |
43b40992 PW |
395 | if (!oh->class->sysc || |
396 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
397 | return -EINVAL; |
398 | ||
43b40992 PW |
399 | if (!oh->class->sysc->sysc_fields) { |
400 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
401 | return -EINVAL; |
402 | } | |
403 | ||
43b40992 | 404 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); |
358f0e63 | 405 | |
63c85238 | 406 | v = oh->_sysc_cache; |
358f0e63 | 407 | v |= wakeup_mask; |
63c85238 PW |
408 | _write_sysconfig(v, oh); |
409 | ||
410 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | |
411 | ||
412 | oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | /** | |
418 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
419 | * @oh: struct omap_hwmod * | |
420 | * | |
421 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
422 | * upon error or 0 upon success. | |
423 | */ | |
424 | static int _disable_wakeup(struct omap_hwmod *oh) | |
425 | { | |
358f0e63 | 426 | u32 v, wakeup_mask; |
63c85238 | 427 | |
43b40992 PW |
428 | if (!oh->class->sysc || |
429 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
430 | return -EINVAL; |
431 | ||
43b40992 PW |
432 | if (!oh->class->sysc->sysc_fields) { |
433 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
434 | return -EINVAL; |
435 | } | |
436 | ||
43b40992 | 437 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); |
358f0e63 | 438 | |
63c85238 | 439 | v = oh->_sysc_cache; |
358f0e63 | 440 | v &= ~wakeup_mask; |
63c85238 PW |
441 | _write_sysconfig(v, oh); |
442 | ||
443 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | |
444 | ||
445 | oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; | |
446 | ||
447 | return 0; | |
448 | } | |
449 | ||
450 | /** | |
451 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
452 | * @oh: struct omap_hwmod * | |
453 | * | |
454 | * Prevent the hardware module @oh from entering idle while the | |
455 | * hardare module initiator @init_oh is active. Useful when a module | |
456 | * will be accessed by a particular initiator (e.g., if a module will | |
457 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
458 | * initiator and the module). Only applies to modules in smart-idle | |
459 | * mode. Returns -EINVAL upon error or passes along | |
55ed9694 | 460 | * clkdm_add_sleepdep() value upon success. |
63c85238 PW |
461 | */ |
462 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
463 | { | |
464 | if (!oh->_clk) | |
465 | return -EINVAL; | |
466 | ||
55ed9694 | 467 | return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
468 | } |
469 | ||
470 | /** | |
471 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
472 | * @oh: struct omap_hwmod * | |
473 | * | |
474 | * Allow the hardware module @oh to enter idle while the hardare | |
475 | * module initiator @init_oh is active. Useful when a module will not | |
476 | * be accessed by a particular initiator (e.g., if a module will not | |
477 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
478 | * initiator and the module). Only applies to modules in smart-idle | |
479 | * mode. Returns -EINVAL upon error or passes along | |
55ed9694 | 480 | * clkdm_del_sleepdep() value upon success. |
63c85238 PW |
481 | */ |
482 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
483 | { | |
484 | if (!oh->_clk) | |
485 | return -EINVAL; | |
486 | ||
55ed9694 | 487 | return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
488 | } |
489 | ||
490 | /** | |
491 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
492 | * @oh: struct omap_hwmod * | |
493 | * | |
494 | * Called from _init_clocks(). Populates the @oh _clk (main | |
495 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
496 | * success or -EINVAL on error. | |
497 | */ | |
498 | static int _init_main_clk(struct omap_hwmod *oh) | |
499 | { | |
63c85238 PW |
500 | int ret = 0; |
501 | ||
50ebdac2 | 502 | if (!oh->main_clk) |
63c85238 PW |
503 | return 0; |
504 | ||
63403384 | 505 | oh->_clk = omap_clk_get_by_name(oh->main_clk); |
dc75925d | 506 | if (!oh->_clk) { |
20383d82 BC |
507 | pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
508 | oh->name, oh->main_clk); | |
63403384 | 509 | return -EINVAL; |
dc75925d | 510 | } |
63c85238 | 511 | |
63403384 BC |
512 | if (!oh->_clk->clkdm) |
513 | pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", | |
514 | oh->main_clk, oh->_clk->name); | |
81d7c6ff | 515 | |
63c85238 PW |
516 | return ret; |
517 | } | |
518 | ||
519 | /** | |
887adeac | 520 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
521 | * @oh: struct omap_hwmod * |
522 | * | |
523 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
524 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
525 | */ | |
526 | static int _init_interface_clks(struct omap_hwmod *oh) | |
527 | { | |
63c85238 PW |
528 | struct clk *c; |
529 | int i; | |
530 | int ret = 0; | |
531 | ||
532 | if (oh->slaves_cnt == 0) | |
533 | return 0; | |
534 | ||
682fdc96 BC |
535 | for (i = 0; i < oh->slaves_cnt; i++) { |
536 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
537 | ||
50ebdac2 | 538 | if (!os->clk) |
63c85238 PW |
539 | continue; |
540 | ||
50ebdac2 | 541 | c = omap_clk_get_by_name(os->clk); |
dc75925d | 542 | if (!c) { |
20383d82 BC |
543 | pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
544 | oh->name, os->clk); | |
63c85238 | 545 | ret = -EINVAL; |
dc75925d | 546 | } |
63c85238 PW |
547 | os->_clk = c; |
548 | } | |
549 | ||
550 | return ret; | |
551 | } | |
552 | ||
553 | /** | |
554 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
555 | * @oh: struct omap_hwmod * | |
556 | * | |
557 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
558 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
559 | */ | |
560 | static int _init_opt_clks(struct omap_hwmod *oh) | |
561 | { | |
562 | struct omap_hwmod_opt_clk *oc; | |
563 | struct clk *c; | |
564 | int i; | |
565 | int ret = 0; | |
566 | ||
567 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
50ebdac2 | 568 | c = omap_clk_get_by_name(oc->clk); |
dc75925d | 569 | if (!c) { |
20383d82 BC |
570 | pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
571 | oh->name, oc->clk); | |
63c85238 | 572 | ret = -EINVAL; |
dc75925d | 573 | } |
63c85238 PW |
574 | oc->_clk = c; |
575 | } | |
576 | ||
577 | return ret; | |
578 | } | |
579 | ||
580 | /** | |
581 | * _enable_clocks - enable hwmod main clock and interface clocks | |
582 | * @oh: struct omap_hwmod * | |
583 | * | |
584 | * Enables all clocks necessary for register reads and writes to succeed | |
585 | * on the hwmod @oh. Returns 0. | |
586 | */ | |
587 | static int _enable_clocks(struct omap_hwmod *oh) | |
588 | { | |
63c85238 PW |
589 | int i; |
590 | ||
591 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
592 | ||
4d3ae5a9 | 593 | if (oh->_clk) |
63c85238 PW |
594 | clk_enable(oh->_clk); |
595 | ||
596 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
597 | for (i = 0; i < oh->slaves_cnt; i++) { |
598 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
599 | struct clk *c = os->_clk; |
600 | ||
4d3ae5a9 | 601 | if (c && (os->flags & OCPIF_SWSUP_IDLE)) |
63c85238 PW |
602 | clk_enable(c); |
603 | } | |
604 | } | |
605 | ||
606 | /* The opt clocks are controlled by the device driver. */ | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
611 | /** | |
612 | * _disable_clocks - disable hwmod main clock and interface clocks | |
613 | * @oh: struct omap_hwmod * | |
614 | * | |
615 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
616 | */ | |
617 | static int _disable_clocks(struct omap_hwmod *oh) | |
618 | { | |
63c85238 PW |
619 | int i; |
620 | ||
621 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
622 | ||
4d3ae5a9 | 623 | if (oh->_clk) |
63c85238 PW |
624 | clk_disable(oh->_clk); |
625 | ||
626 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
627 | for (i = 0; i < oh->slaves_cnt; i++) { |
628 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
629 | struct clk *c = os->_clk; |
630 | ||
4d3ae5a9 | 631 | if (c && (os->flags & OCPIF_SWSUP_IDLE)) |
63c85238 PW |
632 | clk_disable(c); |
633 | } | |
634 | } | |
635 | ||
636 | /* The opt clocks are controlled by the device driver. */ | |
637 | ||
638 | return 0; | |
639 | } | |
640 | ||
96835af9 BC |
641 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
642 | { | |
643 | struct omap_hwmod_opt_clk *oc; | |
644 | int i; | |
645 | ||
646 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
647 | ||
648 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
649 | if (oc->_clk) { | |
650 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
651 | oc->_clk->name); | |
652 | clk_enable(oc->_clk); | |
653 | } | |
654 | } | |
655 | ||
656 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
657 | { | |
658 | struct omap_hwmod_opt_clk *oc; | |
659 | int i; | |
660 | ||
661 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
662 | ||
663 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
664 | if (oc->_clk) { | |
665 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
666 | oc->_clk->name); | |
667 | clk_disable(oc->_clk); | |
668 | } | |
669 | } | |
670 | ||
63c85238 PW |
671 | /** |
672 | * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use | |
673 | * @oh: struct omap_hwmod * | |
674 | * | |
675 | * Returns the array index of the OCP slave port that the MPU | |
676 | * addresses the device on, or -EINVAL upon error or not found. | |
677 | */ | |
678 | static int _find_mpu_port_index(struct omap_hwmod *oh) | |
679 | { | |
63c85238 PW |
680 | int i; |
681 | int found = 0; | |
682 | ||
683 | if (!oh || oh->slaves_cnt == 0) | |
684 | return -EINVAL; | |
685 | ||
682fdc96 BC |
686 | for (i = 0; i < oh->slaves_cnt; i++) { |
687 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
688 | ||
63c85238 PW |
689 | if (os->user & OCP_USER_MPU) { |
690 | found = 1; | |
691 | break; | |
692 | } | |
693 | } | |
694 | ||
695 | if (found) | |
696 | pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n", | |
697 | oh->name, i); | |
698 | else | |
699 | pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n", | |
700 | oh->name); | |
701 | ||
702 | return (found) ? i : -EINVAL; | |
703 | } | |
704 | ||
705 | /** | |
706 | * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU | |
707 | * @oh: struct omap_hwmod * | |
708 | * | |
709 | * Return the virtual address of the base of the register target of | |
710 | * device @oh, or NULL on error. | |
711 | */ | |
712 | static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) | |
713 | { | |
714 | struct omap_hwmod_ocp_if *os; | |
715 | struct omap_hwmod_addr_space *mem; | |
716 | int i; | |
717 | int found = 0; | |
986a13f5 | 718 | void __iomem *va_start; |
63c85238 PW |
719 | |
720 | if (!oh || oh->slaves_cnt == 0) | |
721 | return NULL; | |
722 | ||
682fdc96 | 723 | os = oh->slaves[index]; |
63c85238 PW |
724 | |
725 | for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) { | |
726 | if (mem->flags & ADDR_TYPE_RT) { | |
727 | found = 1; | |
728 | break; | |
729 | } | |
730 | } | |
731 | ||
986a13f5 TL |
732 | if (found) { |
733 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
734 | if (!va_start) { | |
735 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
736 | return NULL; | |
737 | } | |
63c85238 | 738 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", |
986a13f5 TL |
739 | oh->name, va_start); |
740 | } else { | |
63c85238 PW |
741 | pr_debug("omap_hwmod: %s: no MPU register target found\n", |
742 | oh->name); | |
986a13f5 | 743 | } |
63c85238 | 744 | |
986a13f5 | 745 | return (found) ? va_start : NULL; |
63c85238 PW |
746 | } |
747 | ||
748 | /** | |
74ff3a68 | 749 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
750 | * @oh: struct omap_hwmod * |
751 | * | |
752 | * If module is marked as SWSUP_SIDLE, force the module out of slave | |
753 | * idle; otherwise, configure it for smart-idle. If module is marked | |
754 | * as SWSUP_MSUSPEND, force the module out of master standby; | |
755 | * otherwise, configure it for smart-standby. No return value. | |
756 | */ | |
74ff3a68 | 757 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 758 | { |
43b40992 | 759 | u8 idlemode, sf; |
63c85238 PW |
760 | u32 v; |
761 | ||
43b40992 | 762 | if (!oh->class->sysc) |
63c85238 PW |
763 | return; |
764 | ||
765 | v = oh->_sysc_cache; | |
43b40992 | 766 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 767 | |
43b40992 | 768 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
769 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
770 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
771 | _set_slave_idlemode(oh, idlemode, &v); | |
772 | } | |
773 | ||
43b40992 | 774 | if (sf & SYSC_HAS_MIDLEMODE) { |
63c85238 PW |
775 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? |
776 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
777 | _set_master_standbymode(oh, idlemode, &v); | |
778 | } | |
779 | ||
a16b1f7f PW |
780 | /* |
781 | * XXX The clock framework should handle this, by | |
782 | * calling into this code. But this must wait until the | |
783 | * clock structures are tagged with omap_hwmod entries | |
784 | */ | |
43b40992 PW |
785 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
786 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
787 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 PW |
788 | |
789 | _write_sysconfig(v, oh); | |
9980ce53 RN |
790 | |
791 | /* If slave is in SMARTIDLE, also enable wakeup */ | |
792 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
793 | _enable_wakeup(oh); | |
78f26e87 HH |
794 | |
795 | /* | |
796 | * Set the autoidle bit only after setting the smartidle bit | |
797 | * Setting this will not have any impact on the other modules. | |
798 | */ | |
799 | if (sf & SYSC_HAS_AUTOIDLE) { | |
800 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
801 | 0 : 1; | |
802 | _set_module_autoidle(oh, idlemode, &v); | |
803 | _write_sysconfig(v, oh); | |
804 | } | |
63c85238 PW |
805 | } |
806 | ||
807 | /** | |
74ff3a68 | 808 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
809 | * @oh: struct omap_hwmod * |
810 | * | |
811 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
812 | * idle; otherwise, configure it for smart-idle. If module is marked | |
813 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
814 | * configure it for smart-standby. No return value. | |
815 | */ | |
74ff3a68 | 816 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 817 | { |
43b40992 | 818 | u8 idlemode, sf; |
63c85238 PW |
819 | u32 v; |
820 | ||
43b40992 | 821 | if (!oh->class->sysc) |
63c85238 PW |
822 | return; |
823 | ||
824 | v = oh->_sysc_cache; | |
43b40992 | 825 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 826 | |
43b40992 | 827 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
828 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
829 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | |
830 | _set_slave_idlemode(oh, idlemode, &v); | |
831 | } | |
832 | ||
43b40992 | 833 | if (sf & SYSC_HAS_MIDLEMODE) { |
63c85238 PW |
834 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? |
835 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | |
836 | _set_master_standbymode(oh, idlemode, &v); | |
837 | } | |
838 | ||
839 | _write_sysconfig(v, oh); | |
840 | } | |
841 | ||
842 | /** | |
74ff3a68 | 843 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
844 | * @oh: struct omap_hwmod * |
845 | * | |
846 | * Force the module into slave idle and master suspend. No return | |
847 | * value. | |
848 | */ | |
74ff3a68 | 849 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
850 | { |
851 | u32 v; | |
43b40992 | 852 | u8 sf; |
63c85238 | 853 | |
43b40992 | 854 | if (!oh->class->sysc) |
63c85238 PW |
855 | return; |
856 | ||
857 | v = oh->_sysc_cache; | |
43b40992 | 858 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 859 | |
43b40992 | 860 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
861 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
862 | ||
43b40992 | 863 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
864 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
865 | ||
43b40992 | 866 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 867 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
868 | |
869 | _write_sysconfig(v, oh); | |
870 | } | |
871 | ||
872 | /** | |
873 | * _lookup - find an omap_hwmod by name | |
874 | * @name: find an omap_hwmod by name | |
875 | * | |
876 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
877 | * Caller must hold omap_hwmod_mutex. | |
878 | */ | |
879 | static struct omap_hwmod *_lookup(const char *name) | |
880 | { | |
881 | struct omap_hwmod *oh, *temp_oh; | |
882 | ||
883 | oh = NULL; | |
884 | ||
885 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
886 | if (!strcmp(name, temp_oh->name)) { | |
887 | oh = temp_oh; | |
888 | break; | |
889 | } | |
890 | } | |
891 | ||
892 | return oh; | |
893 | } | |
894 | ||
895 | /** | |
896 | * _init_clocks - clk_get() all clocks associated with this hwmod | |
897 | * @oh: struct omap_hwmod * | |
97d60162 | 898 | * @data: not used; pass NULL |
63c85238 PW |
899 | * |
900 | * Called by omap_hwmod_late_init() (after omap2_clk_init()). | |
12b1fdb4 KH |
901 | * Resolves all clock names embedded in the hwmod. Returns -EINVAL if |
902 | * the omap_hwmod has not yet been registered or if the clocks have | |
903 | * already been initialized, 0 on success, or a non-zero error on | |
904 | * failure. | |
63c85238 | 905 | */ |
97d60162 | 906 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
907 | { |
908 | int ret = 0; | |
909 | ||
910 | if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED)) | |
911 | return -EINVAL; | |
912 | ||
913 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
914 | ||
915 | ret |= _init_main_clk(oh); | |
916 | ret |= _init_interface_clks(oh); | |
917 | ret |= _init_opt_clks(oh); | |
918 | ||
f5c1f84b BC |
919 | if (!ret) |
920 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
63c85238 | 921 | |
f5c1f84b | 922 | return 0; |
63c85238 PW |
923 | } |
924 | ||
925 | /** | |
926 | * _wait_target_ready - wait for a module to leave slave idle | |
927 | * @oh: struct omap_hwmod * | |
928 | * | |
929 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
930 | * does not have an IDLEST bit or if the module successfully leaves | |
931 | * slave idle; otherwise, pass along the return value of the | |
932 | * appropriate *_cm_wait_module_ready() function. | |
933 | */ | |
934 | static int _wait_target_ready(struct omap_hwmod *oh) | |
935 | { | |
936 | struct omap_hwmod_ocp_if *os; | |
937 | int ret; | |
938 | ||
939 | if (!oh) | |
940 | return -EINVAL; | |
941 | ||
942 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
943 | return 0; | |
944 | ||
682fdc96 | 945 | os = oh->slaves[oh->_mpu_port_index]; |
63c85238 | 946 | |
33f7ec81 | 947 | if (oh->flags & HWMOD_NO_IDLEST) |
63c85238 PW |
948 | return 0; |
949 | ||
950 | /* XXX check module SIDLEMODE */ | |
951 | ||
952 | /* XXX check clock enable states */ | |
953 | ||
954 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
955 | ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, | |
956 | oh->prcm.omap2.idlest_reg_id, | |
957 | oh->prcm.omap2.idlest_idle_bit); | |
63c85238 | 958 | } else if (cpu_is_omap44xx()) { |
9a23dfe1 | 959 | ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg); |
63c85238 PW |
960 | } else { |
961 | BUG(); | |
962 | }; | |
963 | ||
964 | return ret; | |
965 | } | |
966 | ||
5365efbe BC |
967 | /** |
968 | * _lookup_hardreset - return the register bit shift for this hwmod/reset line | |
969 | * @oh: struct omap_hwmod * | |
970 | * @name: name of the reset line in the context of this hwmod | |
971 | * | |
972 | * Return the bit position of the reset line that match the | |
973 | * input name. Return -ENOENT if not found. | |
974 | */ | |
975 | static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name) | |
976 | { | |
977 | int i; | |
978 | ||
979 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
980 | const char *rst_line = oh->rst_lines[i].name; | |
981 | if (!strcmp(rst_line, name)) { | |
982 | u8 shift = oh->rst_lines[i].rst_shift; | |
983 | pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n", | |
984 | oh->name, rst_line, shift); | |
985 | ||
986 | return shift; | |
987 | } | |
988 | } | |
989 | ||
990 | return -ENOENT; | |
991 | } | |
992 | ||
993 | /** | |
994 | * _assert_hardreset - assert the HW reset line of submodules | |
995 | * contained in the hwmod module. | |
996 | * @oh: struct omap_hwmod * | |
997 | * @name: name of the reset line to lookup and assert | |
998 | * | |
999 | * Some IP like dsp, ipu or iva contain processor that require | |
1000 | * an HW reset line to be assert / deassert in order to enable fully | |
1001 | * the IP. | |
1002 | */ | |
1003 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1004 | { | |
1005 | u8 shift; | |
1006 | ||
1007 | if (!oh) | |
1008 | return -EINVAL; | |
1009 | ||
1010 | shift = _lookup_hardreset(oh, name); | |
1011 | if (IS_ERR_VALUE(shift)) | |
1012 | return shift; | |
1013 | ||
1014 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1015 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | |
1016 | shift); | |
1017 | else if (cpu_is_omap44xx()) | |
1018 | return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg, | |
1019 | shift); | |
1020 | else | |
1021 | return -EINVAL; | |
1022 | } | |
1023 | ||
1024 | /** | |
1025 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1026 | * in the hwmod module. | |
1027 | * @oh: struct omap_hwmod * | |
1028 | * @name: name of the reset line to look up and deassert | |
1029 | * | |
1030 | * Some IP like dsp, ipu or iva contain processor that require | |
1031 | * an HW reset line to be assert / deassert in order to enable fully | |
1032 | * the IP. | |
1033 | */ | |
1034 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1035 | { | |
1036 | u8 shift; | |
1037 | int r; | |
1038 | ||
1039 | if (!oh) | |
1040 | return -EINVAL; | |
1041 | ||
1042 | shift = _lookup_hardreset(oh, name); | |
1043 | if (IS_ERR_VALUE(shift)) | |
1044 | return shift; | |
1045 | ||
1046 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1047 | r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | |
1048 | shift); | |
1049 | else if (cpu_is_omap44xx()) | |
1050 | r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg, | |
1051 | shift); | |
1052 | else | |
1053 | return -EINVAL; | |
1054 | ||
1055 | if (r == -EBUSY) | |
1056 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); | |
1057 | ||
1058 | return r; | |
1059 | } | |
1060 | ||
1061 | /** | |
1062 | * _read_hardreset - read the HW reset line state of submodules | |
1063 | * contained in the hwmod module | |
1064 | * @oh: struct omap_hwmod * | |
1065 | * @name: name of the reset line to look up and read | |
1066 | * | |
1067 | * Return the state of the reset line. | |
1068 | */ | |
1069 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1070 | { | |
1071 | u8 shift; | |
1072 | ||
1073 | if (!oh) | |
1074 | return -EINVAL; | |
1075 | ||
1076 | shift = _lookup_hardreset(oh, name); | |
1077 | if (IS_ERR_VALUE(shift)) | |
1078 | return shift; | |
1079 | ||
1080 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1081 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | |
1082 | shift); | |
1083 | } else if (cpu_is_omap44xx()) { | |
1084 | return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg, | |
1085 | shift); | |
1086 | } else { | |
1087 | return -EINVAL; | |
1088 | } | |
1089 | } | |
1090 | ||
63c85238 PW |
1091 | /** |
1092 | * _reset - reset an omap_hwmod | |
1093 | * @oh: struct omap_hwmod * | |
1094 | * | |
1095 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
12b1fdb4 KH |
1096 | * enabled for this to work. Returns -EINVAL if the hwmod cannot be |
1097 | * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if | |
1098 | * the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1099 | * |
1100 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
1101 | * Starting in OMAP4, some IPs does not have SYSSTATUS register and instead | |
1102 | * use the SYSCONFIG softreset bit to provide the status. | |
1103 | * | |
1104 | * Note that some IP like McBSP does have a reset control but no reset status. | |
63c85238 PW |
1105 | */ |
1106 | static int _reset(struct omap_hwmod *oh) | |
1107 | { | |
96835af9 | 1108 | u32 v; |
6f8b7ff5 | 1109 | int c = 0; |
96835af9 | 1110 | int ret = 0; |
63c85238 | 1111 | |
43b40992 | 1112 | if (!oh->class->sysc || |
2cb06814 | 1113 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
63c85238 PW |
1114 | return -EINVAL; |
1115 | ||
1116 | /* clocks must be on for this operation */ | |
1117 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
76e5589e BC |
1118 | pr_warning("omap_hwmod: %s: reset can only be entered from " |
1119 | "enabled state\n", oh->name); | |
63c85238 PW |
1120 | return -EINVAL; |
1121 | } | |
1122 | ||
96835af9 BC |
1123 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1124 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1125 | _enable_optional_clocks(oh); | |
1126 | ||
63c85238 PW |
1127 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); |
1128 | ||
1129 | v = oh->_sysc_cache; | |
96835af9 BC |
1130 | ret = _set_softreset(oh, &v); |
1131 | if (ret) | |
1132 | goto dis_opt_clks; | |
63c85238 PW |
1133 | _write_sysconfig(v, oh); |
1134 | ||
2cb06814 | 1135 | if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) |
cc7a1d2a | 1136 | omap_test_timeout((omap_hwmod_read(oh, |
2cb06814 BC |
1137 | oh->class->sysc->syss_offs) |
1138 | & SYSS_RESETDONE_MASK), | |
1139 | MAX_MODULE_SOFTRESET_WAIT, c); | |
1140 | else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) | |
cc7a1d2a | 1141 | omap_test_timeout(!(omap_hwmod_read(oh, |
2cb06814 BC |
1142 | oh->class->sysc->sysc_offs) |
1143 | & SYSC_TYPE2_SOFTRESET_MASK), | |
1144 | MAX_MODULE_SOFTRESET_WAIT, c); | |
63c85238 | 1145 | |
5365efbe | 1146 | if (c == MAX_MODULE_SOFTRESET_WAIT) |
76e5589e BC |
1147 | pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1148 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
63c85238 | 1149 | else |
5365efbe | 1150 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
63c85238 PW |
1151 | |
1152 | /* | |
1153 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1154 | * _wait_target_ready() or _reset() | |
1155 | */ | |
1156 | ||
96835af9 BC |
1157 | ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; |
1158 | ||
1159 | dis_opt_clks: | |
1160 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1161 | _disable_optional_clocks(oh); | |
1162 | ||
1163 | return ret; | |
63c85238 PW |
1164 | } |
1165 | ||
1166 | /** | |
84824022 | 1167 | * _omap_hwmod_enable - enable an omap_hwmod |
63c85238 PW |
1168 | * @oh: struct omap_hwmod * |
1169 | * | |
1170 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
74ff3a68 PW |
1171 | * register target. (This function has a full name -- |
1172 | * _omap_hwmod_enable() rather than simply _enable() -- because it is | |
1173 | * currently required by the pm34xx.c idle loop.) Returns -EINVAL if | |
1174 | * the hwmod is in the wrong state or passes along the return value of | |
1175 | * _wait_target_ready(). | |
63c85238 | 1176 | */ |
84824022 | 1177 | int _omap_hwmod_enable(struct omap_hwmod *oh) |
63c85238 PW |
1178 | { |
1179 | int r; | |
1180 | ||
1181 | if (oh->_state != _HWMOD_STATE_INITIALIZED && | |
1182 | oh->_state != _HWMOD_STATE_IDLE && | |
1183 | oh->_state != _HWMOD_STATE_DISABLED) { | |
1184 | WARN(1, "omap_hwmod: %s: enabled state can only be entered " | |
1185 | "from initialized, idle, or disabled state\n", oh->name); | |
1186 | return -EINVAL; | |
1187 | } | |
1188 | ||
1189 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); | |
1190 | ||
5365efbe BC |
1191 | /* |
1192 | * If an IP contains only one HW reset line, then de-assert it in order | |
1193 | * to allow to enable the clocks. Otherwise the PRCM will return | |
1194 | * Intransition status, and the init will failed. | |
1195 | */ | |
1196 | if ((oh->_state == _HWMOD_STATE_INITIALIZED || | |
1197 | oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) | |
1198 | _deassert_hardreset(oh, oh->rst_lines[0].name); | |
1199 | ||
63c85238 PW |
1200 | /* XXX mux balls */ |
1201 | ||
1202 | _add_initiator_dep(oh, mpu_oh); | |
1203 | _enable_clocks(oh); | |
1204 | ||
63c85238 | 1205 | r = _wait_target_ready(oh); |
9a23dfe1 | 1206 | if (!r) { |
63c85238 PW |
1207 | oh->_state = _HWMOD_STATE_ENABLED; |
1208 | ||
9a23dfe1 BC |
1209 | /* Access the sysconfig only if the target is ready */ |
1210 | if (oh->class->sysc) { | |
1211 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
1212 | _update_sysc_cache(oh); | |
74ff3a68 | 1213 | _enable_sysc(oh); |
9a23dfe1 BC |
1214 | } |
1215 | } else { | |
1216 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | |
1217 | oh->name, r); | |
1218 | } | |
1219 | ||
63c85238 PW |
1220 | return r; |
1221 | } | |
1222 | ||
1223 | /** | |
74ff3a68 | 1224 | * _omap_hwmod_idle - idle an omap_hwmod |
63c85238 PW |
1225 | * @oh: struct omap_hwmod * |
1226 | * | |
1227 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
74ff3a68 PW |
1228 | * no further work. (This function has a full name -- |
1229 | * _omap_hwmod_idle() rather than simply _idle() -- because it is | |
1230 | * currently required by the pm34xx.c idle loop.) Returns -EINVAL if | |
1231 | * the hwmod is in the wrong state or returns 0. | |
63c85238 | 1232 | */ |
84824022 | 1233 | int _omap_hwmod_idle(struct omap_hwmod *oh) |
63c85238 PW |
1234 | { |
1235 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
1236 | WARN(1, "omap_hwmod: %s: idle state can only be entered from " | |
1237 | "enabled state\n", oh->name); | |
1238 | return -EINVAL; | |
1239 | } | |
1240 | ||
1241 | pr_debug("omap_hwmod: %s: idling\n", oh->name); | |
1242 | ||
43b40992 | 1243 | if (oh->class->sysc) |
74ff3a68 | 1244 | _idle_sysc(oh); |
63c85238 PW |
1245 | _del_initiator_dep(oh, mpu_oh); |
1246 | _disable_clocks(oh); | |
1247 | ||
1248 | oh->_state = _HWMOD_STATE_IDLE; | |
1249 | ||
1250 | return 0; | |
1251 | } | |
1252 | ||
1253 | /** | |
1254 | * _shutdown - shutdown an omap_hwmod | |
1255 | * @oh: struct omap_hwmod * | |
1256 | * | |
1257 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
1258 | * used for the hwmod is removed or unloaded or if the driver is not | |
1259 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
1260 | * state or returns 0. | |
1261 | */ | |
1262 | static int _shutdown(struct omap_hwmod *oh) | |
1263 | { | |
1264 | if (oh->_state != _HWMOD_STATE_IDLE && | |
1265 | oh->_state != _HWMOD_STATE_ENABLED) { | |
1266 | WARN(1, "omap_hwmod: %s: disabled state can only be entered " | |
1267 | "from idle, or enabled state\n", oh->name); | |
1268 | return -EINVAL; | |
1269 | } | |
1270 | ||
1271 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); | |
1272 | ||
43b40992 | 1273 | if (oh->class->sysc) |
74ff3a68 | 1274 | _shutdown_sysc(oh); |
3827f949 | 1275 | |
5365efbe BC |
1276 | /* |
1277 | * If an IP contains only one HW reset line, then assert it | |
1278 | * before disabling the clocks and shutting down the IP. | |
1279 | */ | |
1280 | if (oh->rst_lines_cnt == 1) | |
1281 | _assert_hardreset(oh, oh->rst_lines[0].name); | |
1282 | ||
3827f949 BC |
1283 | /* clocks and deps are already disabled in idle */ |
1284 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
1285 | _del_initiator_dep(oh, mpu_oh); | |
1286 | /* XXX what about the other system initiators here? dma, dsp */ | |
1287 | _disable_clocks(oh); | |
1288 | } | |
63c85238 PW |
1289 | /* XXX Should this code also force-disable the optional clocks? */ |
1290 | ||
1291 | /* XXX mux any associated balls to safe mode */ | |
1292 | ||
1293 | oh->_state = _HWMOD_STATE_DISABLED; | |
1294 | ||
1295 | return 0; | |
1296 | } | |
1297 | ||
63c85238 PW |
1298 | /** |
1299 | * _setup - do initial configuration of omap_hwmod | |
1300 | * @oh: struct omap_hwmod * | |
97d60162 | 1301 | * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1 |
63c85238 PW |
1302 | * |
1303 | * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh | |
12b1fdb4 KH |
1304 | * OCP_SYSCONFIG register. @skip_setup_idle is intended to be used on |
1305 | * a system that will not call omap_hwmod_enable() to enable devices | |
1306 | * (e.g., a system without PM runtime). Returns -EINVAL if the hwmod | |
1307 | * is in the wrong state or returns 0. | |
63c85238 | 1308 | */ |
97d60162 | 1309 | static int _setup(struct omap_hwmod *oh, void *data) |
63c85238 | 1310 | { |
9a23dfe1 | 1311 | int i, r; |
97d60162 | 1312 | u8 skip_setup_idle; |
63c85238 | 1313 | |
97d60162 | 1314 | if (!oh || !data) |
63c85238 PW |
1315 | return -EINVAL; |
1316 | ||
97d60162 PW |
1317 | skip_setup_idle = *(u8 *)data; |
1318 | ||
63c85238 PW |
1319 | /* Set iclk autoidle mode */ |
1320 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
1321 | for (i = 0; i < oh->slaves_cnt; i++) { |
1322 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
1323 | struct clk *c = os->_clk; |
1324 | ||
4d3ae5a9 | 1325 | if (!c) |
63c85238 PW |
1326 | continue; |
1327 | ||
1328 | if (os->flags & OCPIF_SWSUP_IDLE) { | |
1329 | /* XXX omap_iclk_deny_idle(c); */ | |
1330 | } else { | |
1331 | /* XXX omap_iclk_allow_idle(c); */ | |
1332 | clk_enable(c); | |
1333 | } | |
1334 | } | |
1335 | } | |
1336 | ||
12b1fdb4 | 1337 | mutex_init(&oh->_mutex); |
63c85238 PW |
1338 | oh->_state = _HWMOD_STATE_INITIALIZED; |
1339 | ||
5365efbe BC |
1340 | /* |
1341 | * In the case of hwmod with hardreset that should not be | |
1342 | * de-assert at boot time, we have to keep the module | |
1343 | * initialized, because we cannot enable it properly with the | |
1344 | * reset asserted. Exit without warning because that behavior is | |
1345 | * expected. | |
1346 | */ | |
1347 | if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) | |
1348 | return 0; | |
1349 | ||
84824022 | 1350 | r = _omap_hwmod_enable(oh); |
9a23dfe1 BC |
1351 | if (r) { |
1352 | pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", | |
1353 | oh->name, oh->_state); | |
1354 | return 0; | |
1355 | } | |
63c85238 | 1356 | |
b835d014 | 1357 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) { |
76e5589e BC |
1358 | _reset(oh); |
1359 | ||
b835d014 | 1360 | /* |
76e5589e BC |
1361 | * OCP_SYSCONFIG bits need to be reprogrammed after a softreset. |
1362 | * The _omap_hwmod_enable() function should be split to | |
1363 | * avoid the rewrite of the OCP_SYSCONFIG register. | |
b835d014 | 1364 | */ |
43b40992 | 1365 | if (oh->class->sysc) { |
b835d014 | 1366 | _update_sysc_cache(oh); |
74ff3a68 | 1367 | _enable_sysc(oh); |
b835d014 PW |
1368 | } |
1369 | } | |
63c85238 | 1370 | |
97d60162 | 1371 | if (!(oh->flags & HWMOD_INIT_NO_IDLE) && !skip_setup_idle) |
84824022 | 1372 | _omap_hwmod_idle(oh); |
63c85238 PW |
1373 | |
1374 | return 0; | |
1375 | } | |
1376 | ||
1377 | ||
1378 | ||
1379 | /* Public functions */ | |
1380 | ||
cc7a1d2a | 1381 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) |
63c85238 | 1382 | { |
cc7a1d2a RN |
1383 | if (oh->flags & HWMOD_16BIT_REG) |
1384 | return __raw_readw(oh->_mpu_rt_va + reg_offs); | |
1385 | else | |
1386 | return __raw_readl(oh->_mpu_rt_va + reg_offs); | |
63c85238 PW |
1387 | } |
1388 | ||
cc7a1d2a | 1389 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) |
63c85238 | 1390 | { |
cc7a1d2a RN |
1391 | if (oh->flags & HWMOD_16BIT_REG) |
1392 | __raw_writew(v, oh->_mpu_rt_va + reg_offs); | |
1393 | else | |
1394 | __raw_writel(v, oh->_mpu_rt_va + reg_offs); | |
63c85238 PW |
1395 | } |
1396 | ||
887adeac PW |
1397 | /** |
1398 | * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode | |
1399 | * @oh: struct omap_hwmod * | |
1400 | * @idlemode: SIDLEMODE field bits (shifted to bit 0) | |
1401 | * | |
1402 | * Sets the IP block's OCP slave idlemode in hardware, and updates our | |
1403 | * local copy. Intended to be used by drivers that have some erratum | |
1404 | * that requires direct manipulation of the SIDLEMODE bits. Returns | |
1405 | * -EINVAL if @oh is null, or passes along the return value from | |
1406 | * _set_slave_idlemode(). | |
1407 | * | |
1408 | * XXX Does this function have any current users? If not, we should | |
1409 | * remove it; it is better to let the rest of the hwmod code handle this. | |
1410 | * Any users of this function should be scrutinized carefully. | |
1411 | */ | |
46273e6f KH |
1412 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) |
1413 | { | |
1414 | u32 v; | |
1415 | int retval = 0; | |
1416 | ||
1417 | if (!oh) | |
1418 | return -EINVAL; | |
1419 | ||
1420 | v = oh->_sysc_cache; | |
1421 | ||
1422 | retval = _set_slave_idlemode(oh, idlemode, &v); | |
1423 | if (!retval) | |
1424 | _write_sysconfig(v, oh); | |
1425 | ||
1426 | return retval; | |
1427 | } | |
1428 | ||
63c85238 PW |
1429 | /** |
1430 | * omap_hwmod_register - register a struct omap_hwmod | |
1431 | * @oh: struct omap_hwmod * | |
1432 | * | |
43b40992 PW |
1433 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
1434 | * already has been registered by the same name; -EINVAL if the | |
1435 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
1436 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
1437 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
1438 | * success. | |
63c85238 PW |
1439 | * |
1440 | * XXX The data should be copied into bootmem, so the original data | |
1441 | * should be marked __initdata and freed after init. This would allow | |
1442 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
1443 | * that the copy process would be relatively complex due to the large number | |
1444 | * of substructures. | |
1445 | */ | |
1446 | int omap_hwmod_register(struct omap_hwmod *oh) | |
1447 | { | |
1448 | int ret, ms_id; | |
1449 | ||
43b40992 PW |
1450 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
1451 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
1452 | return -EINVAL; |
1453 | ||
1454 | mutex_lock(&omap_hwmod_mutex); | |
1455 | ||
1456 | pr_debug("omap_hwmod: %s: registering\n", oh->name); | |
1457 | ||
1458 | if (_lookup(oh->name)) { | |
1459 | ret = -EEXIST; | |
1460 | goto ohr_unlock; | |
1461 | } | |
1462 | ||
1463 | ms_id = _find_mpu_port_index(oh); | |
1464 | if (!IS_ERR_VALUE(ms_id)) { | |
1465 | oh->_mpu_port_index = ms_id; | |
db2a60bf | 1466 | oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); |
63c85238 PW |
1467 | } else { |
1468 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
1469 | } | |
1470 | ||
1471 | list_add_tail(&oh->node, &omap_hwmod_list); | |
1472 | ||
1473 | oh->_state = _HWMOD_STATE_REGISTERED; | |
1474 | ||
1475 | ret = 0; | |
1476 | ||
1477 | ohr_unlock: | |
1478 | mutex_unlock(&omap_hwmod_mutex); | |
1479 | return ret; | |
1480 | } | |
1481 | ||
1482 | /** | |
1483 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
1484 | * @name: name of the omap_hwmod to look up | |
1485 | * | |
1486 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
1487 | * struct omap_hwmod *, or NULL upon error. | |
1488 | */ | |
1489 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
1490 | { | |
1491 | struct omap_hwmod *oh; | |
1492 | ||
1493 | if (!name) | |
1494 | return NULL; | |
1495 | ||
1496 | mutex_lock(&omap_hwmod_mutex); | |
1497 | oh = _lookup(name); | |
1498 | mutex_unlock(&omap_hwmod_mutex); | |
1499 | ||
1500 | return oh; | |
1501 | } | |
1502 | ||
1503 | /** | |
1504 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
1505 | * @fn: pointer to a callback function | |
97d60162 | 1506 | * @data: void * data to pass to callback function |
63c85238 PW |
1507 | * |
1508 | * Call @fn for each registered omap_hwmod, passing @data to each | |
1509 | * function. @fn must return 0 for success or any other value for | |
1510 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
1511 | * will stop and the non-zero return value will be passed to the | |
1512 | * caller of omap_hwmod_for_each(). @fn is called with | |
1513 | * omap_hwmod_for_each() held. | |
1514 | */ | |
97d60162 PW |
1515 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
1516 | void *data) | |
63c85238 PW |
1517 | { |
1518 | struct omap_hwmod *temp_oh; | |
1519 | int ret; | |
1520 | ||
1521 | if (!fn) | |
1522 | return -EINVAL; | |
1523 | ||
1524 | mutex_lock(&omap_hwmod_mutex); | |
1525 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
97d60162 | 1526 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
1527 | if (ret) |
1528 | break; | |
1529 | } | |
1530 | mutex_unlock(&omap_hwmod_mutex); | |
1531 | ||
1532 | return ret; | |
1533 | } | |
1534 | ||
1535 | ||
1536 | /** | |
1537 | * omap_hwmod_init - init omap_hwmod code and register hwmods | |
1538 | * @ohs: pointer to an array of omap_hwmods to register | |
1539 | * | |
1540 | * Intended to be called early in boot before the clock framework is | |
1541 | * initialized. If @ohs is not null, will register all omap_hwmods | |
1542 | * listed in @ohs that are valid for this chip. Returns -EINVAL if | |
1543 | * omap_hwmod_init() has already been called or 0 otherwise. | |
1544 | */ | |
1545 | int omap_hwmod_init(struct omap_hwmod **ohs) | |
1546 | { | |
1547 | struct omap_hwmod *oh; | |
1548 | int r; | |
1549 | ||
1550 | if (inited) | |
1551 | return -EINVAL; | |
1552 | ||
1553 | inited = 1; | |
1554 | ||
1555 | if (!ohs) | |
1556 | return 0; | |
1557 | ||
1558 | oh = *ohs; | |
1559 | while (oh) { | |
1560 | if (omap_chip_is(oh->omap_chip)) { | |
1561 | r = omap_hwmod_register(oh); | |
1562 | WARN(r, "omap_hwmod: %s: omap_hwmod_register returned " | |
1563 | "%d\n", oh->name, r); | |
1564 | } | |
1565 | oh = *++ohs; | |
1566 | } | |
1567 | ||
1568 | return 0; | |
1569 | } | |
1570 | ||
1571 | /** | |
1572 | * omap_hwmod_late_init - do some post-clock framework initialization | |
97d60162 | 1573 | * @skip_setup_idle: if 1, do not idle hwmods in _setup() |
63c85238 PW |
1574 | * |
1575 | * Must be called after omap2_clk_init(). Resolves the struct clk names | |
1576 | * to struct clk pointers for each registered omap_hwmod. Also calls | |
1577 | * _setup() on each hwmod. Returns 0. | |
1578 | */ | |
97d60162 | 1579 | int omap_hwmod_late_init(u8 skip_setup_idle) |
63c85238 PW |
1580 | { |
1581 | int r; | |
1582 | ||
1583 | /* XXX check return value */ | |
97d60162 | 1584 | r = omap_hwmod_for_each(_init_clocks, NULL); |
63c85238 PW |
1585 | WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); |
1586 | ||
1587 | mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); | |
1588 | WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", | |
1589 | MPU_INITIATOR_NAME); | |
1590 | ||
97d60162 PW |
1591 | if (skip_setup_idle) |
1592 | pr_debug("omap_hwmod: will leave hwmods enabled during setup\n"); | |
1593 | ||
1594 | omap_hwmod_for_each(_setup, &skip_setup_idle); | |
63c85238 PW |
1595 | |
1596 | return 0; | |
1597 | } | |
1598 | ||
1599 | /** | |
1600 | * omap_hwmod_unregister - unregister an omap_hwmod | |
1601 | * @oh: struct omap_hwmod * | |
1602 | * | |
1603 | * Unregisters a previously-registered omap_hwmod @oh. There's probably | |
1604 | * no use case for this, so it is likely to be removed in a later version. | |
1605 | * | |
1606 | * XXX Free all of the bootmem-allocated structures here when that is | |
1607 | * implemented. Make it clear that core code is the only code that is | |
1608 | * expected to unregister modules. | |
1609 | */ | |
1610 | int omap_hwmod_unregister(struct omap_hwmod *oh) | |
1611 | { | |
1612 | if (!oh) | |
1613 | return -EINVAL; | |
1614 | ||
1615 | pr_debug("omap_hwmod: %s: unregistering\n", oh->name); | |
1616 | ||
1617 | mutex_lock(&omap_hwmod_mutex); | |
db2a60bf | 1618 | iounmap(oh->_mpu_rt_va); |
63c85238 PW |
1619 | list_del(&oh->node); |
1620 | mutex_unlock(&omap_hwmod_mutex); | |
1621 | ||
1622 | return 0; | |
1623 | } | |
1624 | ||
1625 | /** | |
1626 | * omap_hwmod_enable - enable an omap_hwmod | |
1627 | * @oh: struct omap_hwmod * | |
1628 | * | |
74ff3a68 | 1629 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
1630 | * Returns -EINVAL on error or passes along the return value from _enable(). |
1631 | */ | |
1632 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
1633 | { | |
1634 | int r; | |
1635 | ||
1636 | if (!oh) | |
1637 | return -EINVAL; | |
1638 | ||
12b1fdb4 | 1639 | mutex_lock(&oh->_mutex); |
84824022 | 1640 | r = _omap_hwmod_enable(oh); |
12b1fdb4 | 1641 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1642 | |
1643 | return r; | |
1644 | } | |
1645 | ||
84824022 | 1646 | |
63c85238 PW |
1647 | /** |
1648 | * omap_hwmod_idle - idle an omap_hwmod | |
1649 | * @oh: struct omap_hwmod * | |
1650 | * | |
74ff3a68 | 1651 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
1652 | * Returns -EINVAL on error or passes along the return value from _idle(). |
1653 | */ | |
1654 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
1655 | { | |
1656 | if (!oh) | |
1657 | return -EINVAL; | |
1658 | ||
12b1fdb4 | 1659 | mutex_lock(&oh->_mutex); |
84824022 | 1660 | _omap_hwmod_idle(oh); |
12b1fdb4 | 1661 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1662 | |
1663 | return 0; | |
1664 | } | |
1665 | ||
1666 | /** | |
1667 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
1668 | * @oh: struct omap_hwmod * | |
1669 | * | |
74ff3a68 | 1670 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
1671 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
1672 | * the return value from _shutdown(). | |
1673 | */ | |
1674 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
1675 | { | |
1676 | if (!oh) | |
1677 | return -EINVAL; | |
1678 | ||
12b1fdb4 | 1679 | mutex_lock(&oh->_mutex); |
63c85238 | 1680 | _shutdown(oh); |
12b1fdb4 | 1681 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1682 | |
1683 | return 0; | |
1684 | } | |
1685 | ||
1686 | /** | |
1687 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
1688 | * @oh: struct omap_hwmod *oh | |
1689 | * | |
1690 | * Intended to be called by the omap_device code. | |
1691 | */ | |
1692 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
1693 | { | |
12b1fdb4 | 1694 | mutex_lock(&oh->_mutex); |
63c85238 | 1695 | _enable_clocks(oh); |
12b1fdb4 | 1696 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1697 | |
1698 | return 0; | |
1699 | } | |
1700 | ||
1701 | /** | |
1702 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
1703 | * @oh: struct omap_hwmod *oh | |
1704 | * | |
1705 | * Intended to be called by the omap_device code. | |
1706 | */ | |
1707 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
1708 | { | |
12b1fdb4 | 1709 | mutex_lock(&oh->_mutex); |
63c85238 | 1710 | _disable_clocks(oh); |
12b1fdb4 | 1711 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1712 | |
1713 | return 0; | |
1714 | } | |
1715 | ||
1716 | /** | |
1717 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
1718 | * @oh: struct omap_hwmod *oh | |
1719 | * | |
1720 | * Intended to be called by drivers and core code when all posted | |
1721 | * writes to a device must complete before continuing further | |
1722 | * execution (for example, after clearing some device IRQSTATUS | |
1723 | * register bits) | |
1724 | * | |
1725 | * XXX what about targets with multiple OCP threads? | |
1726 | */ | |
1727 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
1728 | { | |
1729 | BUG_ON(!oh); | |
1730 | ||
43b40992 | 1731 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
63c85238 PW |
1732 | WARN(1, "omap_device: %s: OCP barrier impossible due to " |
1733 | "device configuration\n", oh->name); | |
1734 | return; | |
1735 | } | |
1736 | ||
1737 | /* | |
1738 | * Forces posted writes to complete on the OCP thread handling | |
1739 | * register writes | |
1740 | */ | |
cc7a1d2a | 1741 | omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
1742 | } |
1743 | ||
1744 | /** | |
1745 | * omap_hwmod_reset - reset the hwmod | |
1746 | * @oh: struct omap_hwmod * | |
1747 | * | |
1748 | * Under some conditions, a driver may wish to reset the entire device. | |
1749 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 1750 | * the return value from _reset(). |
63c85238 PW |
1751 | */ |
1752 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
1753 | { | |
1754 | int r; | |
1755 | ||
9b579114 | 1756 | if (!oh) |
63c85238 PW |
1757 | return -EINVAL; |
1758 | ||
12b1fdb4 | 1759 | mutex_lock(&oh->_mutex); |
63c85238 | 1760 | r = _reset(oh); |
12b1fdb4 | 1761 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1762 | |
1763 | return r; | |
1764 | } | |
1765 | ||
1766 | /** | |
1767 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
1768 | * @oh: struct omap_hwmod * | |
1769 | * @res: pointer to the first element of an array of struct resource to fill | |
1770 | * | |
1771 | * Count the number of struct resource array elements necessary to | |
1772 | * contain omap_hwmod @oh resources. Intended to be called by code | |
1773 | * that registers omap_devices. Intended to be used to determine the | |
1774 | * size of a dynamically-allocated struct resource array, before | |
1775 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
1776 | * resource array elements needed. | |
1777 | * | |
1778 | * XXX This code is not optimized. It could attempt to merge adjacent | |
1779 | * resource IDs. | |
1780 | * | |
1781 | */ | |
1782 | int omap_hwmod_count_resources(struct omap_hwmod *oh) | |
1783 | { | |
1784 | int ret, i; | |
1785 | ||
9ee9fff9 | 1786 | ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt; |
63c85238 PW |
1787 | |
1788 | for (i = 0; i < oh->slaves_cnt; i++) | |
682fdc96 | 1789 | ret += oh->slaves[i]->addr_cnt; |
63c85238 PW |
1790 | |
1791 | return ret; | |
1792 | } | |
1793 | ||
1794 | /** | |
1795 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
1796 | * @oh: struct omap_hwmod * | |
1797 | * @res: pointer to the first element of an array of struct resource to fill | |
1798 | * | |
1799 | * Fill the struct resource array @res with resource data from the | |
1800 | * omap_hwmod @oh. Intended to be called by code that registers | |
1801 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
1802 | * number of array elements filled. | |
1803 | */ | |
1804 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
1805 | { | |
1806 | int i, j; | |
1807 | int r = 0; | |
1808 | ||
1809 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
1810 | ||
1811 | for (i = 0; i < oh->mpu_irqs_cnt; i++) { | |
718bfd76 PW |
1812 | (res + r)->name = (oh->mpu_irqs + i)->name; |
1813 | (res + r)->start = (oh->mpu_irqs + i)->irq; | |
1814 | (res + r)->end = (oh->mpu_irqs + i)->irq; | |
63c85238 PW |
1815 | (res + r)->flags = IORESOURCE_IRQ; |
1816 | r++; | |
1817 | } | |
1818 | ||
9ee9fff9 BC |
1819 | for (i = 0; i < oh->sdma_reqs_cnt; i++) { |
1820 | (res + r)->name = (oh->sdma_reqs + i)->name; | |
1821 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
1822 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
1823 | (res + r)->flags = IORESOURCE_DMA; |
1824 | r++; | |
1825 | } | |
1826 | ||
1827 | for (i = 0; i < oh->slaves_cnt; i++) { | |
1828 | struct omap_hwmod_ocp_if *os; | |
1829 | ||
682fdc96 | 1830 | os = oh->slaves[i]; |
63c85238 PW |
1831 | |
1832 | for (j = 0; j < os->addr_cnt; j++) { | |
1833 | (res + r)->start = (os->addr + j)->pa_start; | |
1834 | (res + r)->end = (os->addr + j)->pa_end; | |
1835 | (res + r)->flags = IORESOURCE_MEM; | |
1836 | r++; | |
1837 | } | |
1838 | } | |
1839 | ||
1840 | return r; | |
1841 | } | |
1842 | ||
1843 | /** | |
1844 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
1845 | * @oh: struct omap_hwmod * | |
1846 | * | |
1847 | * Return the powerdomain pointer associated with the OMAP module | |
1848 | * @oh's main clock. If @oh does not have a main clk, return the | |
1849 | * powerdomain associated with the interface clock associated with the | |
1850 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
1851 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
1852 | * success. | |
1853 | */ | |
1854 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
1855 | { | |
1856 | struct clk *c; | |
1857 | ||
1858 | if (!oh) | |
1859 | return NULL; | |
1860 | ||
1861 | if (oh->_clk) { | |
1862 | c = oh->_clk; | |
1863 | } else { | |
1864 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
1865 | return NULL; | |
1866 | c = oh->slaves[oh->_mpu_port_index]->_clk; | |
1867 | } | |
1868 | ||
d5647c18 TG |
1869 | if (!c->clkdm) |
1870 | return NULL; | |
1871 | ||
63c85238 PW |
1872 | return c->clkdm->pwrdm.ptr; |
1873 | ||
1874 | } | |
1875 | ||
db2a60bf PW |
1876 | /** |
1877 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
1878 | * @oh: struct omap_hwmod * | |
1879 | * | |
1880 | * Returns the virtual address corresponding to the beginning of the | |
1881 | * module's register target, in the address range that is intended to | |
1882 | * be used by the MPU. Returns the virtual address upon success or NULL | |
1883 | * upon error. | |
1884 | */ | |
1885 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
1886 | { | |
1887 | if (!oh) | |
1888 | return NULL; | |
1889 | ||
1890 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
1891 | return NULL; | |
1892 | ||
1893 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
1894 | return NULL; | |
1895 | ||
1896 | return oh->_mpu_rt_va; | |
1897 | } | |
1898 | ||
63c85238 PW |
1899 | /** |
1900 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
1901 | * @oh: struct omap_hwmod * | |
1902 | * @init_oh: struct omap_hwmod * (initiator) | |
1903 | * | |
1904 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
1905 | * Intended to be called by DSP/Bridge code via platform_data for the | |
1906 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
1907 | * code needs to add/del initiator dependencies dynamically | |
1908 | * before/after accessing a device. Returns the return value from | |
1909 | * _add_initiator_dep(). | |
1910 | * | |
1911 | * XXX Keep a usecount in the clockdomain code | |
1912 | */ | |
1913 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
1914 | struct omap_hwmod *init_oh) | |
1915 | { | |
1916 | return _add_initiator_dep(oh, init_oh); | |
1917 | } | |
1918 | ||
1919 | /* | |
1920 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
1921 | * for context save/restore operations? | |
1922 | */ | |
1923 | ||
1924 | /** | |
1925 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
1926 | * @oh: struct omap_hwmod * | |
1927 | * @init_oh: struct omap_hwmod * (initiator) | |
1928 | * | |
1929 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
1930 | * Intended to be called by DSP/Bridge code via platform_data for the | |
1931 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
1932 | * code needs to add/del initiator dependencies dynamically | |
1933 | * before/after accessing a device. Returns the return value from | |
1934 | * _del_initiator_dep(). | |
1935 | * | |
1936 | * XXX Keep a usecount in the clockdomain code | |
1937 | */ | |
1938 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
1939 | struct omap_hwmod *init_oh) | |
1940 | { | |
1941 | return _del_initiator_dep(oh, init_oh); | |
1942 | } | |
1943 | ||
63c85238 PW |
1944 | /** |
1945 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
1946 | * @oh: struct omap_hwmod * | |
1947 | * | |
1948 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
1949 | * send wakeups to the PRCM. Eventually this should sets PRCM wakeup | |
1950 | * registers to cause the PRCM to receive wakeup events from the | |
1951 | * module. Does not set any wakeup routing registers beyond this | |
1952 | * point - if the module is to wake up any other module or subsystem, | |
1953 | * that must be set separately. Called by omap_device code. Returns | |
1954 | * -EINVAL on error or 0 upon success. | |
1955 | */ | |
1956 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
1957 | { | |
43b40992 PW |
1958 | if (!oh->class->sysc || |
1959 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
1960 | return -EINVAL; |
1961 | ||
12b1fdb4 | 1962 | mutex_lock(&oh->_mutex); |
63c85238 | 1963 | _enable_wakeup(oh); |
12b1fdb4 | 1964 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1965 | |
1966 | return 0; | |
1967 | } | |
1968 | ||
1969 | /** | |
1970 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
1971 | * @oh: struct omap_hwmod * | |
1972 | * | |
1973 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
1974 | * from sending wakeups to the PRCM. Eventually this should clear | |
1975 | * PRCM wakeup registers to cause the PRCM to ignore wakeup events | |
1976 | * from the module. Does not set any wakeup routing registers beyond | |
1977 | * this point - if the module is to wake up any other module or | |
1978 | * subsystem, that must be set separately. Called by omap_device | |
1979 | * code. Returns -EINVAL on error or 0 upon success. | |
1980 | */ | |
1981 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
1982 | { | |
43b40992 PW |
1983 | if (!oh->class->sysc || |
1984 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
1985 | return -EINVAL; |
1986 | ||
12b1fdb4 | 1987 | mutex_lock(&oh->_mutex); |
63c85238 | 1988 | _disable_wakeup(oh); |
12b1fdb4 | 1989 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1990 | |
1991 | return 0; | |
1992 | } | |
43b40992 | 1993 | |
aee48e3c PW |
1994 | /** |
1995 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
1996 | * contained in the hwmod module. | |
1997 | * @oh: struct omap_hwmod * | |
1998 | * @name: name of the reset line to lookup and assert | |
1999 | * | |
2000 | * Some IP like dsp, ipu or iva contain processor that require | |
2001 | * an HW reset line to be assert / deassert in order to enable fully | |
2002 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
2003 | * yet supported on this OMAP; otherwise, passes along the return value | |
2004 | * from _assert_hardreset(). | |
2005 | */ | |
2006 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
2007 | { | |
2008 | int ret; | |
2009 | ||
2010 | if (!oh) | |
2011 | return -EINVAL; | |
2012 | ||
2013 | mutex_lock(&oh->_mutex); | |
2014 | ret = _assert_hardreset(oh, name); | |
2015 | mutex_unlock(&oh->_mutex); | |
2016 | ||
2017 | return ret; | |
2018 | } | |
2019 | ||
2020 | /** | |
2021 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
2022 | * contained in the hwmod module. | |
2023 | * @oh: struct omap_hwmod * | |
2024 | * @name: name of the reset line to look up and deassert | |
2025 | * | |
2026 | * Some IP like dsp, ipu or iva contain processor that require | |
2027 | * an HW reset line to be assert / deassert in order to enable fully | |
2028 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
2029 | * yet supported on this OMAP; otherwise, passes along the return value | |
2030 | * from _deassert_hardreset(). | |
2031 | */ | |
2032 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
2033 | { | |
2034 | int ret; | |
2035 | ||
2036 | if (!oh) | |
2037 | return -EINVAL; | |
2038 | ||
2039 | mutex_lock(&oh->_mutex); | |
2040 | ret = _deassert_hardreset(oh, name); | |
2041 | mutex_unlock(&oh->_mutex); | |
2042 | ||
2043 | return ret; | |
2044 | } | |
2045 | ||
2046 | /** | |
2047 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
2048 | * contained in the hwmod module | |
2049 | * @oh: struct omap_hwmod * | |
2050 | * @name: name of the reset line to look up and read | |
2051 | * | |
2052 | * Return the current state of the hwmod @oh's reset line named @name: | |
2053 | * returns -EINVAL upon parameter error or if this operation | |
2054 | * is unsupported on the current OMAP; otherwise, passes along the return | |
2055 | * value from _read_hardreset(). | |
2056 | */ | |
2057 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
2058 | { | |
2059 | int ret; | |
2060 | ||
2061 | if (!oh) | |
2062 | return -EINVAL; | |
2063 | ||
2064 | mutex_lock(&oh->_mutex); | |
2065 | ret = _read_hardreset(oh, name); | |
2066 | mutex_unlock(&oh->_mutex); | |
2067 | ||
2068 | return ret; | |
2069 | } | |
2070 | ||
2071 | ||
43b40992 PW |
2072 | /** |
2073 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
2074 | * @classname: struct omap_hwmod_class name to search for | |
2075 | * @fn: callback function pointer to call for each hwmod in class @classname | |
2076 | * @user: arbitrary context data to pass to the callback function | |
2077 | * | |
2078 | * For each omap_hwmod of class @classname, call @fn. Takes | |
2079 | * omap_hwmod_mutex to prevent the hwmod list from changing during the | |
2080 | * iteration. If the callback function returns something other than | |
2081 | * zero, the iterator is terminated, and the callback function's return | |
2082 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
2083 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
2084 | */ | |
2085 | int omap_hwmod_for_each_by_class(const char *classname, | |
2086 | int (*fn)(struct omap_hwmod *oh, | |
2087 | void *user), | |
2088 | void *user) | |
2089 | { | |
2090 | struct omap_hwmod *temp_oh; | |
2091 | int ret = 0; | |
2092 | ||
2093 | if (!classname || !fn) | |
2094 | return -EINVAL; | |
2095 | ||
2096 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
2097 | __func__, classname); | |
2098 | ||
2099 | mutex_lock(&omap_hwmod_mutex); | |
2100 | ||
2101 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
2102 | if (!strcmp(temp_oh->class->name, classname)) { | |
2103 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
2104 | __func__, temp_oh->name); | |
2105 | ret = (*fn)(temp_oh, user); | |
2106 | if (ret) | |
2107 | break; | |
2108 | } | |
2109 | } | |
2110 | ||
2111 | mutex_unlock(&omap_hwmod_mutex); | |
2112 | ||
2113 | if (ret) | |
2114 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
2115 | __func__, ret); | |
2116 | ||
2117 | return ret; | |
2118 | } | |
2119 |