ARM: OMAP2+: hwmod: reorganize and document the initialization process
[linux-2.6-block.git] / arch / arm / mach-omap2 / omap_hwmod.c
CommitLineData
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1/*
2 * omap_hwmod implementation for OMAP2/3/4
3 *
550c8092 4 * Copyright (C) 2009-2011 Nokia Corporation
30e105c0 5 * Copyright (C) 2011-2012 Texas Instruments, Inc.
63c85238 6 *
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7 * Paul Walmsley, Benoît Cousson, Kevin Hilman
8 *
9 * Created in collaboration with (alphabetical order): Thara Gopinath,
10 * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand
11 * Sawant, Santosh Shilimkar, Richard Woodruff
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12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
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17 * Introduction
18 * ------------
19 * One way to view an OMAP SoC is as a collection of largely unrelated
20 * IP blocks connected by interconnects. The IP blocks include
21 * devices such as ARM processors, audio serial interfaces, UARTs,
22 * etc. Some of these devices, like the DSP, are created by TI;
23 * others, like the SGX, largely originate from external vendors. In
24 * TI's documentation, on-chip devices are referred to as "OMAP
25 * modules." Some of these IP blocks are identical across several
26 * OMAP versions. Others are revised frequently.
63c85238 27 *
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28 * These OMAP modules are tied together by various interconnects.
29 * Most of the address and data flow between modules is via OCP-based
30 * interconnects such as the L3 and L4 buses; but there are other
31 * interconnects that distribute the hardware clock tree, handle idle
32 * and reset signaling, supply power, and connect the modules to
33 * various pads or balls on the OMAP package.
34 *
35 * OMAP hwmod provides a consistent way to describe the on-chip
36 * hardware blocks and their integration into the rest of the chip.
37 * This description can be automatically generated from the TI
38 * hardware database. OMAP hwmod provides a standard, consistent API
39 * to reset, enable, idle, and disable these hardware blocks. And
40 * hwmod provides a way for other core code, such as the Linux device
41 * code or the OMAP power management and address space mapping code,
42 * to query the hardware database.
43 *
44 * Using hwmod
45 * -----------
46 * Drivers won't call hwmod functions directly. That is done by the
47 * omap_device code, and in rare occasions, by custom integration code
48 * in arch/arm/ *omap*. The omap_device code includes functions to
49 * build a struct platform_device using omap_hwmod data, and that is
50 * currently how hwmod data is communicated to drivers and to the
51 * Linux driver model. Most drivers will call omap_hwmod functions only
52 * indirectly, via pm_runtime*() functions.
53 *
54 * From a layering perspective, here is where the OMAP hwmod code
55 * fits into the kernel software stack:
56 *
57 * +-------------------------------+
58 * | Device driver code |
59 * | (e.g., drivers/) |
60 * +-------------------------------+
61 * | Linux driver model |
62 * | (platform_device / |
63 * | platform_driver data/code) |
64 * +-------------------------------+
65 * | OMAP core-driver integration |
66 * |(arch/arm/mach-omap2/devices.c)|
67 * +-------------------------------+
68 * | omap_device code |
69 * | (../plat-omap/omap_device.c) |
70 * +-------------------------------+
71 * ----> | omap_hwmod code/data | <-----
72 * | (../mach-omap2/omap_hwmod*) |
73 * +-------------------------------+
74 * | OMAP clock/PRCM/register fns |
75 * | (__raw_{read,write}l, clk*) |
76 * +-------------------------------+
77 *
78 * Device drivers should not contain any OMAP-specific code or data in
79 * them. They should only contain code to operate the IP block that
80 * the driver is responsible for. This is because these IP blocks can
81 * also appear in other SoCs, either from TI (such as DaVinci) or from
82 * other manufacturers; and drivers should be reusable across other
83 * platforms.
84 *
85 * The OMAP hwmod code also will attempt to reset and idle all on-chip
86 * devices upon boot. The goal here is for the kernel to be
87 * completely self-reliant and independent from bootloaders. This is
88 * to ensure a repeatable configuration, both to ensure consistent
89 * runtime behavior, and to make it easier for others to reproduce
90 * bugs.
91 *
92 * OMAP module activity states
93 * ---------------------------
94 * The hwmod code considers modules to be in one of several activity
95 * states. IP blocks start out in an UNKNOWN state, then once they
96 * are registered via the hwmod code, proceed to the REGISTERED state.
97 * Once their clock names are resolved to clock pointers, the module
98 * enters the CLKS_INITED state; and finally, once the module has been
99 * reset and the integration registers programmed, the INITIALIZED state
100 * is entered. The hwmod code will then place the module into either
101 * the IDLE state to save power, or in the case of a critical system
102 * module, the ENABLED state.
103 *
104 * OMAP core integration code can then call omap_hwmod*() functions
105 * directly to move the module between the IDLE, ENABLED, and DISABLED
106 * states, as needed. This is done during both the PM idle loop, and
107 * in the OMAP core integration code's implementation of the PM runtime
108 * functions.
109 *
110 * References
111 * ----------
112 * This is a partial list.
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113 * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064)
114 * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090)
115 * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108)
116 * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140)
117 * - Open Core Protocol Specification 2.2
118 *
119 * To do:
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120 * - handle IO mapping
121 * - bus throughput & module latency measurement code
122 *
123 * XXX add tests at the beginning of each function to ensure the hwmod is
124 * in the appropriate state
125 * XXX error return values should be checked to ensure that they are
126 * appropriate
127 */
128#undef DEBUG
129
130#include <linux/kernel.h>
131#include <linux/errno.h>
132#include <linux/io.h>
133#include <linux/clk.h>
134#include <linux/delay.h>
135#include <linux/err.h>
136#include <linux/list.h>
137#include <linux/mutex.h>
dc6d1cda 138#include <linux/spinlock.h>
abc2d545 139#include <linux/slab.h>
63c85238 140
4e65331c 141#include "common.h"
ce491cf8 142#include <plat/cpu.h>
1540f214 143#include "clockdomain.h"
72e06d08 144#include "powerdomain.h"
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145#include <plat/clock.h>
146#include <plat/omap_hwmod.h>
5365efbe 147#include <plat/prcm.h>
63c85238 148
59fb659b 149#include "cm2xxx_3xxx.h"
d0f0631d 150#include "cminst44xx.h"
59fb659b 151#include "prm2xxx_3xxx.h"
d198b514 152#include "prm44xx.h"
eaac329d 153#include "prminst44xx.h"
8d9af88f 154#include "mux.h"
63c85238 155
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156/* Maximum microseconds to wait for OMAP module to softreset */
157#define MAX_MODULE_SOFTRESET_WAIT 10000
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158
159/* Name of the OMAP hwmod for the MPU */
5c2c0296 160#define MPU_INITIATOR_NAME "mpu"
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161
162/* omap_hwmod_list contains all registered struct omap_hwmods */
163static LIST_HEAD(omap_hwmod_list);
164
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165/* mpu_oh: used to add/remove MPU initiator from sleepdep list */
166static struct omap_hwmod *mpu_oh;
167
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168
169/* Private functions */
170
171/**
172 * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy
173 * @oh: struct omap_hwmod *
174 *
175 * Load the current value of the hwmod OCP_SYSCONFIG register into the
176 * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no
177 * OCP_SYSCONFIG register or 0 upon success.
178 */
179static int _update_sysc_cache(struct omap_hwmod *oh)
180{
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181 if (!oh->class->sysc) {
182 WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
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183 return -EINVAL;
184 }
185
186 /* XXX ensure module interface clock is up */
187
cc7a1d2a 188 oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
63c85238 189
43b40992 190 if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE))
883edfdd 191 oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED;
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192
193 return 0;
194}
195
196/**
197 * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register
198 * @v: OCP_SYSCONFIG value to write
199 * @oh: struct omap_hwmod *
200 *
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201 * Write @v into the module class' OCP_SYSCONFIG register, if it has
202 * one. No return value.
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203 */
204static void _write_sysconfig(u32 v, struct omap_hwmod *oh)
205{
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206 if (!oh->class->sysc) {
207 WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name);
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208 return;
209 }
210
211 /* XXX ensure module interface clock is up */
212
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213 /* Module might have lost context, always update cache and register */
214 oh->_sysc_cache = v;
215 omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs);
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216}
217
218/**
219 * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v
220 * @oh: struct omap_hwmod *
221 * @standbymode: MIDLEMODE field bits
222 * @v: pointer to register contents to modify
223 *
224 * Update the master standby mode bits in @v to be @standbymode for
225 * the @oh hwmod. Does not write to the hardware. Returns -EINVAL
226 * upon error or 0 upon success.
227 */
228static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode,
229 u32 *v)
230{
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231 u32 mstandby_mask;
232 u8 mstandby_shift;
233
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234 if (!oh->class->sysc ||
235 !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE))
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236 return -EINVAL;
237
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238 if (!oh->class->sysc->sysc_fields) {
239 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
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240 return -EINVAL;
241 }
242
43b40992 243 mstandby_shift = oh->class->sysc->sysc_fields->midle_shift;
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244 mstandby_mask = (0x3 << mstandby_shift);
245
246 *v &= ~mstandby_mask;
247 *v |= __ffs(standbymode) << mstandby_shift;
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248
249 return 0;
250}
251
252/**
253 * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v
254 * @oh: struct omap_hwmod *
255 * @idlemode: SIDLEMODE field bits
256 * @v: pointer to register contents to modify
257 *
258 * Update the slave idle mode bits in @v to be @idlemode for the @oh
259 * hwmod. Does not write to the hardware. Returns -EINVAL upon error
260 * or 0 upon success.
261 */
262static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v)
263{
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264 u32 sidle_mask;
265 u8 sidle_shift;
266
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267 if (!oh->class->sysc ||
268 !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE))
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269 return -EINVAL;
270
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271 if (!oh->class->sysc->sysc_fields) {
272 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
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273 return -EINVAL;
274 }
275
43b40992 276 sidle_shift = oh->class->sysc->sysc_fields->sidle_shift;
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277 sidle_mask = (0x3 << sidle_shift);
278
279 *v &= ~sidle_mask;
280 *v |= __ffs(idlemode) << sidle_shift;
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281
282 return 0;
283}
284
285/**
286 * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
287 * @oh: struct omap_hwmod *
288 * @clockact: CLOCKACTIVITY field bits
289 * @v: pointer to register contents to modify
290 *
291 * Update the clockactivity mode bits in @v to be @clockact for the
292 * @oh hwmod. Used for additional powersaving on some modules. Does
293 * not write to the hardware. Returns -EINVAL upon error or 0 upon
294 * success.
295 */
296static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v)
297{
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298 u32 clkact_mask;
299 u8 clkact_shift;
300
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301 if (!oh->class->sysc ||
302 !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
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303 return -EINVAL;
304
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305 if (!oh->class->sysc->sysc_fields) {
306 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
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307 return -EINVAL;
308 }
309
43b40992 310 clkact_shift = oh->class->sysc->sysc_fields->clkact_shift;
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311 clkact_mask = (0x3 << clkact_shift);
312
313 *v &= ~clkact_mask;
314 *v |= clockact << clkact_shift;
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315
316 return 0;
317}
318
319/**
320 * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v
321 * @oh: struct omap_hwmod *
322 * @v: pointer to register contents to modify
323 *
324 * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon
325 * error or 0 upon success.
326 */
327static int _set_softreset(struct omap_hwmod *oh, u32 *v)
328{
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329 u32 softrst_mask;
330
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331 if (!oh->class->sysc ||
332 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
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333 return -EINVAL;
334
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335 if (!oh->class->sysc->sysc_fields) {
336 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
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337 return -EINVAL;
338 }
339
43b40992 340 softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
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341
342 *v |= softrst_mask;
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343
344 return 0;
345}
346
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347/**
348 * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
349 * @oh: struct omap_hwmod *
350 * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
351 * @v: pointer to register contents to modify
352 *
353 * Update the module autoidle bit in @v to be @autoidle for the @oh
354 * hwmod. The autoidle bit controls whether the module can gate
355 * internal clocks automatically when it isn't doing anything; the
356 * exact function of this bit varies on a per-module basis. This
357 * function does not write to the hardware. Returns -EINVAL upon
358 * error or 0 upon success.
359 */
360static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
361 u32 *v)
362{
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TG
363 u32 autoidle_mask;
364 u8 autoidle_shift;
365
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366 if (!oh->class->sysc ||
367 !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE))
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368 return -EINVAL;
369
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370 if (!oh->class->sysc->sysc_fields) {
371 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
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TG
372 return -EINVAL;
373 }
374
43b40992 375 autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift;
8985b63d 376 autoidle_mask = (0x1 << autoidle_shift);
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TG
377
378 *v &= ~autoidle_mask;
379 *v |= autoidle << autoidle_shift;
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380
381 return 0;
382}
383
eceec009
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384/**
385 * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux
386 * @oh: struct omap_hwmod *
387 * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable
388 *
389 * Set or clear the I/O pad wakeup flag in the mux entries for the
390 * hwmod @oh. This function changes the @oh->mux->pads_dynamic array
391 * in memory. If the hwmod is currently idled, and the new idle
392 * values don't match the previous ones, this function will also
393 * update the SCM PADCTRL registers. Otherwise, if the hwmod is not
394 * currently idled, this function won't touch the hardware: the new
395 * mux settings are written to the SCM PADCTRL registers when the
396 * hwmod is idled. No return value.
397 */
398static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake)
399{
400 struct omap_device_pad *pad;
401 bool change = false;
402 u16 prev_idle;
403 int j;
404
405 if (!oh->mux || !oh->mux->enabled)
406 return;
407
408 for (j = 0; j < oh->mux->nr_pads_dynamic; j++) {
409 pad = oh->mux->pads_dynamic[j];
410
411 if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP))
412 continue;
413
414 prev_idle = pad->idle;
415
416 if (set_wake)
417 pad->idle |= OMAP_WAKEUP_EN;
418 else
419 pad->idle &= ~OMAP_WAKEUP_EN;
420
421 if (prev_idle != pad->idle)
422 change = true;
423 }
424
425 if (change && oh->_state == _HWMOD_STATE_IDLE)
426 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
427}
428
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429/**
430 * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
431 * @oh: struct omap_hwmod *
432 *
433 * Allow the hardware module @oh to send wakeups. Returns -EINVAL
434 * upon error or 0 upon success.
435 */
5a7ddcbd 436static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
63c85238 437{
43b40992 438 if (!oh->class->sysc ||
86009eb3 439 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
724019b0
BC
440 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
441 (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
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442 return -EINVAL;
443
43b40992
PW
444 if (!oh->class->sysc->sysc_fields) {
445 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
358f0e63
TG
446 return -EINVAL;
447 }
448
1fe74113
BC
449 if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
450 *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
63c85238 451
86009eb3
BC
452 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
453 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
724019b0
BC
454 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
455 _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
86009eb3 456
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457 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
458
459 oh->_int_flags |= _HWMOD_WAKEUP_ENABLED;
460
461 return 0;
462}
463
464/**
465 * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
466 * @oh: struct omap_hwmod *
467 *
468 * Prevent the hardware module @oh to send wakeups. Returns -EINVAL
469 * upon error or 0 upon success.
470 */
5a7ddcbd 471static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
63c85238 472{
43b40992 473 if (!oh->class->sysc ||
86009eb3 474 !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
724019b0
BC
475 (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
476 (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
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477 return -EINVAL;
478
43b40992
PW
479 if (!oh->class->sysc->sysc_fields) {
480 WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name);
358f0e63
TG
481 return -EINVAL;
482 }
483
1fe74113
BC
484 if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
485 *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
63c85238 486
86009eb3
BC
487 if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
488 _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
724019b0
BC
489 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
490 _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
86009eb3 491
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492 /* XXX test pwrdm_get_wken for this hwmod's subsystem */
493
494 oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED;
495
496 return 0;
497}
498
499/**
500 * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active
501 * @oh: struct omap_hwmod *
502 *
503 * Prevent the hardware module @oh from entering idle while the
504 * hardare module initiator @init_oh is active. Useful when a module
505 * will be accessed by a particular initiator (e.g., if a module will
506 * be accessed by the IVA, there should be a sleepdep between the IVA
507 * initiator and the module). Only applies to modules in smart-idle
570b54c7
PW
508 * mode. If the clockdomain is marked as not needing autodeps, return
509 * 0 without doing anything. Otherwise, returns -EINVAL upon error or
510 * passes along clkdm_add_sleepdep() value upon success.
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511 */
512static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
513{
514 if (!oh->_clk)
515 return -EINVAL;
516
570b54c7
PW
517 if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
518 return 0;
519
55ed9694 520 return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
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521}
522
523/**
524 * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active
525 * @oh: struct omap_hwmod *
526 *
527 * Allow the hardware module @oh to enter idle while the hardare
528 * module initiator @init_oh is active. Useful when a module will not
529 * be accessed by a particular initiator (e.g., if a module will not
530 * be accessed by the IVA, there should be no sleepdep between the IVA
531 * initiator and the module). Only applies to modules in smart-idle
570b54c7
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532 * mode. If the clockdomain is marked as not needing autodeps, return
533 * 0 without doing anything. Returns -EINVAL upon error or passes
534 * along clkdm_del_sleepdep() value upon success.
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535 */
536static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
537{
538 if (!oh->_clk)
539 return -EINVAL;
540
570b54c7
PW
541 if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
542 return 0;
543
55ed9694 544 return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
63c85238
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545}
546
547/**
548 * _init_main_clk - get a struct clk * for the the hwmod's main functional clk
549 * @oh: struct omap_hwmod *
550 *
551 * Called from _init_clocks(). Populates the @oh _clk (main
552 * functional clock pointer) if a main_clk is present. Returns 0 on
553 * success or -EINVAL on error.
554 */
555static int _init_main_clk(struct omap_hwmod *oh)
556{
63c85238
PW
557 int ret = 0;
558
50ebdac2 559 if (!oh->main_clk)
63c85238
PW
560 return 0;
561
63403384 562 oh->_clk = omap_clk_get_by_name(oh->main_clk);
dc75925d 563 if (!oh->_clk) {
20383d82
BC
564 pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
565 oh->name, oh->main_clk);
63403384 566 return -EINVAL;
dc75925d 567 }
63c85238 568
63403384
BC
569 if (!oh->_clk->clkdm)
570 pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
571 oh->main_clk, oh->_clk->name);
81d7c6ff 572
63c85238
PW
573 return ret;
574}
575
576/**
887adeac 577 * _init_interface_clks - get a struct clk * for the the hwmod's interface clks
63c85238
PW
578 * @oh: struct omap_hwmod *
579 *
580 * Called from _init_clocks(). Populates the @oh OCP slave interface
581 * clock pointers. Returns 0 on success or -EINVAL on error.
582 */
583static int _init_interface_clks(struct omap_hwmod *oh)
584{
63c85238
PW
585 struct clk *c;
586 int i;
587 int ret = 0;
588
589 if (oh->slaves_cnt == 0)
590 return 0;
591
682fdc96
BC
592 for (i = 0; i < oh->slaves_cnt; i++) {
593 struct omap_hwmod_ocp_if *os = oh->slaves[i];
594
50ebdac2 595 if (!os->clk)
63c85238
PW
596 continue;
597
50ebdac2 598 c = omap_clk_get_by_name(os->clk);
dc75925d 599 if (!c) {
20383d82
BC
600 pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
601 oh->name, os->clk);
63c85238 602 ret = -EINVAL;
dc75925d 603 }
63c85238
PW
604 os->_clk = c;
605 }
606
607 return ret;
608}
609
610/**
611 * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks
612 * @oh: struct omap_hwmod *
613 *
614 * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk
615 * clock pointers. Returns 0 on success or -EINVAL on error.
616 */
617static int _init_opt_clks(struct omap_hwmod *oh)
618{
619 struct omap_hwmod_opt_clk *oc;
620 struct clk *c;
621 int i;
622 int ret = 0;
623
624 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
50ebdac2 625 c = omap_clk_get_by_name(oc->clk);
dc75925d 626 if (!c) {
20383d82
BC
627 pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
628 oh->name, oc->clk);
63c85238 629 ret = -EINVAL;
dc75925d 630 }
63c85238
PW
631 oc->_clk = c;
632 }
633
634 return ret;
635}
636
637/**
638 * _enable_clocks - enable hwmod main clock and interface clocks
639 * @oh: struct omap_hwmod *
640 *
641 * Enables all clocks necessary for register reads and writes to succeed
642 * on the hwmod @oh. Returns 0.
643 */
644static int _enable_clocks(struct omap_hwmod *oh)
645{
63c85238
PW
646 int i;
647
648 pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name);
649
4d3ae5a9 650 if (oh->_clk)
63c85238
PW
651 clk_enable(oh->_clk);
652
653 if (oh->slaves_cnt > 0) {
682fdc96
BC
654 for (i = 0; i < oh->slaves_cnt; i++) {
655 struct omap_hwmod_ocp_if *os = oh->slaves[i];
63c85238
PW
656 struct clk *c = os->_clk;
657
4d3ae5a9 658 if (c && (os->flags & OCPIF_SWSUP_IDLE))
63c85238
PW
659 clk_enable(c);
660 }
661 }
662
663 /* The opt clocks are controlled by the device driver. */
664
665 return 0;
666}
667
668/**
669 * _disable_clocks - disable hwmod main clock and interface clocks
670 * @oh: struct omap_hwmod *
671 *
672 * Disables the hwmod @oh main functional and interface clocks. Returns 0.
673 */
674static int _disable_clocks(struct omap_hwmod *oh)
675{
63c85238
PW
676 int i;
677
678 pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name);
679
4d3ae5a9 680 if (oh->_clk)
63c85238
PW
681 clk_disable(oh->_clk);
682
683 if (oh->slaves_cnt > 0) {
682fdc96
BC
684 for (i = 0; i < oh->slaves_cnt; i++) {
685 struct omap_hwmod_ocp_if *os = oh->slaves[i];
63c85238
PW
686 struct clk *c = os->_clk;
687
4d3ae5a9 688 if (c && (os->flags & OCPIF_SWSUP_IDLE))
63c85238
PW
689 clk_disable(c);
690 }
691 }
692
693 /* The opt clocks are controlled by the device driver. */
694
695 return 0;
696}
697
96835af9
BC
698static void _enable_optional_clocks(struct omap_hwmod *oh)
699{
700 struct omap_hwmod_opt_clk *oc;
701 int i;
702
703 pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name);
704
705 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
706 if (oc->_clk) {
707 pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
708 oc->_clk->name);
709 clk_enable(oc->_clk);
710 }
711}
712
713static void _disable_optional_clocks(struct omap_hwmod *oh)
714{
715 struct omap_hwmod_opt_clk *oc;
716 int i;
717
718 pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name);
719
720 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
721 if (oc->_clk) {
722 pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
723 oc->_clk->name);
724 clk_disable(oc->_clk);
725 }
726}
727
45c38252
BC
728/**
729 * _enable_module - enable CLKCTRL modulemode on OMAP4
730 * @oh: struct omap_hwmod *
731 *
732 * Enables the PRCM module mode related to the hwmod @oh.
733 * No return value.
734 */
735static void _enable_module(struct omap_hwmod *oh)
736{
737 /* The module mode does not exist prior OMAP4 */
738 if (cpu_is_omap24xx() || cpu_is_omap34xx())
739 return;
740
741 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
742 return;
743
744 pr_debug("omap_hwmod: %s: _enable_module: %d\n",
745 oh->name, oh->prcm.omap4.modulemode);
746
747 omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
748 oh->clkdm->prcm_partition,
749 oh->clkdm->cm_inst,
750 oh->clkdm->clkdm_offs,
751 oh->prcm.omap4.clkctrl_offs);
752}
753
754/**
bfc141e3
BC
755 * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4
756 * @oh: struct omap_hwmod *
757 *
758 * Wait for a module @oh to enter slave idle. Returns 0 if the module
759 * does not have an IDLEST bit or if the module successfully enters
760 * slave idle; otherwise, pass along the return value of the
761 * appropriate *_cm*_wait_module_idle() function.
762 */
763static int _omap4_wait_target_disable(struct omap_hwmod *oh)
764{
765 if (!cpu_is_omap44xx())
766 return 0;
767
768 if (!oh)
769 return -EINVAL;
770
771 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
772 return 0;
773
774 if (oh->flags & HWMOD_NO_IDLEST)
775 return 0;
776
777 return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
778 oh->clkdm->cm_inst,
779 oh->clkdm->clkdm_offs,
780 oh->prcm.omap4.clkctrl_offs);
781}
782
783/**
784 * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4
45c38252
BC
785 * @oh: struct omap_hwmod *
786 *
787 * Disable the PRCM module mode related to the hwmod @oh.
bfc141e3 788 * Return EINVAL if the modulemode is not supported and 0 in case of success.
45c38252 789 */
bfc141e3 790static int _omap4_disable_module(struct omap_hwmod *oh)
45c38252 791{
bfc141e3
BC
792 int v;
793
45c38252 794 /* The module mode does not exist prior OMAP4 */
bfc141e3
BC
795 if (!cpu_is_omap44xx())
796 return -EINVAL;
45c38252
BC
797
798 if (!oh->clkdm || !oh->prcm.omap4.modulemode)
bfc141e3 799 return -EINVAL;
45c38252 800
bfc141e3 801 pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
45c38252
BC
802
803 omap4_cminst_module_disable(oh->clkdm->prcm_partition,
804 oh->clkdm->cm_inst,
805 oh->clkdm->clkdm_offs,
806 oh->prcm.omap4.clkctrl_offs);
bfc141e3
BC
807
808 v = _omap4_wait_target_disable(oh);
809 if (v)
810 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
811 oh->name);
812
813 return 0;
45c38252
BC
814}
815
212738a4
PW
816/**
817 * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
818 * @oh: struct omap_hwmod *oh
819 *
820 * Count and return the number of MPU IRQs associated with the hwmod
821 * @oh. Used to allocate struct resource data. Returns 0 if @oh is
822 * NULL.
823 */
824static int _count_mpu_irqs(struct omap_hwmod *oh)
825{
826 struct omap_hwmod_irq_info *ohii;
827 int i = 0;
828
829 if (!oh || !oh->mpu_irqs)
830 return 0;
831
832 do {
833 ohii = &oh->mpu_irqs[i++];
834 } while (ohii->irq != -1);
835
cc1b0765 836 return i-1;
212738a4
PW
837}
838
bc614958
PW
839/**
840 * _count_sdma_reqs - count the number of SDMA request lines associated with @oh
841 * @oh: struct omap_hwmod *oh
842 *
843 * Count and return the number of SDMA request lines associated with
844 * the hwmod @oh. Used to allocate struct resource data. Returns 0
845 * if @oh is NULL.
846 */
847static int _count_sdma_reqs(struct omap_hwmod *oh)
848{
849 struct omap_hwmod_dma_info *ohdi;
850 int i = 0;
851
852 if (!oh || !oh->sdma_reqs)
853 return 0;
854
855 do {
856 ohdi = &oh->sdma_reqs[i++];
857 } while (ohdi->dma_req != -1);
858
cc1b0765 859 return i-1;
bc614958
PW
860}
861
78183f3f
PW
862/**
863 * _count_ocp_if_addr_spaces - count the number of address space entries for @oh
864 * @oh: struct omap_hwmod *oh
865 *
866 * Count and return the number of address space ranges associated with
867 * the hwmod @oh. Used to allocate struct resource data. Returns 0
868 * if @oh is NULL.
869 */
870static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
871{
872 struct omap_hwmod_addr_space *mem;
873 int i = 0;
874
875 if (!os || !os->addr)
876 return 0;
877
878 do {
879 mem = &os->addr[i++];
880 } while (mem->pa_start != mem->pa_end);
881
cc1b0765 882 return i-1;
78183f3f
PW
883}
884
63c85238
PW
885/**
886 * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
887 * @oh: struct omap_hwmod *
888 *
889 * Returns the array index of the OCP slave port that the MPU
890 * addresses the device on, or -EINVAL upon error or not found.
891 */
01592df9 892static int __init _find_mpu_port_index(struct omap_hwmod *oh)
63c85238 893{
63c85238
PW
894 int i;
895 int found = 0;
896
897 if (!oh || oh->slaves_cnt == 0)
898 return -EINVAL;
899
682fdc96
BC
900 for (i = 0; i < oh->slaves_cnt; i++) {
901 struct omap_hwmod_ocp_if *os = oh->slaves[i];
902
63c85238
PW
903 if (os->user & OCP_USER_MPU) {
904 found = 1;
905 break;
906 }
907 }
908
909 if (found)
910 pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n",
911 oh->name, i);
912 else
913 pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n",
914 oh->name);
915
916 return (found) ? i : -EINVAL;
917}
918
919/**
920 * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU
921 * @oh: struct omap_hwmod *
922 *
923 * Return the virtual address of the base of the register target of
924 * device @oh, or NULL on error.
925 */
01592df9 926static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
63c85238
PW
927{
928 struct omap_hwmod_ocp_if *os;
929 struct omap_hwmod_addr_space *mem;
78183f3f 930 int i = 0, found = 0;
986a13f5 931 void __iomem *va_start;
63c85238
PW
932
933 if (!oh || oh->slaves_cnt == 0)
934 return NULL;
935
682fdc96 936 os = oh->slaves[index];
63c85238 937
78183f3f
PW
938 if (!os->addr)
939 return NULL;
940
941 do {
942 mem = &os->addr[i++];
943 if (mem->flags & ADDR_TYPE_RT)
63c85238 944 found = 1;
78183f3f 945 } while (!found && mem->pa_start != mem->pa_end);
63c85238 946
986a13f5
TL
947 if (found) {
948 va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
949 if (!va_start) {
950 pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name);
951 return NULL;
952 }
63c85238 953 pr_debug("omap_hwmod: %s: MPU register target at va %p\n",
986a13f5
TL
954 oh->name, va_start);
955 } else {
63c85238
PW
956 pr_debug("omap_hwmod: %s: no MPU register target found\n",
957 oh->name);
986a13f5 958 }
63c85238 959
986a13f5 960 return (found) ? va_start : NULL;
63c85238
PW
961}
962
963/**
74ff3a68 964 * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
63c85238
PW
965 * @oh: struct omap_hwmod *
966 *
967 * If module is marked as SWSUP_SIDLE, force the module out of slave
968 * idle; otherwise, configure it for smart-idle. If module is marked
969 * as SWSUP_MSUSPEND, force the module out of master standby;
970 * otherwise, configure it for smart-standby. No return value.
971 */
74ff3a68 972static void _enable_sysc(struct omap_hwmod *oh)
63c85238 973{
43b40992 974 u8 idlemode, sf;
63c85238
PW
975 u32 v;
976
43b40992 977 if (!oh->class->sysc)
63c85238
PW
978 return;
979
980 v = oh->_sysc_cache;
43b40992 981 sf = oh->class->sysc->sysc_flags;
63c85238 982
43b40992 983 if (sf & SYSC_HAS_SIDLEMODE) {
63c85238
PW
984 idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
985 HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
986 _set_slave_idlemode(oh, idlemode, &v);
987 }
988
43b40992 989 if (sf & SYSC_HAS_MIDLEMODE) {
724019b0
BC
990 if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
991 idlemode = HWMOD_IDLEMODE_NO;
992 } else {
993 if (sf & SYSC_HAS_ENAWAKEUP)
994 _enable_wakeup(oh, &v);
995 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
996 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
997 else
998 idlemode = HWMOD_IDLEMODE_SMART;
999 }
63c85238
PW
1000 _set_master_standbymode(oh, idlemode, &v);
1001 }
1002
a16b1f7f
PW
1003 /*
1004 * XXX The clock framework should handle this, by
1005 * calling into this code. But this must wait until the
1006 * clock structures are tagged with omap_hwmod entries
1007 */
43b40992
PW
1008 if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) &&
1009 (sf & SYSC_HAS_CLOCKACTIVITY))
1010 _set_clockactivity(oh, oh->class->sysc->clockact, &v);
63c85238 1011
9980ce53
RN
1012 /* If slave is in SMARTIDLE, also enable wakeup */
1013 if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
5a7ddcbd
KH
1014 _enable_wakeup(oh, &v);
1015
1016 _write_sysconfig(v, oh);
78f26e87
HH
1017
1018 /*
1019 * Set the autoidle bit only after setting the smartidle bit
1020 * Setting this will not have any impact on the other modules.
1021 */
1022 if (sf & SYSC_HAS_AUTOIDLE) {
1023 idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
1024 0 : 1;
1025 _set_module_autoidle(oh, idlemode, &v);
1026 _write_sysconfig(v, oh);
1027 }
63c85238
PW
1028}
1029
1030/**
74ff3a68 1031 * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG
63c85238
PW
1032 * @oh: struct omap_hwmod *
1033 *
1034 * If module is marked as SWSUP_SIDLE, force the module into slave
1035 * idle; otherwise, configure it for smart-idle. If module is marked
1036 * as SWSUP_MSUSPEND, force the module into master standby; otherwise,
1037 * configure it for smart-standby. No return value.
1038 */
74ff3a68 1039static void _idle_sysc(struct omap_hwmod *oh)
63c85238 1040{
43b40992 1041 u8 idlemode, sf;
63c85238
PW
1042 u32 v;
1043
43b40992 1044 if (!oh->class->sysc)
63c85238
PW
1045 return;
1046
1047 v = oh->_sysc_cache;
43b40992 1048 sf = oh->class->sysc->sysc_flags;
63c85238 1049
43b40992 1050 if (sf & SYSC_HAS_SIDLEMODE) {
63c85238
PW
1051 idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
1052 HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
1053 _set_slave_idlemode(oh, idlemode, &v);
1054 }
1055
43b40992 1056 if (sf & SYSC_HAS_MIDLEMODE) {
724019b0
BC
1057 if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
1058 idlemode = HWMOD_IDLEMODE_FORCE;
1059 } else {
1060 if (sf & SYSC_HAS_ENAWAKEUP)
1061 _enable_wakeup(oh, &v);
1062 if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
1063 idlemode = HWMOD_IDLEMODE_SMART_WKUP;
1064 else
1065 idlemode = HWMOD_IDLEMODE_SMART;
1066 }
63c85238
PW
1067 _set_master_standbymode(oh, idlemode, &v);
1068 }
1069
86009eb3
BC
1070 /* If slave is in SMARTIDLE, also enable wakeup */
1071 if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE))
1072 _enable_wakeup(oh, &v);
1073
63c85238
PW
1074 _write_sysconfig(v, oh);
1075}
1076
1077/**
74ff3a68 1078 * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG
63c85238
PW
1079 * @oh: struct omap_hwmod *
1080 *
1081 * Force the module into slave idle and master suspend. No return
1082 * value.
1083 */
74ff3a68 1084static void _shutdown_sysc(struct omap_hwmod *oh)
63c85238
PW
1085{
1086 u32 v;
43b40992 1087 u8 sf;
63c85238 1088
43b40992 1089 if (!oh->class->sysc)
63c85238
PW
1090 return;
1091
1092 v = oh->_sysc_cache;
43b40992 1093 sf = oh->class->sysc->sysc_flags;
63c85238 1094
43b40992 1095 if (sf & SYSC_HAS_SIDLEMODE)
63c85238
PW
1096 _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v);
1097
43b40992 1098 if (sf & SYSC_HAS_MIDLEMODE)
63c85238
PW
1099 _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
1100
43b40992 1101 if (sf & SYSC_HAS_AUTOIDLE)
726072e5 1102 _set_module_autoidle(oh, 1, &v);
63c85238
PW
1103
1104 _write_sysconfig(v, oh);
1105}
1106
1107/**
1108 * _lookup - find an omap_hwmod by name
1109 * @name: find an omap_hwmod by name
1110 *
1111 * Return a pointer to an omap_hwmod by name, or NULL if not found.
63c85238
PW
1112 */
1113static struct omap_hwmod *_lookup(const char *name)
1114{
1115 struct omap_hwmod *oh, *temp_oh;
1116
1117 oh = NULL;
1118
1119 list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
1120 if (!strcmp(name, temp_oh->name)) {
1121 oh = temp_oh;
1122 break;
1123 }
1124 }
1125
1126 return oh;
1127}
6ae76997
BC
1128/**
1129 * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
1130 * @oh: struct omap_hwmod *
1131 *
1132 * Convert a clockdomain name stored in a struct omap_hwmod into a
1133 * clockdomain pointer, and save it into the struct omap_hwmod.
1134 * return -EINVAL if clkdm_name does not exist or if the lookup failed.
1135 */
1136static int _init_clkdm(struct omap_hwmod *oh)
1137{
1138 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1139 return 0;
1140
1141 if (!oh->clkdm_name) {
1142 pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name);
1143 return -EINVAL;
1144 }
1145
1146 oh->clkdm = clkdm_lookup(oh->clkdm_name);
1147 if (!oh->clkdm) {
1148 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
1149 oh->name, oh->clkdm_name);
1150 return -EINVAL;
1151 }
1152
1153 pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
1154 oh->name, oh->clkdm_name);
1155
1156 return 0;
1157}
63c85238
PW
1158
1159/**
6ae76997
BC
1160 * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
1161 * well the clockdomain.
63c85238 1162 * @oh: struct omap_hwmod *
97d60162 1163 * @data: not used; pass NULL
63c85238 1164 *
a2debdbd 1165 * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
48d54f3f
PW
1166 * Resolves all clock names embedded in the hwmod. Returns 0 on
1167 * success, or a negative error code on failure.
63c85238 1168 */
97d60162 1169static int _init_clocks(struct omap_hwmod *oh, void *data)
63c85238
PW
1170{
1171 int ret = 0;
1172
48d54f3f
PW
1173 if (oh->_state != _HWMOD_STATE_REGISTERED)
1174 return 0;
63c85238
PW
1175
1176 pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
1177
1178 ret |= _init_main_clk(oh);
1179 ret |= _init_interface_clks(oh);
1180 ret |= _init_opt_clks(oh);
6ae76997 1181 ret |= _init_clkdm(oh);
63c85238 1182
f5c1f84b
BC
1183 if (!ret)
1184 oh->_state = _HWMOD_STATE_CLKS_INITED;
6652271a
BC
1185 else
1186 pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
63c85238 1187
09c35f2f 1188 return ret;
63c85238
PW
1189}
1190
1191/**
1192 * _wait_target_ready - wait for a module to leave slave idle
1193 * @oh: struct omap_hwmod *
1194 *
1195 * Wait for a module @oh to leave slave idle. Returns 0 if the module
1196 * does not have an IDLEST bit or if the module successfully leaves
1197 * slave idle; otherwise, pass along the return value of the
d0f0631d 1198 * appropriate *_cm*_wait_module_ready() function.
63c85238
PW
1199 */
1200static int _wait_target_ready(struct omap_hwmod *oh)
1201{
1202 struct omap_hwmod_ocp_if *os;
1203 int ret;
1204
1205 if (!oh)
1206 return -EINVAL;
1207
1208 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
1209 return 0;
1210
682fdc96 1211 os = oh->slaves[oh->_mpu_port_index];
63c85238 1212
33f7ec81 1213 if (oh->flags & HWMOD_NO_IDLEST)
63c85238
PW
1214 return 0;
1215
1216 /* XXX check module SIDLEMODE */
1217
1218 /* XXX check clock enable states */
1219
1220 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1221 ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
1222 oh->prcm.omap2.idlest_reg_id,
1223 oh->prcm.omap2.idlest_idle_bit);
63c85238 1224 } else if (cpu_is_omap44xx()) {
d0f0631d
BC
1225 if (!oh->clkdm)
1226 return -EINVAL;
1227
1228 ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
1229 oh->clkdm->cm_inst,
1230 oh->clkdm->clkdm_offs,
1231 oh->prcm.omap4.clkctrl_offs);
63c85238
PW
1232 } else {
1233 BUG();
1234 };
1235
1236 return ret;
1237}
1238
5365efbe 1239/**
cc1226e7 1240 * _lookup_hardreset - fill register bit info for this hwmod/reset line
5365efbe
BC
1241 * @oh: struct omap_hwmod *
1242 * @name: name of the reset line in the context of this hwmod
cc1226e7 1243 * @ohri: struct omap_hwmod_rst_info * that this function will fill in
5365efbe
BC
1244 *
1245 * Return the bit position of the reset line that match the
1246 * input name. Return -ENOENT if not found.
1247 */
cc1226e7 1248static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
1249 struct omap_hwmod_rst_info *ohri)
5365efbe
BC
1250{
1251 int i;
1252
1253 for (i = 0; i < oh->rst_lines_cnt; i++) {
1254 const char *rst_line = oh->rst_lines[i].name;
1255 if (!strcmp(rst_line, name)) {
cc1226e7 1256 ohri->rst_shift = oh->rst_lines[i].rst_shift;
1257 ohri->st_shift = oh->rst_lines[i].st_shift;
1258 pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n",
1259 oh->name, __func__, rst_line, ohri->rst_shift,
1260 ohri->st_shift);
5365efbe 1261
cc1226e7 1262 return 0;
5365efbe
BC
1263 }
1264 }
1265
1266 return -ENOENT;
1267}
1268
1269/**
1270 * _assert_hardreset - assert the HW reset line of submodules
1271 * contained in the hwmod module.
1272 * @oh: struct omap_hwmod *
1273 * @name: name of the reset line to lookup and assert
1274 *
1275 * Some IP like dsp, ipu or iva contain processor that require
1276 * an HW reset line to be assert / deassert in order to enable fully
1277 * the IP.
1278 */
1279static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
1280{
cc1226e7 1281 struct omap_hwmod_rst_info ohri;
1282 u8 ret;
5365efbe
BC
1283
1284 if (!oh)
1285 return -EINVAL;
1286
cc1226e7 1287 ret = _lookup_hardreset(oh, name, &ohri);
1288 if (IS_ERR_VALUE(ret))
1289 return ret;
5365efbe
BC
1290
1291 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1292 return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
cc1226e7 1293 ohri.rst_shift);
5365efbe 1294 else if (cpu_is_omap44xx())
eaac329d
BC
1295 return omap4_prminst_assert_hardreset(ohri.rst_shift,
1296 oh->clkdm->pwrdm.ptr->prcm_partition,
1297 oh->clkdm->pwrdm.ptr->prcm_offs,
1298 oh->prcm.omap4.rstctrl_offs);
5365efbe
BC
1299 else
1300 return -EINVAL;
1301}
1302
1303/**
1304 * _deassert_hardreset - deassert the HW reset line of submodules contained
1305 * in the hwmod module.
1306 * @oh: struct omap_hwmod *
1307 * @name: name of the reset line to look up and deassert
1308 *
1309 * Some IP like dsp, ipu or iva contain processor that require
1310 * an HW reset line to be assert / deassert in order to enable fully
1311 * the IP.
1312 */
1313static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
1314{
cc1226e7 1315 struct omap_hwmod_rst_info ohri;
1316 int ret;
5365efbe
BC
1317
1318 if (!oh)
1319 return -EINVAL;
1320
cc1226e7 1321 ret = _lookup_hardreset(oh, name, &ohri);
1322 if (IS_ERR_VALUE(ret))
1323 return ret;
5365efbe 1324
cc1226e7 1325 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1326 ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
1327 ohri.rst_shift,
1328 ohri.st_shift);
1329 } else if (cpu_is_omap44xx()) {
1330 if (ohri.st_shift)
1331 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
1332 oh->name, name);
eaac329d
BC
1333 ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
1334 oh->clkdm->pwrdm.ptr->prcm_partition,
1335 oh->clkdm->pwrdm.ptr->prcm_offs,
1336 oh->prcm.omap4.rstctrl_offs);
cc1226e7 1337 } else {
5365efbe 1338 return -EINVAL;
cc1226e7 1339 }
5365efbe 1340
cc1226e7 1341 if (ret == -EBUSY)
5365efbe
BC
1342 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
1343
cc1226e7 1344 return ret;
5365efbe
BC
1345}
1346
1347/**
1348 * _read_hardreset - read the HW reset line state of submodules
1349 * contained in the hwmod module
1350 * @oh: struct omap_hwmod *
1351 * @name: name of the reset line to look up and read
1352 *
1353 * Return the state of the reset line.
1354 */
1355static int _read_hardreset(struct omap_hwmod *oh, const char *name)
1356{
cc1226e7 1357 struct omap_hwmod_rst_info ohri;
1358 u8 ret;
5365efbe
BC
1359
1360 if (!oh)
1361 return -EINVAL;
1362
cc1226e7 1363 ret = _lookup_hardreset(oh, name, &ohri);
1364 if (IS_ERR_VALUE(ret))
1365 return ret;
5365efbe
BC
1366
1367 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1368 return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
cc1226e7 1369 ohri.st_shift);
5365efbe 1370 } else if (cpu_is_omap44xx()) {
eaac329d
BC
1371 return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
1372 oh->clkdm->pwrdm.ptr->prcm_partition,
1373 oh->clkdm->pwrdm.ptr->prcm_offs,
1374 oh->prcm.omap4.rstctrl_offs);
5365efbe
BC
1375 } else {
1376 return -EINVAL;
1377 }
1378}
1379
63c85238 1380/**
bd36179e 1381 * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit
63c85238
PW
1382 * @oh: struct omap_hwmod *
1383 *
1384 * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be
30e105c0
PW
1385 * enabled for this to work. Returns -ENOENT if the hwmod cannot be
1386 * reset this way, -EINVAL if the hwmod is in the wrong state,
1387 * -ETIMEDOUT if the module did not reset in time, or 0 upon success.
2cb06814
BC
1388 *
1389 * In OMAP3 a specific SYSSTATUS register is used to get the reset status.
bd36179e 1390 * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead
2cb06814
BC
1391 * use the SYSCONFIG softreset bit to provide the status.
1392 *
bd36179e
PW
1393 * Note that some IP like McBSP do have reset control but don't have
1394 * reset status.
63c85238 1395 */
bd36179e 1396static int _ocp_softreset(struct omap_hwmod *oh)
63c85238 1397{
387ca5bf 1398 u32 v, softrst_mask;
6f8b7ff5 1399 int c = 0;
96835af9 1400 int ret = 0;
63c85238 1401
43b40992 1402 if (!oh->class->sysc ||
2cb06814 1403 !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET))
30e105c0 1404 return -ENOENT;
63c85238
PW
1405
1406 /* clocks must be on for this operation */
1407 if (oh->_state != _HWMOD_STATE_ENABLED) {
76e5589e
BC
1408 pr_warning("omap_hwmod: %s: reset can only be entered from "
1409 "enabled state\n", oh->name);
63c85238
PW
1410 return -EINVAL;
1411 }
1412
96835af9
BC
1413 /* For some modules, all optionnal clocks need to be enabled as well */
1414 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1415 _enable_optional_clocks(oh);
1416
bd36179e 1417 pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name);
63c85238
PW
1418
1419 v = oh->_sysc_cache;
96835af9
BC
1420 ret = _set_softreset(oh, &v);
1421 if (ret)
1422 goto dis_opt_clks;
63c85238
PW
1423 _write_sysconfig(v, oh);
1424
d99de7f5
FGL
1425 if (oh->class->sysc->srst_udelay)
1426 udelay(oh->class->sysc->srst_udelay);
1427
2cb06814 1428 if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
cc7a1d2a 1429 omap_test_timeout((omap_hwmod_read(oh,
2cb06814
BC
1430 oh->class->sysc->syss_offs)
1431 & SYSS_RESETDONE_MASK),
1432 MAX_MODULE_SOFTRESET_WAIT, c);
387ca5bf
RN
1433 else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) {
1434 softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift);
cc7a1d2a 1435 omap_test_timeout(!(omap_hwmod_read(oh,
2cb06814 1436 oh->class->sysc->sysc_offs)
387ca5bf 1437 & softrst_mask),
2cb06814 1438 MAX_MODULE_SOFTRESET_WAIT, c);
387ca5bf 1439 }
63c85238 1440
5365efbe 1441 if (c == MAX_MODULE_SOFTRESET_WAIT)
76e5589e
BC
1442 pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n",
1443 oh->name, MAX_MODULE_SOFTRESET_WAIT);
63c85238 1444 else
5365efbe 1445 pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c);
63c85238
PW
1446
1447 /*
1448 * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from
1449 * _wait_target_ready() or _reset()
1450 */
1451
96835af9
BC
1452 ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
1453
1454dis_opt_clks:
1455 if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET)
1456 _disable_optional_clocks(oh);
1457
1458 return ret;
63c85238
PW
1459}
1460
bd36179e
PW
1461/**
1462 * _reset - reset an omap_hwmod
1463 * @oh: struct omap_hwmod *
1464 *
30e105c0
PW
1465 * Resets an omap_hwmod @oh. If the module has a custom reset
1466 * function pointer defined, then call it to reset the IP block, and
1467 * pass along its return value to the caller. Otherwise, if the IP
1468 * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield
1469 * associated with it, call a function to reset the IP block via that
1470 * method, and pass along the return value to the caller. Finally, if
1471 * the IP block has some hardreset lines associated with it, assert
1472 * all of those, but do _not_ deassert them. (This is because driver
1473 * authors have expressed an apparent requirement to control the
1474 * deassertion of the hardreset lines themselves.)
1475 *
1476 * The default software reset mechanism for most OMAP IP blocks is
1477 * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some
1478 * hwmods cannot be reset via this method. Some are not targets and
1479 * therefore have no OCP header registers to access. Others (like the
1480 * IVA) have idiosyncratic reset sequences. So for these relatively
1481 * rare cases, custom reset code can be supplied in the struct
1482 * omap_hwmod_class .reset function pointer. Passes along the return
1483 * value from either _ocp_softreset() or the custom reset function -
1484 * these must return -EINVAL if the hwmod cannot be reset this way or
1485 * if the hwmod is in the wrong state, -ETIMEDOUT if the module did
1486 * not reset in time, or 0 upon success.
bd36179e
PW
1487 */
1488static int _reset(struct omap_hwmod *oh)
1489{
30e105c0 1490 int i, r;
bd36179e
PW
1491
1492 pr_debug("omap_hwmod: %s: resetting\n", oh->name);
1493
30e105c0
PW
1494 if (oh->class->reset) {
1495 r = oh->class->reset(oh);
1496 } else {
1497 if (oh->rst_lines_cnt > 0) {
1498 for (i = 0; i < oh->rst_lines_cnt; i++)
1499 _assert_hardreset(oh, oh->rst_lines[i].name);
1500 return 0;
1501 } else {
1502 r = _ocp_softreset(oh);
1503 if (r == -ENOENT)
1504 r = 0;
1505 }
1506 }
1507
9c8b0ec7 1508 /*
30e105c0
PW
1509 * OCP_SYSCONFIG bits need to be reprogrammed after a
1510 * softreset. The _enable() function should be split to avoid
1511 * the rewrite of the OCP_SYSCONFIG register.
9c8b0ec7 1512 */
2800852a
RN
1513 if (oh->class->sysc) {
1514 _update_sysc_cache(oh);
1515 _enable_sysc(oh);
1516 }
1517
30e105c0 1518 return r;
bd36179e
PW
1519}
1520
63c85238 1521/**
dc6d1cda 1522 * _enable - enable an omap_hwmod
63c85238
PW
1523 * @oh: struct omap_hwmod *
1524 *
1525 * Enables an omap_hwmod @oh such that the MPU can access the hwmod's
dc6d1cda
PW
1526 * register target. Returns -EINVAL if the hwmod is in the wrong
1527 * state or passes along the return value of _wait_target_ready().
63c85238 1528 */
dc6d1cda 1529static int _enable(struct omap_hwmod *oh)
63c85238 1530{
9c8b0ec7 1531 int r, i;
665d0013 1532 int hwsup = 0;
63c85238 1533
34617e2a
BC
1534 pr_debug("omap_hwmod: %s: enabling\n", oh->name);
1535
aacf0941
RN
1536 /*
1537 * hwmods with HWMOD_INIT_NO_IDLE flag set are left
1538 * in enabled state at init.
1539 * Now that someone is really trying to enable them,
1540 * just ensure that the hwmod mux is set.
1541 */
1542 if (oh->_int_flags & _HWMOD_SKIP_ENABLE) {
1543 /*
1544 * If the caller has mux data populated, do the mux'ing
1545 * which wouldn't have been done as part of the _enable()
1546 * done during setup.
1547 */
1548 if (oh->mux)
1549 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
1550
1551 oh->_int_flags &= ~_HWMOD_SKIP_ENABLE;
1552 return 0;
1553 }
1554
63c85238
PW
1555 if (oh->_state != _HWMOD_STATE_INITIALIZED &&
1556 oh->_state != _HWMOD_STATE_IDLE &&
1557 oh->_state != _HWMOD_STATE_DISABLED) {
4f8a428d
RK
1558 WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n",
1559 oh->name);
63c85238
PW
1560 return -EINVAL;
1561 }
1562
31f62866 1563 /*
9c8b0ec7 1564 * If an IP contains HW reset lines, then de-assert them in order
31f62866
BC
1565 * to allow the module state transition. Otherwise the PRCM will return
1566 * Intransition status, and the init will failed.
1567 */
9c8b0ec7
PW
1568 if (oh->_state == _HWMOD_STATE_INITIALIZED ||
1569 oh->_state == _HWMOD_STATE_DISABLED)
1570 for (i = 0; i < oh->rst_lines_cnt; i++)
1571 _deassert_hardreset(oh, oh->rst_lines[i].name);
63c85238 1572
665d0013
RN
1573 /* Mux pins for device runtime if populated */
1574 if (oh->mux && (!oh->mux->enabled ||
1575 ((oh->_state == _HWMOD_STATE_IDLE) &&
1576 oh->mux->pads_dynamic)))
1577 omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
1578
1579 _add_initiator_dep(oh, mpu_oh);
34617e2a 1580
665d0013
RN
1581 if (oh->clkdm) {
1582 /*
1583 * A clockdomain must be in SW_SUP before enabling
1584 * completely the module. The clockdomain can be set
1585 * in HW_AUTO only when the module become ready.
1586 */
1587 hwsup = clkdm_in_hwsup(oh->clkdm);
1588 r = clkdm_hwmod_enable(oh->clkdm, oh);
1589 if (r) {
1590 WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
1591 oh->name, oh->clkdm->name, r);
1592 return r;
1593 }
34617e2a 1594 }
665d0013
RN
1595
1596 _enable_clocks(oh);
45c38252 1597 _enable_module(oh);
34617e2a 1598
665d0013
RN
1599 r = _wait_target_ready(oh);
1600 if (!r) {
1601 /*
1602 * Set the clockdomain to HW_AUTO only if the target is ready,
1603 * assuming that the previous state was HW_AUTO
1604 */
1605 if (oh->clkdm && hwsup)
1606 clkdm_allow_idle(oh->clkdm);
1607
1608 oh->_state = _HWMOD_STATE_ENABLED;
1609
1610 /* Access the sysconfig only if the target is ready */
1611 if (oh->class->sysc) {
1612 if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED))
1613 _update_sysc_cache(oh);
1614 _enable_sysc(oh);
1615 }
1616 } else {
1617 _disable_clocks(oh);
1618 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
1619 oh->name, r);
34617e2a 1620
665d0013
RN
1621 if (oh->clkdm)
1622 clkdm_hwmod_disable(oh->clkdm, oh);
9a23dfe1
BC
1623 }
1624
63c85238
PW
1625 return r;
1626}
1627
1628/**
dc6d1cda 1629 * _idle - idle an omap_hwmod
63c85238
PW
1630 * @oh: struct omap_hwmod *
1631 *
1632 * Idles an omap_hwmod @oh. This should be called once the hwmod has
dc6d1cda
PW
1633 * no further work. Returns -EINVAL if the hwmod is in the wrong
1634 * state or returns 0.
63c85238 1635 */
dc6d1cda 1636static int _idle(struct omap_hwmod *oh)
63c85238 1637{
34617e2a
BC
1638 pr_debug("omap_hwmod: %s: idling\n", oh->name);
1639
63c85238 1640 if (oh->_state != _HWMOD_STATE_ENABLED) {
4f8a428d
RK
1641 WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n",
1642 oh->name);
63c85238
PW
1643 return -EINVAL;
1644 }
1645
43b40992 1646 if (oh->class->sysc)
74ff3a68 1647 _idle_sysc(oh);
63c85238 1648 _del_initiator_dep(oh, mpu_oh);
bfc141e3
BC
1649
1650 _omap4_disable_module(oh);
1651
45c38252
BC
1652 /*
1653 * The module must be in idle mode before disabling any parents
1654 * clocks. Otherwise, the parent clock might be disabled before
1655 * the module transition is done, and thus will prevent the
1656 * transition to complete properly.
1657 */
1658 _disable_clocks(oh);
665d0013
RN
1659 if (oh->clkdm)
1660 clkdm_hwmod_disable(oh->clkdm, oh);
63c85238 1661
8d9af88f 1662 /* Mux pins for device idle if populated */
029268e4 1663 if (oh->mux && oh->mux->pads_dynamic)
8d9af88f
TL
1664 omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE);
1665
63c85238
PW
1666 oh->_state = _HWMOD_STATE_IDLE;
1667
1668 return 0;
1669}
1670
9599217a
KVA
1671/**
1672 * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit
1673 * @oh: struct omap_hwmod *
1674 * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
1675 *
1676 * Sets the IP block's OCP autoidle bit in hardware, and updates our
1677 * local copy. Intended to be used by drivers that require
1678 * direct manipulation of the AUTOIDLE bits.
1679 * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes
1680 * along the return value from _set_module_autoidle().
1681 *
1682 * Any users of this function should be scrutinized carefully.
1683 */
1684int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
1685{
1686 u32 v;
1687 int retval = 0;
1688 unsigned long flags;
1689
1690 if (!oh || oh->_state != _HWMOD_STATE_ENABLED)
1691 return -EINVAL;
1692
1693 spin_lock_irqsave(&oh->_lock, flags);
1694
1695 v = oh->_sysc_cache;
1696
1697 retval = _set_module_autoidle(oh, autoidle, &v);
1698
1699 if (!retval)
1700 _write_sysconfig(v, oh);
1701
1702 spin_unlock_irqrestore(&oh->_lock, flags);
1703
1704 return retval;
1705}
1706
63c85238
PW
1707/**
1708 * _shutdown - shutdown an omap_hwmod
1709 * @oh: struct omap_hwmod *
1710 *
1711 * Shut down an omap_hwmod @oh. This should be called when the driver
1712 * used for the hwmod is removed or unloaded or if the driver is not
1713 * used by the system. Returns -EINVAL if the hwmod is in the wrong
1714 * state or returns 0.
1715 */
1716static int _shutdown(struct omap_hwmod *oh)
1717{
9c8b0ec7 1718 int ret, i;
e4dc8f50
PW
1719 u8 prev_state;
1720
63c85238
PW
1721 if (oh->_state != _HWMOD_STATE_IDLE &&
1722 oh->_state != _HWMOD_STATE_ENABLED) {
4f8a428d
RK
1723 WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n",
1724 oh->name);
63c85238
PW
1725 return -EINVAL;
1726 }
1727
1728 pr_debug("omap_hwmod: %s: disabling\n", oh->name);
1729
e4dc8f50
PW
1730 if (oh->class->pre_shutdown) {
1731 prev_state = oh->_state;
1732 if (oh->_state == _HWMOD_STATE_IDLE)
dc6d1cda 1733 _enable(oh);
e4dc8f50
PW
1734 ret = oh->class->pre_shutdown(oh);
1735 if (ret) {
1736 if (prev_state == _HWMOD_STATE_IDLE)
dc6d1cda 1737 _idle(oh);
e4dc8f50
PW
1738 return ret;
1739 }
1740 }
1741
6481c73c
MV
1742 if (oh->class->sysc) {
1743 if (oh->_state == _HWMOD_STATE_IDLE)
1744 _enable(oh);
74ff3a68 1745 _shutdown_sysc(oh);
6481c73c 1746 }
5365efbe 1747
3827f949
BC
1748 /* clocks and deps are already disabled in idle */
1749 if (oh->_state == _HWMOD_STATE_ENABLED) {
1750 _del_initiator_dep(oh, mpu_oh);
1751 /* XXX what about the other system initiators here? dma, dsp */
bfc141e3 1752 _omap4_disable_module(oh);
45c38252 1753 _disable_clocks(oh);
665d0013
RN
1754 if (oh->clkdm)
1755 clkdm_hwmod_disable(oh->clkdm, oh);
3827f949 1756 }
63c85238
PW
1757 /* XXX Should this code also force-disable the optional clocks? */
1758
9c8b0ec7
PW
1759 for (i = 0; i < oh->rst_lines_cnt; i++)
1760 _assert_hardreset(oh, oh->rst_lines[i].name);
31f62866 1761
8d9af88f
TL
1762 /* Mux pins to safe mode or use populated off mode values */
1763 if (oh->mux)
1764 omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
63c85238
PW
1765
1766 oh->_state = _HWMOD_STATE_DISABLED;
1767
1768 return 0;
1769}
1770
381d033a
PW
1771/**
1772 * _init_mpu_rt_base - populate the virtual address for a hwmod
1773 * @oh: struct omap_hwmod * to locate the virtual address
1774 *
1775 * Cache the virtual address used by the MPU to access this IP block's
1776 * registers. This address is needed early so the OCP registers that
1777 * are part of the device's address space can be ioremapped properly.
1778 * No return value.
1779 */
1780static void __init _init_mpu_rt_base(struct omap_hwmod *oh, void *data)
1781{
1782 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
1783 return;
1784
1785 oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
1786}
1787
1788/**
1789 * _init - initialize internal data for the hwmod @oh
1790 * @oh: struct omap_hwmod *
1791 * @n: (unused)
1792 *
1793 * Look up the clocks and the address space used by the MPU to access
1794 * registers belonging to the hwmod @oh. @oh must already be
1795 * registered at this point. This is the first of two phases for
1796 * hwmod initialization. Code called here does not touch any hardware
1797 * registers, it simply prepares internal data structures. Returns 0
1798 * upon success or if the hwmod isn't registered, or -EINVAL upon
1799 * failure.
1800 */
1801static int __init _init(struct omap_hwmod *oh, void *data)
1802{
1803 int r;
1804
1805 if (oh->_state != _HWMOD_STATE_REGISTERED)
1806 return 0;
1807
1808 _init_mpu_rt_base(oh, NULL);
1809
1810 r = _init_clocks(oh, NULL);
1811 if (IS_ERR_VALUE(r)) {
1812 WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh->name);
1813 return -EINVAL;
1814 }
1815
1816 oh->_state = _HWMOD_STATE_INITIALIZED;
1817
1818 return 0;
1819}
1820
63c85238
PW
1821/**
1822 * _setup - do initial configuration of omap_hwmod
1823 * @oh: struct omap_hwmod *
1824 *
1825 * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
48d54f3f 1826 * OCP_SYSCONFIG register. Returns 0.
63c85238 1827 */
97d60162 1828static int _setup(struct omap_hwmod *oh, void *data)
63c85238 1829{
9a23dfe1 1830 int i, r;
2092e5cc 1831 u8 postsetup_state;
97d60162 1832
381d033a 1833 if (oh->_state != _HWMOD_STATE_INITIALIZED)
48d54f3f
PW
1834 return 0;
1835
63c85238
PW
1836 /* Set iclk autoidle mode */
1837 if (oh->slaves_cnt > 0) {
682fdc96
BC
1838 for (i = 0; i < oh->slaves_cnt; i++) {
1839 struct omap_hwmod_ocp_if *os = oh->slaves[i];
63c85238
PW
1840 struct clk *c = os->_clk;
1841
4d3ae5a9 1842 if (!c)
63c85238
PW
1843 continue;
1844
1845 if (os->flags & OCPIF_SWSUP_IDLE) {
1846 /* XXX omap_iclk_deny_idle(c); */
1847 } else {
1848 /* XXX omap_iclk_allow_idle(c); */
1849 clk_enable(c);
1850 }
1851 }
1852 }
1853
1854 oh->_state = _HWMOD_STATE_INITIALIZED;
1855
5365efbe
BC
1856 /*
1857 * In the case of hwmod with hardreset that should not be
1858 * de-assert at boot time, we have to keep the module
1859 * initialized, because we cannot enable it properly with the
1860 * reset asserted. Exit without warning because that behavior is
1861 * expected.
1862 */
9c8b0ec7 1863 if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt > 0)
5365efbe
BC
1864 return 0;
1865
dc6d1cda 1866 r = _enable(oh);
9a23dfe1
BC
1867 if (r) {
1868 pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n",
1869 oh->name, oh->_state);
1870 return 0;
1871 }
63c85238 1872
2800852a 1873 if (!(oh->flags & HWMOD_INIT_NO_RESET))
76e5589e
BC
1874 _reset(oh);
1875
2092e5cc
PW
1876 postsetup_state = oh->_postsetup_state;
1877 if (postsetup_state == _HWMOD_STATE_UNKNOWN)
1878 postsetup_state = _HWMOD_STATE_ENABLED;
1879
1880 /*
1881 * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data -
1882 * it should be set by the core code as a runtime flag during startup
1883 */
1884 if ((oh->flags & HWMOD_INIT_NO_IDLE) &&
aacf0941
RN
1885 (postsetup_state == _HWMOD_STATE_IDLE)) {
1886 oh->_int_flags |= _HWMOD_SKIP_ENABLE;
2092e5cc 1887 postsetup_state = _HWMOD_STATE_ENABLED;
aacf0941 1888 }
2092e5cc
PW
1889
1890 if (postsetup_state == _HWMOD_STATE_IDLE)
dc6d1cda 1891 _idle(oh);
2092e5cc
PW
1892 else if (postsetup_state == _HWMOD_STATE_DISABLED)
1893 _shutdown(oh);
1894 else if (postsetup_state != _HWMOD_STATE_ENABLED)
1895 WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n",
1896 oh->name, postsetup_state);
63c85238
PW
1897
1898 return 0;
1899}
1900
63c85238 1901/**
0102b627 1902 * _register - register a struct omap_hwmod
63c85238
PW
1903 * @oh: struct omap_hwmod *
1904 *
43b40992
PW
1905 * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod
1906 * already has been registered by the same name; -EINVAL if the
1907 * omap_hwmod is in the wrong state, if @oh is NULL, if the
1908 * omap_hwmod's class field is NULL; if the omap_hwmod is missing a
1909 * name, or if the omap_hwmod's class is missing a name; or 0 upon
1910 * success.
63c85238
PW
1911 *
1912 * XXX The data should be copied into bootmem, so the original data
1913 * should be marked __initdata and freed after init. This would allow
1914 * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note
1915 * that the copy process would be relatively complex due to the large number
1916 * of substructures.
1917 */
01592df9 1918static int __init _register(struct omap_hwmod *oh)
63c85238 1919{
569edd70 1920 int ms_id;
63c85238 1921
43b40992
PW
1922 if (!oh || !oh->name || !oh->class || !oh->class->name ||
1923 (oh->_state != _HWMOD_STATE_UNKNOWN))
63c85238
PW
1924 return -EINVAL;
1925
63c85238
PW
1926 pr_debug("omap_hwmod: %s: registering\n", oh->name);
1927
ce35b244
BC
1928 if (_lookup(oh->name))
1929 return -EEXIST;
63c85238
PW
1930
1931 ms_id = _find_mpu_port_index(oh);
e7c7d760 1932 if (!IS_ERR_VALUE(ms_id))
63c85238 1933 oh->_mpu_port_index = ms_id;
e7c7d760 1934 else
63c85238 1935 oh->_int_flags |= _HWMOD_NO_MPU_PORT;
63c85238
PW
1936
1937 list_add_tail(&oh->node, &omap_hwmod_list);
1938
dc6d1cda 1939 spin_lock_init(&oh->_lock);
2092e5cc 1940
63c85238
PW
1941 oh->_state = _HWMOD_STATE_REGISTERED;
1942
569edd70
PW
1943 /*
1944 * XXX Rather than doing a strcmp(), this should test a flag
1945 * set in the hwmod data, inserted by the autogenerator code.
1946 */
1947 if (!strcmp(oh->name, MPU_INITIATOR_NAME))
1948 mpu_oh = oh;
63c85238 1949
569edd70 1950 return 0;
63c85238
PW
1951}
1952
0102b627
BC
1953
1954/* Public functions */
1955
1956u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
1957{
1958 if (oh->flags & HWMOD_16BIT_REG)
1959 return __raw_readw(oh->_mpu_rt_va + reg_offs);
1960 else
1961 return __raw_readl(oh->_mpu_rt_va + reg_offs);
1962}
1963
1964void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
1965{
1966 if (oh->flags & HWMOD_16BIT_REG)
1967 __raw_writew(v, oh->_mpu_rt_va + reg_offs);
1968 else
1969 __raw_writel(v, oh->_mpu_rt_va + reg_offs);
1970}
1971
6d3c55fd
A
1972/**
1973 * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
1974 * @oh: struct omap_hwmod *
1975 *
1976 * This is a public function exposed to drivers. Some drivers may need to do
1977 * some settings before and after resetting the device. Those drivers after
1978 * doing the necessary settings could use this function to start a reset by
1979 * setting the SYSCONFIG.SOFTRESET bit.
1980 */
1981int omap_hwmod_softreset(struct omap_hwmod *oh)
1982{
3c55c1ba
PW
1983 u32 v;
1984 int ret;
1985
1986 if (!oh || !(oh->_sysc_cache))
6d3c55fd
A
1987 return -EINVAL;
1988
3c55c1ba
PW
1989 v = oh->_sysc_cache;
1990 ret = _set_softreset(oh, &v);
1991 if (ret)
1992 goto error;
1993 _write_sysconfig(v, oh);
1994
1995error:
1996 return ret;
6d3c55fd
A
1997}
1998
0102b627
BC
1999/**
2000 * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
2001 * @oh: struct omap_hwmod *
2002 * @idlemode: SIDLEMODE field bits (shifted to bit 0)
2003 *
2004 * Sets the IP block's OCP slave idlemode in hardware, and updates our
2005 * local copy. Intended to be used by drivers that have some erratum
2006 * that requires direct manipulation of the SIDLEMODE bits. Returns
2007 * -EINVAL if @oh is null, or passes along the return value from
2008 * _set_slave_idlemode().
2009 *
2010 * XXX Does this function have any current users? If not, we should
2011 * remove it; it is better to let the rest of the hwmod code handle this.
2012 * Any users of this function should be scrutinized carefully.
2013 */
2014int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode)
2015{
2016 u32 v;
2017 int retval = 0;
2018
2019 if (!oh)
2020 return -EINVAL;
2021
2022 v = oh->_sysc_cache;
2023
2024 retval = _set_slave_idlemode(oh, idlemode, &v);
2025 if (!retval)
2026 _write_sysconfig(v, oh);
2027
2028 return retval;
2029}
2030
63c85238
PW
2031/**
2032 * omap_hwmod_lookup - look up a registered omap_hwmod by name
2033 * @name: name of the omap_hwmod to look up
2034 *
2035 * Given a @name of an omap_hwmod, return a pointer to the registered
2036 * struct omap_hwmod *, or NULL upon error.
2037 */
2038struct omap_hwmod *omap_hwmod_lookup(const char *name)
2039{
2040 struct omap_hwmod *oh;
2041
2042 if (!name)
2043 return NULL;
2044
63c85238 2045 oh = _lookup(name);
63c85238
PW
2046
2047 return oh;
2048}
2049
2050/**
2051 * omap_hwmod_for_each - call function for each registered omap_hwmod
2052 * @fn: pointer to a callback function
97d60162 2053 * @data: void * data to pass to callback function
63c85238
PW
2054 *
2055 * Call @fn for each registered omap_hwmod, passing @data to each
2056 * function. @fn must return 0 for success or any other value for
2057 * failure. If @fn returns non-zero, the iteration across omap_hwmods
2058 * will stop and the non-zero return value will be passed to the
2059 * caller of omap_hwmod_for_each(). @fn is called with
2060 * omap_hwmod_for_each() held.
2061 */
97d60162
PW
2062int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
2063 void *data)
63c85238
PW
2064{
2065 struct omap_hwmod *temp_oh;
30ebad9d 2066 int ret = 0;
63c85238
PW
2067
2068 if (!fn)
2069 return -EINVAL;
2070
63c85238 2071 list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
97d60162 2072 ret = (*fn)(temp_oh, data);
63c85238
PW
2073 if (ret)
2074 break;
2075 }
63c85238
PW
2076
2077 return ret;
2078}
2079
63c85238 2080/**
550c8092 2081 * omap_hwmod_register - register an array of hwmods
63c85238
PW
2082 * @ohs: pointer to an array of omap_hwmods to register
2083 *
2084 * Intended to be called early in boot before the clock framework is
2085 * initialized. If @ohs is not null, will register all omap_hwmods
550c8092 2086 * listed in @ohs that are valid for this chip. Returns 0.
63c85238 2087 */
550c8092 2088int __init omap_hwmod_register(struct omap_hwmod **ohs)
63c85238 2089{
bac1a0f0 2090 int r, i;
63c85238
PW
2091
2092 if (!ohs)
2093 return 0;
2094
bac1a0f0
PW
2095 i = 0;
2096 do {
bac1a0f0
PW
2097 r = _register(ohs[i]);
2098 WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
2099 r);
2100 } while (ohs[++i]);
63c85238
PW
2101
2102 return 0;
2103}
2104
381d033a
PW
2105/**
2106 * _ensure_mpu_hwmod_is_setup - ensure the MPU SS hwmod is init'ed and set up
2107 * @oh: pointer to the hwmod currently being set up (usually not the MPU)
2108 *
2109 * If the hwmod data corresponding to the MPU subsystem IP block
2110 * hasn't been initialized and set up yet, do so now. This must be
2111 * done first since sleep dependencies may be added from other hwmods
2112 * to the MPU. Intended to be called only by omap_hwmod_setup*(). No
2113 * return value.
63c85238 2114 */
381d033a 2115static void __init _ensure_mpu_hwmod_is_setup(struct omap_hwmod *oh)
e7c7d760 2116{
381d033a
PW
2117 if (!mpu_oh || mpu_oh->_state == _HWMOD_STATE_UNKNOWN)
2118 pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
2119 __func__, MPU_INITIATOR_NAME);
2120 else if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
2121 omap_hwmod_setup_one(MPU_INITIATOR_NAME);
e7c7d760
TL
2122}
2123
63c85238 2124/**
a2debdbd
PW
2125 * omap_hwmod_setup_one - set up a single hwmod
2126 * @oh_name: const char * name of the already-registered hwmod to set up
2127 *
381d033a
PW
2128 * Initialize and set up a single hwmod. Intended to be used for a
2129 * small number of early devices, such as the timer IP blocks used for
2130 * the scheduler clock. Must be called after omap2_clk_init().
2131 * Resolves the struct clk names to struct clk pointers for each
2132 * registered omap_hwmod. Also calls _setup() on each hwmod. Returns
2133 * -EINVAL upon error or 0 upon success.
a2debdbd
PW
2134 */
2135int __init omap_hwmod_setup_one(const char *oh_name)
63c85238
PW
2136{
2137 struct omap_hwmod *oh;
63c85238 2138
a2debdbd
PW
2139 pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
2140
a2debdbd
PW
2141 oh = _lookup(oh_name);
2142 if (!oh) {
2143 WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
2144 return -EINVAL;
2145 }
63c85238 2146
381d033a 2147 _ensure_mpu_hwmod_is_setup(oh);
63c85238 2148
381d033a 2149 _init(oh, NULL);
a2debdbd
PW
2150 _setup(oh, NULL);
2151
63c85238
PW
2152 return 0;
2153}
2154
2155/**
381d033a 2156 * omap_hwmod_setup_all - set up all registered IP blocks
63c85238 2157 *
381d033a
PW
2158 * Initialize and set up all IP blocks registered with the hwmod code.
2159 * Must be called after omap2_clk_init(). Resolves the struct clk
2160 * names to struct clk pointers for each registered omap_hwmod. Also
2161 * calls _setup() on each hwmod. Returns 0 upon success.
63c85238 2162 */
550c8092 2163static int __init omap_hwmod_setup_all(void)
63c85238 2164{
381d033a 2165 _ensure_mpu_hwmod_is_setup(NULL);
63c85238 2166
381d033a 2167 omap_hwmod_for_each(_init, NULL);
2092e5cc 2168 omap_hwmod_for_each(_setup, NULL);
63c85238
PW
2169
2170 return 0;
2171}
550c8092 2172core_initcall(omap_hwmod_setup_all);
63c85238 2173
63c85238
PW
2174/**
2175 * omap_hwmod_enable - enable an omap_hwmod
2176 * @oh: struct omap_hwmod *
2177 *
74ff3a68 2178 * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable().
63c85238
PW
2179 * Returns -EINVAL on error or passes along the return value from _enable().
2180 */
2181int omap_hwmod_enable(struct omap_hwmod *oh)
2182{
2183 int r;
dc6d1cda 2184 unsigned long flags;
63c85238
PW
2185
2186 if (!oh)
2187 return -EINVAL;
2188
dc6d1cda
PW
2189 spin_lock_irqsave(&oh->_lock, flags);
2190 r = _enable(oh);
2191 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
2192
2193 return r;
2194}
2195
2196/**
2197 * omap_hwmod_idle - idle an omap_hwmod
2198 * @oh: struct omap_hwmod *
2199 *
74ff3a68 2200 * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle().
63c85238
PW
2201 * Returns -EINVAL on error or passes along the return value from _idle().
2202 */
2203int omap_hwmod_idle(struct omap_hwmod *oh)
2204{
dc6d1cda
PW
2205 unsigned long flags;
2206
63c85238
PW
2207 if (!oh)
2208 return -EINVAL;
2209
dc6d1cda
PW
2210 spin_lock_irqsave(&oh->_lock, flags);
2211 _idle(oh);
2212 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
2213
2214 return 0;
2215}
2216
2217/**
2218 * omap_hwmod_shutdown - shutdown an omap_hwmod
2219 * @oh: struct omap_hwmod *
2220 *
74ff3a68 2221 * Shutdown an omap_hwmod @oh. Intended to be called by
63c85238
PW
2222 * omap_device_shutdown(). Returns -EINVAL on error or passes along
2223 * the return value from _shutdown().
2224 */
2225int omap_hwmod_shutdown(struct omap_hwmod *oh)
2226{
dc6d1cda
PW
2227 unsigned long flags;
2228
63c85238
PW
2229 if (!oh)
2230 return -EINVAL;
2231
dc6d1cda 2232 spin_lock_irqsave(&oh->_lock, flags);
63c85238 2233 _shutdown(oh);
dc6d1cda 2234 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
2235
2236 return 0;
2237}
2238
2239/**
2240 * omap_hwmod_enable_clocks - enable main_clk, all interface clocks
2241 * @oh: struct omap_hwmod *oh
2242 *
2243 * Intended to be called by the omap_device code.
2244 */
2245int omap_hwmod_enable_clocks(struct omap_hwmod *oh)
2246{
dc6d1cda
PW
2247 unsigned long flags;
2248
2249 spin_lock_irqsave(&oh->_lock, flags);
63c85238 2250 _enable_clocks(oh);
dc6d1cda 2251 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
2252
2253 return 0;
2254}
2255
2256/**
2257 * omap_hwmod_disable_clocks - disable main_clk, all interface clocks
2258 * @oh: struct omap_hwmod *oh
2259 *
2260 * Intended to be called by the omap_device code.
2261 */
2262int omap_hwmod_disable_clocks(struct omap_hwmod *oh)
2263{
dc6d1cda
PW
2264 unsigned long flags;
2265
2266 spin_lock_irqsave(&oh->_lock, flags);
63c85238 2267 _disable_clocks(oh);
dc6d1cda 2268 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
2269
2270 return 0;
2271}
2272
2273/**
2274 * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete
2275 * @oh: struct omap_hwmod *oh
2276 *
2277 * Intended to be called by drivers and core code when all posted
2278 * writes to a device must complete before continuing further
2279 * execution (for example, after clearing some device IRQSTATUS
2280 * register bits)
2281 *
2282 * XXX what about targets with multiple OCP threads?
2283 */
2284void omap_hwmod_ocp_barrier(struct omap_hwmod *oh)
2285{
2286 BUG_ON(!oh);
2287
43b40992 2288 if (!oh->class->sysc || !oh->class->sysc->sysc_flags) {
4f8a428d
RK
2289 WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n",
2290 oh->name);
63c85238
PW
2291 return;
2292 }
2293
2294 /*
2295 * Forces posted writes to complete on the OCP thread handling
2296 * register writes
2297 */
cc7a1d2a 2298 omap_hwmod_read(oh, oh->class->sysc->sysc_offs);
63c85238
PW
2299}
2300
2301/**
2302 * omap_hwmod_reset - reset the hwmod
2303 * @oh: struct omap_hwmod *
2304 *
2305 * Under some conditions, a driver may wish to reset the entire device.
2306 * Called from omap_device code. Returns -EINVAL on error or passes along
9b579114 2307 * the return value from _reset().
63c85238
PW
2308 */
2309int omap_hwmod_reset(struct omap_hwmod *oh)
2310{
2311 int r;
dc6d1cda 2312 unsigned long flags;
63c85238 2313
9b579114 2314 if (!oh)
63c85238
PW
2315 return -EINVAL;
2316
dc6d1cda 2317 spin_lock_irqsave(&oh->_lock, flags);
63c85238 2318 r = _reset(oh);
dc6d1cda 2319 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
2320
2321 return r;
2322}
2323
2324/**
2325 * omap_hwmod_count_resources - count number of struct resources needed by hwmod
2326 * @oh: struct omap_hwmod *
2327 * @res: pointer to the first element of an array of struct resource to fill
2328 *
2329 * Count the number of struct resource array elements necessary to
2330 * contain omap_hwmod @oh resources. Intended to be called by code
2331 * that registers omap_devices. Intended to be used to determine the
2332 * size of a dynamically-allocated struct resource array, before
2333 * calling omap_hwmod_fill_resources(). Returns the number of struct
2334 * resource array elements needed.
2335 *
2336 * XXX This code is not optimized. It could attempt to merge adjacent
2337 * resource IDs.
2338 *
2339 */
2340int omap_hwmod_count_resources(struct omap_hwmod *oh)
2341{
2342 int ret, i;
2343
bc614958 2344 ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
63c85238
PW
2345
2346 for (i = 0; i < oh->slaves_cnt; i++)
78183f3f 2347 ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
63c85238
PW
2348
2349 return ret;
2350}
2351
2352/**
2353 * omap_hwmod_fill_resources - fill struct resource array with hwmod data
2354 * @oh: struct omap_hwmod *
2355 * @res: pointer to the first element of an array of struct resource to fill
2356 *
2357 * Fill the struct resource array @res with resource data from the
2358 * omap_hwmod @oh. Intended to be called by code that registers
2359 * omap_devices. See also omap_hwmod_count_resources(). Returns the
2360 * number of array elements filled.
2361 */
2362int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
2363{
bc614958 2364 int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
63c85238
PW
2365 int r = 0;
2366
2367 /* For each IRQ, DMA, memory area, fill in array.*/
2368
212738a4
PW
2369 mpu_irqs_cnt = _count_mpu_irqs(oh);
2370 for (i = 0; i < mpu_irqs_cnt; i++) {
718bfd76
PW
2371 (res + r)->name = (oh->mpu_irqs + i)->name;
2372 (res + r)->start = (oh->mpu_irqs + i)->irq;
2373 (res + r)->end = (oh->mpu_irqs + i)->irq;
63c85238
PW
2374 (res + r)->flags = IORESOURCE_IRQ;
2375 r++;
2376 }
2377
bc614958
PW
2378 sdma_reqs_cnt = _count_sdma_reqs(oh);
2379 for (i = 0; i < sdma_reqs_cnt; i++) {
9ee9fff9
BC
2380 (res + r)->name = (oh->sdma_reqs + i)->name;
2381 (res + r)->start = (oh->sdma_reqs + i)->dma_req;
2382 (res + r)->end = (oh->sdma_reqs + i)->dma_req;
63c85238
PW
2383 (res + r)->flags = IORESOURCE_DMA;
2384 r++;
2385 }
2386
2387 for (i = 0; i < oh->slaves_cnt; i++) {
2388 struct omap_hwmod_ocp_if *os;
78183f3f 2389 int addr_cnt;
63c85238 2390
682fdc96 2391 os = oh->slaves[i];
78183f3f 2392 addr_cnt = _count_ocp_if_addr_spaces(os);
63c85238 2393
78183f3f 2394 for (j = 0; j < addr_cnt; j++) {
cd503802 2395 (res + r)->name = (os->addr + j)->name;
63c85238
PW
2396 (res + r)->start = (os->addr + j)->pa_start;
2397 (res + r)->end = (os->addr + j)->pa_end;
2398 (res + r)->flags = IORESOURCE_MEM;
2399 r++;
2400 }
2401 }
2402
2403 return r;
2404}
2405
2406/**
2407 * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain
2408 * @oh: struct omap_hwmod *
2409 *
2410 * Return the powerdomain pointer associated with the OMAP module
2411 * @oh's main clock. If @oh does not have a main clk, return the
2412 * powerdomain associated with the interface clock associated with the
2413 * module's MPU port. (XXX Perhaps this should use the SDMA port
2414 * instead?) Returns NULL on error, or a struct powerdomain * on
2415 * success.
2416 */
2417struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh)
2418{
2419 struct clk *c;
2420
2421 if (!oh)
2422 return NULL;
2423
2424 if (oh->_clk) {
2425 c = oh->_clk;
2426 } else {
2427 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
2428 return NULL;
2429 c = oh->slaves[oh->_mpu_port_index]->_clk;
2430 }
2431
d5647c18
TG
2432 if (!c->clkdm)
2433 return NULL;
2434
63c85238
PW
2435 return c->clkdm->pwrdm.ptr;
2436
2437}
2438
db2a60bf
PW
2439/**
2440 * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU)
2441 * @oh: struct omap_hwmod *
2442 *
2443 * Returns the virtual address corresponding to the beginning of the
2444 * module's register target, in the address range that is intended to
2445 * be used by the MPU. Returns the virtual address upon success or NULL
2446 * upon error.
2447 */
2448void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh)
2449{
2450 if (!oh)
2451 return NULL;
2452
2453 if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
2454 return NULL;
2455
2456 if (oh->_state == _HWMOD_STATE_UNKNOWN)
2457 return NULL;
2458
2459 return oh->_mpu_rt_va;
2460}
2461
63c85238
PW
2462/**
2463 * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh
2464 * @oh: struct omap_hwmod *
2465 * @init_oh: struct omap_hwmod * (initiator)
2466 *
2467 * Add a sleep dependency between the initiator @init_oh and @oh.
2468 * Intended to be called by DSP/Bridge code via platform_data for the
2469 * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge
2470 * code needs to add/del initiator dependencies dynamically
2471 * before/after accessing a device. Returns the return value from
2472 * _add_initiator_dep().
2473 *
2474 * XXX Keep a usecount in the clockdomain code
2475 */
2476int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
2477 struct omap_hwmod *init_oh)
2478{
2479 return _add_initiator_dep(oh, init_oh);
2480}
2481
2482/*
2483 * XXX what about functions for drivers to save/restore ocp_sysconfig
2484 * for context save/restore operations?
2485 */
2486
2487/**
2488 * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh
2489 * @oh: struct omap_hwmod *
2490 * @init_oh: struct omap_hwmod * (initiator)
2491 *
2492 * Remove a sleep dependency between the initiator @init_oh and @oh.
2493 * Intended to be called by DSP/Bridge code via platform_data for the
2494 * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge
2495 * code needs to add/del initiator dependencies dynamically
2496 * before/after accessing a device. Returns the return value from
2497 * _del_initiator_dep().
2498 *
2499 * XXX Keep a usecount in the clockdomain code
2500 */
2501int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
2502 struct omap_hwmod *init_oh)
2503{
2504 return _del_initiator_dep(oh, init_oh);
2505}
2506
63c85238
PW
2507/**
2508 * omap_hwmod_enable_wakeup - allow device to wake up the system
2509 * @oh: struct omap_hwmod *
2510 *
2511 * Sets the module OCP socket ENAWAKEUP bit to allow the module to
2a1cc144
G
2512 * send wakeups to the PRCM, and enable I/O ring wakeup events for
2513 * this IP block if it has dynamic mux entries. Eventually this
2514 * should set PRCM wakeup registers to cause the PRCM to receive
2515 * wakeup events from the module. Does not set any wakeup routing
2516 * registers beyond this point - if the module is to wake up any other
2517 * module or subsystem, that must be set separately. Called by
2518 * omap_device code. Returns -EINVAL on error or 0 upon success.
63c85238
PW
2519 */
2520int omap_hwmod_enable_wakeup(struct omap_hwmod *oh)
2521{
dc6d1cda 2522 unsigned long flags;
5a7ddcbd 2523 u32 v;
dc6d1cda 2524
dc6d1cda 2525 spin_lock_irqsave(&oh->_lock, flags);
2a1cc144
G
2526
2527 if (oh->class->sysc &&
2528 (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
2529 v = oh->_sysc_cache;
2530 _enable_wakeup(oh, &v);
2531 _write_sysconfig(v, oh);
2532 }
2533
eceec009 2534 _set_idle_ioring_wakeup(oh, true);
dc6d1cda 2535 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
2536
2537 return 0;
2538}
2539
2540/**
2541 * omap_hwmod_disable_wakeup - prevent device from waking the system
2542 * @oh: struct omap_hwmod *
2543 *
2544 * Clears the module OCP socket ENAWAKEUP bit to prevent the module
2a1cc144
G
2545 * from sending wakeups to the PRCM, and disable I/O ring wakeup
2546 * events for this IP block if it has dynamic mux entries. Eventually
2547 * this should clear PRCM wakeup registers to cause the PRCM to ignore
2548 * wakeup events from the module. Does not set any wakeup routing
2549 * registers beyond this point - if the module is to wake up any other
2550 * module or subsystem, that must be set separately. Called by
2551 * omap_device code. Returns -EINVAL on error or 0 upon success.
63c85238
PW
2552 */
2553int omap_hwmod_disable_wakeup(struct omap_hwmod *oh)
2554{
dc6d1cda 2555 unsigned long flags;
5a7ddcbd 2556 u32 v;
dc6d1cda 2557
dc6d1cda 2558 spin_lock_irqsave(&oh->_lock, flags);
2a1cc144
G
2559
2560 if (oh->class->sysc &&
2561 (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) {
2562 v = oh->_sysc_cache;
2563 _disable_wakeup(oh, &v);
2564 _write_sysconfig(v, oh);
2565 }
2566
eceec009 2567 _set_idle_ioring_wakeup(oh, false);
dc6d1cda 2568 spin_unlock_irqrestore(&oh->_lock, flags);
63c85238
PW
2569
2570 return 0;
2571}
43b40992 2572
aee48e3c
PW
2573/**
2574 * omap_hwmod_assert_hardreset - assert the HW reset line of submodules
2575 * contained in the hwmod module.
2576 * @oh: struct omap_hwmod *
2577 * @name: name of the reset line to lookup and assert
2578 *
2579 * Some IP like dsp, ipu or iva contain processor that require
2580 * an HW reset line to be assert / deassert in order to enable fully
2581 * the IP. Returns -EINVAL if @oh is null or if the operation is not
2582 * yet supported on this OMAP; otherwise, passes along the return value
2583 * from _assert_hardreset().
2584 */
2585int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name)
2586{
2587 int ret;
dc6d1cda 2588 unsigned long flags;
aee48e3c
PW
2589
2590 if (!oh)
2591 return -EINVAL;
2592
dc6d1cda 2593 spin_lock_irqsave(&oh->_lock, flags);
aee48e3c 2594 ret = _assert_hardreset(oh, name);
dc6d1cda 2595 spin_unlock_irqrestore(&oh->_lock, flags);
aee48e3c
PW
2596
2597 return ret;
2598}
2599
2600/**
2601 * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules
2602 * contained in the hwmod module.
2603 * @oh: struct omap_hwmod *
2604 * @name: name of the reset line to look up and deassert
2605 *
2606 * Some IP like dsp, ipu or iva contain processor that require
2607 * an HW reset line to be assert / deassert in order to enable fully
2608 * the IP. Returns -EINVAL if @oh is null or if the operation is not
2609 * yet supported on this OMAP; otherwise, passes along the return value
2610 * from _deassert_hardreset().
2611 */
2612int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name)
2613{
2614 int ret;
dc6d1cda 2615 unsigned long flags;
aee48e3c
PW
2616
2617 if (!oh)
2618 return -EINVAL;
2619
dc6d1cda 2620 spin_lock_irqsave(&oh->_lock, flags);
aee48e3c 2621 ret = _deassert_hardreset(oh, name);
dc6d1cda 2622 spin_unlock_irqrestore(&oh->_lock, flags);
aee48e3c
PW
2623
2624 return ret;
2625}
2626
2627/**
2628 * omap_hwmod_read_hardreset - read the HW reset line state of submodules
2629 * contained in the hwmod module
2630 * @oh: struct omap_hwmod *
2631 * @name: name of the reset line to look up and read
2632 *
2633 * Return the current state of the hwmod @oh's reset line named @name:
2634 * returns -EINVAL upon parameter error or if this operation
2635 * is unsupported on the current OMAP; otherwise, passes along the return
2636 * value from _read_hardreset().
2637 */
2638int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name)
2639{
2640 int ret;
dc6d1cda 2641 unsigned long flags;
aee48e3c
PW
2642
2643 if (!oh)
2644 return -EINVAL;
2645
dc6d1cda 2646 spin_lock_irqsave(&oh->_lock, flags);
aee48e3c 2647 ret = _read_hardreset(oh, name);
dc6d1cda 2648 spin_unlock_irqrestore(&oh->_lock, flags);
aee48e3c
PW
2649
2650 return ret;
2651}
2652
2653
43b40992
PW
2654/**
2655 * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname
2656 * @classname: struct omap_hwmod_class name to search for
2657 * @fn: callback function pointer to call for each hwmod in class @classname
2658 * @user: arbitrary context data to pass to the callback function
2659 *
ce35b244
BC
2660 * For each omap_hwmod of class @classname, call @fn.
2661 * If the callback function returns something other than
43b40992
PW
2662 * zero, the iterator is terminated, and the callback function's return
2663 * value is passed back to the caller. Returns 0 upon success, -EINVAL
2664 * if @classname or @fn are NULL, or passes back the error code from @fn.
2665 */
2666int omap_hwmod_for_each_by_class(const char *classname,
2667 int (*fn)(struct omap_hwmod *oh,
2668 void *user),
2669 void *user)
2670{
2671 struct omap_hwmod *temp_oh;
2672 int ret = 0;
2673
2674 if (!classname || !fn)
2675 return -EINVAL;
2676
2677 pr_debug("omap_hwmod: %s: looking for modules of class %s\n",
2678 __func__, classname);
2679
43b40992
PW
2680 list_for_each_entry(temp_oh, &omap_hwmod_list, node) {
2681 if (!strcmp(temp_oh->class->name, classname)) {
2682 pr_debug("omap_hwmod: %s: %s: calling callback fn\n",
2683 __func__, temp_oh->name);
2684 ret = (*fn)(temp_oh, user);
2685 if (ret)
2686 break;
2687 }
2688 }
2689
43b40992
PW
2690 if (ret)
2691 pr_debug("omap_hwmod: %s: iterator terminated early: %d\n",
2692 __func__, ret);
2693
2694 return ret;
2695}
2696
2092e5cc
PW
2697/**
2698 * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod
2699 * @oh: struct omap_hwmod *
2700 * @state: state that _setup() should leave the hwmod in
2701 *
550c8092 2702 * Sets the hwmod state that @oh will enter at the end of _setup()
a2debdbd
PW
2703 * (called by omap_hwmod_setup_*()). Only valid to call between
2704 * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns
550c8092
PW
2705 * 0 upon success or -EINVAL if there is a problem with the arguments
2706 * or if the hwmod is in the wrong state.
2092e5cc
PW
2707 */
2708int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
2709{
2710 int ret;
dc6d1cda 2711 unsigned long flags;
2092e5cc
PW
2712
2713 if (!oh)
2714 return -EINVAL;
2715
2716 if (state != _HWMOD_STATE_DISABLED &&
2717 state != _HWMOD_STATE_ENABLED &&
2718 state != _HWMOD_STATE_IDLE)
2719 return -EINVAL;
2720
dc6d1cda 2721 spin_lock_irqsave(&oh->_lock, flags);
2092e5cc
PW
2722
2723 if (oh->_state != _HWMOD_STATE_REGISTERED) {
2724 ret = -EINVAL;
2725 goto ohsps_unlock;
2726 }
2727
2728 oh->_postsetup_state = state;
2729 ret = 0;
2730
2731ohsps_unlock:
dc6d1cda 2732 spin_unlock_irqrestore(&oh->_lock, flags);
2092e5cc
PW
2733
2734 return ret;
2735}
c80705aa
KH
2736
2737/**
2738 * omap_hwmod_get_context_loss_count - get lost context count
2739 * @oh: struct omap_hwmod *
2740 *
2741 * Query the powerdomain of of @oh to get the context loss
2742 * count for this device.
2743 *
2744 * Returns the context loss count of the powerdomain assocated with @oh
2745 * upon success, or zero if no powerdomain exists for @oh.
2746 */
fc013873 2747int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
c80705aa
KH
2748{
2749 struct powerdomain *pwrdm;
2750 int ret = 0;
2751
2752 pwrdm = omap_hwmod_get_pwrdm(oh);
2753 if (pwrdm)
2754 ret = pwrdm_get_context_loss_count(pwrdm);
2755
2756 return ret;
2757}
43b01643
PW
2758
2759/**
2760 * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup
2761 * @oh: struct omap_hwmod *
2762 *
2763 * Prevent the hwmod @oh from being reset during the setup process.
2764 * Intended for use by board-*.c files on boards with devices that
2765 * cannot tolerate being reset. Must be called before the hwmod has
2766 * been set up. Returns 0 upon success or negative error code upon
2767 * failure.
2768 */
2769int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
2770{
2771 if (!oh)
2772 return -EINVAL;
2773
2774 if (oh->_state != _HWMOD_STATE_REGISTERED) {
2775 pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n",
2776 oh->name);
2777 return -EINVAL;
2778 }
2779
2780 oh->flags |= HWMOD_INIT_NO_RESET;
2781
2782 return 0;
2783}
abc2d545
TK
2784
2785/**
2786 * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ
2787 * @oh: struct omap_hwmod * containing hwmod mux entries
2788 * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup
2789 * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup
2790 *
2791 * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux
2792 * entry number @pad_idx for the hwmod @oh, trigger the interrupt
2793 * service routine for the hwmod's mpu_irqs array index @irq_idx. If
2794 * this function is not called for a given pad_idx, then the ISR
2795 * associated with @oh's first MPU IRQ will be triggered when an I/O
2796 * pad wakeup occurs on that pad. Note that @pad_idx is the index of
2797 * the _dynamic or wakeup_ entry: if there are other entries not
2798 * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these
2799 * entries are NOT COUNTED in the dynamic pad index. This function
2800 * must be called separately for each pad that requires its interrupt
2801 * to be re-routed this way. Returns -EINVAL if there is an argument
2802 * problem or if @oh does not have hwmod mux entries or MPU IRQs;
2803 * returns -ENOMEM if memory cannot be allocated; or 0 upon success.
2804 *
2805 * XXX This function interface is fragile. Rather than using array
2806 * indexes, which are subject to unpredictable change, it should be
2807 * using hwmod IRQ names, and some other stable key for the hwmod mux
2808 * pad records.
2809 */
2810int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
2811{
2812 int nr_irqs;
2813
2814 might_sleep();
2815
2816 if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 ||
2817 pad_idx >= oh->mux->nr_pads_dynamic)
2818 return -EINVAL;
2819
2820 /* Check the number of available mpu_irqs */
2821 for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++)
2822 ;
2823
2824 if (irq_idx >= nr_irqs)
2825 return -EINVAL;
2826
2827 if (!oh->mux->irqs) {
2828 /* XXX What frees this? */
2829 oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic,
2830 GFP_KERNEL);
2831 if (!oh->mux->irqs)
2832 return -ENOMEM;
2833 }
2834 oh->mux->irqs[pad_idx] = irq_idx;
2835
2836 return 0;
2837}