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63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
550c8092 | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
30e105c0 | 5 | * Copyright (C) 2011-2012 Texas Instruments, Inc. |
63c85238 | 6 | * |
4788da26 PW |
7 | * Paul Walmsley, Benoît Cousson, Kevin Hilman |
8 | * | |
9 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
10 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
11 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
12 | * |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License version 2 as | |
15 | * published by the Free Software Foundation. | |
16 | * | |
74ff3a68 PW |
17 | * Introduction |
18 | * ------------ | |
19 | * One way to view an OMAP SoC is as a collection of largely unrelated | |
20 | * IP blocks connected by interconnects. The IP blocks include | |
21 | * devices such as ARM processors, audio serial interfaces, UARTs, | |
22 | * etc. Some of these devices, like the DSP, are created by TI; | |
23 | * others, like the SGX, largely originate from external vendors. In | |
24 | * TI's documentation, on-chip devices are referred to as "OMAP | |
25 | * modules." Some of these IP blocks are identical across several | |
26 | * OMAP versions. Others are revised frequently. | |
63c85238 | 27 | * |
74ff3a68 PW |
28 | * These OMAP modules are tied together by various interconnects. |
29 | * Most of the address and data flow between modules is via OCP-based | |
30 | * interconnects such as the L3 and L4 buses; but there are other | |
31 | * interconnects that distribute the hardware clock tree, handle idle | |
32 | * and reset signaling, supply power, and connect the modules to | |
33 | * various pads or balls on the OMAP package. | |
34 | * | |
35 | * OMAP hwmod provides a consistent way to describe the on-chip | |
36 | * hardware blocks and their integration into the rest of the chip. | |
37 | * This description can be automatically generated from the TI | |
38 | * hardware database. OMAP hwmod provides a standard, consistent API | |
39 | * to reset, enable, idle, and disable these hardware blocks. And | |
40 | * hwmod provides a way for other core code, such as the Linux device | |
41 | * code or the OMAP power management and address space mapping code, | |
42 | * to query the hardware database. | |
43 | * | |
44 | * Using hwmod | |
45 | * ----------- | |
46 | * Drivers won't call hwmod functions directly. That is done by the | |
47 | * omap_device code, and in rare occasions, by custom integration code | |
48 | * in arch/arm/ *omap*. The omap_device code includes functions to | |
49 | * build a struct platform_device using omap_hwmod data, and that is | |
50 | * currently how hwmod data is communicated to drivers and to the | |
51 | * Linux driver model. Most drivers will call omap_hwmod functions only | |
52 | * indirectly, via pm_runtime*() functions. | |
53 | * | |
54 | * From a layering perspective, here is where the OMAP hwmod code | |
55 | * fits into the kernel software stack: | |
56 | * | |
57 | * +-------------------------------+ | |
58 | * | Device driver code | | |
59 | * | (e.g., drivers/) | | |
60 | * +-------------------------------+ | |
61 | * | Linux driver model | | |
62 | * | (platform_device / | | |
63 | * | platform_driver data/code) | | |
64 | * +-------------------------------+ | |
65 | * | OMAP core-driver integration | | |
66 | * |(arch/arm/mach-omap2/devices.c)| | |
67 | * +-------------------------------+ | |
68 | * | omap_device code | | |
69 | * | (../plat-omap/omap_device.c) | | |
70 | * +-------------------------------+ | |
71 | * ----> | omap_hwmod code/data | <----- | |
72 | * | (../mach-omap2/omap_hwmod*) | | |
73 | * +-------------------------------+ | |
74 | * | OMAP clock/PRCM/register fns | | |
75 | * | (__raw_{read,write}l, clk*) | | |
76 | * +-------------------------------+ | |
77 | * | |
78 | * Device drivers should not contain any OMAP-specific code or data in | |
79 | * them. They should only contain code to operate the IP block that | |
80 | * the driver is responsible for. This is because these IP blocks can | |
81 | * also appear in other SoCs, either from TI (such as DaVinci) or from | |
82 | * other manufacturers; and drivers should be reusable across other | |
83 | * platforms. | |
84 | * | |
85 | * The OMAP hwmod code also will attempt to reset and idle all on-chip | |
86 | * devices upon boot. The goal here is for the kernel to be | |
87 | * completely self-reliant and independent from bootloaders. This is | |
88 | * to ensure a repeatable configuration, both to ensure consistent | |
89 | * runtime behavior, and to make it easier for others to reproduce | |
90 | * bugs. | |
91 | * | |
92 | * OMAP module activity states | |
93 | * --------------------------- | |
94 | * The hwmod code considers modules to be in one of several activity | |
95 | * states. IP blocks start out in an UNKNOWN state, then once they | |
96 | * are registered via the hwmod code, proceed to the REGISTERED state. | |
97 | * Once their clock names are resolved to clock pointers, the module | |
98 | * enters the CLKS_INITED state; and finally, once the module has been | |
99 | * reset and the integration registers programmed, the INITIALIZED state | |
100 | * is entered. The hwmod code will then place the module into either | |
101 | * the IDLE state to save power, or in the case of a critical system | |
102 | * module, the ENABLED state. | |
103 | * | |
104 | * OMAP core integration code can then call omap_hwmod*() functions | |
105 | * directly to move the module between the IDLE, ENABLED, and DISABLED | |
106 | * states, as needed. This is done during both the PM idle loop, and | |
107 | * in the OMAP core integration code's implementation of the PM runtime | |
108 | * functions. | |
109 | * | |
110 | * References | |
111 | * ---------- | |
112 | * This is a partial list. | |
63c85238 PW |
113 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) |
114 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
115 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
116 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
117 | * - Open Core Protocol Specification 2.2 | |
118 | * | |
119 | * To do: | |
63c85238 PW |
120 | * - handle IO mapping |
121 | * - bus throughput & module latency measurement code | |
122 | * | |
123 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
124 | * in the appropriate state | |
125 | * XXX error return values should be checked to ensure that they are | |
126 | * appropriate | |
127 | */ | |
128 | #undef DEBUG | |
129 | ||
130 | #include <linux/kernel.h> | |
131 | #include <linux/errno.h> | |
132 | #include <linux/io.h> | |
133 | #include <linux/clk.h> | |
134 | #include <linux/delay.h> | |
135 | #include <linux/err.h> | |
136 | #include <linux/list.h> | |
137 | #include <linux/mutex.h> | |
dc6d1cda | 138 | #include <linux/spinlock.h> |
abc2d545 | 139 | #include <linux/slab.h> |
63c85238 | 140 | |
4e65331c | 141 | #include "common.h" |
ce491cf8 | 142 | #include <plat/cpu.h> |
1540f214 | 143 | #include "clockdomain.h" |
72e06d08 | 144 | #include "powerdomain.h" |
ce491cf8 TL |
145 | #include <plat/clock.h> |
146 | #include <plat/omap_hwmod.h> | |
5365efbe | 147 | #include <plat/prcm.h> |
63c85238 | 148 | |
59fb659b | 149 | #include "cm2xxx_3xxx.h" |
d0f0631d | 150 | #include "cminst44xx.h" |
59fb659b | 151 | #include "prm2xxx_3xxx.h" |
d198b514 | 152 | #include "prm44xx.h" |
eaac329d | 153 | #include "prminst44xx.h" |
8d9af88f | 154 | #include "mux.h" |
63c85238 | 155 | |
5365efbe BC |
156 | /* Maximum microseconds to wait for OMAP module to softreset */ |
157 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | |
63c85238 PW |
158 | |
159 | /* Name of the OMAP hwmod for the MPU */ | |
5c2c0296 | 160 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 PW |
161 | |
162 | /* omap_hwmod_list contains all registered struct omap_hwmods */ | |
163 | static LIST_HEAD(omap_hwmod_list); | |
164 | ||
63c85238 PW |
165 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ |
166 | static struct omap_hwmod *mpu_oh; | |
167 | ||
63c85238 PW |
168 | |
169 | /* Private functions */ | |
170 | ||
171 | /** | |
172 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
173 | * @oh: struct omap_hwmod * | |
174 | * | |
175 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
176 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
177 | * OCP_SYSCONFIG register or 0 upon success. | |
178 | */ | |
179 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
180 | { | |
43b40992 PW |
181 | if (!oh->class->sysc) { |
182 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
183 | return -EINVAL; |
184 | } | |
185 | ||
186 | /* XXX ensure module interface clock is up */ | |
187 | ||
cc7a1d2a | 188 | oh->_sysc_cache = omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 | 189 | |
43b40992 | 190 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 191 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
192 | |
193 | return 0; | |
194 | } | |
195 | ||
196 | /** | |
197 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
198 | * @v: OCP_SYSCONFIG value to write | |
199 | * @oh: struct omap_hwmod * | |
200 | * | |
43b40992 PW |
201 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
202 | * one. No return value. | |
63c85238 PW |
203 | */ |
204 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
205 | { | |
43b40992 PW |
206 | if (!oh->class->sysc) { |
207 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
208 | return; |
209 | } | |
210 | ||
211 | /* XXX ensure module interface clock is up */ | |
212 | ||
233cbe5b RN |
213 | /* Module might have lost context, always update cache and register */ |
214 | oh->_sysc_cache = v; | |
215 | omap_hwmod_write(v, oh, oh->class->sysc->sysc_offs); | |
63c85238 PW |
216 | } |
217 | ||
218 | /** | |
219 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
220 | * @oh: struct omap_hwmod * | |
221 | * @standbymode: MIDLEMODE field bits | |
222 | * @v: pointer to register contents to modify | |
223 | * | |
224 | * Update the master standby mode bits in @v to be @standbymode for | |
225 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
226 | * upon error or 0 upon success. | |
227 | */ | |
228 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
229 | u32 *v) | |
230 | { | |
358f0e63 TG |
231 | u32 mstandby_mask; |
232 | u8 mstandby_shift; | |
233 | ||
43b40992 PW |
234 | if (!oh->class->sysc || |
235 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
236 | return -EINVAL; |
237 | ||
43b40992 PW |
238 | if (!oh->class->sysc->sysc_fields) { |
239 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
240 | return -EINVAL; |
241 | } | |
242 | ||
43b40992 | 243 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
244 | mstandby_mask = (0x3 << mstandby_shift); |
245 | ||
246 | *v &= ~mstandby_mask; | |
247 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
248 | |
249 | return 0; | |
250 | } | |
251 | ||
252 | /** | |
253 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
254 | * @oh: struct omap_hwmod * | |
255 | * @idlemode: SIDLEMODE field bits | |
256 | * @v: pointer to register contents to modify | |
257 | * | |
258 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
259 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
260 | * or 0 upon success. | |
261 | */ | |
262 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
263 | { | |
358f0e63 TG |
264 | u32 sidle_mask; |
265 | u8 sidle_shift; | |
266 | ||
43b40992 PW |
267 | if (!oh->class->sysc || |
268 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
269 | return -EINVAL; |
270 | ||
43b40992 PW |
271 | if (!oh->class->sysc->sysc_fields) { |
272 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
273 | return -EINVAL; |
274 | } | |
275 | ||
43b40992 | 276 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
277 | sidle_mask = (0x3 << sidle_shift); |
278 | ||
279 | *v &= ~sidle_mask; | |
280 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
281 | |
282 | return 0; | |
283 | } | |
284 | ||
285 | /** | |
286 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
287 | * @oh: struct omap_hwmod * | |
288 | * @clockact: CLOCKACTIVITY field bits | |
289 | * @v: pointer to register contents to modify | |
290 | * | |
291 | * Update the clockactivity mode bits in @v to be @clockact for the | |
292 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
293 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
294 | * success. | |
295 | */ | |
296 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
297 | { | |
358f0e63 TG |
298 | u32 clkact_mask; |
299 | u8 clkact_shift; | |
300 | ||
43b40992 PW |
301 | if (!oh->class->sysc || |
302 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
303 | return -EINVAL; |
304 | ||
43b40992 PW |
305 | if (!oh->class->sysc->sysc_fields) { |
306 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
307 | return -EINVAL; |
308 | } | |
309 | ||
43b40992 | 310 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
311 | clkact_mask = (0x3 << clkact_shift); |
312 | ||
313 | *v &= ~clkact_mask; | |
314 | *v |= clockact << clkact_shift; | |
63c85238 PW |
315 | |
316 | return 0; | |
317 | } | |
318 | ||
319 | /** | |
320 | * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
321 | * @oh: struct omap_hwmod * | |
322 | * @v: pointer to register contents to modify | |
323 | * | |
324 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
325 | * error or 0 upon success. | |
326 | */ | |
327 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
328 | { | |
358f0e63 TG |
329 | u32 softrst_mask; |
330 | ||
43b40992 PW |
331 | if (!oh->class->sysc || |
332 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
333 | return -EINVAL; |
334 | ||
43b40992 PW |
335 | if (!oh->class->sysc->sysc_fields) { |
336 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
337 | return -EINVAL; |
338 | } | |
339 | ||
43b40992 | 340 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
341 | |
342 | *v |= softrst_mask; | |
63c85238 PW |
343 | |
344 | return 0; | |
345 | } | |
346 | ||
726072e5 PW |
347 | /** |
348 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
349 | * @oh: struct omap_hwmod * | |
350 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
351 | * @v: pointer to register contents to modify | |
352 | * | |
353 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
354 | * hwmod. The autoidle bit controls whether the module can gate | |
355 | * internal clocks automatically when it isn't doing anything; the | |
356 | * exact function of this bit varies on a per-module basis. This | |
357 | * function does not write to the hardware. Returns -EINVAL upon | |
358 | * error or 0 upon success. | |
359 | */ | |
360 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
361 | u32 *v) | |
362 | { | |
358f0e63 TG |
363 | u32 autoidle_mask; |
364 | u8 autoidle_shift; | |
365 | ||
43b40992 PW |
366 | if (!oh->class->sysc || |
367 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
368 | return -EINVAL; |
369 | ||
43b40992 PW |
370 | if (!oh->class->sysc->sysc_fields) { |
371 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
372 | return -EINVAL; |
373 | } | |
374 | ||
43b40992 | 375 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
8985b63d | 376 | autoidle_mask = (0x1 << autoidle_shift); |
358f0e63 TG |
377 | |
378 | *v &= ~autoidle_mask; | |
379 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
380 | |
381 | return 0; | |
382 | } | |
383 | ||
eceec009 G |
384 | /** |
385 | * _set_idle_ioring_wakeup - enable/disable IO pad wakeup on hwmod idle for mux | |
386 | * @oh: struct omap_hwmod * | |
387 | * @set_wake: bool value indicating to set (true) or clear (false) wakeup enable | |
388 | * | |
389 | * Set or clear the I/O pad wakeup flag in the mux entries for the | |
390 | * hwmod @oh. This function changes the @oh->mux->pads_dynamic array | |
391 | * in memory. If the hwmod is currently idled, and the new idle | |
392 | * values don't match the previous ones, this function will also | |
393 | * update the SCM PADCTRL registers. Otherwise, if the hwmod is not | |
394 | * currently idled, this function won't touch the hardware: the new | |
395 | * mux settings are written to the SCM PADCTRL registers when the | |
396 | * hwmod is idled. No return value. | |
397 | */ | |
398 | static void _set_idle_ioring_wakeup(struct omap_hwmod *oh, bool set_wake) | |
399 | { | |
400 | struct omap_device_pad *pad; | |
401 | bool change = false; | |
402 | u16 prev_idle; | |
403 | int j; | |
404 | ||
405 | if (!oh->mux || !oh->mux->enabled) | |
406 | return; | |
407 | ||
408 | for (j = 0; j < oh->mux->nr_pads_dynamic; j++) { | |
409 | pad = oh->mux->pads_dynamic[j]; | |
410 | ||
411 | if (!(pad->flags & OMAP_DEVICE_PAD_WAKEUP)) | |
412 | continue; | |
413 | ||
414 | prev_idle = pad->idle; | |
415 | ||
416 | if (set_wake) | |
417 | pad->idle |= OMAP_WAKEUP_EN; | |
418 | else | |
419 | pad->idle &= ~OMAP_WAKEUP_EN; | |
420 | ||
421 | if (prev_idle != pad->idle) | |
422 | change = true; | |
423 | } | |
424 | ||
425 | if (change && oh->_state == _HWMOD_STATE_IDLE) | |
426 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); | |
427 | } | |
428 | ||
63c85238 PW |
429 | /** |
430 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
431 | * @oh: struct omap_hwmod * | |
432 | * | |
433 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
434 | * upon error or 0 upon success. | |
435 | */ | |
5a7ddcbd | 436 | static int _enable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 437 | { |
43b40992 | 438 | if (!oh->class->sysc || |
86009eb3 | 439 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
440 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
441 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
442 | return -EINVAL; |
443 | ||
43b40992 PW |
444 | if (!oh->class->sysc->sysc_fields) { |
445 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
446 | return -EINVAL; |
447 | } | |
448 | ||
1fe74113 BC |
449 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
450 | *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift; | |
63c85238 | 451 | |
86009eb3 BC |
452 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
453 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
724019b0 BC |
454 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
455 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 456 | |
63c85238 PW |
457 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
458 | ||
459 | oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; | |
460 | ||
461 | return 0; | |
462 | } | |
463 | ||
464 | /** | |
465 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
466 | * @oh: struct omap_hwmod * | |
467 | * | |
468 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
469 | * upon error or 0 upon success. | |
470 | */ | |
5a7ddcbd | 471 | static int _disable_wakeup(struct omap_hwmod *oh, u32 *v) |
63c85238 | 472 | { |
43b40992 | 473 | if (!oh->class->sysc || |
86009eb3 | 474 | !((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) || |
724019b0 BC |
475 | (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) || |
476 | (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP))) | |
63c85238 PW |
477 | return -EINVAL; |
478 | ||
43b40992 PW |
479 | if (!oh->class->sysc->sysc_fields) { |
480 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
481 | return -EINVAL; |
482 | } | |
483 | ||
1fe74113 BC |
484 | if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) |
485 | *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift); | |
63c85238 | 486 | |
86009eb3 BC |
487 | if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) |
488 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v); | |
724019b0 BC |
489 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) |
490 | _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v); | |
86009eb3 | 491 | |
63c85238 PW |
492 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ |
493 | ||
494 | oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
499 | /** | |
500 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
501 | * @oh: struct omap_hwmod * | |
502 | * | |
503 | * Prevent the hardware module @oh from entering idle while the | |
504 | * hardare module initiator @init_oh is active. Useful when a module | |
505 | * will be accessed by a particular initiator (e.g., if a module will | |
506 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
507 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
508 | * mode. If the clockdomain is marked as not needing autodeps, return |
509 | * 0 without doing anything. Otherwise, returns -EINVAL upon error or | |
510 | * passes along clkdm_add_sleepdep() value upon success. | |
63c85238 PW |
511 | */ |
512 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
513 | { | |
514 | if (!oh->_clk) | |
515 | return -EINVAL; | |
516 | ||
570b54c7 PW |
517 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
518 | return 0; | |
519 | ||
55ed9694 | 520 | return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
521 | } |
522 | ||
523 | /** | |
524 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
525 | * @oh: struct omap_hwmod * | |
526 | * | |
527 | * Allow the hardware module @oh to enter idle while the hardare | |
528 | * module initiator @init_oh is active. Useful when a module will not | |
529 | * be accessed by a particular initiator (e.g., if a module will not | |
530 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
531 | * initiator and the module). Only applies to modules in smart-idle | |
570b54c7 PW |
532 | * mode. If the clockdomain is marked as not needing autodeps, return |
533 | * 0 without doing anything. Returns -EINVAL upon error or passes | |
534 | * along clkdm_del_sleepdep() value upon success. | |
63c85238 PW |
535 | */ |
536 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
537 | { | |
538 | if (!oh->_clk) | |
539 | return -EINVAL; | |
540 | ||
570b54c7 PW |
541 | if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS) |
542 | return 0; | |
543 | ||
55ed9694 | 544 | return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
545 | } |
546 | ||
547 | /** | |
548 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
549 | * @oh: struct omap_hwmod * | |
550 | * | |
551 | * Called from _init_clocks(). Populates the @oh _clk (main | |
552 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
553 | * success or -EINVAL on error. | |
554 | */ | |
555 | static int _init_main_clk(struct omap_hwmod *oh) | |
556 | { | |
63c85238 PW |
557 | int ret = 0; |
558 | ||
50ebdac2 | 559 | if (!oh->main_clk) |
63c85238 PW |
560 | return 0; |
561 | ||
63403384 | 562 | oh->_clk = omap_clk_get_by_name(oh->main_clk); |
dc75925d | 563 | if (!oh->_clk) { |
20383d82 BC |
564 | pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
565 | oh->name, oh->main_clk); | |
63403384 | 566 | return -EINVAL; |
dc75925d | 567 | } |
63c85238 | 568 | |
63403384 BC |
569 | if (!oh->_clk->clkdm) |
570 | pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", | |
571 | oh->main_clk, oh->_clk->name); | |
81d7c6ff | 572 | |
63c85238 PW |
573 | return ret; |
574 | } | |
575 | ||
576 | /** | |
887adeac | 577 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
578 | * @oh: struct omap_hwmod * |
579 | * | |
580 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
581 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
582 | */ | |
583 | static int _init_interface_clks(struct omap_hwmod *oh) | |
584 | { | |
63c85238 PW |
585 | struct clk *c; |
586 | int i; | |
587 | int ret = 0; | |
588 | ||
589 | if (oh->slaves_cnt == 0) | |
590 | return 0; | |
591 | ||
682fdc96 BC |
592 | for (i = 0; i < oh->slaves_cnt; i++) { |
593 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
594 | ||
50ebdac2 | 595 | if (!os->clk) |
63c85238 PW |
596 | continue; |
597 | ||
50ebdac2 | 598 | c = omap_clk_get_by_name(os->clk); |
dc75925d | 599 | if (!c) { |
20383d82 BC |
600 | pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
601 | oh->name, os->clk); | |
63c85238 | 602 | ret = -EINVAL; |
dc75925d | 603 | } |
63c85238 PW |
604 | os->_clk = c; |
605 | } | |
606 | ||
607 | return ret; | |
608 | } | |
609 | ||
610 | /** | |
611 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
612 | * @oh: struct omap_hwmod * | |
613 | * | |
614 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
615 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
616 | */ | |
617 | static int _init_opt_clks(struct omap_hwmod *oh) | |
618 | { | |
619 | struct omap_hwmod_opt_clk *oc; | |
620 | struct clk *c; | |
621 | int i; | |
622 | int ret = 0; | |
623 | ||
624 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
50ebdac2 | 625 | c = omap_clk_get_by_name(oc->clk); |
dc75925d | 626 | if (!c) { |
20383d82 BC |
627 | pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
628 | oh->name, oc->clk); | |
63c85238 | 629 | ret = -EINVAL; |
dc75925d | 630 | } |
63c85238 PW |
631 | oc->_clk = c; |
632 | } | |
633 | ||
634 | return ret; | |
635 | } | |
636 | ||
637 | /** | |
638 | * _enable_clocks - enable hwmod main clock and interface clocks | |
639 | * @oh: struct omap_hwmod * | |
640 | * | |
641 | * Enables all clocks necessary for register reads and writes to succeed | |
642 | * on the hwmod @oh. Returns 0. | |
643 | */ | |
644 | static int _enable_clocks(struct omap_hwmod *oh) | |
645 | { | |
63c85238 PW |
646 | int i; |
647 | ||
648 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
649 | ||
4d3ae5a9 | 650 | if (oh->_clk) |
63c85238 PW |
651 | clk_enable(oh->_clk); |
652 | ||
653 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
654 | for (i = 0; i < oh->slaves_cnt; i++) { |
655 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
656 | struct clk *c = os->_clk; |
657 | ||
4d3ae5a9 | 658 | if (c && (os->flags & OCPIF_SWSUP_IDLE)) |
63c85238 PW |
659 | clk_enable(c); |
660 | } | |
661 | } | |
662 | ||
663 | /* The opt clocks are controlled by the device driver. */ | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
668 | /** | |
669 | * _disable_clocks - disable hwmod main clock and interface clocks | |
670 | * @oh: struct omap_hwmod * | |
671 | * | |
672 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
673 | */ | |
674 | static int _disable_clocks(struct omap_hwmod *oh) | |
675 | { | |
63c85238 PW |
676 | int i; |
677 | ||
678 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
679 | ||
4d3ae5a9 | 680 | if (oh->_clk) |
63c85238 PW |
681 | clk_disable(oh->_clk); |
682 | ||
683 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
684 | for (i = 0; i < oh->slaves_cnt; i++) { |
685 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
686 | struct clk *c = os->_clk; |
687 | ||
4d3ae5a9 | 688 | if (c && (os->flags & OCPIF_SWSUP_IDLE)) |
63c85238 PW |
689 | clk_disable(c); |
690 | } | |
691 | } | |
692 | ||
693 | /* The opt clocks are controlled by the device driver. */ | |
694 | ||
695 | return 0; | |
696 | } | |
697 | ||
96835af9 BC |
698 | static void _enable_optional_clocks(struct omap_hwmod *oh) |
699 | { | |
700 | struct omap_hwmod_opt_clk *oc; | |
701 | int i; | |
702 | ||
703 | pr_debug("omap_hwmod: %s: enabling optional clocks\n", oh->name); | |
704 | ||
705 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
706 | if (oc->_clk) { | |
707 | pr_debug("omap_hwmod: enable %s:%s\n", oc->role, | |
708 | oc->_clk->name); | |
709 | clk_enable(oc->_clk); | |
710 | } | |
711 | } | |
712 | ||
713 | static void _disable_optional_clocks(struct omap_hwmod *oh) | |
714 | { | |
715 | struct omap_hwmod_opt_clk *oc; | |
716 | int i; | |
717 | ||
718 | pr_debug("omap_hwmod: %s: disabling optional clocks\n", oh->name); | |
719 | ||
720 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
721 | if (oc->_clk) { | |
722 | pr_debug("omap_hwmod: disable %s:%s\n", oc->role, | |
723 | oc->_clk->name); | |
724 | clk_disable(oc->_clk); | |
725 | } | |
726 | } | |
727 | ||
45c38252 BC |
728 | /** |
729 | * _enable_module - enable CLKCTRL modulemode on OMAP4 | |
730 | * @oh: struct omap_hwmod * | |
731 | * | |
732 | * Enables the PRCM module mode related to the hwmod @oh. | |
733 | * No return value. | |
734 | */ | |
735 | static void _enable_module(struct omap_hwmod *oh) | |
736 | { | |
737 | /* The module mode does not exist prior OMAP4 */ | |
738 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
739 | return; | |
740 | ||
741 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
742 | return; | |
743 | ||
744 | pr_debug("omap_hwmod: %s: _enable_module: %d\n", | |
745 | oh->name, oh->prcm.omap4.modulemode); | |
746 | ||
747 | omap4_cminst_module_enable(oh->prcm.omap4.modulemode, | |
748 | oh->clkdm->prcm_partition, | |
749 | oh->clkdm->cm_inst, | |
750 | oh->clkdm->clkdm_offs, | |
751 | oh->prcm.omap4.clkctrl_offs); | |
752 | } | |
753 | ||
754 | /** | |
bfc141e3 BC |
755 | * _omap4_wait_target_disable - wait for a module to be disabled on OMAP4 |
756 | * @oh: struct omap_hwmod * | |
757 | * | |
758 | * Wait for a module @oh to enter slave idle. Returns 0 if the module | |
759 | * does not have an IDLEST bit or if the module successfully enters | |
760 | * slave idle; otherwise, pass along the return value of the | |
761 | * appropriate *_cm*_wait_module_idle() function. | |
762 | */ | |
763 | static int _omap4_wait_target_disable(struct omap_hwmod *oh) | |
764 | { | |
765 | if (!cpu_is_omap44xx()) | |
766 | return 0; | |
767 | ||
768 | if (!oh) | |
769 | return -EINVAL; | |
770 | ||
771 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
772 | return 0; | |
773 | ||
774 | if (oh->flags & HWMOD_NO_IDLEST) | |
775 | return 0; | |
776 | ||
777 | return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition, | |
778 | oh->clkdm->cm_inst, | |
779 | oh->clkdm->clkdm_offs, | |
780 | oh->prcm.omap4.clkctrl_offs); | |
781 | } | |
782 | ||
783 | /** | |
784 | * _omap4_disable_module - enable CLKCTRL modulemode on OMAP4 | |
45c38252 BC |
785 | * @oh: struct omap_hwmod * |
786 | * | |
787 | * Disable the PRCM module mode related to the hwmod @oh. | |
bfc141e3 | 788 | * Return EINVAL if the modulemode is not supported and 0 in case of success. |
45c38252 | 789 | */ |
bfc141e3 | 790 | static int _omap4_disable_module(struct omap_hwmod *oh) |
45c38252 | 791 | { |
bfc141e3 BC |
792 | int v; |
793 | ||
45c38252 | 794 | /* The module mode does not exist prior OMAP4 */ |
bfc141e3 BC |
795 | if (!cpu_is_omap44xx()) |
796 | return -EINVAL; | |
45c38252 BC |
797 | |
798 | if (!oh->clkdm || !oh->prcm.omap4.modulemode) | |
bfc141e3 | 799 | return -EINVAL; |
45c38252 | 800 | |
bfc141e3 | 801 | pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__); |
45c38252 BC |
802 | |
803 | omap4_cminst_module_disable(oh->clkdm->prcm_partition, | |
804 | oh->clkdm->cm_inst, | |
805 | oh->clkdm->clkdm_offs, | |
806 | oh->prcm.omap4.clkctrl_offs); | |
bfc141e3 BC |
807 | |
808 | v = _omap4_wait_target_disable(oh); | |
809 | if (v) | |
810 | pr_warn("omap_hwmod: %s: _wait_target_disable failed\n", | |
811 | oh->name); | |
812 | ||
813 | return 0; | |
45c38252 BC |
814 | } |
815 | ||
212738a4 PW |
816 | /** |
817 | * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh | |
818 | * @oh: struct omap_hwmod *oh | |
819 | * | |
820 | * Count and return the number of MPU IRQs associated with the hwmod | |
821 | * @oh. Used to allocate struct resource data. Returns 0 if @oh is | |
822 | * NULL. | |
823 | */ | |
824 | static int _count_mpu_irqs(struct omap_hwmod *oh) | |
825 | { | |
826 | struct omap_hwmod_irq_info *ohii; | |
827 | int i = 0; | |
828 | ||
829 | if (!oh || !oh->mpu_irqs) | |
830 | return 0; | |
831 | ||
832 | do { | |
833 | ohii = &oh->mpu_irqs[i++]; | |
834 | } while (ohii->irq != -1); | |
835 | ||
cc1b0765 | 836 | return i-1; |
212738a4 PW |
837 | } |
838 | ||
bc614958 PW |
839 | /** |
840 | * _count_sdma_reqs - count the number of SDMA request lines associated with @oh | |
841 | * @oh: struct omap_hwmod *oh | |
842 | * | |
843 | * Count and return the number of SDMA request lines associated with | |
844 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
845 | * if @oh is NULL. | |
846 | */ | |
847 | static int _count_sdma_reqs(struct omap_hwmod *oh) | |
848 | { | |
849 | struct omap_hwmod_dma_info *ohdi; | |
850 | int i = 0; | |
851 | ||
852 | if (!oh || !oh->sdma_reqs) | |
853 | return 0; | |
854 | ||
855 | do { | |
856 | ohdi = &oh->sdma_reqs[i++]; | |
857 | } while (ohdi->dma_req != -1); | |
858 | ||
cc1b0765 | 859 | return i-1; |
bc614958 PW |
860 | } |
861 | ||
78183f3f PW |
862 | /** |
863 | * _count_ocp_if_addr_spaces - count the number of address space entries for @oh | |
864 | * @oh: struct omap_hwmod *oh | |
865 | * | |
866 | * Count and return the number of address space ranges associated with | |
867 | * the hwmod @oh. Used to allocate struct resource data. Returns 0 | |
868 | * if @oh is NULL. | |
869 | */ | |
870 | static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os) | |
871 | { | |
872 | struct omap_hwmod_addr_space *mem; | |
873 | int i = 0; | |
874 | ||
875 | if (!os || !os->addr) | |
876 | return 0; | |
877 | ||
878 | do { | |
879 | mem = &os->addr[i++]; | |
880 | } while (mem->pa_start != mem->pa_end); | |
881 | ||
cc1b0765 | 882 | return i-1; |
78183f3f PW |
883 | } |
884 | ||
63c85238 PW |
885 | /** |
886 | * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use | |
887 | * @oh: struct omap_hwmod * | |
888 | * | |
889 | * Returns the array index of the OCP slave port that the MPU | |
890 | * addresses the device on, or -EINVAL upon error or not found. | |
891 | */ | |
01592df9 | 892 | static int __init _find_mpu_port_index(struct omap_hwmod *oh) |
63c85238 | 893 | { |
63c85238 PW |
894 | int i; |
895 | int found = 0; | |
896 | ||
897 | if (!oh || oh->slaves_cnt == 0) | |
898 | return -EINVAL; | |
899 | ||
682fdc96 BC |
900 | for (i = 0; i < oh->slaves_cnt; i++) { |
901 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
902 | ||
63c85238 PW |
903 | if (os->user & OCP_USER_MPU) { |
904 | found = 1; | |
905 | break; | |
906 | } | |
907 | } | |
908 | ||
909 | if (found) | |
910 | pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n", | |
911 | oh->name, i); | |
912 | else | |
913 | pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n", | |
914 | oh->name); | |
915 | ||
916 | return (found) ? i : -EINVAL; | |
917 | } | |
918 | ||
919 | /** | |
920 | * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU | |
921 | * @oh: struct omap_hwmod * | |
922 | * | |
923 | * Return the virtual address of the base of the register target of | |
924 | * device @oh, or NULL on error. | |
925 | */ | |
01592df9 | 926 | static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index) |
63c85238 PW |
927 | { |
928 | struct omap_hwmod_ocp_if *os; | |
929 | struct omap_hwmod_addr_space *mem; | |
78183f3f | 930 | int i = 0, found = 0; |
986a13f5 | 931 | void __iomem *va_start; |
63c85238 PW |
932 | |
933 | if (!oh || oh->slaves_cnt == 0) | |
934 | return NULL; | |
935 | ||
682fdc96 | 936 | os = oh->slaves[index]; |
63c85238 | 937 | |
78183f3f PW |
938 | if (!os->addr) |
939 | return NULL; | |
940 | ||
941 | do { | |
942 | mem = &os->addr[i++]; | |
943 | if (mem->flags & ADDR_TYPE_RT) | |
63c85238 | 944 | found = 1; |
78183f3f | 945 | } while (!found && mem->pa_start != mem->pa_end); |
63c85238 | 946 | |
986a13f5 TL |
947 | if (found) { |
948 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
949 | if (!va_start) { | |
950 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
951 | return NULL; | |
952 | } | |
63c85238 | 953 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", |
986a13f5 TL |
954 | oh->name, va_start); |
955 | } else { | |
63c85238 PW |
956 | pr_debug("omap_hwmod: %s: no MPU register target found\n", |
957 | oh->name); | |
986a13f5 | 958 | } |
63c85238 | 959 | |
986a13f5 | 960 | return (found) ? va_start : NULL; |
63c85238 PW |
961 | } |
962 | ||
963 | /** | |
74ff3a68 | 964 | * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG |
63c85238 PW |
965 | * @oh: struct omap_hwmod * |
966 | * | |
967 | * If module is marked as SWSUP_SIDLE, force the module out of slave | |
968 | * idle; otherwise, configure it for smart-idle. If module is marked | |
969 | * as SWSUP_MSUSPEND, force the module out of master standby; | |
970 | * otherwise, configure it for smart-standby. No return value. | |
971 | */ | |
74ff3a68 | 972 | static void _enable_sysc(struct omap_hwmod *oh) |
63c85238 | 973 | { |
43b40992 | 974 | u8 idlemode, sf; |
63c85238 PW |
975 | u32 v; |
976 | ||
43b40992 | 977 | if (!oh->class->sysc) |
63c85238 PW |
978 | return; |
979 | ||
980 | v = oh->_sysc_cache; | |
43b40992 | 981 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 982 | |
43b40992 | 983 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
984 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
985 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
986 | _set_slave_idlemode(oh, idlemode, &v); | |
987 | } | |
988 | ||
43b40992 | 989 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
990 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
991 | idlemode = HWMOD_IDLEMODE_NO; | |
992 | } else { | |
993 | if (sf & SYSC_HAS_ENAWAKEUP) | |
994 | _enable_wakeup(oh, &v); | |
995 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
996 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
997 | else | |
998 | idlemode = HWMOD_IDLEMODE_SMART; | |
999 | } | |
63c85238 PW |
1000 | _set_master_standbymode(oh, idlemode, &v); |
1001 | } | |
1002 | ||
a16b1f7f PW |
1003 | /* |
1004 | * XXX The clock framework should handle this, by | |
1005 | * calling into this code. But this must wait until the | |
1006 | * clock structures are tagged with omap_hwmod entries | |
1007 | */ | |
43b40992 PW |
1008 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
1009 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
1010 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 | 1011 | |
9980ce53 RN |
1012 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1013 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
5a7ddcbd KH |
1014 | _enable_wakeup(oh, &v); |
1015 | ||
1016 | _write_sysconfig(v, oh); | |
78f26e87 HH |
1017 | |
1018 | /* | |
1019 | * Set the autoidle bit only after setting the smartidle bit | |
1020 | * Setting this will not have any impact on the other modules. | |
1021 | */ | |
1022 | if (sf & SYSC_HAS_AUTOIDLE) { | |
1023 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? | |
1024 | 0 : 1; | |
1025 | _set_module_autoidle(oh, idlemode, &v); | |
1026 | _write_sysconfig(v, oh); | |
1027 | } | |
63c85238 PW |
1028 | } |
1029 | ||
1030 | /** | |
74ff3a68 | 1031 | * _idle_sysc - try to put a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1032 | * @oh: struct omap_hwmod * |
1033 | * | |
1034 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
1035 | * idle; otherwise, configure it for smart-idle. If module is marked | |
1036 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
1037 | * configure it for smart-standby. No return value. | |
1038 | */ | |
74ff3a68 | 1039 | static void _idle_sysc(struct omap_hwmod *oh) |
63c85238 | 1040 | { |
43b40992 | 1041 | u8 idlemode, sf; |
63c85238 PW |
1042 | u32 v; |
1043 | ||
43b40992 | 1044 | if (!oh->class->sysc) |
63c85238 PW |
1045 | return; |
1046 | ||
1047 | v = oh->_sysc_cache; | |
43b40992 | 1048 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1049 | |
43b40992 | 1050 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
1051 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
1052 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | |
1053 | _set_slave_idlemode(oh, idlemode, &v); | |
1054 | } | |
1055 | ||
43b40992 | 1056 | if (sf & SYSC_HAS_MIDLEMODE) { |
724019b0 BC |
1057 | if (oh->flags & HWMOD_SWSUP_MSTANDBY) { |
1058 | idlemode = HWMOD_IDLEMODE_FORCE; | |
1059 | } else { | |
1060 | if (sf & SYSC_HAS_ENAWAKEUP) | |
1061 | _enable_wakeup(oh, &v); | |
1062 | if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP) | |
1063 | idlemode = HWMOD_IDLEMODE_SMART_WKUP; | |
1064 | else | |
1065 | idlemode = HWMOD_IDLEMODE_SMART; | |
1066 | } | |
63c85238 PW |
1067 | _set_master_standbymode(oh, idlemode, &v); |
1068 | } | |
1069 | ||
86009eb3 BC |
1070 | /* If slave is in SMARTIDLE, also enable wakeup */ |
1071 | if ((sf & SYSC_HAS_SIDLEMODE) && !(oh->flags & HWMOD_SWSUP_SIDLE)) | |
1072 | _enable_wakeup(oh, &v); | |
1073 | ||
63c85238 PW |
1074 | _write_sysconfig(v, oh); |
1075 | } | |
1076 | ||
1077 | /** | |
74ff3a68 | 1078 | * _shutdown_sysc - force a module into idle via OCP_SYSCONFIG |
63c85238 PW |
1079 | * @oh: struct omap_hwmod * |
1080 | * | |
1081 | * Force the module into slave idle and master suspend. No return | |
1082 | * value. | |
1083 | */ | |
74ff3a68 | 1084 | static void _shutdown_sysc(struct omap_hwmod *oh) |
63c85238 PW |
1085 | { |
1086 | u32 v; | |
43b40992 | 1087 | u8 sf; |
63c85238 | 1088 | |
43b40992 | 1089 | if (!oh->class->sysc) |
63c85238 PW |
1090 | return; |
1091 | ||
1092 | v = oh->_sysc_cache; | |
43b40992 | 1093 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 1094 | |
43b40992 | 1095 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
1096 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1097 | ||
43b40992 | 1098 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
1099 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
1100 | ||
43b40992 | 1101 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 1102 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
1103 | |
1104 | _write_sysconfig(v, oh); | |
1105 | } | |
1106 | ||
1107 | /** | |
1108 | * _lookup - find an omap_hwmod by name | |
1109 | * @name: find an omap_hwmod by name | |
1110 | * | |
1111 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
63c85238 PW |
1112 | */ |
1113 | static struct omap_hwmod *_lookup(const char *name) | |
1114 | { | |
1115 | struct omap_hwmod *oh, *temp_oh; | |
1116 | ||
1117 | oh = NULL; | |
1118 | ||
1119 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1120 | if (!strcmp(name, temp_oh->name)) { | |
1121 | oh = temp_oh; | |
1122 | break; | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | return oh; | |
1127 | } | |
6ae76997 BC |
1128 | /** |
1129 | * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod | |
1130 | * @oh: struct omap_hwmod * | |
1131 | * | |
1132 | * Convert a clockdomain name stored in a struct omap_hwmod into a | |
1133 | * clockdomain pointer, and save it into the struct omap_hwmod. | |
1134 | * return -EINVAL if clkdm_name does not exist or if the lookup failed. | |
1135 | */ | |
1136 | static int _init_clkdm(struct omap_hwmod *oh) | |
1137 | { | |
1138 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1139 | return 0; | |
1140 | ||
1141 | if (!oh->clkdm_name) { | |
1142 | pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name); | |
1143 | return -EINVAL; | |
1144 | } | |
1145 | ||
1146 | oh->clkdm = clkdm_lookup(oh->clkdm_name); | |
1147 | if (!oh->clkdm) { | |
1148 | pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n", | |
1149 | oh->name, oh->clkdm_name); | |
1150 | return -EINVAL; | |
1151 | } | |
1152 | ||
1153 | pr_debug("omap_hwmod: %s: associated to clkdm %s\n", | |
1154 | oh->name, oh->clkdm_name); | |
1155 | ||
1156 | return 0; | |
1157 | } | |
63c85238 PW |
1158 | |
1159 | /** | |
6ae76997 BC |
1160 | * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as |
1161 | * well the clockdomain. | |
63c85238 | 1162 | * @oh: struct omap_hwmod * |
97d60162 | 1163 | * @data: not used; pass NULL |
63c85238 | 1164 | * |
a2debdbd | 1165 | * Called by omap_hwmod_setup_*() (after omap2_clk_init()). |
48d54f3f PW |
1166 | * Resolves all clock names embedded in the hwmod. Returns 0 on |
1167 | * success, or a negative error code on failure. | |
63c85238 | 1168 | */ |
97d60162 | 1169 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
1170 | { |
1171 | int ret = 0; | |
1172 | ||
48d54f3f PW |
1173 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
1174 | return 0; | |
63c85238 PW |
1175 | |
1176 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
1177 | ||
1178 | ret |= _init_main_clk(oh); | |
1179 | ret |= _init_interface_clks(oh); | |
1180 | ret |= _init_opt_clks(oh); | |
6ae76997 | 1181 | ret |= _init_clkdm(oh); |
63c85238 | 1182 | |
f5c1f84b BC |
1183 | if (!ret) |
1184 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
6652271a BC |
1185 | else |
1186 | pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name); | |
63c85238 | 1187 | |
09c35f2f | 1188 | return ret; |
63c85238 PW |
1189 | } |
1190 | ||
1191 | /** | |
1192 | * _wait_target_ready - wait for a module to leave slave idle | |
1193 | * @oh: struct omap_hwmod * | |
1194 | * | |
1195 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
1196 | * does not have an IDLEST bit or if the module successfully leaves | |
1197 | * slave idle; otherwise, pass along the return value of the | |
d0f0631d | 1198 | * appropriate *_cm*_wait_module_ready() function. |
63c85238 PW |
1199 | */ |
1200 | static int _wait_target_ready(struct omap_hwmod *oh) | |
1201 | { | |
1202 | struct omap_hwmod_ocp_if *os; | |
1203 | int ret; | |
1204 | ||
1205 | if (!oh) | |
1206 | return -EINVAL; | |
1207 | ||
1208 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
1209 | return 0; | |
1210 | ||
682fdc96 | 1211 | os = oh->slaves[oh->_mpu_port_index]; |
63c85238 | 1212 | |
33f7ec81 | 1213 | if (oh->flags & HWMOD_NO_IDLEST) |
63c85238 PW |
1214 | return 0; |
1215 | ||
1216 | /* XXX check module SIDLEMODE */ | |
1217 | ||
1218 | /* XXX check clock enable states */ | |
1219 | ||
1220 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1221 | ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, | |
1222 | oh->prcm.omap2.idlest_reg_id, | |
1223 | oh->prcm.omap2.idlest_idle_bit); | |
63c85238 | 1224 | } else if (cpu_is_omap44xx()) { |
d0f0631d BC |
1225 | if (!oh->clkdm) |
1226 | return -EINVAL; | |
1227 | ||
1228 | ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition, | |
1229 | oh->clkdm->cm_inst, | |
1230 | oh->clkdm->clkdm_offs, | |
1231 | oh->prcm.omap4.clkctrl_offs); | |
63c85238 PW |
1232 | } else { |
1233 | BUG(); | |
1234 | }; | |
1235 | ||
1236 | return ret; | |
1237 | } | |
1238 | ||
5365efbe | 1239 | /** |
cc1226e7 | 1240 | * _lookup_hardreset - fill register bit info for this hwmod/reset line |
5365efbe BC |
1241 | * @oh: struct omap_hwmod * |
1242 | * @name: name of the reset line in the context of this hwmod | |
cc1226e7 | 1243 | * @ohri: struct omap_hwmod_rst_info * that this function will fill in |
5365efbe BC |
1244 | * |
1245 | * Return the bit position of the reset line that match the | |
1246 | * input name. Return -ENOENT if not found. | |
1247 | */ | |
cc1226e7 | 1248 | static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name, |
1249 | struct omap_hwmod_rst_info *ohri) | |
5365efbe BC |
1250 | { |
1251 | int i; | |
1252 | ||
1253 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
1254 | const char *rst_line = oh->rst_lines[i].name; | |
1255 | if (!strcmp(rst_line, name)) { | |
cc1226e7 | 1256 | ohri->rst_shift = oh->rst_lines[i].rst_shift; |
1257 | ohri->st_shift = oh->rst_lines[i].st_shift; | |
1258 | pr_debug("omap_hwmod: %s: %s: %s: rst %d st %d\n", | |
1259 | oh->name, __func__, rst_line, ohri->rst_shift, | |
1260 | ohri->st_shift); | |
5365efbe | 1261 | |
cc1226e7 | 1262 | return 0; |
5365efbe BC |
1263 | } |
1264 | } | |
1265 | ||
1266 | return -ENOENT; | |
1267 | } | |
1268 | ||
1269 | /** | |
1270 | * _assert_hardreset - assert the HW reset line of submodules | |
1271 | * contained in the hwmod module. | |
1272 | * @oh: struct omap_hwmod * | |
1273 | * @name: name of the reset line to lookup and assert | |
1274 | * | |
1275 | * Some IP like dsp, ipu or iva contain processor that require | |
1276 | * an HW reset line to be assert / deassert in order to enable fully | |
1277 | * the IP. | |
1278 | */ | |
1279 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1280 | { | |
cc1226e7 | 1281 | struct omap_hwmod_rst_info ohri; |
1282 | u8 ret; | |
5365efbe BC |
1283 | |
1284 | if (!oh) | |
1285 | return -EINVAL; | |
1286 | ||
cc1226e7 | 1287 | ret = _lookup_hardreset(oh, name, &ohri); |
1288 | if (IS_ERR_VALUE(ret)) | |
1289 | return ret; | |
5365efbe BC |
1290 | |
1291 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
1292 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | |
cc1226e7 | 1293 | ohri.rst_shift); |
5365efbe | 1294 | else if (cpu_is_omap44xx()) |
eaac329d BC |
1295 | return omap4_prminst_assert_hardreset(ohri.rst_shift, |
1296 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
1297 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
1298 | oh->prcm.omap4.rstctrl_offs); | |
5365efbe BC |
1299 | else |
1300 | return -EINVAL; | |
1301 | } | |
1302 | ||
1303 | /** | |
1304 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
1305 | * in the hwmod module. | |
1306 | * @oh: struct omap_hwmod * | |
1307 | * @name: name of the reset line to look up and deassert | |
1308 | * | |
1309 | * Some IP like dsp, ipu or iva contain processor that require | |
1310 | * an HW reset line to be assert / deassert in order to enable fully | |
1311 | * the IP. | |
1312 | */ | |
1313 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1314 | { | |
cc1226e7 | 1315 | struct omap_hwmod_rst_info ohri; |
1316 | int ret; | |
5365efbe BC |
1317 | |
1318 | if (!oh) | |
1319 | return -EINVAL; | |
1320 | ||
cc1226e7 | 1321 | ret = _lookup_hardreset(oh, name, &ohri); |
1322 | if (IS_ERR_VALUE(ret)) | |
1323 | return ret; | |
5365efbe | 1324 | |
cc1226e7 | 1325 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
1326 | ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | |
1327 | ohri.rst_shift, | |
1328 | ohri.st_shift); | |
1329 | } else if (cpu_is_omap44xx()) { | |
1330 | if (ohri.st_shift) | |
1331 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | |
1332 | oh->name, name); | |
eaac329d BC |
1333 | ret = omap4_prminst_deassert_hardreset(ohri.rst_shift, |
1334 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
1335 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
1336 | oh->prcm.omap4.rstctrl_offs); | |
cc1226e7 | 1337 | } else { |
5365efbe | 1338 | return -EINVAL; |
cc1226e7 | 1339 | } |
5365efbe | 1340 | |
cc1226e7 | 1341 | if (ret == -EBUSY) |
5365efbe BC |
1342 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); |
1343 | ||
cc1226e7 | 1344 | return ret; |
5365efbe BC |
1345 | } |
1346 | ||
1347 | /** | |
1348 | * _read_hardreset - read the HW reset line state of submodules | |
1349 | * contained in the hwmod module | |
1350 | * @oh: struct omap_hwmod * | |
1351 | * @name: name of the reset line to look up and read | |
1352 | * | |
1353 | * Return the state of the reset line. | |
1354 | */ | |
1355 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
1356 | { | |
cc1226e7 | 1357 | struct omap_hwmod_rst_info ohri; |
1358 | u8 ret; | |
5365efbe BC |
1359 | |
1360 | if (!oh) | |
1361 | return -EINVAL; | |
1362 | ||
cc1226e7 | 1363 | ret = _lookup_hardreset(oh, name, &ohri); |
1364 | if (IS_ERR_VALUE(ret)) | |
1365 | return ret; | |
5365efbe BC |
1366 | |
1367 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
1368 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | |
cc1226e7 | 1369 | ohri.st_shift); |
5365efbe | 1370 | } else if (cpu_is_omap44xx()) { |
eaac329d BC |
1371 | return omap4_prminst_is_hardreset_asserted(ohri.rst_shift, |
1372 | oh->clkdm->pwrdm.ptr->prcm_partition, | |
1373 | oh->clkdm->pwrdm.ptr->prcm_offs, | |
1374 | oh->prcm.omap4.rstctrl_offs); | |
5365efbe BC |
1375 | } else { |
1376 | return -EINVAL; | |
1377 | } | |
1378 | } | |
1379 | ||
63c85238 | 1380 | /** |
bd36179e | 1381 | * _ocp_softreset - reset an omap_hwmod via the OCP_SYSCONFIG bit |
63c85238 PW |
1382 | * @oh: struct omap_hwmod * |
1383 | * | |
1384 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
30e105c0 PW |
1385 | * enabled for this to work. Returns -ENOENT if the hwmod cannot be |
1386 | * reset this way, -EINVAL if the hwmod is in the wrong state, | |
1387 | * -ETIMEDOUT if the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
1388 | * |
1389 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
bd36179e | 1390 | * Starting in OMAP4, some IPs do not have SYSSTATUS registers and instead |
2cb06814 BC |
1391 | * use the SYSCONFIG softreset bit to provide the status. |
1392 | * | |
bd36179e PW |
1393 | * Note that some IP like McBSP do have reset control but don't have |
1394 | * reset status. | |
63c85238 | 1395 | */ |
bd36179e | 1396 | static int _ocp_softreset(struct omap_hwmod *oh) |
63c85238 | 1397 | { |
387ca5bf | 1398 | u32 v, softrst_mask; |
6f8b7ff5 | 1399 | int c = 0; |
96835af9 | 1400 | int ret = 0; |
63c85238 | 1401 | |
43b40992 | 1402 | if (!oh->class->sysc || |
2cb06814 | 1403 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
30e105c0 | 1404 | return -ENOENT; |
63c85238 PW |
1405 | |
1406 | /* clocks must be on for this operation */ | |
1407 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
76e5589e BC |
1408 | pr_warning("omap_hwmod: %s: reset can only be entered from " |
1409 | "enabled state\n", oh->name); | |
63c85238 PW |
1410 | return -EINVAL; |
1411 | } | |
1412 | ||
96835af9 BC |
1413 | /* For some modules, all optionnal clocks need to be enabled as well */ |
1414 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1415 | _enable_optional_clocks(oh); | |
1416 | ||
bd36179e | 1417 | pr_debug("omap_hwmod: %s: resetting via OCP SOFTRESET\n", oh->name); |
63c85238 PW |
1418 | |
1419 | v = oh->_sysc_cache; | |
96835af9 BC |
1420 | ret = _set_softreset(oh, &v); |
1421 | if (ret) | |
1422 | goto dis_opt_clks; | |
63c85238 PW |
1423 | _write_sysconfig(v, oh); |
1424 | ||
d99de7f5 FGL |
1425 | if (oh->class->sysc->srst_udelay) |
1426 | udelay(oh->class->sysc->srst_udelay); | |
1427 | ||
2cb06814 | 1428 | if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) |
cc7a1d2a | 1429 | omap_test_timeout((omap_hwmod_read(oh, |
2cb06814 BC |
1430 | oh->class->sysc->syss_offs) |
1431 | & SYSS_RESETDONE_MASK), | |
1432 | MAX_MODULE_SOFTRESET_WAIT, c); | |
387ca5bf RN |
1433 | else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) { |
1434 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); | |
cc7a1d2a | 1435 | omap_test_timeout(!(omap_hwmod_read(oh, |
2cb06814 | 1436 | oh->class->sysc->sysc_offs) |
387ca5bf | 1437 | & softrst_mask), |
2cb06814 | 1438 | MAX_MODULE_SOFTRESET_WAIT, c); |
387ca5bf | 1439 | } |
63c85238 | 1440 | |
5365efbe | 1441 | if (c == MAX_MODULE_SOFTRESET_WAIT) |
76e5589e BC |
1442 | pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1443 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
63c85238 | 1444 | else |
5365efbe | 1445 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
63c85238 PW |
1446 | |
1447 | /* | |
1448 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1449 | * _wait_target_ready() or _reset() | |
1450 | */ | |
1451 | ||
96835af9 BC |
1452 | ret = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; |
1453 | ||
1454 | dis_opt_clks: | |
1455 | if (oh->flags & HWMOD_CONTROL_OPT_CLKS_IN_RESET) | |
1456 | _disable_optional_clocks(oh); | |
1457 | ||
1458 | return ret; | |
63c85238 PW |
1459 | } |
1460 | ||
bd36179e PW |
1461 | /** |
1462 | * _reset - reset an omap_hwmod | |
1463 | * @oh: struct omap_hwmod * | |
1464 | * | |
30e105c0 PW |
1465 | * Resets an omap_hwmod @oh. If the module has a custom reset |
1466 | * function pointer defined, then call it to reset the IP block, and | |
1467 | * pass along its return value to the caller. Otherwise, if the IP | |
1468 | * block has an OCP_SYSCONFIG register with a SOFTRESET bitfield | |
1469 | * associated with it, call a function to reset the IP block via that | |
1470 | * method, and pass along the return value to the caller. Finally, if | |
1471 | * the IP block has some hardreset lines associated with it, assert | |
1472 | * all of those, but do _not_ deassert them. (This is because driver | |
1473 | * authors have expressed an apparent requirement to control the | |
1474 | * deassertion of the hardreset lines themselves.) | |
1475 | * | |
1476 | * The default software reset mechanism for most OMAP IP blocks is | |
1477 | * triggered via the OCP_SYSCONFIG.SOFTRESET bit. However, some | |
1478 | * hwmods cannot be reset via this method. Some are not targets and | |
1479 | * therefore have no OCP header registers to access. Others (like the | |
1480 | * IVA) have idiosyncratic reset sequences. So for these relatively | |
1481 | * rare cases, custom reset code can be supplied in the struct | |
1482 | * omap_hwmod_class .reset function pointer. Passes along the return | |
1483 | * value from either _ocp_softreset() or the custom reset function - | |
1484 | * these must return -EINVAL if the hwmod cannot be reset this way or | |
1485 | * if the hwmod is in the wrong state, -ETIMEDOUT if the module did | |
1486 | * not reset in time, or 0 upon success. | |
bd36179e PW |
1487 | */ |
1488 | static int _reset(struct omap_hwmod *oh) | |
1489 | { | |
30e105c0 | 1490 | int i, r; |
bd36179e PW |
1491 | |
1492 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
1493 | ||
30e105c0 PW |
1494 | if (oh->class->reset) { |
1495 | r = oh->class->reset(oh); | |
1496 | } else { | |
1497 | if (oh->rst_lines_cnt > 0) { | |
1498 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1499 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
1500 | return 0; | |
1501 | } else { | |
1502 | r = _ocp_softreset(oh); | |
1503 | if (r == -ENOENT) | |
1504 | r = 0; | |
1505 | } | |
1506 | } | |
1507 | ||
9c8b0ec7 | 1508 | /* |
30e105c0 PW |
1509 | * OCP_SYSCONFIG bits need to be reprogrammed after a |
1510 | * softreset. The _enable() function should be split to avoid | |
1511 | * the rewrite of the OCP_SYSCONFIG register. | |
9c8b0ec7 | 1512 | */ |
2800852a RN |
1513 | if (oh->class->sysc) { |
1514 | _update_sysc_cache(oh); | |
1515 | _enable_sysc(oh); | |
1516 | } | |
1517 | ||
30e105c0 | 1518 | return r; |
bd36179e PW |
1519 | } |
1520 | ||
63c85238 | 1521 | /** |
dc6d1cda | 1522 | * _enable - enable an omap_hwmod |
63c85238 PW |
1523 | * @oh: struct omap_hwmod * |
1524 | * | |
1525 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
dc6d1cda PW |
1526 | * register target. Returns -EINVAL if the hwmod is in the wrong |
1527 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 1528 | */ |
dc6d1cda | 1529 | static int _enable(struct omap_hwmod *oh) |
63c85238 | 1530 | { |
9c8b0ec7 | 1531 | int r, i; |
665d0013 | 1532 | int hwsup = 0; |
63c85238 | 1533 | |
34617e2a BC |
1534 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); |
1535 | ||
aacf0941 RN |
1536 | /* |
1537 | * hwmods with HWMOD_INIT_NO_IDLE flag set are left | |
1538 | * in enabled state at init. | |
1539 | * Now that someone is really trying to enable them, | |
1540 | * just ensure that the hwmod mux is set. | |
1541 | */ | |
1542 | if (oh->_int_flags & _HWMOD_SKIP_ENABLE) { | |
1543 | /* | |
1544 | * If the caller has mux data populated, do the mux'ing | |
1545 | * which wouldn't have been done as part of the _enable() | |
1546 | * done during setup. | |
1547 | */ | |
1548 | if (oh->mux) | |
1549 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
1550 | ||
1551 | oh->_int_flags &= ~_HWMOD_SKIP_ENABLE; | |
1552 | return 0; | |
1553 | } | |
1554 | ||
63c85238 PW |
1555 | if (oh->_state != _HWMOD_STATE_INITIALIZED && |
1556 | oh->_state != _HWMOD_STATE_IDLE && | |
1557 | oh->_state != _HWMOD_STATE_DISABLED) { | |
4f8a428d RK |
1558 | WARN(1, "omap_hwmod: %s: enabled state can only be entered from initialized, idle, or disabled state\n", |
1559 | oh->name); | |
63c85238 PW |
1560 | return -EINVAL; |
1561 | } | |
1562 | ||
31f62866 | 1563 | /* |
9c8b0ec7 | 1564 | * If an IP contains HW reset lines, then de-assert them in order |
31f62866 BC |
1565 | * to allow the module state transition. Otherwise the PRCM will return |
1566 | * Intransition status, and the init will failed. | |
1567 | */ | |
9c8b0ec7 PW |
1568 | if (oh->_state == _HWMOD_STATE_INITIALIZED || |
1569 | oh->_state == _HWMOD_STATE_DISABLED) | |
1570 | for (i = 0; i < oh->rst_lines_cnt; i++) | |
1571 | _deassert_hardreset(oh, oh->rst_lines[i].name); | |
63c85238 | 1572 | |
665d0013 RN |
1573 | /* Mux pins for device runtime if populated */ |
1574 | if (oh->mux && (!oh->mux->enabled || | |
1575 | ((oh->_state == _HWMOD_STATE_IDLE) && | |
1576 | oh->mux->pads_dynamic))) | |
1577 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED); | |
1578 | ||
1579 | _add_initiator_dep(oh, mpu_oh); | |
34617e2a | 1580 | |
665d0013 RN |
1581 | if (oh->clkdm) { |
1582 | /* | |
1583 | * A clockdomain must be in SW_SUP before enabling | |
1584 | * completely the module. The clockdomain can be set | |
1585 | * in HW_AUTO only when the module become ready. | |
1586 | */ | |
1587 | hwsup = clkdm_in_hwsup(oh->clkdm); | |
1588 | r = clkdm_hwmod_enable(oh->clkdm, oh); | |
1589 | if (r) { | |
1590 | WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n", | |
1591 | oh->name, oh->clkdm->name, r); | |
1592 | return r; | |
1593 | } | |
34617e2a | 1594 | } |
665d0013 RN |
1595 | |
1596 | _enable_clocks(oh); | |
45c38252 | 1597 | _enable_module(oh); |
34617e2a | 1598 | |
665d0013 RN |
1599 | r = _wait_target_ready(oh); |
1600 | if (!r) { | |
1601 | /* | |
1602 | * Set the clockdomain to HW_AUTO only if the target is ready, | |
1603 | * assuming that the previous state was HW_AUTO | |
1604 | */ | |
1605 | if (oh->clkdm && hwsup) | |
1606 | clkdm_allow_idle(oh->clkdm); | |
1607 | ||
1608 | oh->_state = _HWMOD_STATE_ENABLED; | |
1609 | ||
1610 | /* Access the sysconfig only if the target is ready */ | |
1611 | if (oh->class->sysc) { | |
1612 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
1613 | _update_sysc_cache(oh); | |
1614 | _enable_sysc(oh); | |
1615 | } | |
1616 | } else { | |
1617 | _disable_clocks(oh); | |
1618 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | |
1619 | oh->name, r); | |
34617e2a | 1620 | |
665d0013 RN |
1621 | if (oh->clkdm) |
1622 | clkdm_hwmod_disable(oh->clkdm, oh); | |
9a23dfe1 BC |
1623 | } |
1624 | ||
63c85238 PW |
1625 | return r; |
1626 | } | |
1627 | ||
1628 | /** | |
dc6d1cda | 1629 | * _idle - idle an omap_hwmod |
63c85238 PW |
1630 | * @oh: struct omap_hwmod * |
1631 | * | |
1632 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
dc6d1cda PW |
1633 | * no further work. Returns -EINVAL if the hwmod is in the wrong |
1634 | * state or returns 0. | |
63c85238 | 1635 | */ |
dc6d1cda | 1636 | static int _idle(struct omap_hwmod *oh) |
63c85238 | 1637 | { |
34617e2a BC |
1638 | pr_debug("omap_hwmod: %s: idling\n", oh->name); |
1639 | ||
63c85238 | 1640 | if (oh->_state != _HWMOD_STATE_ENABLED) { |
4f8a428d RK |
1641 | WARN(1, "omap_hwmod: %s: idle state can only be entered from enabled state\n", |
1642 | oh->name); | |
63c85238 PW |
1643 | return -EINVAL; |
1644 | } | |
1645 | ||
43b40992 | 1646 | if (oh->class->sysc) |
74ff3a68 | 1647 | _idle_sysc(oh); |
63c85238 | 1648 | _del_initiator_dep(oh, mpu_oh); |
bfc141e3 BC |
1649 | |
1650 | _omap4_disable_module(oh); | |
1651 | ||
45c38252 BC |
1652 | /* |
1653 | * The module must be in idle mode before disabling any parents | |
1654 | * clocks. Otherwise, the parent clock might be disabled before | |
1655 | * the module transition is done, and thus will prevent the | |
1656 | * transition to complete properly. | |
1657 | */ | |
1658 | _disable_clocks(oh); | |
665d0013 RN |
1659 | if (oh->clkdm) |
1660 | clkdm_hwmod_disable(oh->clkdm, oh); | |
63c85238 | 1661 | |
8d9af88f | 1662 | /* Mux pins for device idle if populated */ |
029268e4 | 1663 | if (oh->mux && oh->mux->pads_dynamic) |
8d9af88f TL |
1664 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_IDLE); |
1665 | ||
63c85238 PW |
1666 | oh->_state = _HWMOD_STATE_IDLE; |
1667 | ||
1668 | return 0; | |
1669 | } | |
1670 | ||
9599217a KVA |
1671 | /** |
1672 | * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit | |
1673 | * @oh: struct omap_hwmod * | |
1674 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
1675 | * | |
1676 | * Sets the IP block's OCP autoidle bit in hardware, and updates our | |
1677 | * local copy. Intended to be used by drivers that require | |
1678 | * direct manipulation of the AUTOIDLE bits. | |
1679 | * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes | |
1680 | * along the return value from _set_module_autoidle(). | |
1681 | * | |
1682 | * Any users of this function should be scrutinized carefully. | |
1683 | */ | |
1684 | int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle) | |
1685 | { | |
1686 | u32 v; | |
1687 | int retval = 0; | |
1688 | unsigned long flags; | |
1689 | ||
1690 | if (!oh || oh->_state != _HWMOD_STATE_ENABLED) | |
1691 | return -EINVAL; | |
1692 | ||
1693 | spin_lock_irqsave(&oh->_lock, flags); | |
1694 | ||
1695 | v = oh->_sysc_cache; | |
1696 | ||
1697 | retval = _set_module_autoidle(oh, autoidle, &v); | |
1698 | ||
1699 | if (!retval) | |
1700 | _write_sysconfig(v, oh); | |
1701 | ||
1702 | spin_unlock_irqrestore(&oh->_lock, flags); | |
1703 | ||
1704 | return retval; | |
1705 | } | |
1706 | ||
63c85238 PW |
1707 | /** |
1708 | * _shutdown - shutdown an omap_hwmod | |
1709 | * @oh: struct omap_hwmod * | |
1710 | * | |
1711 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
1712 | * used for the hwmod is removed or unloaded or if the driver is not | |
1713 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
1714 | * state or returns 0. | |
1715 | */ | |
1716 | static int _shutdown(struct omap_hwmod *oh) | |
1717 | { | |
9c8b0ec7 | 1718 | int ret, i; |
e4dc8f50 PW |
1719 | u8 prev_state; |
1720 | ||
63c85238 PW |
1721 | if (oh->_state != _HWMOD_STATE_IDLE && |
1722 | oh->_state != _HWMOD_STATE_ENABLED) { | |
4f8a428d RK |
1723 | WARN(1, "omap_hwmod: %s: disabled state can only be entered from idle, or enabled state\n", |
1724 | oh->name); | |
63c85238 PW |
1725 | return -EINVAL; |
1726 | } | |
1727 | ||
1728 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); | |
1729 | ||
e4dc8f50 PW |
1730 | if (oh->class->pre_shutdown) { |
1731 | prev_state = oh->_state; | |
1732 | if (oh->_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1733 | _enable(oh); |
e4dc8f50 PW |
1734 | ret = oh->class->pre_shutdown(oh); |
1735 | if (ret) { | |
1736 | if (prev_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1737 | _idle(oh); |
e4dc8f50 PW |
1738 | return ret; |
1739 | } | |
1740 | } | |
1741 | ||
6481c73c MV |
1742 | if (oh->class->sysc) { |
1743 | if (oh->_state == _HWMOD_STATE_IDLE) | |
1744 | _enable(oh); | |
74ff3a68 | 1745 | _shutdown_sysc(oh); |
6481c73c | 1746 | } |
5365efbe | 1747 | |
3827f949 BC |
1748 | /* clocks and deps are already disabled in idle */ |
1749 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
1750 | _del_initiator_dep(oh, mpu_oh); | |
1751 | /* XXX what about the other system initiators here? dma, dsp */ | |
bfc141e3 | 1752 | _omap4_disable_module(oh); |
45c38252 | 1753 | _disable_clocks(oh); |
665d0013 RN |
1754 | if (oh->clkdm) |
1755 | clkdm_hwmod_disable(oh->clkdm, oh); | |
3827f949 | 1756 | } |
63c85238 PW |
1757 | /* XXX Should this code also force-disable the optional clocks? */ |
1758 | ||
9c8b0ec7 PW |
1759 | for (i = 0; i < oh->rst_lines_cnt; i++) |
1760 | _assert_hardreset(oh, oh->rst_lines[i].name); | |
31f62866 | 1761 | |
8d9af88f TL |
1762 | /* Mux pins to safe mode or use populated off mode values */ |
1763 | if (oh->mux) | |
1764 | omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED); | |
63c85238 PW |
1765 | |
1766 | oh->_state = _HWMOD_STATE_DISABLED; | |
1767 | ||
1768 | return 0; | |
1769 | } | |
1770 | ||
63c85238 PW |
1771 | /** |
1772 | * _setup - do initial configuration of omap_hwmod | |
1773 | * @oh: struct omap_hwmod * | |
1774 | * | |
1775 | * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh | |
48d54f3f | 1776 | * OCP_SYSCONFIG register. Returns 0. |
63c85238 | 1777 | */ |
97d60162 | 1778 | static int _setup(struct omap_hwmod *oh, void *data) |
63c85238 | 1779 | { |
9a23dfe1 | 1780 | int i, r; |
2092e5cc | 1781 | u8 postsetup_state; |
97d60162 | 1782 | |
48d54f3f PW |
1783 | if (oh->_state != _HWMOD_STATE_CLKS_INITED) |
1784 | return 0; | |
1785 | ||
63c85238 PW |
1786 | /* Set iclk autoidle mode */ |
1787 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
1788 | for (i = 0; i < oh->slaves_cnt; i++) { |
1789 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
1790 | struct clk *c = os->_clk; |
1791 | ||
4d3ae5a9 | 1792 | if (!c) |
63c85238 PW |
1793 | continue; |
1794 | ||
1795 | if (os->flags & OCPIF_SWSUP_IDLE) { | |
1796 | /* XXX omap_iclk_deny_idle(c); */ | |
1797 | } else { | |
1798 | /* XXX omap_iclk_allow_idle(c); */ | |
1799 | clk_enable(c); | |
1800 | } | |
1801 | } | |
1802 | } | |
1803 | ||
1804 | oh->_state = _HWMOD_STATE_INITIALIZED; | |
1805 | ||
5365efbe BC |
1806 | /* |
1807 | * In the case of hwmod with hardreset that should not be | |
1808 | * de-assert at boot time, we have to keep the module | |
1809 | * initialized, because we cannot enable it properly with the | |
1810 | * reset asserted. Exit without warning because that behavior is | |
1811 | * expected. | |
1812 | */ | |
9c8b0ec7 | 1813 | if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt > 0) |
5365efbe BC |
1814 | return 0; |
1815 | ||
dc6d1cda | 1816 | r = _enable(oh); |
9a23dfe1 BC |
1817 | if (r) { |
1818 | pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", | |
1819 | oh->name, oh->_state); | |
1820 | return 0; | |
1821 | } | |
63c85238 | 1822 | |
2800852a | 1823 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) |
76e5589e BC |
1824 | _reset(oh); |
1825 | ||
2092e5cc PW |
1826 | postsetup_state = oh->_postsetup_state; |
1827 | if (postsetup_state == _HWMOD_STATE_UNKNOWN) | |
1828 | postsetup_state = _HWMOD_STATE_ENABLED; | |
1829 | ||
1830 | /* | |
1831 | * XXX HWMOD_INIT_NO_IDLE does not belong in hwmod data - | |
1832 | * it should be set by the core code as a runtime flag during startup | |
1833 | */ | |
1834 | if ((oh->flags & HWMOD_INIT_NO_IDLE) && | |
aacf0941 RN |
1835 | (postsetup_state == _HWMOD_STATE_IDLE)) { |
1836 | oh->_int_flags |= _HWMOD_SKIP_ENABLE; | |
2092e5cc | 1837 | postsetup_state = _HWMOD_STATE_ENABLED; |
aacf0941 | 1838 | } |
2092e5cc PW |
1839 | |
1840 | if (postsetup_state == _HWMOD_STATE_IDLE) | |
dc6d1cda | 1841 | _idle(oh); |
2092e5cc PW |
1842 | else if (postsetup_state == _HWMOD_STATE_DISABLED) |
1843 | _shutdown(oh); | |
1844 | else if (postsetup_state != _HWMOD_STATE_ENABLED) | |
1845 | WARN(1, "hwmod: %s: unknown postsetup state %d! defaulting to enabled\n", | |
1846 | oh->name, postsetup_state); | |
63c85238 PW |
1847 | |
1848 | return 0; | |
1849 | } | |
1850 | ||
63c85238 | 1851 | /** |
0102b627 | 1852 | * _register - register a struct omap_hwmod |
63c85238 PW |
1853 | * @oh: struct omap_hwmod * |
1854 | * | |
43b40992 PW |
1855 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
1856 | * already has been registered by the same name; -EINVAL if the | |
1857 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
1858 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
1859 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
1860 | * success. | |
63c85238 PW |
1861 | * |
1862 | * XXX The data should be copied into bootmem, so the original data | |
1863 | * should be marked __initdata and freed after init. This would allow | |
1864 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
1865 | * that the copy process would be relatively complex due to the large number | |
1866 | * of substructures. | |
1867 | */ | |
01592df9 | 1868 | static int __init _register(struct omap_hwmod *oh) |
63c85238 | 1869 | { |
569edd70 | 1870 | int ms_id; |
63c85238 | 1871 | |
43b40992 PW |
1872 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
1873 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
1874 | return -EINVAL; |
1875 | ||
63c85238 PW |
1876 | pr_debug("omap_hwmod: %s: registering\n", oh->name); |
1877 | ||
ce35b244 BC |
1878 | if (_lookup(oh->name)) |
1879 | return -EEXIST; | |
63c85238 PW |
1880 | |
1881 | ms_id = _find_mpu_port_index(oh); | |
e7c7d760 | 1882 | if (!IS_ERR_VALUE(ms_id)) |
63c85238 | 1883 | oh->_mpu_port_index = ms_id; |
e7c7d760 | 1884 | else |
63c85238 | 1885 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; |
63c85238 PW |
1886 | |
1887 | list_add_tail(&oh->node, &omap_hwmod_list); | |
1888 | ||
dc6d1cda | 1889 | spin_lock_init(&oh->_lock); |
2092e5cc | 1890 | |
63c85238 PW |
1891 | oh->_state = _HWMOD_STATE_REGISTERED; |
1892 | ||
569edd70 PW |
1893 | /* |
1894 | * XXX Rather than doing a strcmp(), this should test a flag | |
1895 | * set in the hwmod data, inserted by the autogenerator code. | |
1896 | */ | |
1897 | if (!strcmp(oh->name, MPU_INITIATOR_NAME)) | |
1898 | mpu_oh = oh; | |
63c85238 | 1899 | |
569edd70 | 1900 | return 0; |
63c85238 PW |
1901 | } |
1902 | ||
0102b627 BC |
1903 | |
1904 | /* Public functions */ | |
1905 | ||
1906 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | |
1907 | { | |
1908 | if (oh->flags & HWMOD_16BIT_REG) | |
1909 | return __raw_readw(oh->_mpu_rt_va + reg_offs); | |
1910 | else | |
1911 | return __raw_readl(oh->_mpu_rt_va + reg_offs); | |
1912 | } | |
1913 | ||
1914 | void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
1915 | { | |
1916 | if (oh->flags & HWMOD_16BIT_REG) | |
1917 | __raw_writew(v, oh->_mpu_rt_va + reg_offs); | |
1918 | else | |
1919 | __raw_writel(v, oh->_mpu_rt_va + reg_offs); | |
1920 | } | |
1921 | ||
6d3c55fd A |
1922 | /** |
1923 | * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit | |
1924 | * @oh: struct omap_hwmod * | |
1925 | * | |
1926 | * This is a public function exposed to drivers. Some drivers may need to do | |
1927 | * some settings before and after resetting the device. Those drivers after | |
1928 | * doing the necessary settings could use this function to start a reset by | |
1929 | * setting the SYSCONFIG.SOFTRESET bit. | |
1930 | */ | |
1931 | int omap_hwmod_softreset(struct omap_hwmod *oh) | |
1932 | { | |
3c55c1ba PW |
1933 | u32 v; |
1934 | int ret; | |
1935 | ||
1936 | if (!oh || !(oh->_sysc_cache)) | |
6d3c55fd A |
1937 | return -EINVAL; |
1938 | ||
3c55c1ba PW |
1939 | v = oh->_sysc_cache; |
1940 | ret = _set_softreset(oh, &v); | |
1941 | if (ret) | |
1942 | goto error; | |
1943 | _write_sysconfig(v, oh); | |
1944 | ||
1945 | error: | |
1946 | return ret; | |
6d3c55fd A |
1947 | } |
1948 | ||
0102b627 BC |
1949 | /** |
1950 | * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode | |
1951 | * @oh: struct omap_hwmod * | |
1952 | * @idlemode: SIDLEMODE field bits (shifted to bit 0) | |
1953 | * | |
1954 | * Sets the IP block's OCP slave idlemode in hardware, and updates our | |
1955 | * local copy. Intended to be used by drivers that have some erratum | |
1956 | * that requires direct manipulation of the SIDLEMODE bits. Returns | |
1957 | * -EINVAL if @oh is null, or passes along the return value from | |
1958 | * _set_slave_idlemode(). | |
1959 | * | |
1960 | * XXX Does this function have any current users? If not, we should | |
1961 | * remove it; it is better to let the rest of the hwmod code handle this. | |
1962 | * Any users of this function should be scrutinized carefully. | |
1963 | */ | |
1964 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) | |
1965 | { | |
1966 | u32 v; | |
1967 | int retval = 0; | |
1968 | ||
1969 | if (!oh) | |
1970 | return -EINVAL; | |
1971 | ||
1972 | v = oh->_sysc_cache; | |
1973 | ||
1974 | retval = _set_slave_idlemode(oh, idlemode, &v); | |
1975 | if (!retval) | |
1976 | _write_sysconfig(v, oh); | |
1977 | ||
1978 | return retval; | |
1979 | } | |
1980 | ||
63c85238 PW |
1981 | /** |
1982 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
1983 | * @name: name of the omap_hwmod to look up | |
1984 | * | |
1985 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
1986 | * struct omap_hwmod *, or NULL upon error. | |
1987 | */ | |
1988 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
1989 | { | |
1990 | struct omap_hwmod *oh; | |
1991 | ||
1992 | if (!name) | |
1993 | return NULL; | |
1994 | ||
63c85238 | 1995 | oh = _lookup(name); |
63c85238 PW |
1996 | |
1997 | return oh; | |
1998 | } | |
1999 | ||
2000 | /** | |
2001 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
2002 | * @fn: pointer to a callback function | |
97d60162 | 2003 | * @data: void * data to pass to callback function |
63c85238 PW |
2004 | * |
2005 | * Call @fn for each registered omap_hwmod, passing @data to each | |
2006 | * function. @fn must return 0 for success or any other value for | |
2007 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
2008 | * will stop and the non-zero return value will be passed to the | |
2009 | * caller of omap_hwmod_for_each(). @fn is called with | |
2010 | * omap_hwmod_for_each() held. | |
2011 | */ | |
97d60162 PW |
2012 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
2013 | void *data) | |
63c85238 PW |
2014 | { |
2015 | struct omap_hwmod *temp_oh; | |
30ebad9d | 2016 | int ret = 0; |
63c85238 PW |
2017 | |
2018 | if (!fn) | |
2019 | return -EINVAL; | |
2020 | ||
63c85238 | 2021 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
97d60162 | 2022 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
2023 | if (ret) |
2024 | break; | |
2025 | } | |
63c85238 PW |
2026 | |
2027 | return ret; | |
2028 | } | |
2029 | ||
63c85238 | 2030 | /** |
550c8092 | 2031 | * omap_hwmod_register - register an array of hwmods |
63c85238 PW |
2032 | * @ohs: pointer to an array of omap_hwmods to register |
2033 | * | |
2034 | * Intended to be called early in boot before the clock framework is | |
2035 | * initialized. If @ohs is not null, will register all omap_hwmods | |
550c8092 | 2036 | * listed in @ohs that are valid for this chip. Returns 0. |
63c85238 | 2037 | */ |
550c8092 | 2038 | int __init omap_hwmod_register(struct omap_hwmod **ohs) |
63c85238 | 2039 | { |
bac1a0f0 | 2040 | int r, i; |
63c85238 PW |
2041 | |
2042 | if (!ohs) | |
2043 | return 0; | |
2044 | ||
bac1a0f0 PW |
2045 | i = 0; |
2046 | do { | |
bac1a0f0 PW |
2047 | r = _register(ohs[i]); |
2048 | WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name, | |
2049 | r); | |
2050 | } while (ohs[++i]); | |
63c85238 PW |
2051 | |
2052 | return 0; | |
2053 | } | |
2054 | ||
e7c7d760 TL |
2055 | /* |
2056 | * _populate_mpu_rt_base - populate the virtual address for a hwmod | |
2057 | * | |
a2debdbd | 2058 | * Must be called only from omap_hwmod_setup_*() so ioremap works properly. |
e7c7d760 | 2059 | * Assumes the caller takes care of locking if needed. |
63c85238 | 2060 | */ |
e7c7d760 TL |
2061 | static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data) |
2062 | { | |
48d54f3f PW |
2063 | if (oh->_state != _HWMOD_STATE_REGISTERED) |
2064 | return 0; | |
2065 | ||
e7c7d760 TL |
2066 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) |
2067 | return 0; | |
2068 | ||
2069 | oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); | |
e7c7d760 TL |
2070 | |
2071 | return 0; | |
2072 | } | |
2073 | ||
63c85238 | 2074 | /** |
a2debdbd PW |
2075 | * omap_hwmod_setup_one - set up a single hwmod |
2076 | * @oh_name: const char * name of the already-registered hwmod to set up | |
2077 | * | |
2078 | * Must be called after omap2_clk_init(). Resolves the struct clk | |
2079 | * names to struct clk pointers for each registered omap_hwmod. Also | |
2080 | * calls _setup() on each hwmod. Returns -EINVAL upon error or 0 upon | |
2081 | * success. | |
2082 | */ | |
2083 | int __init omap_hwmod_setup_one(const char *oh_name) | |
63c85238 PW |
2084 | { |
2085 | struct omap_hwmod *oh; | |
2086 | int r; | |
2087 | ||
a2debdbd PW |
2088 | pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__); |
2089 | ||
2090 | if (!mpu_oh) { | |
2091 | pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n", | |
2092 | oh_name, MPU_INITIATOR_NAME); | |
63c85238 | 2093 | return -EINVAL; |
a2debdbd | 2094 | } |
63c85238 | 2095 | |
a2debdbd PW |
2096 | oh = _lookup(oh_name); |
2097 | if (!oh) { | |
2098 | WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name); | |
2099 | return -EINVAL; | |
2100 | } | |
63c85238 | 2101 | |
a2debdbd PW |
2102 | if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh) |
2103 | omap_hwmod_setup_one(MPU_INITIATOR_NAME); | |
63c85238 | 2104 | |
a2debdbd PW |
2105 | r = _populate_mpu_rt_base(oh, NULL); |
2106 | if (IS_ERR_VALUE(r)) { | |
2107 | WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name); | |
2108 | return -EINVAL; | |
2109 | } | |
2110 | ||
2111 | r = _init_clocks(oh, NULL); | |
2112 | if (IS_ERR_VALUE(r)) { | |
2113 | WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name); | |
2114 | return -EINVAL; | |
63c85238 PW |
2115 | } |
2116 | ||
a2debdbd PW |
2117 | _setup(oh, NULL); |
2118 | ||
63c85238 PW |
2119 | return 0; |
2120 | } | |
2121 | ||
2122 | /** | |
550c8092 | 2123 | * omap_hwmod_setup - do some post-clock framework initialization |
63c85238 PW |
2124 | * |
2125 | * Must be called after omap2_clk_init(). Resolves the struct clk names | |
2126 | * to struct clk pointers for each registered omap_hwmod. Also calls | |
a2debdbd | 2127 | * _setup() on each hwmod. Returns 0 upon success. |
63c85238 | 2128 | */ |
550c8092 | 2129 | static int __init omap_hwmod_setup_all(void) |
63c85238 PW |
2130 | { |
2131 | int r; | |
2132 | ||
569edd70 PW |
2133 | if (!mpu_oh) { |
2134 | pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n", | |
2135 | __func__, MPU_INITIATOR_NAME); | |
2136 | return -EINVAL; | |
2137 | } | |
2138 | ||
e7c7d760 | 2139 | r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL); |
63c85238 | 2140 | |
97d60162 | 2141 | r = omap_hwmod_for_each(_init_clocks, NULL); |
a2debdbd PW |
2142 | WARN(IS_ERR_VALUE(r), |
2143 | "omap_hwmod: %s: _init_clocks failed\n", __func__); | |
63c85238 | 2144 | |
2092e5cc | 2145 | omap_hwmod_for_each(_setup, NULL); |
63c85238 PW |
2146 | |
2147 | return 0; | |
2148 | } | |
550c8092 | 2149 | core_initcall(omap_hwmod_setup_all); |
63c85238 | 2150 | |
63c85238 PW |
2151 | /** |
2152 | * omap_hwmod_enable - enable an omap_hwmod | |
2153 | * @oh: struct omap_hwmod * | |
2154 | * | |
74ff3a68 | 2155 | * Enable an omap_hwmod @oh. Intended to be called by omap_device_enable(). |
63c85238 PW |
2156 | * Returns -EINVAL on error or passes along the return value from _enable(). |
2157 | */ | |
2158 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
2159 | { | |
2160 | int r; | |
dc6d1cda | 2161 | unsigned long flags; |
63c85238 PW |
2162 | |
2163 | if (!oh) | |
2164 | return -EINVAL; | |
2165 | ||
dc6d1cda PW |
2166 | spin_lock_irqsave(&oh->_lock, flags); |
2167 | r = _enable(oh); | |
2168 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
2169 | |
2170 | return r; | |
2171 | } | |
2172 | ||
2173 | /** | |
2174 | * omap_hwmod_idle - idle an omap_hwmod | |
2175 | * @oh: struct omap_hwmod * | |
2176 | * | |
74ff3a68 | 2177 | * Idle an omap_hwmod @oh. Intended to be called by omap_device_idle(). |
63c85238 PW |
2178 | * Returns -EINVAL on error or passes along the return value from _idle(). |
2179 | */ | |
2180 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
2181 | { | |
dc6d1cda PW |
2182 | unsigned long flags; |
2183 | ||
63c85238 PW |
2184 | if (!oh) |
2185 | return -EINVAL; | |
2186 | ||
dc6d1cda PW |
2187 | spin_lock_irqsave(&oh->_lock, flags); |
2188 | _idle(oh); | |
2189 | spin_unlock_irqrestore(&oh->_lock, flags); | |
63c85238 PW |
2190 | |
2191 | return 0; | |
2192 | } | |
2193 | ||
2194 | /** | |
2195 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
2196 | * @oh: struct omap_hwmod * | |
2197 | * | |
74ff3a68 | 2198 | * Shutdown an omap_hwmod @oh. Intended to be called by |
63c85238 PW |
2199 | * omap_device_shutdown(). Returns -EINVAL on error or passes along |
2200 | * the return value from _shutdown(). | |
2201 | */ | |
2202 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
2203 | { | |
dc6d1cda PW |
2204 | unsigned long flags; |
2205 | ||
63c85238 PW |
2206 | if (!oh) |
2207 | return -EINVAL; | |
2208 | ||
dc6d1cda | 2209 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 2210 | _shutdown(oh); |
dc6d1cda | 2211 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2212 | |
2213 | return 0; | |
2214 | } | |
2215 | ||
2216 | /** | |
2217 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
2218 | * @oh: struct omap_hwmod *oh | |
2219 | * | |
2220 | * Intended to be called by the omap_device code. | |
2221 | */ | |
2222 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
2223 | { | |
dc6d1cda PW |
2224 | unsigned long flags; |
2225 | ||
2226 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 2227 | _enable_clocks(oh); |
dc6d1cda | 2228 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2229 | |
2230 | return 0; | |
2231 | } | |
2232 | ||
2233 | /** | |
2234 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
2235 | * @oh: struct omap_hwmod *oh | |
2236 | * | |
2237 | * Intended to be called by the omap_device code. | |
2238 | */ | |
2239 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
2240 | { | |
dc6d1cda PW |
2241 | unsigned long flags; |
2242 | ||
2243 | spin_lock_irqsave(&oh->_lock, flags); | |
63c85238 | 2244 | _disable_clocks(oh); |
dc6d1cda | 2245 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2246 | |
2247 | return 0; | |
2248 | } | |
2249 | ||
2250 | /** | |
2251 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
2252 | * @oh: struct omap_hwmod *oh | |
2253 | * | |
2254 | * Intended to be called by drivers and core code when all posted | |
2255 | * writes to a device must complete before continuing further | |
2256 | * execution (for example, after clearing some device IRQSTATUS | |
2257 | * register bits) | |
2258 | * | |
2259 | * XXX what about targets with multiple OCP threads? | |
2260 | */ | |
2261 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
2262 | { | |
2263 | BUG_ON(!oh); | |
2264 | ||
43b40992 | 2265 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
4f8a428d RK |
2266 | WARN(1, "omap_device: %s: OCP barrier impossible due to device configuration\n", |
2267 | oh->name); | |
63c85238 PW |
2268 | return; |
2269 | } | |
2270 | ||
2271 | /* | |
2272 | * Forces posted writes to complete on the OCP thread handling | |
2273 | * register writes | |
2274 | */ | |
cc7a1d2a | 2275 | omap_hwmod_read(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
2276 | } |
2277 | ||
2278 | /** | |
2279 | * omap_hwmod_reset - reset the hwmod | |
2280 | * @oh: struct omap_hwmod * | |
2281 | * | |
2282 | * Under some conditions, a driver may wish to reset the entire device. | |
2283 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 2284 | * the return value from _reset(). |
63c85238 PW |
2285 | */ |
2286 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
2287 | { | |
2288 | int r; | |
dc6d1cda | 2289 | unsigned long flags; |
63c85238 | 2290 | |
9b579114 | 2291 | if (!oh) |
63c85238 PW |
2292 | return -EINVAL; |
2293 | ||
dc6d1cda | 2294 | spin_lock_irqsave(&oh->_lock, flags); |
63c85238 | 2295 | r = _reset(oh); |
dc6d1cda | 2296 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2297 | |
2298 | return r; | |
2299 | } | |
2300 | ||
2301 | /** | |
2302 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
2303 | * @oh: struct omap_hwmod * | |
2304 | * @res: pointer to the first element of an array of struct resource to fill | |
2305 | * | |
2306 | * Count the number of struct resource array elements necessary to | |
2307 | * contain omap_hwmod @oh resources. Intended to be called by code | |
2308 | * that registers omap_devices. Intended to be used to determine the | |
2309 | * size of a dynamically-allocated struct resource array, before | |
2310 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
2311 | * resource array elements needed. | |
2312 | * | |
2313 | * XXX This code is not optimized. It could attempt to merge adjacent | |
2314 | * resource IDs. | |
2315 | * | |
2316 | */ | |
2317 | int omap_hwmod_count_resources(struct omap_hwmod *oh) | |
2318 | { | |
2319 | int ret, i; | |
2320 | ||
bc614958 | 2321 | ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh); |
63c85238 PW |
2322 | |
2323 | for (i = 0; i < oh->slaves_cnt; i++) | |
78183f3f | 2324 | ret += _count_ocp_if_addr_spaces(oh->slaves[i]); |
63c85238 PW |
2325 | |
2326 | return ret; | |
2327 | } | |
2328 | ||
2329 | /** | |
2330 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
2331 | * @oh: struct omap_hwmod * | |
2332 | * @res: pointer to the first element of an array of struct resource to fill | |
2333 | * | |
2334 | * Fill the struct resource array @res with resource data from the | |
2335 | * omap_hwmod @oh. Intended to be called by code that registers | |
2336 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
2337 | * number of array elements filled. | |
2338 | */ | |
2339 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
2340 | { | |
bc614958 | 2341 | int i, j, mpu_irqs_cnt, sdma_reqs_cnt; |
63c85238 PW |
2342 | int r = 0; |
2343 | ||
2344 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
2345 | ||
212738a4 PW |
2346 | mpu_irqs_cnt = _count_mpu_irqs(oh); |
2347 | for (i = 0; i < mpu_irqs_cnt; i++) { | |
718bfd76 PW |
2348 | (res + r)->name = (oh->mpu_irqs + i)->name; |
2349 | (res + r)->start = (oh->mpu_irqs + i)->irq; | |
2350 | (res + r)->end = (oh->mpu_irqs + i)->irq; | |
63c85238 PW |
2351 | (res + r)->flags = IORESOURCE_IRQ; |
2352 | r++; | |
2353 | } | |
2354 | ||
bc614958 PW |
2355 | sdma_reqs_cnt = _count_sdma_reqs(oh); |
2356 | for (i = 0; i < sdma_reqs_cnt; i++) { | |
9ee9fff9 BC |
2357 | (res + r)->name = (oh->sdma_reqs + i)->name; |
2358 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
2359 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
2360 | (res + r)->flags = IORESOURCE_DMA; |
2361 | r++; | |
2362 | } | |
2363 | ||
2364 | for (i = 0; i < oh->slaves_cnt; i++) { | |
2365 | struct omap_hwmod_ocp_if *os; | |
78183f3f | 2366 | int addr_cnt; |
63c85238 | 2367 | |
682fdc96 | 2368 | os = oh->slaves[i]; |
78183f3f | 2369 | addr_cnt = _count_ocp_if_addr_spaces(os); |
63c85238 | 2370 | |
78183f3f | 2371 | for (j = 0; j < addr_cnt; j++) { |
cd503802 | 2372 | (res + r)->name = (os->addr + j)->name; |
63c85238 PW |
2373 | (res + r)->start = (os->addr + j)->pa_start; |
2374 | (res + r)->end = (os->addr + j)->pa_end; | |
2375 | (res + r)->flags = IORESOURCE_MEM; | |
2376 | r++; | |
2377 | } | |
2378 | } | |
2379 | ||
2380 | return r; | |
2381 | } | |
2382 | ||
2383 | /** | |
2384 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
2385 | * @oh: struct omap_hwmod * | |
2386 | * | |
2387 | * Return the powerdomain pointer associated with the OMAP module | |
2388 | * @oh's main clock. If @oh does not have a main clk, return the | |
2389 | * powerdomain associated with the interface clock associated with the | |
2390 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
2391 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
2392 | * success. | |
2393 | */ | |
2394 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
2395 | { | |
2396 | struct clk *c; | |
2397 | ||
2398 | if (!oh) | |
2399 | return NULL; | |
2400 | ||
2401 | if (oh->_clk) { | |
2402 | c = oh->_clk; | |
2403 | } else { | |
2404 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
2405 | return NULL; | |
2406 | c = oh->slaves[oh->_mpu_port_index]->_clk; | |
2407 | } | |
2408 | ||
d5647c18 TG |
2409 | if (!c->clkdm) |
2410 | return NULL; | |
2411 | ||
63c85238 PW |
2412 | return c->clkdm->pwrdm.ptr; |
2413 | ||
2414 | } | |
2415 | ||
db2a60bf PW |
2416 | /** |
2417 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
2418 | * @oh: struct omap_hwmod * | |
2419 | * | |
2420 | * Returns the virtual address corresponding to the beginning of the | |
2421 | * module's register target, in the address range that is intended to | |
2422 | * be used by the MPU. Returns the virtual address upon success or NULL | |
2423 | * upon error. | |
2424 | */ | |
2425 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
2426 | { | |
2427 | if (!oh) | |
2428 | return NULL; | |
2429 | ||
2430 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
2431 | return NULL; | |
2432 | ||
2433 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
2434 | return NULL; | |
2435 | ||
2436 | return oh->_mpu_rt_va; | |
2437 | } | |
2438 | ||
63c85238 PW |
2439 | /** |
2440 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
2441 | * @oh: struct omap_hwmod * | |
2442 | * @init_oh: struct omap_hwmod * (initiator) | |
2443 | * | |
2444 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
2445 | * Intended to be called by DSP/Bridge code via platform_data for the | |
2446 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
2447 | * code needs to add/del initiator dependencies dynamically | |
2448 | * before/after accessing a device. Returns the return value from | |
2449 | * _add_initiator_dep(). | |
2450 | * | |
2451 | * XXX Keep a usecount in the clockdomain code | |
2452 | */ | |
2453 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
2454 | struct omap_hwmod *init_oh) | |
2455 | { | |
2456 | return _add_initiator_dep(oh, init_oh); | |
2457 | } | |
2458 | ||
2459 | /* | |
2460 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
2461 | * for context save/restore operations? | |
2462 | */ | |
2463 | ||
2464 | /** | |
2465 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
2466 | * @oh: struct omap_hwmod * | |
2467 | * @init_oh: struct omap_hwmod * (initiator) | |
2468 | * | |
2469 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
2470 | * Intended to be called by DSP/Bridge code via platform_data for the | |
2471 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
2472 | * code needs to add/del initiator dependencies dynamically | |
2473 | * before/after accessing a device. Returns the return value from | |
2474 | * _del_initiator_dep(). | |
2475 | * | |
2476 | * XXX Keep a usecount in the clockdomain code | |
2477 | */ | |
2478 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
2479 | struct omap_hwmod *init_oh) | |
2480 | { | |
2481 | return _del_initiator_dep(oh, init_oh); | |
2482 | } | |
2483 | ||
63c85238 PW |
2484 | /** |
2485 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
2486 | * @oh: struct omap_hwmod * | |
2487 | * | |
2488 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
2a1cc144 G |
2489 | * send wakeups to the PRCM, and enable I/O ring wakeup events for |
2490 | * this IP block if it has dynamic mux entries. Eventually this | |
2491 | * should set PRCM wakeup registers to cause the PRCM to receive | |
2492 | * wakeup events from the module. Does not set any wakeup routing | |
2493 | * registers beyond this point - if the module is to wake up any other | |
2494 | * module or subsystem, that must be set separately. Called by | |
2495 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
2496 | */ |
2497 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
2498 | { | |
dc6d1cda | 2499 | unsigned long flags; |
5a7ddcbd | 2500 | u32 v; |
dc6d1cda | 2501 | |
dc6d1cda | 2502 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
2503 | |
2504 | if (oh->class->sysc && | |
2505 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
2506 | v = oh->_sysc_cache; | |
2507 | _enable_wakeup(oh, &v); | |
2508 | _write_sysconfig(v, oh); | |
2509 | } | |
2510 | ||
eceec009 | 2511 | _set_idle_ioring_wakeup(oh, true); |
dc6d1cda | 2512 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2513 | |
2514 | return 0; | |
2515 | } | |
2516 | ||
2517 | /** | |
2518 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
2519 | * @oh: struct omap_hwmod * | |
2520 | * | |
2521 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
2a1cc144 G |
2522 | * from sending wakeups to the PRCM, and disable I/O ring wakeup |
2523 | * events for this IP block if it has dynamic mux entries. Eventually | |
2524 | * this should clear PRCM wakeup registers to cause the PRCM to ignore | |
2525 | * wakeup events from the module. Does not set any wakeup routing | |
2526 | * registers beyond this point - if the module is to wake up any other | |
2527 | * module or subsystem, that must be set separately. Called by | |
2528 | * omap_device code. Returns -EINVAL on error or 0 upon success. | |
63c85238 PW |
2529 | */ |
2530 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
2531 | { | |
dc6d1cda | 2532 | unsigned long flags; |
5a7ddcbd | 2533 | u32 v; |
dc6d1cda | 2534 | |
dc6d1cda | 2535 | spin_lock_irqsave(&oh->_lock, flags); |
2a1cc144 G |
2536 | |
2537 | if (oh->class->sysc && | |
2538 | (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) { | |
2539 | v = oh->_sysc_cache; | |
2540 | _disable_wakeup(oh, &v); | |
2541 | _write_sysconfig(v, oh); | |
2542 | } | |
2543 | ||
eceec009 | 2544 | _set_idle_ioring_wakeup(oh, false); |
dc6d1cda | 2545 | spin_unlock_irqrestore(&oh->_lock, flags); |
63c85238 PW |
2546 | |
2547 | return 0; | |
2548 | } | |
43b40992 | 2549 | |
aee48e3c PW |
2550 | /** |
2551 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
2552 | * contained in the hwmod module. | |
2553 | * @oh: struct omap_hwmod * | |
2554 | * @name: name of the reset line to lookup and assert | |
2555 | * | |
2556 | * Some IP like dsp, ipu or iva contain processor that require | |
2557 | * an HW reset line to be assert / deassert in order to enable fully | |
2558 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
2559 | * yet supported on this OMAP; otherwise, passes along the return value | |
2560 | * from _assert_hardreset(). | |
2561 | */ | |
2562 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
2563 | { | |
2564 | int ret; | |
dc6d1cda | 2565 | unsigned long flags; |
aee48e3c PW |
2566 | |
2567 | if (!oh) | |
2568 | return -EINVAL; | |
2569 | ||
dc6d1cda | 2570 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 2571 | ret = _assert_hardreset(oh, name); |
dc6d1cda | 2572 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
2573 | |
2574 | return ret; | |
2575 | } | |
2576 | ||
2577 | /** | |
2578 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
2579 | * contained in the hwmod module. | |
2580 | * @oh: struct omap_hwmod * | |
2581 | * @name: name of the reset line to look up and deassert | |
2582 | * | |
2583 | * Some IP like dsp, ipu or iva contain processor that require | |
2584 | * an HW reset line to be assert / deassert in order to enable fully | |
2585 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
2586 | * yet supported on this OMAP; otherwise, passes along the return value | |
2587 | * from _deassert_hardreset(). | |
2588 | */ | |
2589 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
2590 | { | |
2591 | int ret; | |
dc6d1cda | 2592 | unsigned long flags; |
aee48e3c PW |
2593 | |
2594 | if (!oh) | |
2595 | return -EINVAL; | |
2596 | ||
dc6d1cda | 2597 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 2598 | ret = _deassert_hardreset(oh, name); |
dc6d1cda | 2599 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
2600 | |
2601 | return ret; | |
2602 | } | |
2603 | ||
2604 | /** | |
2605 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
2606 | * contained in the hwmod module | |
2607 | * @oh: struct omap_hwmod * | |
2608 | * @name: name of the reset line to look up and read | |
2609 | * | |
2610 | * Return the current state of the hwmod @oh's reset line named @name: | |
2611 | * returns -EINVAL upon parameter error or if this operation | |
2612 | * is unsupported on the current OMAP; otherwise, passes along the return | |
2613 | * value from _read_hardreset(). | |
2614 | */ | |
2615 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
2616 | { | |
2617 | int ret; | |
dc6d1cda | 2618 | unsigned long flags; |
aee48e3c PW |
2619 | |
2620 | if (!oh) | |
2621 | return -EINVAL; | |
2622 | ||
dc6d1cda | 2623 | spin_lock_irqsave(&oh->_lock, flags); |
aee48e3c | 2624 | ret = _read_hardreset(oh, name); |
dc6d1cda | 2625 | spin_unlock_irqrestore(&oh->_lock, flags); |
aee48e3c PW |
2626 | |
2627 | return ret; | |
2628 | } | |
2629 | ||
2630 | ||
43b40992 PW |
2631 | /** |
2632 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
2633 | * @classname: struct omap_hwmod_class name to search for | |
2634 | * @fn: callback function pointer to call for each hwmod in class @classname | |
2635 | * @user: arbitrary context data to pass to the callback function | |
2636 | * | |
ce35b244 BC |
2637 | * For each omap_hwmod of class @classname, call @fn. |
2638 | * If the callback function returns something other than | |
43b40992 PW |
2639 | * zero, the iterator is terminated, and the callback function's return |
2640 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
2641 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
2642 | */ | |
2643 | int omap_hwmod_for_each_by_class(const char *classname, | |
2644 | int (*fn)(struct omap_hwmod *oh, | |
2645 | void *user), | |
2646 | void *user) | |
2647 | { | |
2648 | struct omap_hwmod *temp_oh; | |
2649 | int ret = 0; | |
2650 | ||
2651 | if (!classname || !fn) | |
2652 | return -EINVAL; | |
2653 | ||
2654 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
2655 | __func__, classname); | |
2656 | ||
43b40992 PW |
2657 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { |
2658 | if (!strcmp(temp_oh->class->name, classname)) { | |
2659 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
2660 | __func__, temp_oh->name); | |
2661 | ret = (*fn)(temp_oh, user); | |
2662 | if (ret) | |
2663 | break; | |
2664 | } | |
2665 | } | |
2666 | ||
43b40992 PW |
2667 | if (ret) |
2668 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
2669 | __func__, ret); | |
2670 | ||
2671 | return ret; | |
2672 | } | |
2673 | ||
2092e5cc PW |
2674 | /** |
2675 | * omap_hwmod_set_postsetup_state - set the post-_setup() state for this hwmod | |
2676 | * @oh: struct omap_hwmod * | |
2677 | * @state: state that _setup() should leave the hwmod in | |
2678 | * | |
550c8092 | 2679 | * Sets the hwmod state that @oh will enter at the end of _setup() |
a2debdbd PW |
2680 | * (called by omap_hwmod_setup_*()). Only valid to call between |
2681 | * calling omap_hwmod_register() and omap_hwmod_setup_*(). Returns | |
550c8092 PW |
2682 | * 0 upon success or -EINVAL if there is a problem with the arguments |
2683 | * or if the hwmod is in the wrong state. | |
2092e5cc PW |
2684 | */ |
2685 | int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state) | |
2686 | { | |
2687 | int ret; | |
dc6d1cda | 2688 | unsigned long flags; |
2092e5cc PW |
2689 | |
2690 | if (!oh) | |
2691 | return -EINVAL; | |
2692 | ||
2693 | if (state != _HWMOD_STATE_DISABLED && | |
2694 | state != _HWMOD_STATE_ENABLED && | |
2695 | state != _HWMOD_STATE_IDLE) | |
2696 | return -EINVAL; | |
2697 | ||
dc6d1cda | 2698 | spin_lock_irqsave(&oh->_lock, flags); |
2092e5cc PW |
2699 | |
2700 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
2701 | ret = -EINVAL; | |
2702 | goto ohsps_unlock; | |
2703 | } | |
2704 | ||
2705 | oh->_postsetup_state = state; | |
2706 | ret = 0; | |
2707 | ||
2708 | ohsps_unlock: | |
dc6d1cda | 2709 | spin_unlock_irqrestore(&oh->_lock, flags); |
2092e5cc PW |
2710 | |
2711 | return ret; | |
2712 | } | |
c80705aa KH |
2713 | |
2714 | /** | |
2715 | * omap_hwmod_get_context_loss_count - get lost context count | |
2716 | * @oh: struct omap_hwmod * | |
2717 | * | |
2718 | * Query the powerdomain of of @oh to get the context loss | |
2719 | * count for this device. | |
2720 | * | |
2721 | * Returns the context loss count of the powerdomain assocated with @oh | |
2722 | * upon success, or zero if no powerdomain exists for @oh. | |
2723 | */ | |
fc013873 | 2724 | int omap_hwmod_get_context_loss_count(struct omap_hwmod *oh) |
c80705aa KH |
2725 | { |
2726 | struct powerdomain *pwrdm; | |
2727 | int ret = 0; | |
2728 | ||
2729 | pwrdm = omap_hwmod_get_pwrdm(oh); | |
2730 | if (pwrdm) | |
2731 | ret = pwrdm_get_context_loss_count(pwrdm); | |
2732 | ||
2733 | return ret; | |
2734 | } | |
43b01643 PW |
2735 | |
2736 | /** | |
2737 | * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup | |
2738 | * @oh: struct omap_hwmod * | |
2739 | * | |
2740 | * Prevent the hwmod @oh from being reset during the setup process. | |
2741 | * Intended for use by board-*.c files on boards with devices that | |
2742 | * cannot tolerate being reset. Must be called before the hwmod has | |
2743 | * been set up. Returns 0 upon success or negative error code upon | |
2744 | * failure. | |
2745 | */ | |
2746 | int omap_hwmod_no_setup_reset(struct omap_hwmod *oh) | |
2747 | { | |
2748 | if (!oh) | |
2749 | return -EINVAL; | |
2750 | ||
2751 | if (oh->_state != _HWMOD_STATE_REGISTERED) { | |
2752 | pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n", | |
2753 | oh->name); | |
2754 | return -EINVAL; | |
2755 | } | |
2756 | ||
2757 | oh->flags |= HWMOD_INIT_NO_RESET; | |
2758 | ||
2759 | return 0; | |
2760 | } | |
abc2d545 TK |
2761 | |
2762 | /** | |
2763 | * omap_hwmod_pad_route_irq - route an I/O pad wakeup to a particular MPU IRQ | |
2764 | * @oh: struct omap_hwmod * containing hwmod mux entries | |
2765 | * @pad_idx: array index in oh->mux of the hwmod mux entry to route wakeup | |
2766 | * @irq_idx: the hwmod mpu_irqs array index of the IRQ to trigger on wakeup | |
2767 | * | |
2768 | * When an I/O pad wakeup arrives for the dynamic or wakeup hwmod mux | |
2769 | * entry number @pad_idx for the hwmod @oh, trigger the interrupt | |
2770 | * service routine for the hwmod's mpu_irqs array index @irq_idx. If | |
2771 | * this function is not called for a given pad_idx, then the ISR | |
2772 | * associated with @oh's first MPU IRQ will be triggered when an I/O | |
2773 | * pad wakeup occurs on that pad. Note that @pad_idx is the index of | |
2774 | * the _dynamic or wakeup_ entry: if there are other entries not | |
2775 | * marked with OMAP_DEVICE_PAD_WAKEUP or OMAP_DEVICE_PAD_REMUX, these | |
2776 | * entries are NOT COUNTED in the dynamic pad index. This function | |
2777 | * must be called separately for each pad that requires its interrupt | |
2778 | * to be re-routed this way. Returns -EINVAL if there is an argument | |
2779 | * problem or if @oh does not have hwmod mux entries or MPU IRQs; | |
2780 | * returns -ENOMEM if memory cannot be allocated; or 0 upon success. | |
2781 | * | |
2782 | * XXX This function interface is fragile. Rather than using array | |
2783 | * indexes, which are subject to unpredictable change, it should be | |
2784 | * using hwmod IRQ names, and some other stable key for the hwmod mux | |
2785 | * pad records. | |
2786 | */ | |
2787 | int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx) | |
2788 | { | |
2789 | int nr_irqs; | |
2790 | ||
2791 | might_sleep(); | |
2792 | ||
2793 | if (!oh || !oh->mux || !oh->mpu_irqs || pad_idx < 0 || | |
2794 | pad_idx >= oh->mux->nr_pads_dynamic) | |
2795 | return -EINVAL; | |
2796 | ||
2797 | /* Check the number of available mpu_irqs */ | |
2798 | for (nr_irqs = 0; oh->mpu_irqs[nr_irqs].irq >= 0; nr_irqs++) | |
2799 | ; | |
2800 | ||
2801 | if (irq_idx >= nr_irqs) | |
2802 | return -EINVAL; | |
2803 | ||
2804 | if (!oh->mux->irqs) { | |
2805 | /* XXX What frees this? */ | |
2806 | oh->mux->irqs = kzalloc(sizeof(int) * oh->mux->nr_pads_dynamic, | |
2807 | GFP_KERNEL); | |
2808 | if (!oh->mux->irqs) | |
2809 | return -ENOMEM; | |
2810 | } | |
2811 | oh->mux->irqs[pad_idx] = irq_idx; | |
2812 | ||
2813 | return 0; | |
2814 | } |