Commit | Line | Data |
---|---|---|
63c85238 PW |
1 | /* |
2 | * omap_hwmod implementation for OMAP2/3/4 | |
3 | * | |
db2a60bf | 4 | * Copyright (C) 2009-2010 Nokia Corporation |
63c85238 | 5 | * |
4788da26 PW |
6 | * Paul Walmsley, Benoît Cousson, Kevin Hilman |
7 | * | |
8 | * Created in collaboration with (alphabetical order): Thara Gopinath, | |
9 | * Tony Lindgren, Rajendra Nayak, Vikram Pandita, Sakari Poussa, Anand | |
10 | * Sawant, Santosh Shilimkar, Richard Woodruff | |
63c85238 PW |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | * | |
16 | * This code manages "OMAP modules" (on-chip devices) and their | |
17 | * integration with Linux device driver and bus code. | |
18 | * | |
19 | * References: | |
20 | * - OMAP2420 Multimedia Processor Silicon Revision 2.1.1, 2.2 (SWPU064) | |
21 | * - OMAP2430 Multimedia Device POP Silicon Revision 2.1 (SWPU090) | |
22 | * - OMAP34xx Multimedia Device Silicon Revision 3.1 (SWPU108) | |
23 | * - OMAP4430 Multimedia Device Silicon Revision 1.0 (SWPU140) | |
24 | * - Open Core Protocol Specification 2.2 | |
25 | * | |
26 | * To do: | |
27 | * - pin mux handling | |
28 | * - handle IO mapping | |
29 | * - bus throughput & module latency measurement code | |
30 | * | |
31 | * XXX add tests at the beginning of each function to ensure the hwmod is | |
32 | * in the appropriate state | |
33 | * XXX error return values should be checked to ensure that they are | |
34 | * appropriate | |
35 | */ | |
36 | #undef DEBUG | |
37 | ||
38 | #include <linux/kernel.h> | |
39 | #include <linux/errno.h> | |
40 | #include <linux/io.h> | |
41 | #include <linux/clk.h> | |
42 | #include <linux/delay.h> | |
43 | #include <linux/err.h> | |
44 | #include <linux/list.h> | |
45 | #include <linux/mutex.h> | |
63c85238 | 46 | |
6f8b7ff5 | 47 | #include <plat/common.h> |
ce491cf8 TL |
48 | #include <plat/cpu.h> |
49 | #include <plat/clockdomain.h> | |
50 | #include <plat/powerdomain.h> | |
51 | #include <plat/clock.h> | |
52 | #include <plat/omap_hwmod.h> | |
5365efbe | 53 | #include <plat/prcm.h> |
63c85238 PW |
54 | |
55 | #include "cm.h" | |
5365efbe | 56 | #include "prm.h" |
63c85238 | 57 | |
5365efbe BC |
58 | /* Maximum microseconds to wait for OMAP module to softreset */ |
59 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | |
63c85238 PW |
60 | |
61 | /* Name of the OMAP hwmod for the MPU */ | |
5c2c0296 | 62 | #define MPU_INITIATOR_NAME "mpu" |
63c85238 PW |
63 | |
64 | /* omap_hwmod_list contains all registered struct omap_hwmods */ | |
65 | static LIST_HEAD(omap_hwmod_list); | |
66 | ||
67 | static DEFINE_MUTEX(omap_hwmod_mutex); | |
68 | ||
69 | /* mpu_oh: used to add/remove MPU initiator from sleepdep list */ | |
70 | static struct omap_hwmod *mpu_oh; | |
71 | ||
72 | /* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */ | |
73 | static u8 inited; | |
74 | ||
75 | ||
76 | /* Private functions */ | |
77 | ||
78 | /** | |
79 | * _update_sysc_cache - return the module OCP_SYSCONFIG register, keep copy | |
80 | * @oh: struct omap_hwmod * | |
81 | * | |
82 | * Load the current value of the hwmod OCP_SYSCONFIG register into the | |
83 | * struct omap_hwmod for later use. Returns -EINVAL if the hwmod has no | |
84 | * OCP_SYSCONFIG register or 0 upon success. | |
85 | */ | |
86 | static int _update_sysc_cache(struct omap_hwmod *oh) | |
87 | { | |
43b40992 PW |
88 | if (!oh->class->sysc) { |
89 | WARN(1, "omap_hwmod: %s: cannot read OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
90 | return -EINVAL; |
91 | } | |
92 | ||
93 | /* XXX ensure module interface clock is up */ | |
94 | ||
43b40992 | 95 | oh->_sysc_cache = omap_hwmod_readl(oh, oh->class->sysc->sysc_offs); |
63c85238 | 96 | |
43b40992 | 97 | if (!(oh->class->sysc->sysc_flags & SYSC_NO_CACHE)) |
883edfdd | 98 | oh->_int_flags |= _HWMOD_SYSCONFIG_LOADED; |
63c85238 PW |
99 | |
100 | return 0; | |
101 | } | |
102 | ||
103 | /** | |
104 | * _write_sysconfig - write a value to the module's OCP_SYSCONFIG register | |
105 | * @v: OCP_SYSCONFIG value to write | |
106 | * @oh: struct omap_hwmod * | |
107 | * | |
43b40992 PW |
108 | * Write @v into the module class' OCP_SYSCONFIG register, if it has |
109 | * one. No return value. | |
63c85238 PW |
110 | */ |
111 | static void _write_sysconfig(u32 v, struct omap_hwmod *oh) | |
112 | { | |
43b40992 PW |
113 | if (!oh->class->sysc) { |
114 | WARN(1, "omap_hwmod: %s: cannot write OCP_SYSCONFIG: not defined on hwmod's class\n", oh->name); | |
63c85238 PW |
115 | return; |
116 | } | |
117 | ||
118 | /* XXX ensure module interface clock is up */ | |
119 | ||
120 | if (oh->_sysc_cache != v) { | |
121 | oh->_sysc_cache = v; | |
43b40992 | 122 | omap_hwmod_writel(v, oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
123 | } |
124 | } | |
125 | ||
126 | /** | |
127 | * _set_master_standbymode: set the OCP_SYSCONFIG MIDLEMODE field in @v | |
128 | * @oh: struct omap_hwmod * | |
129 | * @standbymode: MIDLEMODE field bits | |
130 | * @v: pointer to register contents to modify | |
131 | * | |
132 | * Update the master standby mode bits in @v to be @standbymode for | |
133 | * the @oh hwmod. Does not write to the hardware. Returns -EINVAL | |
134 | * upon error or 0 upon success. | |
135 | */ | |
136 | static int _set_master_standbymode(struct omap_hwmod *oh, u8 standbymode, | |
137 | u32 *v) | |
138 | { | |
358f0e63 TG |
139 | u32 mstandby_mask; |
140 | u8 mstandby_shift; | |
141 | ||
43b40992 PW |
142 | if (!oh->class->sysc || |
143 | !(oh->class->sysc->sysc_flags & SYSC_HAS_MIDLEMODE)) | |
63c85238 PW |
144 | return -EINVAL; |
145 | ||
43b40992 PW |
146 | if (!oh->class->sysc->sysc_fields) { |
147 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
148 | return -EINVAL; |
149 | } | |
150 | ||
43b40992 | 151 | mstandby_shift = oh->class->sysc->sysc_fields->midle_shift; |
358f0e63 TG |
152 | mstandby_mask = (0x3 << mstandby_shift); |
153 | ||
154 | *v &= ~mstandby_mask; | |
155 | *v |= __ffs(standbymode) << mstandby_shift; | |
63c85238 PW |
156 | |
157 | return 0; | |
158 | } | |
159 | ||
160 | /** | |
161 | * _set_slave_idlemode: set the OCP_SYSCONFIG SIDLEMODE field in @v | |
162 | * @oh: struct omap_hwmod * | |
163 | * @idlemode: SIDLEMODE field bits | |
164 | * @v: pointer to register contents to modify | |
165 | * | |
166 | * Update the slave idle mode bits in @v to be @idlemode for the @oh | |
167 | * hwmod. Does not write to the hardware. Returns -EINVAL upon error | |
168 | * or 0 upon success. | |
169 | */ | |
170 | static int _set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode, u32 *v) | |
171 | { | |
358f0e63 TG |
172 | u32 sidle_mask; |
173 | u8 sidle_shift; | |
174 | ||
43b40992 PW |
175 | if (!oh->class->sysc || |
176 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SIDLEMODE)) | |
63c85238 PW |
177 | return -EINVAL; |
178 | ||
43b40992 PW |
179 | if (!oh->class->sysc->sysc_fields) { |
180 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
181 | return -EINVAL; |
182 | } | |
183 | ||
43b40992 | 184 | sidle_shift = oh->class->sysc->sysc_fields->sidle_shift; |
358f0e63 TG |
185 | sidle_mask = (0x3 << sidle_shift); |
186 | ||
187 | *v &= ~sidle_mask; | |
188 | *v |= __ffs(idlemode) << sidle_shift; | |
63c85238 PW |
189 | |
190 | return 0; | |
191 | } | |
192 | ||
193 | /** | |
194 | * _set_clockactivity: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
195 | * @oh: struct omap_hwmod * | |
196 | * @clockact: CLOCKACTIVITY field bits | |
197 | * @v: pointer to register contents to modify | |
198 | * | |
199 | * Update the clockactivity mode bits in @v to be @clockact for the | |
200 | * @oh hwmod. Used for additional powersaving on some modules. Does | |
201 | * not write to the hardware. Returns -EINVAL upon error or 0 upon | |
202 | * success. | |
203 | */ | |
204 | static int _set_clockactivity(struct omap_hwmod *oh, u8 clockact, u32 *v) | |
205 | { | |
358f0e63 TG |
206 | u32 clkact_mask; |
207 | u8 clkact_shift; | |
208 | ||
43b40992 PW |
209 | if (!oh->class->sysc || |
210 | !(oh->class->sysc->sysc_flags & SYSC_HAS_CLOCKACTIVITY)) | |
63c85238 PW |
211 | return -EINVAL; |
212 | ||
43b40992 PW |
213 | if (!oh->class->sysc->sysc_fields) { |
214 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
215 | return -EINVAL; |
216 | } | |
217 | ||
43b40992 | 218 | clkact_shift = oh->class->sysc->sysc_fields->clkact_shift; |
358f0e63 TG |
219 | clkact_mask = (0x3 << clkact_shift); |
220 | ||
221 | *v &= ~clkact_mask; | |
222 | *v |= clockact << clkact_shift; | |
63c85238 PW |
223 | |
224 | return 0; | |
225 | } | |
226 | ||
227 | /** | |
228 | * _set_softreset: set OCP_SYSCONFIG.CLOCKACTIVITY bits in @v | |
229 | * @oh: struct omap_hwmod * | |
230 | * @v: pointer to register contents to modify | |
231 | * | |
232 | * Set the SOFTRESET bit in @v for hwmod @oh. Returns -EINVAL upon | |
233 | * error or 0 upon success. | |
234 | */ | |
235 | static int _set_softreset(struct omap_hwmod *oh, u32 *v) | |
236 | { | |
358f0e63 TG |
237 | u32 softrst_mask; |
238 | ||
43b40992 PW |
239 | if (!oh->class->sysc || |
240 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) | |
63c85238 PW |
241 | return -EINVAL; |
242 | ||
43b40992 PW |
243 | if (!oh->class->sysc->sysc_fields) { |
244 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
245 | return -EINVAL; |
246 | } | |
247 | ||
43b40992 | 248 | softrst_mask = (0x1 << oh->class->sysc->sysc_fields->srst_shift); |
358f0e63 TG |
249 | |
250 | *v |= softrst_mask; | |
63c85238 PW |
251 | |
252 | return 0; | |
253 | } | |
254 | ||
726072e5 PW |
255 | /** |
256 | * _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v | |
257 | * @oh: struct omap_hwmod * | |
258 | * @autoidle: desired AUTOIDLE bitfield value (0 or 1) | |
259 | * @v: pointer to register contents to modify | |
260 | * | |
261 | * Update the module autoidle bit in @v to be @autoidle for the @oh | |
262 | * hwmod. The autoidle bit controls whether the module can gate | |
263 | * internal clocks automatically when it isn't doing anything; the | |
264 | * exact function of this bit varies on a per-module basis. This | |
265 | * function does not write to the hardware. Returns -EINVAL upon | |
266 | * error or 0 upon success. | |
267 | */ | |
268 | static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle, | |
269 | u32 *v) | |
270 | { | |
358f0e63 TG |
271 | u32 autoidle_mask; |
272 | u8 autoidle_shift; | |
273 | ||
43b40992 PW |
274 | if (!oh->class->sysc || |
275 | !(oh->class->sysc->sysc_flags & SYSC_HAS_AUTOIDLE)) | |
726072e5 PW |
276 | return -EINVAL; |
277 | ||
43b40992 PW |
278 | if (!oh->class->sysc->sysc_fields) { |
279 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
280 | return -EINVAL; |
281 | } | |
282 | ||
43b40992 | 283 | autoidle_shift = oh->class->sysc->sysc_fields->autoidle_shift; |
358f0e63 TG |
284 | autoidle_mask = (0x3 << autoidle_shift); |
285 | ||
286 | *v &= ~autoidle_mask; | |
287 | *v |= autoidle << autoidle_shift; | |
726072e5 PW |
288 | |
289 | return 0; | |
290 | } | |
291 | ||
63c85238 PW |
292 | /** |
293 | * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
294 | * @oh: struct omap_hwmod * | |
295 | * | |
296 | * Allow the hardware module @oh to send wakeups. Returns -EINVAL | |
297 | * upon error or 0 upon success. | |
298 | */ | |
299 | static int _enable_wakeup(struct omap_hwmod *oh) | |
300 | { | |
358f0e63 | 301 | u32 v, wakeup_mask; |
63c85238 | 302 | |
43b40992 PW |
303 | if (!oh->class->sysc || |
304 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
305 | return -EINVAL; |
306 | ||
43b40992 PW |
307 | if (!oh->class->sysc->sysc_fields) { |
308 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
309 | return -EINVAL; |
310 | } | |
311 | ||
43b40992 | 312 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); |
358f0e63 | 313 | |
63c85238 | 314 | v = oh->_sysc_cache; |
358f0e63 | 315 | v |= wakeup_mask; |
63c85238 PW |
316 | _write_sysconfig(v, oh); |
317 | ||
318 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | |
319 | ||
320 | oh->_int_flags |= _HWMOD_WAKEUP_ENABLED; | |
321 | ||
322 | return 0; | |
323 | } | |
324 | ||
325 | /** | |
326 | * _disable_wakeup: clear OCP_SYSCONFIG.ENAWAKEUP bit in the hardware | |
327 | * @oh: struct omap_hwmod * | |
328 | * | |
329 | * Prevent the hardware module @oh to send wakeups. Returns -EINVAL | |
330 | * upon error or 0 upon success. | |
331 | */ | |
332 | static int _disable_wakeup(struct omap_hwmod *oh) | |
333 | { | |
358f0e63 | 334 | u32 v, wakeup_mask; |
63c85238 | 335 | |
43b40992 PW |
336 | if (!oh->class->sysc || |
337 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
338 | return -EINVAL; |
339 | ||
43b40992 PW |
340 | if (!oh->class->sysc->sysc_fields) { |
341 | WARN(1, "omap_hwmod: %s: offset struct for sysconfig not provided in class\n", oh->name); | |
358f0e63 TG |
342 | return -EINVAL; |
343 | } | |
344 | ||
43b40992 | 345 | wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift); |
358f0e63 | 346 | |
63c85238 | 347 | v = oh->_sysc_cache; |
358f0e63 | 348 | v &= ~wakeup_mask; |
63c85238 PW |
349 | _write_sysconfig(v, oh); |
350 | ||
351 | /* XXX test pwrdm_get_wken for this hwmod's subsystem */ | |
352 | ||
353 | oh->_int_flags &= ~_HWMOD_WAKEUP_ENABLED; | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | /** | |
359 | * _add_initiator_dep: prevent @oh from smart-idling while @init_oh is active | |
360 | * @oh: struct omap_hwmod * | |
361 | * | |
362 | * Prevent the hardware module @oh from entering idle while the | |
363 | * hardare module initiator @init_oh is active. Useful when a module | |
364 | * will be accessed by a particular initiator (e.g., if a module will | |
365 | * be accessed by the IVA, there should be a sleepdep between the IVA | |
366 | * initiator and the module). Only applies to modules in smart-idle | |
367 | * mode. Returns -EINVAL upon error or passes along | |
55ed9694 | 368 | * clkdm_add_sleepdep() value upon success. |
63c85238 PW |
369 | */ |
370 | static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
371 | { | |
372 | if (!oh->_clk) | |
373 | return -EINVAL; | |
374 | ||
55ed9694 | 375 | return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
376 | } |
377 | ||
378 | /** | |
379 | * _del_initiator_dep: allow @oh to smart-idle even if @init_oh is active | |
380 | * @oh: struct omap_hwmod * | |
381 | * | |
382 | * Allow the hardware module @oh to enter idle while the hardare | |
383 | * module initiator @init_oh is active. Useful when a module will not | |
384 | * be accessed by a particular initiator (e.g., if a module will not | |
385 | * be accessed by the IVA, there should be no sleepdep between the IVA | |
386 | * initiator and the module). Only applies to modules in smart-idle | |
387 | * mode. Returns -EINVAL upon error or passes along | |
55ed9694 | 388 | * clkdm_del_sleepdep() value upon success. |
63c85238 PW |
389 | */ |
390 | static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh) | |
391 | { | |
392 | if (!oh->_clk) | |
393 | return -EINVAL; | |
394 | ||
55ed9694 | 395 | return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm); |
63c85238 PW |
396 | } |
397 | ||
398 | /** | |
399 | * _init_main_clk - get a struct clk * for the the hwmod's main functional clk | |
400 | * @oh: struct omap_hwmod * | |
401 | * | |
402 | * Called from _init_clocks(). Populates the @oh _clk (main | |
403 | * functional clock pointer) if a main_clk is present. Returns 0 on | |
404 | * success or -EINVAL on error. | |
405 | */ | |
406 | static int _init_main_clk(struct omap_hwmod *oh) | |
407 | { | |
63c85238 PW |
408 | int ret = 0; |
409 | ||
50ebdac2 | 410 | if (!oh->main_clk) |
63c85238 PW |
411 | return 0; |
412 | ||
63403384 | 413 | oh->_clk = omap_clk_get_by_name(oh->main_clk); |
dc75925d | 414 | if (!oh->_clk) { |
20383d82 BC |
415 | pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n", |
416 | oh->name, oh->main_clk); | |
63403384 | 417 | return -EINVAL; |
dc75925d | 418 | } |
63c85238 | 419 | |
63403384 BC |
420 | if (!oh->_clk->clkdm) |
421 | pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n", | |
422 | oh->main_clk, oh->_clk->name); | |
81d7c6ff | 423 | |
63c85238 PW |
424 | return ret; |
425 | } | |
426 | ||
427 | /** | |
887adeac | 428 | * _init_interface_clks - get a struct clk * for the the hwmod's interface clks |
63c85238 PW |
429 | * @oh: struct omap_hwmod * |
430 | * | |
431 | * Called from _init_clocks(). Populates the @oh OCP slave interface | |
432 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
433 | */ | |
434 | static int _init_interface_clks(struct omap_hwmod *oh) | |
435 | { | |
63c85238 PW |
436 | struct clk *c; |
437 | int i; | |
438 | int ret = 0; | |
439 | ||
440 | if (oh->slaves_cnt == 0) | |
441 | return 0; | |
442 | ||
682fdc96 BC |
443 | for (i = 0; i < oh->slaves_cnt; i++) { |
444 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
445 | ||
50ebdac2 | 446 | if (!os->clk) |
63c85238 PW |
447 | continue; |
448 | ||
50ebdac2 | 449 | c = omap_clk_get_by_name(os->clk); |
dc75925d | 450 | if (!c) { |
20383d82 BC |
451 | pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n", |
452 | oh->name, os->clk); | |
63c85238 | 453 | ret = -EINVAL; |
dc75925d | 454 | } |
63c85238 PW |
455 | os->_clk = c; |
456 | } | |
457 | ||
458 | return ret; | |
459 | } | |
460 | ||
461 | /** | |
462 | * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks | |
463 | * @oh: struct omap_hwmod * | |
464 | * | |
465 | * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk | |
466 | * clock pointers. Returns 0 on success or -EINVAL on error. | |
467 | */ | |
468 | static int _init_opt_clks(struct omap_hwmod *oh) | |
469 | { | |
470 | struct omap_hwmod_opt_clk *oc; | |
471 | struct clk *c; | |
472 | int i; | |
473 | int ret = 0; | |
474 | ||
475 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) { | |
50ebdac2 | 476 | c = omap_clk_get_by_name(oc->clk); |
dc75925d | 477 | if (!c) { |
20383d82 BC |
478 | pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n", |
479 | oh->name, oc->clk); | |
63c85238 | 480 | ret = -EINVAL; |
dc75925d | 481 | } |
63c85238 PW |
482 | oc->_clk = c; |
483 | } | |
484 | ||
485 | return ret; | |
486 | } | |
487 | ||
488 | /** | |
489 | * _enable_clocks - enable hwmod main clock and interface clocks | |
490 | * @oh: struct omap_hwmod * | |
491 | * | |
492 | * Enables all clocks necessary for register reads and writes to succeed | |
493 | * on the hwmod @oh. Returns 0. | |
494 | */ | |
495 | static int _enable_clocks(struct omap_hwmod *oh) | |
496 | { | |
63c85238 PW |
497 | int i; |
498 | ||
499 | pr_debug("omap_hwmod: %s: enabling clocks\n", oh->name); | |
500 | ||
4d3ae5a9 | 501 | if (oh->_clk) |
63c85238 PW |
502 | clk_enable(oh->_clk); |
503 | ||
504 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
505 | for (i = 0; i < oh->slaves_cnt; i++) { |
506 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
507 | struct clk *c = os->_clk; |
508 | ||
4d3ae5a9 | 509 | if (c && (os->flags & OCPIF_SWSUP_IDLE)) |
63c85238 PW |
510 | clk_enable(c); |
511 | } | |
512 | } | |
513 | ||
514 | /* The opt clocks are controlled by the device driver. */ | |
515 | ||
516 | return 0; | |
517 | } | |
518 | ||
519 | /** | |
520 | * _disable_clocks - disable hwmod main clock and interface clocks | |
521 | * @oh: struct omap_hwmod * | |
522 | * | |
523 | * Disables the hwmod @oh main functional and interface clocks. Returns 0. | |
524 | */ | |
525 | static int _disable_clocks(struct omap_hwmod *oh) | |
526 | { | |
63c85238 PW |
527 | int i; |
528 | ||
529 | pr_debug("omap_hwmod: %s: disabling clocks\n", oh->name); | |
530 | ||
4d3ae5a9 | 531 | if (oh->_clk) |
63c85238 PW |
532 | clk_disable(oh->_clk); |
533 | ||
534 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
535 | for (i = 0; i < oh->slaves_cnt; i++) { |
536 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
537 | struct clk *c = os->_clk; |
538 | ||
4d3ae5a9 | 539 | if (c && (os->flags & OCPIF_SWSUP_IDLE)) |
63c85238 PW |
540 | clk_disable(c); |
541 | } | |
542 | } | |
543 | ||
544 | /* The opt clocks are controlled by the device driver. */ | |
545 | ||
546 | return 0; | |
547 | } | |
548 | ||
549 | /** | |
550 | * _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use | |
551 | * @oh: struct omap_hwmod * | |
552 | * | |
553 | * Returns the array index of the OCP slave port that the MPU | |
554 | * addresses the device on, or -EINVAL upon error or not found. | |
555 | */ | |
556 | static int _find_mpu_port_index(struct omap_hwmod *oh) | |
557 | { | |
63c85238 PW |
558 | int i; |
559 | int found = 0; | |
560 | ||
561 | if (!oh || oh->slaves_cnt == 0) | |
562 | return -EINVAL; | |
563 | ||
682fdc96 BC |
564 | for (i = 0; i < oh->slaves_cnt; i++) { |
565 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
566 | ||
63c85238 PW |
567 | if (os->user & OCP_USER_MPU) { |
568 | found = 1; | |
569 | break; | |
570 | } | |
571 | } | |
572 | ||
573 | if (found) | |
574 | pr_debug("omap_hwmod: %s: MPU OCP slave port ID %d\n", | |
575 | oh->name, i); | |
576 | else | |
577 | pr_debug("omap_hwmod: %s: no MPU OCP slave port found\n", | |
578 | oh->name); | |
579 | ||
580 | return (found) ? i : -EINVAL; | |
581 | } | |
582 | ||
583 | /** | |
584 | * _find_mpu_rt_base - find hwmod register target base addr accessible by MPU | |
585 | * @oh: struct omap_hwmod * | |
586 | * | |
587 | * Return the virtual address of the base of the register target of | |
588 | * device @oh, or NULL on error. | |
589 | */ | |
590 | static void __iomem *_find_mpu_rt_base(struct omap_hwmod *oh, u8 index) | |
591 | { | |
592 | struct omap_hwmod_ocp_if *os; | |
593 | struct omap_hwmod_addr_space *mem; | |
594 | int i; | |
595 | int found = 0; | |
986a13f5 | 596 | void __iomem *va_start; |
63c85238 PW |
597 | |
598 | if (!oh || oh->slaves_cnt == 0) | |
599 | return NULL; | |
600 | ||
682fdc96 | 601 | os = oh->slaves[index]; |
63c85238 PW |
602 | |
603 | for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) { | |
604 | if (mem->flags & ADDR_TYPE_RT) { | |
605 | found = 1; | |
606 | break; | |
607 | } | |
608 | } | |
609 | ||
986a13f5 TL |
610 | if (found) { |
611 | va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start); | |
612 | if (!va_start) { | |
613 | pr_err("omap_hwmod: %s: Could not ioremap\n", oh->name); | |
614 | return NULL; | |
615 | } | |
63c85238 | 616 | pr_debug("omap_hwmod: %s: MPU register target at va %p\n", |
986a13f5 TL |
617 | oh->name, va_start); |
618 | } else { | |
63c85238 PW |
619 | pr_debug("omap_hwmod: %s: no MPU register target found\n", |
620 | oh->name); | |
986a13f5 | 621 | } |
63c85238 | 622 | |
986a13f5 | 623 | return (found) ? va_start : NULL; |
63c85238 PW |
624 | } |
625 | ||
626 | /** | |
627 | * _sysc_enable - try to bring a module out of idle via OCP_SYSCONFIG | |
628 | * @oh: struct omap_hwmod * | |
629 | * | |
630 | * If module is marked as SWSUP_SIDLE, force the module out of slave | |
631 | * idle; otherwise, configure it for smart-idle. If module is marked | |
632 | * as SWSUP_MSUSPEND, force the module out of master standby; | |
633 | * otherwise, configure it for smart-standby. No return value. | |
634 | */ | |
635 | static void _sysc_enable(struct omap_hwmod *oh) | |
636 | { | |
43b40992 | 637 | u8 idlemode, sf; |
63c85238 PW |
638 | u32 v; |
639 | ||
43b40992 | 640 | if (!oh->class->sysc) |
63c85238 PW |
641 | return; |
642 | ||
643 | v = oh->_sysc_cache; | |
43b40992 | 644 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 645 | |
43b40992 | 646 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
647 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
648 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
649 | _set_slave_idlemode(oh, idlemode, &v); | |
650 | } | |
651 | ||
43b40992 | 652 | if (sf & SYSC_HAS_MIDLEMODE) { |
63c85238 PW |
653 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? |
654 | HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART; | |
655 | _set_master_standbymode(oh, idlemode, &v); | |
656 | } | |
657 | ||
43b40992 | 658 | if (sf & SYSC_HAS_AUTOIDLE) { |
726072e5 PW |
659 | idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ? |
660 | 0 : 1; | |
661 | _set_module_autoidle(oh, idlemode, &v); | |
662 | } | |
663 | ||
664 | /* XXX OCP ENAWAKEUP bit? */ | |
63c85238 | 665 | |
a16b1f7f PW |
666 | /* |
667 | * XXX The clock framework should handle this, by | |
668 | * calling into this code. But this must wait until the | |
669 | * clock structures are tagged with omap_hwmod entries | |
670 | */ | |
43b40992 PW |
671 | if ((oh->flags & HWMOD_SET_DEFAULT_CLOCKACT) && |
672 | (sf & SYSC_HAS_CLOCKACTIVITY)) | |
673 | _set_clockactivity(oh, oh->class->sysc->clockact, &v); | |
63c85238 PW |
674 | |
675 | _write_sysconfig(v, oh); | |
676 | } | |
677 | ||
678 | /** | |
679 | * _sysc_idle - try to put a module into idle via OCP_SYSCONFIG | |
680 | * @oh: struct omap_hwmod * | |
681 | * | |
682 | * If module is marked as SWSUP_SIDLE, force the module into slave | |
683 | * idle; otherwise, configure it for smart-idle. If module is marked | |
684 | * as SWSUP_MSUSPEND, force the module into master standby; otherwise, | |
685 | * configure it for smart-standby. No return value. | |
686 | */ | |
687 | static void _sysc_idle(struct omap_hwmod *oh) | |
688 | { | |
43b40992 | 689 | u8 idlemode, sf; |
63c85238 PW |
690 | u32 v; |
691 | ||
43b40992 | 692 | if (!oh->class->sysc) |
63c85238 PW |
693 | return; |
694 | ||
695 | v = oh->_sysc_cache; | |
43b40992 | 696 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 697 | |
43b40992 | 698 | if (sf & SYSC_HAS_SIDLEMODE) { |
63c85238 PW |
699 | idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ? |
700 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | |
701 | _set_slave_idlemode(oh, idlemode, &v); | |
702 | } | |
703 | ||
43b40992 | 704 | if (sf & SYSC_HAS_MIDLEMODE) { |
63c85238 PW |
705 | idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ? |
706 | HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART; | |
707 | _set_master_standbymode(oh, idlemode, &v); | |
708 | } | |
709 | ||
710 | _write_sysconfig(v, oh); | |
711 | } | |
712 | ||
713 | /** | |
714 | * _sysc_shutdown - force a module into idle via OCP_SYSCONFIG | |
715 | * @oh: struct omap_hwmod * | |
716 | * | |
717 | * Force the module into slave idle and master suspend. No return | |
718 | * value. | |
719 | */ | |
720 | static void _sysc_shutdown(struct omap_hwmod *oh) | |
721 | { | |
722 | u32 v; | |
43b40992 | 723 | u8 sf; |
63c85238 | 724 | |
43b40992 | 725 | if (!oh->class->sysc) |
63c85238 PW |
726 | return; |
727 | ||
728 | v = oh->_sysc_cache; | |
43b40992 | 729 | sf = oh->class->sysc->sysc_flags; |
63c85238 | 730 | |
43b40992 | 731 | if (sf & SYSC_HAS_SIDLEMODE) |
63c85238 PW |
732 | _set_slave_idlemode(oh, HWMOD_IDLEMODE_FORCE, &v); |
733 | ||
43b40992 | 734 | if (sf & SYSC_HAS_MIDLEMODE) |
63c85238 PW |
735 | _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); |
736 | ||
43b40992 | 737 | if (sf & SYSC_HAS_AUTOIDLE) |
726072e5 | 738 | _set_module_autoidle(oh, 1, &v); |
63c85238 PW |
739 | |
740 | _write_sysconfig(v, oh); | |
741 | } | |
742 | ||
743 | /** | |
744 | * _lookup - find an omap_hwmod by name | |
745 | * @name: find an omap_hwmod by name | |
746 | * | |
747 | * Return a pointer to an omap_hwmod by name, or NULL if not found. | |
748 | * Caller must hold omap_hwmod_mutex. | |
749 | */ | |
750 | static struct omap_hwmod *_lookup(const char *name) | |
751 | { | |
752 | struct omap_hwmod *oh, *temp_oh; | |
753 | ||
754 | oh = NULL; | |
755 | ||
756 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
757 | if (!strcmp(name, temp_oh->name)) { | |
758 | oh = temp_oh; | |
759 | break; | |
760 | } | |
761 | } | |
762 | ||
763 | return oh; | |
764 | } | |
765 | ||
766 | /** | |
767 | * _init_clocks - clk_get() all clocks associated with this hwmod | |
768 | * @oh: struct omap_hwmod * | |
97d60162 | 769 | * @data: not used; pass NULL |
63c85238 PW |
770 | * |
771 | * Called by omap_hwmod_late_init() (after omap2_clk_init()). | |
12b1fdb4 KH |
772 | * Resolves all clock names embedded in the hwmod. Returns -EINVAL if |
773 | * the omap_hwmod has not yet been registered or if the clocks have | |
774 | * already been initialized, 0 on success, or a non-zero error on | |
775 | * failure. | |
63c85238 | 776 | */ |
97d60162 | 777 | static int _init_clocks(struct omap_hwmod *oh, void *data) |
63c85238 PW |
778 | { |
779 | int ret = 0; | |
780 | ||
781 | if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED)) | |
782 | return -EINVAL; | |
783 | ||
784 | pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name); | |
785 | ||
786 | ret |= _init_main_clk(oh); | |
787 | ret |= _init_interface_clks(oh); | |
788 | ret |= _init_opt_clks(oh); | |
789 | ||
f5c1f84b BC |
790 | if (!ret) |
791 | oh->_state = _HWMOD_STATE_CLKS_INITED; | |
63c85238 | 792 | |
f5c1f84b | 793 | return 0; |
63c85238 PW |
794 | } |
795 | ||
796 | /** | |
797 | * _wait_target_ready - wait for a module to leave slave idle | |
798 | * @oh: struct omap_hwmod * | |
799 | * | |
800 | * Wait for a module @oh to leave slave idle. Returns 0 if the module | |
801 | * does not have an IDLEST bit or if the module successfully leaves | |
802 | * slave idle; otherwise, pass along the return value of the | |
803 | * appropriate *_cm_wait_module_ready() function. | |
804 | */ | |
805 | static int _wait_target_ready(struct omap_hwmod *oh) | |
806 | { | |
807 | struct omap_hwmod_ocp_if *os; | |
808 | int ret; | |
809 | ||
810 | if (!oh) | |
811 | return -EINVAL; | |
812 | ||
813 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
814 | return 0; | |
815 | ||
682fdc96 | 816 | os = oh->slaves[oh->_mpu_port_index]; |
63c85238 | 817 | |
33f7ec81 | 818 | if (oh->flags & HWMOD_NO_IDLEST) |
63c85238 PW |
819 | return 0; |
820 | ||
821 | /* XXX check module SIDLEMODE */ | |
822 | ||
823 | /* XXX check clock enable states */ | |
824 | ||
825 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
826 | ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs, | |
827 | oh->prcm.omap2.idlest_reg_id, | |
828 | oh->prcm.omap2.idlest_idle_bit); | |
63c85238 | 829 | } else if (cpu_is_omap44xx()) { |
9a23dfe1 | 830 | ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg); |
63c85238 PW |
831 | } else { |
832 | BUG(); | |
833 | }; | |
834 | ||
835 | return ret; | |
836 | } | |
837 | ||
5365efbe BC |
838 | /** |
839 | * _lookup_hardreset - return the register bit shift for this hwmod/reset line | |
840 | * @oh: struct omap_hwmod * | |
841 | * @name: name of the reset line in the context of this hwmod | |
842 | * | |
843 | * Return the bit position of the reset line that match the | |
844 | * input name. Return -ENOENT if not found. | |
845 | */ | |
846 | static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name) | |
847 | { | |
848 | int i; | |
849 | ||
850 | for (i = 0; i < oh->rst_lines_cnt; i++) { | |
851 | const char *rst_line = oh->rst_lines[i].name; | |
852 | if (!strcmp(rst_line, name)) { | |
853 | u8 shift = oh->rst_lines[i].rst_shift; | |
854 | pr_debug("omap_hwmod: %s: _lookup_hardreset: %s: %d\n", | |
855 | oh->name, rst_line, shift); | |
856 | ||
857 | return shift; | |
858 | } | |
859 | } | |
860 | ||
861 | return -ENOENT; | |
862 | } | |
863 | ||
864 | /** | |
865 | * _assert_hardreset - assert the HW reset line of submodules | |
866 | * contained in the hwmod module. | |
867 | * @oh: struct omap_hwmod * | |
868 | * @name: name of the reset line to lookup and assert | |
869 | * | |
870 | * Some IP like dsp, ipu or iva contain processor that require | |
871 | * an HW reset line to be assert / deassert in order to enable fully | |
872 | * the IP. | |
873 | */ | |
874 | static int _assert_hardreset(struct omap_hwmod *oh, const char *name) | |
875 | { | |
876 | u8 shift; | |
877 | ||
878 | if (!oh) | |
879 | return -EINVAL; | |
880 | ||
881 | shift = _lookup_hardreset(oh, name); | |
882 | if (IS_ERR_VALUE(shift)) | |
883 | return shift; | |
884 | ||
885 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
886 | return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs, | |
887 | shift); | |
888 | else if (cpu_is_omap44xx()) | |
889 | return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg, | |
890 | shift); | |
891 | else | |
892 | return -EINVAL; | |
893 | } | |
894 | ||
895 | /** | |
896 | * _deassert_hardreset - deassert the HW reset line of submodules contained | |
897 | * in the hwmod module. | |
898 | * @oh: struct omap_hwmod * | |
899 | * @name: name of the reset line to look up and deassert | |
900 | * | |
901 | * Some IP like dsp, ipu or iva contain processor that require | |
902 | * an HW reset line to be assert / deassert in order to enable fully | |
903 | * the IP. | |
904 | */ | |
905 | static int _deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
906 | { | |
907 | u8 shift; | |
908 | int r; | |
909 | ||
910 | if (!oh) | |
911 | return -EINVAL; | |
912 | ||
913 | shift = _lookup_hardreset(oh, name); | |
914 | if (IS_ERR_VALUE(shift)) | |
915 | return shift; | |
916 | ||
917 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | |
918 | r = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs, | |
919 | shift); | |
920 | else if (cpu_is_omap44xx()) | |
921 | r = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg, | |
922 | shift); | |
923 | else | |
924 | return -EINVAL; | |
925 | ||
926 | if (r == -EBUSY) | |
927 | pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name); | |
928 | ||
929 | return r; | |
930 | } | |
931 | ||
932 | /** | |
933 | * _read_hardreset - read the HW reset line state of submodules | |
934 | * contained in the hwmod module | |
935 | * @oh: struct omap_hwmod * | |
936 | * @name: name of the reset line to look up and read | |
937 | * | |
938 | * Return the state of the reset line. | |
939 | */ | |
940 | static int _read_hardreset(struct omap_hwmod *oh, const char *name) | |
941 | { | |
942 | u8 shift; | |
943 | ||
944 | if (!oh) | |
945 | return -EINVAL; | |
946 | ||
947 | shift = _lookup_hardreset(oh, name); | |
948 | if (IS_ERR_VALUE(shift)) | |
949 | return shift; | |
950 | ||
951 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
952 | return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs, | |
953 | shift); | |
954 | } else if (cpu_is_omap44xx()) { | |
955 | return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg, | |
956 | shift); | |
957 | } else { | |
958 | return -EINVAL; | |
959 | } | |
960 | } | |
961 | ||
63c85238 PW |
962 | /** |
963 | * _reset - reset an omap_hwmod | |
964 | * @oh: struct omap_hwmod * | |
965 | * | |
966 | * Resets an omap_hwmod @oh via the OCP_SYSCONFIG bit. hwmod must be | |
12b1fdb4 KH |
967 | * enabled for this to work. Returns -EINVAL if the hwmod cannot be |
968 | * reset this way or if the hwmod is in the wrong state, -ETIMEDOUT if | |
969 | * the module did not reset in time, or 0 upon success. | |
2cb06814 BC |
970 | * |
971 | * In OMAP3 a specific SYSSTATUS register is used to get the reset status. | |
972 | * Starting in OMAP4, some IPs does not have SYSSTATUS register and instead | |
973 | * use the SYSCONFIG softreset bit to provide the status. | |
974 | * | |
975 | * Note that some IP like McBSP does have a reset control but no reset status. | |
63c85238 PW |
976 | */ |
977 | static int _reset(struct omap_hwmod *oh) | |
978 | { | |
979 | u32 r, v; | |
6f8b7ff5 | 980 | int c = 0; |
63c85238 | 981 | |
43b40992 | 982 | if (!oh->class->sysc || |
2cb06814 | 983 | !(oh->class->sysc->sysc_flags & SYSC_HAS_SOFTRESET)) |
63c85238 PW |
984 | return -EINVAL; |
985 | ||
986 | /* clocks must be on for this operation */ | |
987 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
76e5589e BC |
988 | pr_warning("omap_hwmod: %s: reset can only be entered from " |
989 | "enabled state\n", oh->name); | |
63c85238 PW |
990 | return -EINVAL; |
991 | } | |
992 | ||
993 | pr_debug("omap_hwmod: %s: resetting\n", oh->name); | |
994 | ||
995 | v = oh->_sysc_cache; | |
996 | r = _set_softreset(oh, &v); | |
997 | if (r) | |
998 | return r; | |
999 | _write_sysconfig(v, oh); | |
1000 | ||
2cb06814 BC |
1001 | if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS) |
1002 | omap_test_timeout((omap_hwmod_readl(oh, | |
1003 | oh->class->sysc->syss_offs) | |
1004 | & SYSS_RESETDONE_MASK), | |
1005 | MAX_MODULE_SOFTRESET_WAIT, c); | |
1006 | else if (oh->class->sysc->sysc_flags & SYSC_HAS_RESET_STATUS) | |
1007 | omap_test_timeout(!(omap_hwmod_readl(oh, | |
1008 | oh->class->sysc->sysc_offs) | |
1009 | & SYSC_TYPE2_SOFTRESET_MASK), | |
1010 | MAX_MODULE_SOFTRESET_WAIT, c); | |
63c85238 | 1011 | |
5365efbe | 1012 | if (c == MAX_MODULE_SOFTRESET_WAIT) |
76e5589e BC |
1013 | pr_warning("omap_hwmod: %s: softreset failed (waited %d usec)\n", |
1014 | oh->name, MAX_MODULE_SOFTRESET_WAIT); | |
63c85238 | 1015 | else |
5365efbe | 1016 | pr_debug("omap_hwmod: %s: softreset in %d usec\n", oh->name, c); |
63c85238 PW |
1017 | |
1018 | /* | |
1019 | * XXX add _HWMOD_STATE_WEDGED for modules that don't come back from | |
1020 | * _wait_target_ready() or _reset() | |
1021 | */ | |
1022 | ||
5365efbe | 1023 | return (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; |
63c85238 PW |
1024 | } |
1025 | ||
1026 | /** | |
84824022 | 1027 | * _omap_hwmod_enable - enable an omap_hwmod |
63c85238 PW |
1028 | * @oh: struct omap_hwmod * |
1029 | * | |
1030 | * Enables an omap_hwmod @oh such that the MPU can access the hwmod's | |
12b1fdb4 KH |
1031 | * register target. Returns -EINVAL if the hwmod is in the wrong |
1032 | * state or passes along the return value of _wait_target_ready(). | |
63c85238 | 1033 | */ |
84824022 | 1034 | int _omap_hwmod_enable(struct omap_hwmod *oh) |
63c85238 PW |
1035 | { |
1036 | int r; | |
1037 | ||
1038 | if (oh->_state != _HWMOD_STATE_INITIALIZED && | |
1039 | oh->_state != _HWMOD_STATE_IDLE && | |
1040 | oh->_state != _HWMOD_STATE_DISABLED) { | |
1041 | WARN(1, "omap_hwmod: %s: enabled state can only be entered " | |
1042 | "from initialized, idle, or disabled state\n", oh->name); | |
1043 | return -EINVAL; | |
1044 | } | |
1045 | ||
1046 | pr_debug("omap_hwmod: %s: enabling\n", oh->name); | |
1047 | ||
5365efbe BC |
1048 | /* |
1049 | * If an IP contains only one HW reset line, then de-assert it in order | |
1050 | * to allow to enable the clocks. Otherwise the PRCM will return | |
1051 | * Intransition status, and the init will failed. | |
1052 | */ | |
1053 | if ((oh->_state == _HWMOD_STATE_INITIALIZED || | |
1054 | oh->_state == _HWMOD_STATE_DISABLED) && oh->rst_lines_cnt == 1) | |
1055 | _deassert_hardreset(oh, oh->rst_lines[0].name); | |
1056 | ||
63c85238 PW |
1057 | /* XXX mux balls */ |
1058 | ||
1059 | _add_initiator_dep(oh, mpu_oh); | |
1060 | _enable_clocks(oh); | |
1061 | ||
63c85238 | 1062 | r = _wait_target_ready(oh); |
9a23dfe1 | 1063 | if (!r) { |
63c85238 PW |
1064 | oh->_state = _HWMOD_STATE_ENABLED; |
1065 | ||
9a23dfe1 BC |
1066 | /* Access the sysconfig only if the target is ready */ |
1067 | if (oh->class->sysc) { | |
1068 | if (!(oh->_int_flags & _HWMOD_SYSCONFIG_LOADED)) | |
1069 | _update_sysc_cache(oh); | |
1070 | _sysc_enable(oh); | |
1071 | } | |
1072 | } else { | |
1073 | pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n", | |
1074 | oh->name, r); | |
1075 | } | |
1076 | ||
63c85238 PW |
1077 | return r; |
1078 | } | |
1079 | ||
1080 | /** | |
1081 | * _idle - idle an omap_hwmod | |
1082 | * @oh: struct omap_hwmod * | |
1083 | * | |
1084 | * Idles an omap_hwmod @oh. This should be called once the hwmod has | |
1085 | * no further work. Returns -EINVAL if the hwmod is in the wrong | |
1086 | * state or returns 0. | |
1087 | */ | |
84824022 | 1088 | int _omap_hwmod_idle(struct omap_hwmod *oh) |
63c85238 PW |
1089 | { |
1090 | if (oh->_state != _HWMOD_STATE_ENABLED) { | |
1091 | WARN(1, "omap_hwmod: %s: idle state can only be entered from " | |
1092 | "enabled state\n", oh->name); | |
1093 | return -EINVAL; | |
1094 | } | |
1095 | ||
1096 | pr_debug("omap_hwmod: %s: idling\n", oh->name); | |
1097 | ||
43b40992 | 1098 | if (oh->class->sysc) |
63c85238 PW |
1099 | _sysc_idle(oh); |
1100 | _del_initiator_dep(oh, mpu_oh); | |
1101 | _disable_clocks(oh); | |
1102 | ||
1103 | oh->_state = _HWMOD_STATE_IDLE; | |
1104 | ||
1105 | return 0; | |
1106 | } | |
1107 | ||
1108 | /** | |
1109 | * _shutdown - shutdown an omap_hwmod | |
1110 | * @oh: struct omap_hwmod * | |
1111 | * | |
1112 | * Shut down an omap_hwmod @oh. This should be called when the driver | |
1113 | * used for the hwmod is removed or unloaded or if the driver is not | |
1114 | * used by the system. Returns -EINVAL if the hwmod is in the wrong | |
1115 | * state or returns 0. | |
1116 | */ | |
1117 | static int _shutdown(struct omap_hwmod *oh) | |
1118 | { | |
1119 | if (oh->_state != _HWMOD_STATE_IDLE && | |
1120 | oh->_state != _HWMOD_STATE_ENABLED) { | |
1121 | WARN(1, "omap_hwmod: %s: disabled state can only be entered " | |
1122 | "from idle, or enabled state\n", oh->name); | |
1123 | return -EINVAL; | |
1124 | } | |
1125 | ||
1126 | pr_debug("omap_hwmod: %s: disabling\n", oh->name); | |
1127 | ||
43b40992 | 1128 | if (oh->class->sysc) |
63c85238 | 1129 | _sysc_shutdown(oh); |
3827f949 | 1130 | |
5365efbe BC |
1131 | /* |
1132 | * If an IP contains only one HW reset line, then assert it | |
1133 | * before disabling the clocks and shutting down the IP. | |
1134 | */ | |
1135 | if (oh->rst_lines_cnt == 1) | |
1136 | _assert_hardreset(oh, oh->rst_lines[0].name); | |
1137 | ||
3827f949 BC |
1138 | /* clocks and deps are already disabled in idle */ |
1139 | if (oh->_state == _HWMOD_STATE_ENABLED) { | |
1140 | _del_initiator_dep(oh, mpu_oh); | |
1141 | /* XXX what about the other system initiators here? dma, dsp */ | |
1142 | _disable_clocks(oh); | |
1143 | } | |
63c85238 PW |
1144 | /* XXX Should this code also force-disable the optional clocks? */ |
1145 | ||
1146 | /* XXX mux any associated balls to safe mode */ | |
1147 | ||
1148 | oh->_state = _HWMOD_STATE_DISABLED; | |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
63c85238 PW |
1153 | /** |
1154 | * _setup - do initial configuration of omap_hwmod | |
1155 | * @oh: struct omap_hwmod * | |
97d60162 | 1156 | * @skip_setup_idle_p: do not idle hwmods at the end of the fn if 1 |
63c85238 PW |
1157 | * |
1158 | * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh | |
12b1fdb4 KH |
1159 | * OCP_SYSCONFIG register. @skip_setup_idle is intended to be used on |
1160 | * a system that will not call omap_hwmod_enable() to enable devices | |
1161 | * (e.g., a system without PM runtime). Returns -EINVAL if the hwmod | |
1162 | * is in the wrong state or returns 0. | |
63c85238 | 1163 | */ |
97d60162 | 1164 | static int _setup(struct omap_hwmod *oh, void *data) |
63c85238 | 1165 | { |
9a23dfe1 | 1166 | int i, r; |
97d60162 | 1167 | u8 skip_setup_idle; |
63c85238 | 1168 | |
97d60162 | 1169 | if (!oh || !data) |
63c85238 PW |
1170 | return -EINVAL; |
1171 | ||
97d60162 PW |
1172 | skip_setup_idle = *(u8 *)data; |
1173 | ||
63c85238 PW |
1174 | /* Set iclk autoidle mode */ |
1175 | if (oh->slaves_cnt > 0) { | |
682fdc96 BC |
1176 | for (i = 0; i < oh->slaves_cnt; i++) { |
1177 | struct omap_hwmod_ocp_if *os = oh->slaves[i]; | |
63c85238 PW |
1178 | struct clk *c = os->_clk; |
1179 | ||
4d3ae5a9 | 1180 | if (!c) |
63c85238 PW |
1181 | continue; |
1182 | ||
1183 | if (os->flags & OCPIF_SWSUP_IDLE) { | |
1184 | /* XXX omap_iclk_deny_idle(c); */ | |
1185 | } else { | |
1186 | /* XXX omap_iclk_allow_idle(c); */ | |
1187 | clk_enable(c); | |
1188 | } | |
1189 | } | |
1190 | } | |
1191 | ||
12b1fdb4 | 1192 | mutex_init(&oh->_mutex); |
63c85238 PW |
1193 | oh->_state = _HWMOD_STATE_INITIALIZED; |
1194 | ||
5365efbe BC |
1195 | /* |
1196 | * In the case of hwmod with hardreset that should not be | |
1197 | * de-assert at boot time, we have to keep the module | |
1198 | * initialized, because we cannot enable it properly with the | |
1199 | * reset asserted. Exit without warning because that behavior is | |
1200 | * expected. | |
1201 | */ | |
1202 | if ((oh->flags & HWMOD_INIT_NO_RESET) && oh->rst_lines_cnt == 1) | |
1203 | return 0; | |
1204 | ||
84824022 | 1205 | r = _omap_hwmod_enable(oh); |
9a23dfe1 BC |
1206 | if (r) { |
1207 | pr_warning("omap_hwmod: %s: cannot be enabled (%d)\n", | |
1208 | oh->name, oh->_state); | |
1209 | return 0; | |
1210 | } | |
63c85238 | 1211 | |
b835d014 | 1212 | if (!(oh->flags & HWMOD_INIT_NO_RESET)) { |
76e5589e BC |
1213 | _reset(oh); |
1214 | ||
b835d014 | 1215 | /* |
76e5589e BC |
1216 | * OCP_SYSCONFIG bits need to be reprogrammed after a softreset. |
1217 | * The _omap_hwmod_enable() function should be split to | |
1218 | * avoid the rewrite of the OCP_SYSCONFIG register. | |
b835d014 | 1219 | */ |
43b40992 | 1220 | if (oh->class->sysc) { |
b835d014 PW |
1221 | _update_sysc_cache(oh); |
1222 | _sysc_enable(oh); | |
1223 | } | |
1224 | } | |
63c85238 | 1225 | |
97d60162 | 1226 | if (!(oh->flags & HWMOD_INIT_NO_IDLE) && !skip_setup_idle) |
84824022 | 1227 | _omap_hwmod_idle(oh); |
63c85238 PW |
1228 | |
1229 | return 0; | |
1230 | } | |
1231 | ||
1232 | ||
1233 | ||
1234 | /* Public functions */ | |
1235 | ||
1236 | u32 omap_hwmod_readl(struct omap_hwmod *oh, u16 reg_offs) | |
1237 | { | |
db2a60bf | 1238 | return __raw_readl(oh->_mpu_rt_va + reg_offs); |
63c85238 PW |
1239 | } |
1240 | ||
1241 | void omap_hwmod_writel(u32 v, struct omap_hwmod *oh, u16 reg_offs) | |
1242 | { | |
db2a60bf | 1243 | __raw_writel(v, oh->_mpu_rt_va + reg_offs); |
63c85238 PW |
1244 | } |
1245 | ||
887adeac PW |
1246 | /** |
1247 | * omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode | |
1248 | * @oh: struct omap_hwmod * | |
1249 | * @idlemode: SIDLEMODE field bits (shifted to bit 0) | |
1250 | * | |
1251 | * Sets the IP block's OCP slave idlemode in hardware, and updates our | |
1252 | * local copy. Intended to be used by drivers that have some erratum | |
1253 | * that requires direct manipulation of the SIDLEMODE bits. Returns | |
1254 | * -EINVAL if @oh is null, or passes along the return value from | |
1255 | * _set_slave_idlemode(). | |
1256 | * | |
1257 | * XXX Does this function have any current users? If not, we should | |
1258 | * remove it; it is better to let the rest of the hwmod code handle this. | |
1259 | * Any users of this function should be scrutinized carefully. | |
1260 | */ | |
46273e6f KH |
1261 | int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode) |
1262 | { | |
1263 | u32 v; | |
1264 | int retval = 0; | |
1265 | ||
1266 | if (!oh) | |
1267 | return -EINVAL; | |
1268 | ||
1269 | v = oh->_sysc_cache; | |
1270 | ||
1271 | retval = _set_slave_idlemode(oh, idlemode, &v); | |
1272 | if (!retval) | |
1273 | _write_sysconfig(v, oh); | |
1274 | ||
1275 | return retval; | |
1276 | } | |
1277 | ||
63c85238 PW |
1278 | /** |
1279 | * omap_hwmod_register - register a struct omap_hwmod | |
1280 | * @oh: struct omap_hwmod * | |
1281 | * | |
43b40992 PW |
1282 | * Registers the omap_hwmod @oh. Returns -EEXIST if an omap_hwmod |
1283 | * already has been registered by the same name; -EINVAL if the | |
1284 | * omap_hwmod is in the wrong state, if @oh is NULL, if the | |
1285 | * omap_hwmod's class field is NULL; if the omap_hwmod is missing a | |
1286 | * name, or if the omap_hwmod's class is missing a name; or 0 upon | |
1287 | * success. | |
63c85238 PW |
1288 | * |
1289 | * XXX The data should be copied into bootmem, so the original data | |
1290 | * should be marked __initdata and freed after init. This would allow | |
1291 | * unneeded omap_hwmods to be freed on multi-OMAP configurations. Note | |
1292 | * that the copy process would be relatively complex due to the large number | |
1293 | * of substructures. | |
1294 | */ | |
1295 | int omap_hwmod_register(struct omap_hwmod *oh) | |
1296 | { | |
1297 | int ret, ms_id; | |
1298 | ||
43b40992 PW |
1299 | if (!oh || !oh->name || !oh->class || !oh->class->name || |
1300 | (oh->_state != _HWMOD_STATE_UNKNOWN)) | |
63c85238 PW |
1301 | return -EINVAL; |
1302 | ||
1303 | mutex_lock(&omap_hwmod_mutex); | |
1304 | ||
1305 | pr_debug("omap_hwmod: %s: registering\n", oh->name); | |
1306 | ||
1307 | if (_lookup(oh->name)) { | |
1308 | ret = -EEXIST; | |
1309 | goto ohr_unlock; | |
1310 | } | |
1311 | ||
1312 | ms_id = _find_mpu_port_index(oh); | |
1313 | if (!IS_ERR_VALUE(ms_id)) { | |
1314 | oh->_mpu_port_index = ms_id; | |
db2a60bf | 1315 | oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index); |
63c85238 PW |
1316 | } else { |
1317 | oh->_int_flags |= _HWMOD_NO_MPU_PORT; | |
1318 | } | |
1319 | ||
1320 | list_add_tail(&oh->node, &omap_hwmod_list); | |
1321 | ||
1322 | oh->_state = _HWMOD_STATE_REGISTERED; | |
1323 | ||
1324 | ret = 0; | |
1325 | ||
1326 | ohr_unlock: | |
1327 | mutex_unlock(&omap_hwmod_mutex); | |
1328 | return ret; | |
1329 | } | |
1330 | ||
1331 | /** | |
1332 | * omap_hwmod_lookup - look up a registered omap_hwmod by name | |
1333 | * @name: name of the omap_hwmod to look up | |
1334 | * | |
1335 | * Given a @name of an omap_hwmod, return a pointer to the registered | |
1336 | * struct omap_hwmod *, or NULL upon error. | |
1337 | */ | |
1338 | struct omap_hwmod *omap_hwmod_lookup(const char *name) | |
1339 | { | |
1340 | struct omap_hwmod *oh; | |
1341 | ||
1342 | if (!name) | |
1343 | return NULL; | |
1344 | ||
1345 | mutex_lock(&omap_hwmod_mutex); | |
1346 | oh = _lookup(name); | |
1347 | mutex_unlock(&omap_hwmod_mutex); | |
1348 | ||
1349 | return oh; | |
1350 | } | |
1351 | ||
1352 | /** | |
1353 | * omap_hwmod_for_each - call function for each registered omap_hwmod | |
1354 | * @fn: pointer to a callback function | |
97d60162 | 1355 | * @data: void * data to pass to callback function |
63c85238 PW |
1356 | * |
1357 | * Call @fn for each registered omap_hwmod, passing @data to each | |
1358 | * function. @fn must return 0 for success or any other value for | |
1359 | * failure. If @fn returns non-zero, the iteration across omap_hwmods | |
1360 | * will stop and the non-zero return value will be passed to the | |
1361 | * caller of omap_hwmod_for_each(). @fn is called with | |
1362 | * omap_hwmod_for_each() held. | |
1363 | */ | |
97d60162 PW |
1364 | int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data), |
1365 | void *data) | |
63c85238 PW |
1366 | { |
1367 | struct omap_hwmod *temp_oh; | |
1368 | int ret; | |
1369 | ||
1370 | if (!fn) | |
1371 | return -EINVAL; | |
1372 | ||
1373 | mutex_lock(&omap_hwmod_mutex); | |
1374 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
97d60162 | 1375 | ret = (*fn)(temp_oh, data); |
63c85238 PW |
1376 | if (ret) |
1377 | break; | |
1378 | } | |
1379 | mutex_unlock(&omap_hwmod_mutex); | |
1380 | ||
1381 | return ret; | |
1382 | } | |
1383 | ||
1384 | ||
1385 | /** | |
1386 | * omap_hwmod_init - init omap_hwmod code and register hwmods | |
1387 | * @ohs: pointer to an array of omap_hwmods to register | |
1388 | * | |
1389 | * Intended to be called early in boot before the clock framework is | |
1390 | * initialized. If @ohs is not null, will register all omap_hwmods | |
1391 | * listed in @ohs that are valid for this chip. Returns -EINVAL if | |
1392 | * omap_hwmod_init() has already been called or 0 otherwise. | |
1393 | */ | |
1394 | int omap_hwmod_init(struct omap_hwmod **ohs) | |
1395 | { | |
1396 | struct omap_hwmod *oh; | |
1397 | int r; | |
1398 | ||
1399 | if (inited) | |
1400 | return -EINVAL; | |
1401 | ||
1402 | inited = 1; | |
1403 | ||
1404 | if (!ohs) | |
1405 | return 0; | |
1406 | ||
1407 | oh = *ohs; | |
1408 | while (oh) { | |
1409 | if (omap_chip_is(oh->omap_chip)) { | |
1410 | r = omap_hwmod_register(oh); | |
1411 | WARN(r, "omap_hwmod: %s: omap_hwmod_register returned " | |
1412 | "%d\n", oh->name, r); | |
1413 | } | |
1414 | oh = *++ohs; | |
1415 | } | |
1416 | ||
1417 | return 0; | |
1418 | } | |
1419 | ||
1420 | /** | |
1421 | * omap_hwmod_late_init - do some post-clock framework initialization | |
97d60162 | 1422 | * @skip_setup_idle: if 1, do not idle hwmods in _setup() |
63c85238 PW |
1423 | * |
1424 | * Must be called after omap2_clk_init(). Resolves the struct clk names | |
1425 | * to struct clk pointers for each registered omap_hwmod. Also calls | |
1426 | * _setup() on each hwmod. Returns 0. | |
1427 | */ | |
97d60162 | 1428 | int omap_hwmod_late_init(u8 skip_setup_idle) |
63c85238 PW |
1429 | { |
1430 | int r; | |
1431 | ||
1432 | /* XXX check return value */ | |
97d60162 | 1433 | r = omap_hwmod_for_each(_init_clocks, NULL); |
63c85238 PW |
1434 | WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n"); |
1435 | ||
1436 | mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME); | |
1437 | WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n", | |
1438 | MPU_INITIATOR_NAME); | |
1439 | ||
97d60162 PW |
1440 | if (skip_setup_idle) |
1441 | pr_debug("omap_hwmod: will leave hwmods enabled during setup\n"); | |
1442 | ||
1443 | omap_hwmod_for_each(_setup, &skip_setup_idle); | |
63c85238 PW |
1444 | |
1445 | return 0; | |
1446 | } | |
1447 | ||
1448 | /** | |
1449 | * omap_hwmod_unregister - unregister an omap_hwmod | |
1450 | * @oh: struct omap_hwmod * | |
1451 | * | |
1452 | * Unregisters a previously-registered omap_hwmod @oh. There's probably | |
1453 | * no use case for this, so it is likely to be removed in a later version. | |
1454 | * | |
1455 | * XXX Free all of the bootmem-allocated structures here when that is | |
1456 | * implemented. Make it clear that core code is the only code that is | |
1457 | * expected to unregister modules. | |
1458 | */ | |
1459 | int omap_hwmod_unregister(struct omap_hwmod *oh) | |
1460 | { | |
1461 | if (!oh) | |
1462 | return -EINVAL; | |
1463 | ||
1464 | pr_debug("omap_hwmod: %s: unregistering\n", oh->name); | |
1465 | ||
1466 | mutex_lock(&omap_hwmod_mutex); | |
db2a60bf | 1467 | iounmap(oh->_mpu_rt_va); |
63c85238 PW |
1468 | list_del(&oh->node); |
1469 | mutex_unlock(&omap_hwmod_mutex); | |
1470 | ||
1471 | return 0; | |
1472 | } | |
1473 | ||
1474 | /** | |
1475 | * omap_hwmod_enable - enable an omap_hwmod | |
1476 | * @oh: struct omap_hwmod * | |
1477 | * | |
1478 | * Enable an omap_hwomd @oh. Intended to be called by omap_device_enable(). | |
1479 | * Returns -EINVAL on error or passes along the return value from _enable(). | |
1480 | */ | |
1481 | int omap_hwmod_enable(struct omap_hwmod *oh) | |
1482 | { | |
1483 | int r; | |
1484 | ||
1485 | if (!oh) | |
1486 | return -EINVAL; | |
1487 | ||
12b1fdb4 | 1488 | mutex_lock(&oh->_mutex); |
84824022 | 1489 | r = _omap_hwmod_enable(oh); |
12b1fdb4 | 1490 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1491 | |
1492 | return r; | |
1493 | } | |
1494 | ||
84824022 | 1495 | |
63c85238 PW |
1496 | /** |
1497 | * omap_hwmod_idle - idle an omap_hwmod | |
1498 | * @oh: struct omap_hwmod * | |
1499 | * | |
1500 | * Idle an omap_hwomd @oh. Intended to be called by omap_device_idle(). | |
1501 | * Returns -EINVAL on error or passes along the return value from _idle(). | |
1502 | */ | |
1503 | int omap_hwmod_idle(struct omap_hwmod *oh) | |
1504 | { | |
1505 | if (!oh) | |
1506 | return -EINVAL; | |
1507 | ||
12b1fdb4 | 1508 | mutex_lock(&oh->_mutex); |
84824022 | 1509 | _omap_hwmod_idle(oh); |
12b1fdb4 | 1510 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1511 | |
1512 | return 0; | |
1513 | } | |
1514 | ||
1515 | /** | |
1516 | * omap_hwmod_shutdown - shutdown an omap_hwmod | |
1517 | * @oh: struct omap_hwmod * | |
1518 | * | |
1519 | * Shutdown an omap_hwomd @oh. Intended to be called by | |
1520 | * omap_device_shutdown(). Returns -EINVAL on error or passes along | |
1521 | * the return value from _shutdown(). | |
1522 | */ | |
1523 | int omap_hwmod_shutdown(struct omap_hwmod *oh) | |
1524 | { | |
1525 | if (!oh) | |
1526 | return -EINVAL; | |
1527 | ||
12b1fdb4 | 1528 | mutex_lock(&oh->_mutex); |
63c85238 | 1529 | _shutdown(oh); |
12b1fdb4 | 1530 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1531 | |
1532 | return 0; | |
1533 | } | |
1534 | ||
1535 | /** | |
1536 | * omap_hwmod_enable_clocks - enable main_clk, all interface clocks | |
1537 | * @oh: struct omap_hwmod *oh | |
1538 | * | |
1539 | * Intended to be called by the omap_device code. | |
1540 | */ | |
1541 | int omap_hwmod_enable_clocks(struct omap_hwmod *oh) | |
1542 | { | |
12b1fdb4 | 1543 | mutex_lock(&oh->_mutex); |
63c85238 | 1544 | _enable_clocks(oh); |
12b1fdb4 | 1545 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1546 | |
1547 | return 0; | |
1548 | } | |
1549 | ||
1550 | /** | |
1551 | * omap_hwmod_disable_clocks - disable main_clk, all interface clocks | |
1552 | * @oh: struct omap_hwmod *oh | |
1553 | * | |
1554 | * Intended to be called by the omap_device code. | |
1555 | */ | |
1556 | int omap_hwmod_disable_clocks(struct omap_hwmod *oh) | |
1557 | { | |
12b1fdb4 | 1558 | mutex_lock(&oh->_mutex); |
63c85238 | 1559 | _disable_clocks(oh); |
12b1fdb4 | 1560 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1561 | |
1562 | return 0; | |
1563 | } | |
1564 | ||
1565 | /** | |
1566 | * omap_hwmod_ocp_barrier - wait for posted writes against the hwmod to complete | |
1567 | * @oh: struct omap_hwmod *oh | |
1568 | * | |
1569 | * Intended to be called by drivers and core code when all posted | |
1570 | * writes to a device must complete before continuing further | |
1571 | * execution (for example, after clearing some device IRQSTATUS | |
1572 | * register bits) | |
1573 | * | |
1574 | * XXX what about targets with multiple OCP threads? | |
1575 | */ | |
1576 | void omap_hwmod_ocp_barrier(struct omap_hwmod *oh) | |
1577 | { | |
1578 | BUG_ON(!oh); | |
1579 | ||
43b40992 | 1580 | if (!oh->class->sysc || !oh->class->sysc->sysc_flags) { |
63c85238 PW |
1581 | WARN(1, "omap_device: %s: OCP barrier impossible due to " |
1582 | "device configuration\n", oh->name); | |
1583 | return; | |
1584 | } | |
1585 | ||
1586 | /* | |
1587 | * Forces posted writes to complete on the OCP thread handling | |
1588 | * register writes | |
1589 | */ | |
43b40992 | 1590 | omap_hwmod_readl(oh, oh->class->sysc->sysc_offs); |
63c85238 PW |
1591 | } |
1592 | ||
1593 | /** | |
1594 | * omap_hwmod_reset - reset the hwmod | |
1595 | * @oh: struct omap_hwmod * | |
1596 | * | |
1597 | * Under some conditions, a driver may wish to reset the entire device. | |
1598 | * Called from omap_device code. Returns -EINVAL on error or passes along | |
9b579114 | 1599 | * the return value from _reset(). |
63c85238 PW |
1600 | */ |
1601 | int omap_hwmod_reset(struct omap_hwmod *oh) | |
1602 | { | |
1603 | int r; | |
1604 | ||
9b579114 | 1605 | if (!oh) |
63c85238 PW |
1606 | return -EINVAL; |
1607 | ||
12b1fdb4 | 1608 | mutex_lock(&oh->_mutex); |
63c85238 | 1609 | r = _reset(oh); |
12b1fdb4 | 1610 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1611 | |
1612 | return r; | |
1613 | } | |
1614 | ||
1615 | /** | |
1616 | * omap_hwmod_count_resources - count number of struct resources needed by hwmod | |
1617 | * @oh: struct omap_hwmod * | |
1618 | * @res: pointer to the first element of an array of struct resource to fill | |
1619 | * | |
1620 | * Count the number of struct resource array elements necessary to | |
1621 | * contain omap_hwmod @oh resources. Intended to be called by code | |
1622 | * that registers omap_devices. Intended to be used to determine the | |
1623 | * size of a dynamically-allocated struct resource array, before | |
1624 | * calling omap_hwmod_fill_resources(). Returns the number of struct | |
1625 | * resource array elements needed. | |
1626 | * | |
1627 | * XXX This code is not optimized. It could attempt to merge adjacent | |
1628 | * resource IDs. | |
1629 | * | |
1630 | */ | |
1631 | int omap_hwmod_count_resources(struct omap_hwmod *oh) | |
1632 | { | |
1633 | int ret, i; | |
1634 | ||
9ee9fff9 | 1635 | ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt; |
63c85238 PW |
1636 | |
1637 | for (i = 0; i < oh->slaves_cnt; i++) | |
682fdc96 | 1638 | ret += oh->slaves[i]->addr_cnt; |
63c85238 PW |
1639 | |
1640 | return ret; | |
1641 | } | |
1642 | ||
1643 | /** | |
1644 | * omap_hwmod_fill_resources - fill struct resource array with hwmod data | |
1645 | * @oh: struct omap_hwmod * | |
1646 | * @res: pointer to the first element of an array of struct resource to fill | |
1647 | * | |
1648 | * Fill the struct resource array @res with resource data from the | |
1649 | * omap_hwmod @oh. Intended to be called by code that registers | |
1650 | * omap_devices. See also omap_hwmod_count_resources(). Returns the | |
1651 | * number of array elements filled. | |
1652 | */ | |
1653 | int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) | |
1654 | { | |
1655 | int i, j; | |
1656 | int r = 0; | |
1657 | ||
1658 | /* For each IRQ, DMA, memory area, fill in array.*/ | |
1659 | ||
1660 | for (i = 0; i < oh->mpu_irqs_cnt; i++) { | |
718bfd76 PW |
1661 | (res + r)->name = (oh->mpu_irqs + i)->name; |
1662 | (res + r)->start = (oh->mpu_irqs + i)->irq; | |
1663 | (res + r)->end = (oh->mpu_irqs + i)->irq; | |
63c85238 PW |
1664 | (res + r)->flags = IORESOURCE_IRQ; |
1665 | r++; | |
1666 | } | |
1667 | ||
9ee9fff9 BC |
1668 | for (i = 0; i < oh->sdma_reqs_cnt; i++) { |
1669 | (res + r)->name = (oh->sdma_reqs + i)->name; | |
1670 | (res + r)->start = (oh->sdma_reqs + i)->dma_req; | |
1671 | (res + r)->end = (oh->sdma_reqs + i)->dma_req; | |
63c85238 PW |
1672 | (res + r)->flags = IORESOURCE_DMA; |
1673 | r++; | |
1674 | } | |
1675 | ||
1676 | for (i = 0; i < oh->slaves_cnt; i++) { | |
1677 | struct omap_hwmod_ocp_if *os; | |
1678 | ||
682fdc96 | 1679 | os = oh->slaves[i]; |
63c85238 PW |
1680 | |
1681 | for (j = 0; j < os->addr_cnt; j++) { | |
1682 | (res + r)->start = (os->addr + j)->pa_start; | |
1683 | (res + r)->end = (os->addr + j)->pa_end; | |
1684 | (res + r)->flags = IORESOURCE_MEM; | |
1685 | r++; | |
1686 | } | |
1687 | } | |
1688 | ||
1689 | return r; | |
1690 | } | |
1691 | ||
1692 | /** | |
1693 | * omap_hwmod_get_pwrdm - return pointer to this module's main powerdomain | |
1694 | * @oh: struct omap_hwmod * | |
1695 | * | |
1696 | * Return the powerdomain pointer associated with the OMAP module | |
1697 | * @oh's main clock. If @oh does not have a main clk, return the | |
1698 | * powerdomain associated with the interface clock associated with the | |
1699 | * module's MPU port. (XXX Perhaps this should use the SDMA port | |
1700 | * instead?) Returns NULL on error, or a struct powerdomain * on | |
1701 | * success. | |
1702 | */ | |
1703 | struct powerdomain *omap_hwmod_get_pwrdm(struct omap_hwmod *oh) | |
1704 | { | |
1705 | struct clk *c; | |
1706 | ||
1707 | if (!oh) | |
1708 | return NULL; | |
1709 | ||
1710 | if (oh->_clk) { | |
1711 | c = oh->_clk; | |
1712 | } else { | |
1713 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
1714 | return NULL; | |
1715 | c = oh->slaves[oh->_mpu_port_index]->_clk; | |
1716 | } | |
1717 | ||
d5647c18 TG |
1718 | if (!c->clkdm) |
1719 | return NULL; | |
1720 | ||
63c85238 PW |
1721 | return c->clkdm->pwrdm.ptr; |
1722 | ||
1723 | } | |
1724 | ||
db2a60bf PW |
1725 | /** |
1726 | * omap_hwmod_get_mpu_rt_va - return the module's base address (for the MPU) | |
1727 | * @oh: struct omap_hwmod * | |
1728 | * | |
1729 | * Returns the virtual address corresponding to the beginning of the | |
1730 | * module's register target, in the address range that is intended to | |
1731 | * be used by the MPU. Returns the virtual address upon success or NULL | |
1732 | * upon error. | |
1733 | */ | |
1734 | void __iomem *omap_hwmod_get_mpu_rt_va(struct omap_hwmod *oh) | |
1735 | { | |
1736 | if (!oh) | |
1737 | return NULL; | |
1738 | ||
1739 | if (oh->_int_flags & _HWMOD_NO_MPU_PORT) | |
1740 | return NULL; | |
1741 | ||
1742 | if (oh->_state == _HWMOD_STATE_UNKNOWN) | |
1743 | return NULL; | |
1744 | ||
1745 | return oh->_mpu_rt_va; | |
1746 | } | |
1747 | ||
63c85238 PW |
1748 | /** |
1749 | * omap_hwmod_add_initiator_dep - add sleepdep from @init_oh to @oh | |
1750 | * @oh: struct omap_hwmod * | |
1751 | * @init_oh: struct omap_hwmod * (initiator) | |
1752 | * | |
1753 | * Add a sleep dependency between the initiator @init_oh and @oh. | |
1754 | * Intended to be called by DSP/Bridge code via platform_data for the | |
1755 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
1756 | * code needs to add/del initiator dependencies dynamically | |
1757 | * before/after accessing a device. Returns the return value from | |
1758 | * _add_initiator_dep(). | |
1759 | * | |
1760 | * XXX Keep a usecount in the clockdomain code | |
1761 | */ | |
1762 | int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh, | |
1763 | struct omap_hwmod *init_oh) | |
1764 | { | |
1765 | return _add_initiator_dep(oh, init_oh); | |
1766 | } | |
1767 | ||
1768 | /* | |
1769 | * XXX what about functions for drivers to save/restore ocp_sysconfig | |
1770 | * for context save/restore operations? | |
1771 | */ | |
1772 | ||
1773 | /** | |
1774 | * omap_hwmod_del_initiator_dep - remove sleepdep from @init_oh to @oh | |
1775 | * @oh: struct omap_hwmod * | |
1776 | * @init_oh: struct omap_hwmod * (initiator) | |
1777 | * | |
1778 | * Remove a sleep dependency between the initiator @init_oh and @oh. | |
1779 | * Intended to be called by DSP/Bridge code via platform_data for the | |
1780 | * DSP case; and by the DMA code in the sDMA case. DMA code, *Bridge | |
1781 | * code needs to add/del initiator dependencies dynamically | |
1782 | * before/after accessing a device. Returns the return value from | |
1783 | * _del_initiator_dep(). | |
1784 | * | |
1785 | * XXX Keep a usecount in the clockdomain code | |
1786 | */ | |
1787 | int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, | |
1788 | struct omap_hwmod *init_oh) | |
1789 | { | |
1790 | return _del_initiator_dep(oh, init_oh); | |
1791 | } | |
1792 | ||
63c85238 PW |
1793 | /** |
1794 | * omap_hwmod_enable_wakeup - allow device to wake up the system | |
1795 | * @oh: struct omap_hwmod * | |
1796 | * | |
1797 | * Sets the module OCP socket ENAWAKEUP bit to allow the module to | |
1798 | * send wakeups to the PRCM. Eventually this should sets PRCM wakeup | |
1799 | * registers to cause the PRCM to receive wakeup events from the | |
1800 | * module. Does not set any wakeup routing registers beyond this | |
1801 | * point - if the module is to wake up any other module or subsystem, | |
1802 | * that must be set separately. Called by omap_device code. Returns | |
1803 | * -EINVAL on error or 0 upon success. | |
1804 | */ | |
1805 | int omap_hwmod_enable_wakeup(struct omap_hwmod *oh) | |
1806 | { | |
43b40992 PW |
1807 | if (!oh->class->sysc || |
1808 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
1809 | return -EINVAL; |
1810 | ||
12b1fdb4 | 1811 | mutex_lock(&oh->_mutex); |
63c85238 | 1812 | _enable_wakeup(oh); |
12b1fdb4 | 1813 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1814 | |
1815 | return 0; | |
1816 | } | |
1817 | ||
1818 | /** | |
1819 | * omap_hwmod_disable_wakeup - prevent device from waking the system | |
1820 | * @oh: struct omap_hwmod * | |
1821 | * | |
1822 | * Clears the module OCP socket ENAWAKEUP bit to prevent the module | |
1823 | * from sending wakeups to the PRCM. Eventually this should clear | |
1824 | * PRCM wakeup registers to cause the PRCM to ignore wakeup events | |
1825 | * from the module. Does not set any wakeup routing registers beyond | |
1826 | * this point - if the module is to wake up any other module or | |
1827 | * subsystem, that must be set separately. Called by omap_device | |
1828 | * code. Returns -EINVAL on error or 0 upon success. | |
1829 | */ | |
1830 | int omap_hwmod_disable_wakeup(struct omap_hwmod *oh) | |
1831 | { | |
43b40992 PW |
1832 | if (!oh->class->sysc || |
1833 | !(oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)) | |
63c85238 PW |
1834 | return -EINVAL; |
1835 | ||
12b1fdb4 | 1836 | mutex_lock(&oh->_mutex); |
63c85238 | 1837 | _disable_wakeup(oh); |
12b1fdb4 | 1838 | mutex_unlock(&oh->_mutex); |
63c85238 PW |
1839 | |
1840 | return 0; | |
1841 | } | |
43b40992 | 1842 | |
aee48e3c PW |
1843 | /** |
1844 | * omap_hwmod_assert_hardreset - assert the HW reset line of submodules | |
1845 | * contained in the hwmod module. | |
1846 | * @oh: struct omap_hwmod * | |
1847 | * @name: name of the reset line to lookup and assert | |
1848 | * | |
1849 | * Some IP like dsp, ipu or iva contain processor that require | |
1850 | * an HW reset line to be assert / deassert in order to enable fully | |
1851 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
1852 | * yet supported on this OMAP; otherwise, passes along the return value | |
1853 | * from _assert_hardreset(). | |
1854 | */ | |
1855 | int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name) | |
1856 | { | |
1857 | int ret; | |
1858 | ||
1859 | if (!oh) | |
1860 | return -EINVAL; | |
1861 | ||
1862 | mutex_lock(&oh->_mutex); | |
1863 | ret = _assert_hardreset(oh, name); | |
1864 | mutex_unlock(&oh->_mutex); | |
1865 | ||
1866 | return ret; | |
1867 | } | |
1868 | ||
1869 | /** | |
1870 | * omap_hwmod_deassert_hardreset - deassert the HW reset line of submodules | |
1871 | * contained in the hwmod module. | |
1872 | * @oh: struct omap_hwmod * | |
1873 | * @name: name of the reset line to look up and deassert | |
1874 | * | |
1875 | * Some IP like dsp, ipu or iva contain processor that require | |
1876 | * an HW reset line to be assert / deassert in order to enable fully | |
1877 | * the IP. Returns -EINVAL if @oh is null or if the operation is not | |
1878 | * yet supported on this OMAP; otherwise, passes along the return value | |
1879 | * from _deassert_hardreset(). | |
1880 | */ | |
1881 | int omap_hwmod_deassert_hardreset(struct omap_hwmod *oh, const char *name) | |
1882 | { | |
1883 | int ret; | |
1884 | ||
1885 | if (!oh) | |
1886 | return -EINVAL; | |
1887 | ||
1888 | mutex_lock(&oh->_mutex); | |
1889 | ret = _deassert_hardreset(oh, name); | |
1890 | mutex_unlock(&oh->_mutex); | |
1891 | ||
1892 | return ret; | |
1893 | } | |
1894 | ||
1895 | /** | |
1896 | * omap_hwmod_read_hardreset - read the HW reset line state of submodules | |
1897 | * contained in the hwmod module | |
1898 | * @oh: struct omap_hwmod * | |
1899 | * @name: name of the reset line to look up and read | |
1900 | * | |
1901 | * Return the current state of the hwmod @oh's reset line named @name: | |
1902 | * returns -EINVAL upon parameter error or if this operation | |
1903 | * is unsupported on the current OMAP; otherwise, passes along the return | |
1904 | * value from _read_hardreset(). | |
1905 | */ | |
1906 | int omap_hwmod_read_hardreset(struct omap_hwmod *oh, const char *name) | |
1907 | { | |
1908 | int ret; | |
1909 | ||
1910 | if (!oh) | |
1911 | return -EINVAL; | |
1912 | ||
1913 | mutex_lock(&oh->_mutex); | |
1914 | ret = _read_hardreset(oh, name); | |
1915 | mutex_unlock(&oh->_mutex); | |
1916 | ||
1917 | return ret; | |
1918 | } | |
1919 | ||
1920 | ||
43b40992 PW |
1921 | /** |
1922 | * omap_hwmod_for_each_by_class - call @fn for each hwmod of class @classname | |
1923 | * @classname: struct omap_hwmod_class name to search for | |
1924 | * @fn: callback function pointer to call for each hwmod in class @classname | |
1925 | * @user: arbitrary context data to pass to the callback function | |
1926 | * | |
1927 | * For each omap_hwmod of class @classname, call @fn. Takes | |
1928 | * omap_hwmod_mutex to prevent the hwmod list from changing during the | |
1929 | * iteration. If the callback function returns something other than | |
1930 | * zero, the iterator is terminated, and the callback function's return | |
1931 | * value is passed back to the caller. Returns 0 upon success, -EINVAL | |
1932 | * if @classname or @fn are NULL, or passes back the error code from @fn. | |
1933 | */ | |
1934 | int omap_hwmod_for_each_by_class(const char *classname, | |
1935 | int (*fn)(struct omap_hwmod *oh, | |
1936 | void *user), | |
1937 | void *user) | |
1938 | { | |
1939 | struct omap_hwmod *temp_oh; | |
1940 | int ret = 0; | |
1941 | ||
1942 | if (!classname || !fn) | |
1943 | return -EINVAL; | |
1944 | ||
1945 | pr_debug("omap_hwmod: %s: looking for modules of class %s\n", | |
1946 | __func__, classname); | |
1947 | ||
1948 | mutex_lock(&omap_hwmod_mutex); | |
1949 | ||
1950 | list_for_each_entry(temp_oh, &omap_hwmod_list, node) { | |
1951 | if (!strcmp(temp_oh->class->name, classname)) { | |
1952 | pr_debug("omap_hwmod: %s: %s: calling callback fn\n", | |
1953 | __func__, temp_oh->name); | |
1954 | ret = (*fn)(temp_oh, user); | |
1955 | if (ret) | |
1956 | break; | |
1957 | } | |
1958 | } | |
1959 | ||
1960 | mutex_unlock(&omap_hwmod_mutex); | |
1961 | ||
1962 | if (ret) | |
1963 | pr_debug("omap_hwmod: %s: iterator terminated early: %d\n", | |
1964 | __func__, ret); | |
1965 | ||
1966 | return ret; | |
1967 | } | |
1968 |