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Merge commit 'v2.6.34-rc2' into perf/core
[linux-2.6-block.git] / arch / arm / mach-omap2 / io.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
44169075 7 * Copyright (C) 2007-2009 Texas Instruments
646e3ed1
TL		 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
1dbae815 12 *
44169075
SS		 13 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
1dbae815
TL		 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
1dbae815
TL		 20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
fced80c7 23#include <linux/io.h>
2f135eaf 24#include <linux/clk.h>
91773a00 25#include <linux/omapfb.h>
1dbae815 26
120db2cb 27#include <asm/tlb.h>
120db2cb
TL		 28
29#include <asm/mach/map.h>
30
ce491cf8 31#include <plat/mux.h>
ce491cf8
TL		 32#include <plat/sram.h>
33#include <plat/sdrc.h>
34#include <plat/gpmc.h>
35#include <plat/serial.h>
afedec18 36#include <plat/vram.h>
646e3ed1 37
e80a9729 38#include "clock2xxx.h"
657ebfad 39#include "clock3xxx.h"
e80a9729 40#include "clock44xx.h"
1dbae815 41
ce491cf8
TL		 42#include <plat/omap-pm.h>
43#include <plat/powerdomain.h>
9717100f 44#include "powerdomains.h"
1dbae815 45
ce491cf8 46#include <plat/clockdomain.h>
801954d3 47#include "clockdomains.h"
ce491cf8 48#include <plat/omap_hwmod.h>
02bfc030 49
1dbae815
TL		 50/*
51 * The machine specific code may provide the extra mapping besides the
52 * default mapping provided here.
53 */
cc26b3b0 54
088ef950 55#ifdef CONFIG_ARCH_OMAP2
cc26b3b0 56static struct map_desc omap24xx_io_desc[] __initdata = {
1dbae815
TL		 57 {
58 .virtual = L3_24XX_VIRT,
59 .pfn = __phys_to_pfn(L3_24XX_PHYS),
60 .length = L3_24XX_SIZE,
61 .type = MT_DEVICE
62 },
09f21ed4 63 {
cc26b3b0
SMK		 64 .virtual = L4_24XX_VIRT,
65 .pfn = __phys_to_pfn(L4_24XX_PHYS),
66 .length = L4_24XX_SIZE,
67 .type = MT_DEVICE
09f21ed4 68 },
cc26b3b0
SMK		 69};
70
71#ifdef CONFIG_ARCH_OMAP2420
72static struct map_desc omap242x_io_desc[] __initdata = {
73 {
7adb9987
PW		 74 .virtual = DSP_MEM_2420_VIRT,
75 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
76 .length = DSP_MEM_2420_SIZE,
cc26b3b0
SMK		 77 .type = MT_DEVICE
78 },
79 {
7adb9987
PW		 80 .virtual = DSP_IPI_2420_VIRT,
81 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
82 .length = DSP_IPI_2420_SIZE,
cc26b3b0 83 .type = MT_DEVICE
09f21ed4 84 },
cc26b3b0 85 {
7adb9987
PW		 86 .virtual = DSP_MMU_2420_VIRT,
87 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
88 .length = DSP_MMU_2420_SIZE,
cc26b3b0
SMK		 89 .type = MT_DEVICE
90 },
91};
92
93#endif
94
72d0f1c3 95#ifdef CONFIG_ARCH_OMAP2430
cc26b3b0 96static struct map_desc omap243x_io_desc[] __initdata = {
72d0f1c3
SMK		 97 {
98 .virtual = L4_WK_243X_VIRT,
99 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
100 .length = L4_WK_243X_SIZE,
101 .type = MT_DEVICE
102 },
103 {
104 .virtual = OMAP243X_GPMC_VIRT,
105 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
106 .length = OMAP243X_GPMC_SIZE,
107 .type = MT_DEVICE
108 },
cc26b3b0
SMK		 109 {
110 .virtual = OMAP243X_SDRC_VIRT,
111 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
112 .length = OMAP243X_SDRC_SIZE,
113 .type = MT_DEVICE
114 },
115 {
116 .virtual = OMAP243X_SMS_VIRT,
117 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
118 .length = OMAP243X_SMS_SIZE,
119 .type = MT_DEVICE
120 },
121};
72d0f1c3 122#endif
72d0f1c3 123#endif
cc26b3b0 124
a8eb7ca0 125#ifdef CONFIG_ARCH_OMAP3
cc26b3b0 126static struct map_desc omap34xx_io_desc[] __initdata = {
1dbae815 127 {
cc26b3b0
SMK		 128 .virtual = L3_34XX_VIRT,
129 .pfn = __phys_to_pfn(L3_34XX_PHYS),
130 .length = L3_34XX_SIZE,
c40fae95
TL		 131 .type = MT_DEVICE
132 },
133 {
cc26b3b0
SMK		 134 .virtual = L4_34XX_VIRT,
135 .pfn = __phys_to_pfn(L4_34XX_PHYS),
136 .length = L4_34XX_SIZE,
c40fae95
TL		 137 .type = MT_DEVICE
138 },
cc26b3b0
SMK		 139 {
140 .virtual = OMAP34XX_GPMC_VIRT,
141 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
142 .length = OMAP34XX_GPMC_SIZE,
1dbae815 143 .type = MT_DEVICE
cc26b3b0
SMK		 144 },
145 {
146 .virtual = OMAP343X_SMS_VIRT,
147 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
148 .length = OMAP343X_SMS_SIZE,
149 .type = MT_DEVICE
150 },
151 {
152 .virtual = OMAP343X_SDRC_VIRT,
153 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
154 .length = OMAP343X_SDRC_SIZE,
1dbae815 155 .type = MT_DEVICE
cc26b3b0
SMK		 156 },
157 {
158 .virtual = L4_PER_34XX_VIRT,
159 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
160 .length = L4_PER_34XX_SIZE,
161 .type = MT_DEVICE
162 },
163 {
164 .virtual = L4_EMU_34XX_VIRT,
165 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
166 .length = L4_EMU_34XX_SIZE,
167 .type = MT_DEVICE
168 },
1dbae815 169};
cc26b3b0 170#endif
44169075
SS		 171#ifdef CONFIG_ARCH_OMAP4
172static struct map_desc omap44xx_io_desc[] __initdata = {
173 {
174 .virtual = L3_44XX_VIRT,
175 .pfn = __phys_to_pfn(L3_44XX_PHYS),
176 .length = L3_44XX_SIZE,
177 .type = MT_DEVICE,
178 },
179 {
180 .virtual = L4_44XX_VIRT,
181 .pfn = __phys_to_pfn(L4_44XX_PHYS),
182 .length = L4_44XX_SIZE,
183 .type = MT_DEVICE,
184 },
44169075
SS		 185 {
186 .virtual = OMAP44XX_GPMC_VIRT,
187 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
188 .length = OMAP44XX_GPMC_SIZE,
189 .type = MT_DEVICE,
190 },
f5d2d659
SS		 191 {
192 .virtual = OMAP44XX_EMIF1_VIRT,
193 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
194 .length = OMAP44XX_EMIF1_SIZE,
195 .type = MT_DEVICE,
196 },
197 {
198 .virtual = OMAP44XX_EMIF2_VIRT,
199 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
200 .length = OMAP44XX_EMIF2_SIZE,
201 .type = MT_DEVICE,
202 },
203 {
204 .virtual = OMAP44XX_DMM_VIRT,
205 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
206 .length = OMAP44XX_DMM_SIZE,
207 .type = MT_DEVICE,
208 },
44169075
SS		 209 {
210 .virtual = L4_PER_44XX_VIRT,
211 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
212 .length = L4_PER_44XX_SIZE,
213 .type = MT_DEVICE,
214 },
215 {
216 .virtual = L4_EMU_44XX_VIRT,
217 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
218 .length = L4_EMU_44XX_SIZE,
219 .type = MT_DEVICE,
220 },
221};
222#endif
1dbae815 223
6fbd55d0
TL		 224static void __init _omap2_map_common_io(void)
225{
226 /* Normally devicemaps_init() would flush caches and tlb after
227 * mdesc->map_io(), but we must also do it here because of the CPU
228 * revision check below.
229 */
230 local_flush_tlb_all();
231 flush_cache_all();
232
233 omap2_check_revision();
234 omap_sram_init();
235 omapfb_reserve_sdram();
236 omap_vram_reserve_sdram();
237}
238
239#ifdef CONFIG_ARCH_OMAP2420
8185e468 240void __init omap242x_map_common_io(void)
1dbae815 241{
cc26b3b0
SMK		 242 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
243 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
6fbd55d0
TL		 244 _omap2_map_common_io();
245}
cc26b3b0
SMK		 246#endif
247
6fbd55d0 248#ifdef CONFIG_ARCH_OMAP2430
8185e468 249void __init omap243x_map_common_io(void)
6fbd55d0 250{
cc26b3b0
SMK		 251 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
252 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
6fbd55d0
TL		 253 _omap2_map_common_io();
254}
cc26b3b0
SMK		 255#endif
256
a8eb7ca0 257#ifdef CONFIG_ARCH_OMAP3
8185e468 258void __init omap34xx_map_common_io(void)
6fbd55d0 259{
cc26b3b0 260 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
6fbd55d0
TL		 261 _omap2_map_common_io();
262}
cc26b3b0 263#endif
120db2cb 264
6fbd55d0 265#ifdef CONFIG_ARCH_OMAP4
8185e468 266void __init omap44xx_map_common_io(void)
6fbd55d0 267{
44169075 268 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
6fbd55d0 269 _omap2_map_common_io();
120db2cb 270}
6fbd55d0 271#endif
120db2cb 272
2f135eaf
PW		 273/*
274 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
275 *
276 * Sets the CORE DPLL3 M2 divider to the same value that it's at
277 * currently. This has the effect of setting the SDRC SDRAM AC timing
278 * registers to the values currently defined by the kernel. Currently
279 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
280 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
281 * or passes along the return value of clk_set_rate().
282 */
283static int __init _omap2_init_reprogram_sdrc(void)
284{
285 struct clk *dpll3_m2_ck;
286 int v = -EINVAL;
287 long rate;
288
289 if (!cpu_is_omap34xx())
290 return 0;
291
292 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
293 if (!dpll3_m2_ck)
294 return -EINVAL;
295
296 rate = clk_get_rate(dpll3_m2_ck);
297 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
298 v = clk_set_rate(dpll3_m2_ck, rate);
299 if (v)
300 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
301
302 clk_put(dpll3_m2_ck);
303
304 return v;
305}
306
58cda884
JP		 307void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
308 struct omap_sdrc_params *sdrc_cs1)
120db2cb 309{
3a759f09 310 pwrdm_init(powerdomains_omap);
55ed9694 311 clkdm_init(clockdomains_omap, clkdm_autodeps);
7359154e
PW		 312 if (cpu_is_omap242x())
313 omap2420_hwmod_init();
314 else if (cpu_is_omap243x())
315 omap2430_hwmod_init();
316 else if (cpu_is_omap34xx())
317 omap3xxx_hwmod_init();
61f04ee8 318 omap2_mux_init();
7359154e 319 /* The OPP tables have to be registered before a clk init */
c0407a96 320 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
e80a9729 321
81b34fbe
PW		 322 if (cpu_is_omap2420())
323 omap2420_clk_init();
324 else if (cpu_is_omap2430())
325 omap2430_clk_init();
e80a9729
PW		 326 else if (cpu_is_omap34xx())
327 omap3xxx_clk_init();
328 else if (cpu_is_omap44xx())
329 omap4xxx_clk_init();
330 else
331 pr_err("Could not init clock framework - unknown CPU\n");
332
b3c6df3a 333 omap_serial_early_init();
aa4b1f6e
KH		 334 if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */
335 omap_hwmod_late_init();
c0407a96 336 omap_pm_if_init();
aa4b1f6e
KH		 337 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
338 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
339 _omap2_init_reprogram_sdrc();
340 }
4bbbc1ad 341 gpmc_init();
1dbae815 342}
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