[linux-2.6-block.git] / arch / arm / mach-omap2 / dma.c

/*
 * OMAP2+ DMA driver
 *
 * Copyright (C) 2003 - 2008 Nokia Corporation
 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
 * Graphics DMA and LCD DMA graphics tranformations
 * by Imre Deak <imre.deak@nokia.com>
 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
 *
 * Copyright (C) 2009 Texas Instruments
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 * Converted DMA library into platform driver
 *	- G, Manjunath Kondaiah <manjugk@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/dmaengine.h>
#include <linux/of.h>
#include <linux/omap-dma.h>

#include "soc.h"
#include "omap_hwmod.h"
#include "omap_device.h"

static enum omap_reg_offsets dma_common_ch_end;

static const struct omap_dma_reg reg_map[] = {
	[REVISION]	= { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
	[GCR]		= { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
	[IRQSTATUS_L0]	= { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
	[IRQSTATUS_L1]	= { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
	[IRQSTATUS_L2]	= { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
	[IRQSTATUS_L3]	= { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
	[IRQENABLE_L0]	= { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
	[IRQENABLE_L1]	= { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
	[IRQENABLE_L2]	= { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
	[IRQENABLE_L3]	= { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
	[SYSSTATUS]	= { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
	[OCP_SYSCONFIG]	= { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
	[CAPS_0]	= { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
	[CAPS_2]	= { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
	[CAPS_3]	= { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
	[CAPS_4]	= { 0x0074, 0x00, OMAP_DMA_REG_32BIT },

	/* Common register offsets */
	[CCR]		= { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
	[CLNK_CTRL]	= { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
	[CICR]		= { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
	[CSR]		= { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
	[CSDP]		= { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
	[CEN]		= { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
	[CFN]		= { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
	[CSEI]		= { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
	[CSFI]		= { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
	[CDEI]		= { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
	[CDFI]		= { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
	[CSAC]		= { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
	[CDAC]		= { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },

	/* Channel specific register offsets */
	[CSSA]		= { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
	[CDSA]		= { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
	[CCEN]		= { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
	[CCFN]		= { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
	[COLOR]		= { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },

	/* OMAP4 specific registers */
	[CDP]		= { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
	[CNDP]		= { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
	[CCDN]		= { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
};

static void __iomem *dma_base;
static inline void dma_write(u32 val, int reg, int lch)
{
	void __iomem *addr = dma_base;

	addr += reg_map[reg].offset;
	addr += reg_map[reg].stride * lch;

	writel_relaxed(val, addr);
}

static inline u32 dma_read(int reg, int lch)
{
	void __iomem *addr = dma_base;

	addr += reg_map[reg].offset;
	addr += reg_map[reg].stride * lch;

	return readl_relaxed(addr);
}

static void omap2_clear_dma(int lch)
{
	int i;

	for (i = CSDP; i <= dma_common_ch_end; i += 1)
		dma_write(0, i, lch);
}

static void omap2_show_dma_caps(void)
{
	u8 revision = dma_read(REVISION, 0) & 0xff;
	printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
				revision >> 4, revision & 0xf);
}

static unsigned configure_dma_errata(void)
{
	unsigned errata = 0;

	/*
	 * Errata applicable for OMAP2430ES1.0 and all omap2420
	 *
	 * I.
	 * Erratum ID: Not Available
	 * Inter Frame DMA buffering issue DMA will wrongly
	 * buffer elements if packing and bursting is enabled. This might
	 * result in data gets stalled in FIFO at the end of the block.
	 * Workaround: DMA channels must have BUFFERING_DISABLED bit set to
	 * guarantee no data will stay in the DMA FIFO in case inter frame
	 * buffering occurs
	 *
	 * II.
	 * Erratum ID: Not Available
	 * DMA may hang when several channels are used in parallel
	 * In the following configuration, DMA channel hanging can occur:
	 * a. Channel i, hardware synchronized, is enabled
	 * b. Another channel (Channel x), software synchronized, is enabled.
	 * c. Channel i is disabled before end of transfer
	 * d. Channel i is reenabled.
	 * e. Steps 1 to 4 are repeated a certain number of times.
	 * f. A third channel (Channel y), software synchronized, is enabled.
	 * Channel x and Channel y may hang immediately after step 'f'.
	 * Workaround:
	 * For any channel used - make sure NextLCH_ID is set to the value j.
	 */
	if (cpu_is_omap2420() || (cpu_is_omap2430() &&
				(omap_type() == OMAP2430_REV_ES1_0))) {

		SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
		SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
	}

	/*
	 * Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
	 * after a transaction error.
	 * Workaround: SW should explicitely disable the channel.
	 */
	if (cpu_class_is_omap2())
		SET_DMA_ERRATA(DMA_ERRATA_i378);

	/*
	 * Erratum ID: i541: sDMA FIFO draining does not finish
	 * If sDMA channel is disabled on the fly, sDMA enters standby even
	 * through FIFO Drain is still in progress
	 * Workaround: Put sDMA in NoStandby more before a logical channel is
	 * disabled, then put it back to SmartStandby right after the channel
	 * finishes FIFO draining.
	 */
	if (cpu_is_omap34xx())
		SET_DMA_ERRATA(DMA_ERRATA_i541);

	/*
	 * Erratum ID: i88 : Special programming model needed to disable DMA
	 * before end of block.
	 * Workaround: software must ensure that the DMA is configured in No
	 * Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
	 */
	if (omap_type() == OMAP3430_REV_ES1_0)
		SET_DMA_ERRATA(DMA_ERRATA_i88);

	/*
	 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
	 * read before the DMA controller finished disabling the channel.
	 */
	SET_DMA_ERRATA(DMA_ERRATA_3_3);

	/*
	 * Erratum ID: Not Available
	 * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
	 * after secure sram context save and restore.
	 * Work around: Hence we need to manually clear those IRQs to avoid
	 * spurious interrupts. This affects only secure devices.
	 */
	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
		SET_DMA_ERRATA(DMA_ROMCODE_BUG);

	return errata;
}

static const struct dma_slave_map omap24xx_sdma_map[] = {
	{ "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
	{ "omap-aes", "tx", SDMA_FILTER_PARAM(9) },
	{ "omap-aes", "rx", SDMA_FILTER_PARAM(10) },
	{ "omap-sham", "rx", SDMA_FILTER_PARAM(13) },
	{ "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
	{ "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
	{ "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
	{ "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
	{ "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
	{ "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
	{ "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
	{ "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
	{ "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
	{ "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
	{ "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
	{ "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
	{ "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
	{ "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
	{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
	{ "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
	{ "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
	{ "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
	{ "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
	{ "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
	{ "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
	{ "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
	{ "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
	{ "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
	{ "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
	{ "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
	{ "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
	{ "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
	{ "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
	{ "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
	{ "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
	{ "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
	{ "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
	{ "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
	{ "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
	{ "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
	{ "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
	{ "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
	{ "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
	{ "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
};

static const struct dma_slave_map omap3xxx_sdma_map[] = {
	{ "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
	{ "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
	{ "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
	{ "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
	{ "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
	{ "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
	{ "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
	{ "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
	{ "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
	{ "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
	{ "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
	{ "omap_i2c.3", "tx", SDMA_FILTER_PARAM(25) },
	{ "omap_i2c.3", "rx", SDMA_FILTER_PARAM(26) },
	{ "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
	{ "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
	{ "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
	{ "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
	{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
	{ "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
	{ "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
	{ "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
	{ "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
	{ "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
	{ "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
	{ "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
	{ "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
	{ "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
	{ "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
	{ "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
	{ "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
	{ "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
	{ "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
	{ "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
	{ "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
	{ "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
	{ "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
	{ "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
	{ "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
	{ "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
	{ "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
	{ "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
	{ "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
	{ "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
	{ "omap-aes", "tx", SDMA_FILTER_PARAM(65) },
	{ "omap-aes", "rx", SDMA_FILTER_PARAM(66) },
	{ "omap-sham", "rx", SDMA_FILTER_PARAM(69) },
	{ "omap2_mcspi.3", "tx0", SDMA_FILTER_PARAM(70) },
	{ "omap2_mcspi.3", "rx0", SDMA_FILTER_PARAM(71) },
	{ "omap_hsmmc.2", "tx", SDMA_FILTER_PARAM(77) },
	{ "omap_hsmmc.2", "rx", SDMA_FILTER_PARAM(78) },
	{ "omap_uart.3", "tx", SDMA_FILTER_PARAM(81) },
	{ "omap_uart.3", "rx", SDMA_FILTER_PARAM(82) },
};

static struct omap_system_dma_plat_info dma_plat_info __initdata = {
	.reg_map	= reg_map,
	.channel_stride	= 0x60,
	.show_dma_caps	= omap2_show_dma_caps,
	.clear_dma	= omap2_clear_dma,
	.dma_write	= dma_write,
	.dma_read	= dma_read,
};

static struct platform_device_info omap_dma_dev_info = {
	.name = "omap-dma-engine",
	.id = -1,
	.dma_mask = DMA_BIT_MASK(32),
};

/* One time initializations */
static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
{
	struct platform_device			*pdev;
	struct omap_system_dma_plat_info	p;
	struct omap_dma_dev_attr		*d;
	struct resource				*mem;
	char					*name = "omap_dma_system";

	p = dma_plat_info;
	p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
	p.errata = configure_dma_errata();

	if (!of_have_populated_dt()) {
		if (soc_is_omap24xx()) {
			p.slave_map = omap24xx_sdma_map;
			p.slavecnt = ARRAY_SIZE(omap24xx_sdma_map);
		} else if (soc_is_omap34xx() || soc_is_omap3630()) {
			p.slave_map = omap3xxx_sdma_map;
			p.slavecnt = ARRAY_SIZE(omap3xxx_sdma_map);
		} else {
			pr_err("%s: The legacy DMA map is not provided!\n",
			       __func__);
			return -ENODEV;
		}
	}

	pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
	if (IS_ERR(pdev)) {
		pr_err("%s: Can't build omap_device for %s:%s.\n",
			__func__, name, oh->name);
		return PTR_ERR(pdev);
	}

	omap_dma_dev_info.res = pdev->resource;
	omap_dma_dev_info.num_res = pdev->num_resources;

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
		return -EINVAL;
	}

	dma_base = ioremap(mem->start, resource_size(mem));
	if (!dma_base) {
		dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
		return -ENOMEM;
	}

	d = oh->dev_attr;

	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
		d->dev_caps |= HS_CHANNELS_RESERVED;

	if (platform_get_irq_byname(pdev, "0") < 0)
		d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;

	/* Check the capabilities register for descriptor loading feature */
	if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
		dma_common_ch_end = CCDN;
	else
		dma_common_ch_end = CCFN;

	return 0;
}

static int __init omap2_system_dma_init(void)
{
	struct platform_device *pdev;
	int res;

	res = omap_hwmod_for_each_by_class("dma",
			omap2_system_dma_init_dev, NULL);
	if (res)
		return res;

	if (of_have_populated_dt())
		return res;

	pdev = platform_device_register_full(&omap_dma_dev_info);
	if (IS_ERR(pdev))
		return PTR_ERR(pdev);

	return res;
}
omap_arch_initcall(omap2_system_dma_init);
Commit	Line	Data
59de3cf1 MK	1	/*
	2	* OMAP2+ DMA driver
	3	*
	4	* Copyright (C) 2003 - 2008 Nokia Corporation
	5	* Author: Juha Yrjölä <juha.yrjola@nokia.com>
	6	* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
	7	* Graphics DMA and LCD DMA graphics tranformations
	8	* by Imre Deak <imre.deak@nokia.com>
	9	* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
	10	* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
	11	*
	12	* Copyright (C) 2009 Texas Instruments
	13	* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
	14	*
	15	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	16	* Converted DMA library into platform driver
	17	* - G, Manjunath Kondaiah <manjugk@ti.com>
	18	*
	19	* This program is free software; you can redistribute it and/or modify
	20	* it under the terms of the GNU General Public License version 2 as
	21	* published by the Free Software Foundation.
	22	*/
	23
	24	#include <linux/err.h>
	25	#include <linux/io.h>
	26	#include <linux/slab.h>
	27	#include <linux/module.h>
	28	#include <linux/init.h>
	29	#include <linux/device.h>
be1f9481	30	#include <linux/dma-mapping.h>
731ec4d8	31	#include <linux/dmaengine.h>
8d30662a	32	#include <linux/of.h>
45c3eb7d	33	#include <linux/omap-dma.h>
59de3cf1	34
e4c060db	35	#include "soc.h"
2a296c8f	36	#include "omap_hwmod.h"
25c7d49e TL	37	#include "omap_device.h"
25c7d49e TL	38
ad0c381a	39	static enum omap_reg_offsets dma_common_ch_end;
f31cc962	40
64a2dc3d RK	41	static const struct omap_dma_reg reg_map[] = {
	42	[REVISION] = { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
	43	[GCR] = { 0x0078, 0x00, OMAP_DMA_REG_32BIT },
	44	[IRQSTATUS_L0] = { 0x0008, 0x00, OMAP_DMA_REG_32BIT },
	45	[IRQSTATUS_L1] = { 0x000c, 0x00, OMAP_DMA_REG_32BIT },
	46	[IRQSTATUS_L2] = { 0x0010, 0x00, OMAP_DMA_REG_32BIT },
	47	[IRQSTATUS_L3] = { 0x0014, 0x00, OMAP_DMA_REG_32BIT },
	48	[IRQENABLE_L0] = { 0x0018, 0x00, OMAP_DMA_REG_32BIT },
	49	[IRQENABLE_L1] = { 0x001c, 0x00, OMAP_DMA_REG_32BIT },
	50	[IRQENABLE_L2] = { 0x0020, 0x00, OMAP_DMA_REG_32BIT },
	51	[IRQENABLE_L3] = { 0x0024, 0x00, OMAP_DMA_REG_32BIT },
	52	[SYSSTATUS] = { 0x0028, 0x00, OMAP_DMA_REG_32BIT },
	53	[OCP_SYSCONFIG] = { 0x002c, 0x00, OMAP_DMA_REG_32BIT },
	54	[CAPS_0] = { 0x0064, 0x00, OMAP_DMA_REG_32BIT },
	55	[CAPS_2] = { 0x006c, 0x00, OMAP_DMA_REG_32BIT },
	56	[CAPS_3] = { 0x0070, 0x00, OMAP_DMA_REG_32BIT },
	57	[CAPS_4] = { 0x0074, 0x00, OMAP_DMA_REG_32BIT },
f31cc962 MK	58
f31cc962 MK	59	/* Common register offsets */
64a2dc3d RK	60	[CCR] = { 0x0080, 0x60, OMAP_DMA_REG_32BIT },
	61	[CLNK_CTRL] = { 0x0084, 0x60, OMAP_DMA_REG_32BIT },
	62	[CICR] = { 0x0088, 0x60, OMAP_DMA_REG_32BIT },
	63	[CSR] = { 0x008c, 0x60, OMAP_DMA_REG_32BIT },
	64	[CSDP] = { 0x0090, 0x60, OMAP_DMA_REG_32BIT },
	65	[CEN] = { 0x0094, 0x60, OMAP_DMA_REG_32BIT },
	66	[CFN] = { 0x0098, 0x60, OMAP_DMA_REG_32BIT },
	67	[CSEI] = { 0x00a4, 0x60, OMAP_DMA_REG_32BIT },
	68	[CSFI] = { 0x00a8, 0x60, OMAP_DMA_REG_32BIT },
	69	[CDEI] = { 0x00ac, 0x60, OMAP_DMA_REG_32BIT },
	70	[CDFI] = { 0x00b0, 0x60, OMAP_DMA_REG_32BIT },
	71	[CSAC] = { 0x00b4, 0x60, OMAP_DMA_REG_32BIT },
	72	[CDAC] = { 0x00b8, 0x60, OMAP_DMA_REG_32BIT },
f31cc962 MK	73
f31cc962 MK	74	/* Channel specific register offsets */
64a2dc3d RK	75	[CSSA] = { 0x009c, 0x60, OMAP_DMA_REG_32BIT },
	76	[CDSA] = { 0x00a0, 0x60, OMAP_DMA_REG_32BIT },
	77	[CCEN] = { 0x00bc, 0x60, OMAP_DMA_REG_32BIT },
	78	[CCFN] = { 0x00c0, 0x60, OMAP_DMA_REG_32BIT },
	79	[COLOR] = { 0x00c4, 0x60, OMAP_DMA_REG_32BIT },
f31cc962 MK	80
f31cc962 MK	81	/* OMAP4 specific registers */
64a2dc3d RK	82	[CDP] = { 0x00d0, 0x60, OMAP_DMA_REG_32BIT },
	83	[CNDP] = { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
	84	[CCDN] = { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
f31cc962 MK	85	};
f31cc962 MK	86
f31cc962 MK	87	static void __iomem *dma_base;
	88	static inline void dma_write(u32 val, int reg, int lch)
	89	{
64a2dc3d RK	90	void __iomem *addr = dma_base;
	91
	92	addr += reg_map[reg].offset;
	93	addr += reg_map[reg].stride * lch;
f31cc962	94
edfaf05c	95	writel_relaxed(val, addr);
f31cc962 MK	96	}
	97
	98	static inline u32 dma_read(int reg, int lch)
	99	{
64a2dc3d RK	100	void __iomem *addr = dma_base;
	101
	102	addr += reg_map[reg].offset;
	103	addr += reg_map[reg].stride * lch;
f31cc962	104
edfaf05c	105	return readl_relaxed(addr);
f31cc962 MK	106	}
f31cc962 MK	107
f31cc962 MK	108	static void omap2_clear_dma(int lch)
f31cc962 MK	109	{
ad0c381a	110	int i;
f31cc962	111
ad0c381a	112	for (i = CSDP; i <= dma_common_ch_end; i += 1)
f31cc962 MK	113	dma_write(0, i, lch);
	114	}
	115
	116	static void omap2_show_dma_caps(void)
	117	{
	118	u8 revision = dma_read(REVISION, 0) & 0xff;
	119	printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
	120	revision >> 4, revision & 0xf);
f31cc962 MK	121	}
f31cc962 MK	122
0ef64986	123	static unsigned configure_dma_errata(void)
f31cc962	124	{
0ef64986	125	unsigned errata = 0;
f31cc962 MK	126
	127	/*
	128	* Errata applicable for OMAP2430ES1.0 and all omap2420
	129	*
	130	* I.
	131	* Erratum ID: Not Available
	132	* Inter Frame DMA buffering issue DMA will wrongly
	133	* buffer elements if packing and bursting is enabled. This might
	134	* result in data gets stalled in FIFO at the end of the block.
	135	* Workaround: DMA channels must have BUFFERING_DISABLED bit set to
	136	* guarantee no data will stay in the DMA FIFO in case inter frame
	137	* buffering occurs
	138	*
	139	* II.
	140	* Erratum ID: Not Available
	141	* DMA may hang when several channels are used in parallel
	142	* In the following configuration, DMA channel hanging can occur:
	143	* a. Channel i, hardware synchronized, is enabled
	144	* b. Another channel (Channel x), software synchronized, is enabled.
	145	* c. Channel i is disabled before end of transfer
	146	* d. Channel i is reenabled.
	147	* e. Steps 1 to 4 are repeated a certain number of times.
	148	* f. A third channel (Channel y), software synchronized, is enabled.
	149	* Channel x and Channel y may hang immediately after step 'f'.
	150	* Workaround:
	151	* For any channel used - make sure NextLCH_ID is set to the value j.
	152	*/
	153	if (cpu_is_omap2420() \|\| (cpu_is_omap2430() &&
	154	(omap_type() == OMAP2430_REV_ES1_0))) {
	155
	156	SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
	157	SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
	158	}
	159
	160	/*
	161	* Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
	162	* after a transaction error.
	163	* Workaround: SW should explicitely disable the channel.
	164	*/
	165	if (cpu_class_is_omap2())
	166	SET_DMA_ERRATA(DMA_ERRATA_i378);
	167
	168	/*
	169	* Erratum ID: i541: sDMA FIFO draining does not finish
	170	* If sDMA channel is disabled on the fly, sDMA enters standby even
	171	* through FIFO Drain is still in progress
	172	* Workaround: Put sDMA in NoStandby more before a logical channel is
	173	* disabled, then put it back to SmartStandby right after the channel
	174	* finishes FIFO draining.
	175	*/
	176	if (cpu_is_omap34xx())
	177	SET_DMA_ERRATA(DMA_ERRATA_i541);
	178
	179	/*
	180	* Erratum ID: i88 : Special programming model needed to disable DMA
	181	* before end of block.
	182	* Workaround: software must ensure that the DMA is configured in No
	183	* Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
	184	*/
	185	if (omap_type() == OMAP3430_REV_ES1_0)
	186	SET_DMA_ERRATA(DMA_ERRATA_i88);
	187
	188	/*
	189	* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
190	* read before the DMA controller finished disabling the channel.
191	*/
192	SET_DMA_ERRATA(DMA_ERRATA_3_3);
193
194	/*
195	* Erratum ID: Not Available
196	* A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
197	* after secure sram context save and restore.
198	* Work around: Hence we need to manually clear those IRQs to avoid
199	* spurious interrupts. This affects only secure devices.
200	*/
201	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
202	SET_DMA_ERRATA(DMA_ROMCODE_BUG);
203
204	return errata;
205	}
206
731ec4d8 PU	207	static const struct dma_slave_map omap24xx_sdma_map[] = {
	208	{ "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
	209	{ "omap-aes", "tx", SDMA_FILTER_PARAM(9) },
	210	{ "omap-aes", "rx", SDMA_FILTER_PARAM(10) },
	211	{ "omap-sham", "rx", SDMA_FILTER_PARAM(13) },
	212	{ "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
	213	{ "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
	214	{ "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
	215	{ "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
	216	{ "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
	217	{ "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
	218	{ "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
	219	{ "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
	220	{ "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
	221	{ "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
	222	{ "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
	223	{ "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
	224	{ "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
	225	{ "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
	226	{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
	227	{ "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
	228	{ "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
	229	{ "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
	230	{ "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
	231	{ "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
	232	{ "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
	233	{ "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
	234	{ "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
	235	{ "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
	236	{ "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
	237	{ "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
	238	{ "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
	239	{ "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
	240	{ "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
	241	{ "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
	242	{ "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
	243	{ "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
	244	{ "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
	245	{ "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
	246	{ "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
	247	{ "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
	248	{ "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
	249	{ "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
	250	{ "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
	251	{ "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
	252	};
	253
	254	static const struct dma_slave_map omap3xxx_sdma_map[] = {
	255	{ "omap-gpmc", "rxtx", SDMA_FILTER_PARAM(4) },
	256	{ "omap2_mcspi.2", "tx0", SDMA_FILTER_PARAM(15) },
	257	{ "omap2_mcspi.2", "rx0", SDMA_FILTER_PARAM(16) },
	258	{ "omap-mcbsp.3", "tx", SDMA_FILTER_PARAM(17) },
	259	{ "omap-mcbsp.3", "rx", SDMA_FILTER_PARAM(18) },
	260	{ "omap-mcbsp.4", "tx", SDMA_FILTER_PARAM(19) },
	261	{ "omap-mcbsp.4", "rx", SDMA_FILTER_PARAM(20) },
	262	{ "omap-mcbsp.5", "tx", SDMA_FILTER_PARAM(21) },
	263	{ "omap-mcbsp.5", "rx", SDMA_FILTER_PARAM(22) },
	264	{ "omap2_mcspi.2", "tx1", SDMA_FILTER_PARAM(23) },
	265	{ "omap2_mcspi.2", "rx1", SDMA_FILTER_PARAM(24) },
	266	{ "omap_i2c.3", "tx", SDMA_FILTER_PARAM(25) },
	267	{ "omap_i2c.3", "rx", SDMA_FILTER_PARAM(26) },
	268	{ "omap_i2c.1", "tx", SDMA_FILTER_PARAM(27) },
	269	{ "omap_i2c.1", "rx", SDMA_FILTER_PARAM(28) },
	270	{ "omap_i2c.2", "tx", SDMA_FILTER_PARAM(29) },
271	{ "omap_i2c.2", "rx", SDMA_FILTER_PARAM(30) },
272	{ "omap-mcbsp.1", "tx", SDMA_FILTER_PARAM(31) },
273	{ "omap-mcbsp.1", "rx", SDMA_FILTER_PARAM(32) },
274	{ "omap-mcbsp.2", "tx", SDMA_FILTER_PARAM(33) },
275	{ "omap-mcbsp.2", "rx", SDMA_FILTER_PARAM(34) },
276	{ "omap2_mcspi.0", "tx0", SDMA_FILTER_PARAM(35) },
277	{ "omap2_mcspi.0", "rx0", SDMA_FILTER_PARAM(36) },
278	{ "omap2_mcspi.0", "tx1", SDMA_FILTER_PARAM(37) },
279	{ "omap2_mcspi.0", "rx1", SDMA_FILTER_PARAM(38) },
280	{ "omap2_mcspi.0", "tx2", SDMA_FILTER_PARAM(39) },
281	{ "omap2_mcspi.0", "rx2", SDMA_FILTER_PARAM(40) },
282	{ "omap2_mcspi.0", "tx3", SDMA_FILTER_PARAM(41) },
283	{ "omap2_mcspi.0", "rx3", SDMA_FILTER_PARAM(42) },
284	{ "omap2_mcspi.1", "tx0", SDMA_FILTER_PARAM(43) },
285	{ "omap2_mcspi.1", "rx0", SDMA_FILTER_PARAM(44) },
286	{ "omap2_mcspi.1", "tx1", SDMA_FILTER_PARAM(45) },
287	{ "omap2_mcspi.1", "rx1", SDMA_FILTER_PARAM(46) },
288	{ "omap_hsmmc.1", "tx", SDMA_FILTER_PARAM(47) },
289	{ "omap_hsmmc.1", "rx", SDMA_FILTER_PARAM(48) },
290	{ "omap_uart.0", "tx", SDMA_FILTER_PARAM(49) },
291	{ "omap_uart.0", "rx", SDMA_FILTER_PARAM(50) },
292	{ "omap_uart.1", "tx", SDMA_FILTER_PARAM(51) },
293	{ "omap_uart.1", "rx", SDMA_FILTER_PARAM(52) },
294	{ "omap_uart.2", "tx", SDMA_FILTER_PARAM(53) },
295	{ "omap_uart.2", "rx", SDMA_FILTER_PARAM(54) },
296	{ "omap_hsmmc.0", "tx", SDMA_FILTER_PARAM(61) },
297	{ "omap_hsmmc.0", "rx", SDMA_FILTER_PARAM(62) },
298	{ "omap-aes", "tx", SDMA_FILTER_PARAM(65) },
299	{ "omap-aes", "rx", SDMA_FILTER_PARAM(66) },
300	{ "omap-sham", "rx", SDMA_FILTER_PARAM(69) },
301	{ "omap2_mcspi.3", "tx0", SDMA_FILTER_PARAM(70) },
302	{ "omap2_mcspi.3", "rx0", SDMA_FILTER_PARAM(71) },
303	{ "omap_hsmmc.2", "tx", SDMA_FILTER_PARAM(77) },
304	{ "omap_hsmmc.2", "rx", SDMA_FILTER_PARAM(78) },
305	{ "omap_uart.3", "tx", SDMA_FILTER_PARAM(81) },
306	{ "omap_uart.3", "rx", SDMA_FILTER_PARAM(82) },
307	};
308
34a378fc	309	static struct omap_system_dma_plat_info dma_plat_info __initdata = {
596c471b RK	310	.reg_map = reg_map,
596c471b RK	311	.channel_stride = 0x60,
34a378fc RK	312	.show_dma_caps = omap2_show_dma_caps,
	313	.clear_dma = omap2_clear_dma,
	314	.dma_write = dma_write,
	315	.dma_read = dma_read,
	316	};
	317
596c471b RK	318	static struct platform_device_info omap_dma_dev_info = {
	319	.name = "omap-dma-engine",
	320	.id = -1,
	321	.dma_mask = DMA_BIT_MASK(32),
	322	};
	323
59de3cf1 MK	324	/* One time initializations */
	325	static int __init omap2_system_dma_init_dev(struct omap_hwmod oh, void unused)
	326	{
3528c58e	327	struct platform_device *pdev;
34a378fc RK	328	struct omap_system_dma_plat_info p;
34a378fc RK	329	struct omap_dma_dev_attr *d;
f31cc962	330	struct resource *mem;
59de3cf1 MK	331	char *name = "omap_dma_system";
59de3cf1 MK	332
34a378fc RK	333	p = dma_plat_info;
	334	p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
	335	p.errata = configure_dma_errata();
f31cc962	336
731ec4d8 PU	337	if (!of_have_populated_dt()) {
	338	if (soc_is_omap24xx()) {
	339	p.slave_map = omap24xx_sdma_map;
	340	p.slavecnt = ARRAY_SIZE(omap24xx_sdma_map);
	341	} else if (soc_is_omap34xx() \|\| soc_is_omap3630()) {
	342	p.slave_map = omap3xxx_sdma_map;
	343	p.slavecnt = ARRAY_SIZE(omap3xxx_sdma_map);
	344	} else {
	345	pr_err("%s: The legacy DMA map is not provided!\n",
	346	__func__);
	347	return -ENODEV;
	348	}
	349	}
	350
34a378fc	351	pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
3528c58e	352	if (IS_ERR(pdev)) {
25985edc	353	pr_err("%s: Can't build omap_device for %s:%s.\n",
59de3cf1	354	__func__, name, oh->name);
3528c58e	355	return PTR_ERR(pdev);
59de3cf1 MK	356	}
59de3cf1 MK	357
596c471b RK	358	omap_dma_dev_info.res = pdev->resource;
	359	omap_dma_dev_info.num_res = pdev->num_resources;
	360
3528c58e	361	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
f31cc962	362	if (!mem) {
3528c58e	363	dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
f31cc962 MK	364	return -EINVAL;
f31cc962 MK	365	}
596c471b	366
f31cc962 MK	367	dma_base = ioremap(mem->start, resource_size(mem));
f31cc962 MK	368	if (!dma_base) {
3528c58e	369	dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
f31cc962 MK	370	return -ENOMEM;
	371	}
	372
	373	d = oh->dev_attr;
f6d5e079	374
82809601 TL	375	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
	376	d->dev_caps \|= HS_CHANNELS_RESERVED;
	377
76be4a54 NM	378	if (platform_get_irq_byname(pdev, "0") < 0)
	379	d->dev_caps \|= DMA_ENGINE_HANDLE_IRQ;
	380
f6d5e079 S	381	/* Check the capabilities register for descriptor loading feature */
	382	if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
	383	dma_common_ch_end = CCDN;
	384	else
	385	dma_common_ch_end = CCFN;
	386
59de3cf1 MK	387	return 0;
	388	}
	389
	390	static int __init omap2_system_dma_init(void)
	391	{
be1f9481 TL	392	struct platform_device *pdev;
	393	int res;
	394
	395	res = omap_hwmod_for_each_by_class("dma",
59de3cf1	396	omap2_system_dma_init_dev, NULL);
be1f9481 TL	397	if (res)
	398	return res;
	399
8d30662a JH	400	if (of_have_populated_dt())
	401	return res;
	402
be1f9481 TL	403	pdev = platform_device_register_full(&omap_dma_dev_info);
	404	if (IS_ERR(pdev))
	405	return PTR_ERR(pdev);
	406
	407	return res;
59de3cf1	408	}
b76c8b19	409	omap_arch_initcall(omap2_system_dma_init);