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omap: headers: Create headers necessary for compile under mach-omap1 and mach-omap2
[linux-2.6-block.git] / arch / arm / mach-omap2 / clock34xx.c
CommitLineData
02e19a96
PW		 1/*
2 * OMAP3-specific clock framework functions
3 *
542313cc 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
3c82e229 5 * Copyright (C) 2007-2009 Nokia Corporation
02e19a96
PW		 6 *
7 * Written by Paul Walmsley
542313cc 8 * Testing and integration fixes by Jouni Högander
02e19a96
PW		 9 *
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17#undef DEBUG
18
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/device.h>
22#include <linux/list.h>
23#include <linux/errno.h>
24#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/io.h>
542313cc 27#include <linux/limits.h>
fbd3bdb2 28#include <linux/bitops.h>
02e19a96 29
11b66383 30#include <mach/cpu.h>
a09e64fb
RK		 31#include <mach/clock.h>
32#include <mach/sram.h>
02e19a96 33#include <asm/div64.h>
44dc9d02 34#include <asm/clkdev.h>
02e19a96 35
f8de9b2c 36#include <mach/sdrc.h>
02e19a96 37#include "clock.h"
02e19a96
PW		 38#include "prm.h"
39#include "prm-regbits-34xx.h"
40#include "cm.h"
41#include "cm-regbits-34xx.h"
42
548d8495
RK		 43static const struct clkops clkops_noncore_dpll_ops;
44
3c82e229
PW		 45static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
46 void __iomem **idlest_reg,
47 u8 *idlest_bit);
48static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
49 void __iomem **idlest_reg,
50 u8 *idlest_bit);
51static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
52 void __iomem **idlest_reg,
53 u8 *idlest_bit);
54
55static const struct clkops clkops_omap3430es2_ssi_wait = {
56 .enable = omap2_dflt_clk_enable,
57 .disable = omap2_dflt_clk_disable,
58 .find_idlest = omap3430es2_clk_ssi_find_idlest,
59 .find_companion = omap2_clk_dflt_find_companion,
60};
61
62static const struct clkops clkops_omap3430es2_hsotgusb_wait = {
63 .enable = omap2_dflt_clk_enable,
64 .disable = omap2_dflt_clk_disable,
65 .find_idlest = omap3430es2_clk_hsotgusb_find_idlest,
66 .find_companion = omap2_clk_dflt_find_companion,
67};
68
69static const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
70 .enable = omap2_dflt_clk_enable,
71 .disable = omap2_dflt_clk_disable,
72 .find_idlest = omap3430es2_clk_dss_usbhost_find_idlest,
73 .find_companion = omap2_clk_dflt_find_companion,
74};
75
548d8495
RK		 76#include "clock34xx.h"
77
44dc9d02
RK		 78struct omap_clk {
79 u32 cpu;
80 struct clk_lookup lk;
81};
82
83#define CLK(dev, con, ck, cp) \
84 { \
85 .cpu = cp, \
86 .lk = { \
87 .dev_id = dev, \
88 .con_id = con, \
89 .clk = ck, \
90 }, \
91 }
92
93#define CK_343X (1 << 0)
94#define CK_3430ES1 (1 << 1)
95#define CK_3430ES2 (1 << 2)
96
97static struct omap_clk omap34xx_clks[] = {
98 CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X),
99 CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X),
100 CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X),
101 CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2),
102 CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X),
103 CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X),
104 CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X),
105 CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X),
106 CLK(NULL, "sys_ck", &sys_ck, CK_343X),
107 CLK(NULL, "sys_altclk", &sys_altclk, CK_343X),
108 CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X),
109 CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X),
110 CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X),
111 CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X),
112 CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X),
113 CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X),
114 CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X),
115 CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X),
116 CLK(NULL, "core_ck", &core_ck, CK_343X),
117 CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X),
118 CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X),
119 CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X),
120 CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X),
121 CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X),
122 CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X),
123 CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X),
124 CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X),
125 CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X),
126 CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X),
127 CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X),
44dc9d02
RK		 128 CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X),
129 CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X),
130 CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X),
131 CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X),
132 CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X),
133 CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X),
134 CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X),
135 CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X),
136 CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X),
137 CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X),
138 CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X),
139 CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X),
140 CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X),
141 CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X),
142 CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2),
143 CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2),
44dc9d02
RK		 144 CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X),
145 CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X),
146 CLK(NULL, "corex2_fck", &corex2_fck, CK_343X),
147 CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X),
148 CLK(NULL, "mpu_ck", &mpu_ck, CK_343X),
149 CLK(NULL, "arm_fck", &arm_fck, CK_343X),
150 CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X),
151 CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X),
152 CLK(NULL, "iva2_ck", &iva2_ck, CK_343X),
153 CLK(NULL, "l3_ick", &l3_ick, CK_343X),
154 CLK(NULL, "l4_ick", &l4_ick, CK_343X),
155 CLK(NULL, "rm_ick", &rm_ick, CK_343X),
156 CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1),
157 CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1),
158 CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1),
159 CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1),
160 CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1),
161 CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2),
162 CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2),
163 CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1),
8111b221
KH		 164 CLK(NULL, "modem_fck", &modem_fck, CK_343X),
165 CLK(NULL, "sad2d_ick", &sad2d_ick, CK_343X),
166 CLK(NULL, "mad2d_ick", &mad2d_ick, CK_343X),
44dc9d02
RK		 167 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X),
168 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X),
169 CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2),
170 CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2),
171 CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2),
172 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X),
6f7607cc
RK		 173 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2),
174 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X),
44dc9d02 175 CLK(NULL, "mspro_fck", &mspro_fck, CK_343X),
6f7607cc 176 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X),
1d14de08
RK		 177 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X),
178 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X),
179 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X),
b820ce4e
RK		 180 CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X),
181 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X),
44dc9d02 182 CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X),
1b5715ec
RK		 183 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X),
184 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X),
185 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X),
186 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X),
44dc9d02
RK		 187 CLK(NULL, "uart2_fck", &uart2_fck, CK_343X),
188 CLK(NULL, "uart1_fck", &uart1_fck, CK_343X),
189 CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
190 CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X),
cc51c9d4 191 CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X),
3c82e229
PW		 192 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
193 CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2),
194 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
195 CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es2, CK_3430ES2),
44dc9d02 196 CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
3c82e229
PW		 197 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es1, CK_3430ES1),
198 CLK("musb_hdrc", "ick", &hsotgusb_ick_3430es2, CK_3430ES2),
44dc9d02
RK		 199 CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
200 CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
201 CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
202 CLK(NULL, "pka_ick", &pka_ick, CK_343X),
203 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X),
204 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2),
6f7607cc 205 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2),
44dc9d02
RK		 206 CLK(NULL, "icr_ick", &icr_ick, CK_343X),
207 CLK(NULL, "aes2_ick", &aes2_ick, CK_343X),
208 CLK(NULL, "sha12_ick", &sha12_ick, CK_343X),
209 CLK(NULL, "des2_ick", &des2_ick, CK_343X),
6f7607cc
RK		 210 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X),
211 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X),
44dc9d02 212 CLK(NULL, "mspro_ick", &mspro_ick, CK_343X),
cc51c9d4 213 CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X),
1b5715ec
RK		 214 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X),
215 CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X),
216 CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X),
217 CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X),
1d14de08
RK		 218 CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X),
219 CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X),
220 CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X),
44dc9d02
RK		 221 CLK(NULL, "uart2_ick", &uart2_ick, CK_343X),
222 CLK(NULL, "uart1_ick", &uart1_ick, CK_343X),
223 CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X),
224 CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X),
b820ce4e
RK		 225 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X),
226 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X),
44dc9d02
RK		 227 CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1),
228 CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X),
229 CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X),
230 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X),
3c82e229
PW		 231 CLK(NULL, "ssi_ick", &ssi_ick_3430es1, CK_3430ES1),
232 CLK(NULL, "ssi_ick", &ssi_ick_3430es2, CK_3430ES2),
44dc9d02
RK		 233 CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1),
234 CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X),
235 CLK(NULL, "aes1_ick", &aes1_ick, CK_343X),
eeec7c8d 236 CLK("omap_rng", "ick", &rng_ick, CK_343X),
44dc9d02
RK		 237 CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
238 CLK(NULL, "des1_ick", &des1_ick, CK_343X),
3c82e229
PW		 239 CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
240 CLK("omapfb", "dss1_fck", &dss1_alwon_fck_3430es2, CK_3430ES2),
005187ee
TL		 241 CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
242 CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
243 CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
3c82e229
PW		 244 CLK("omapfb", "ick", &dss_ick_3430es1, CK_3430ES1),
245 CLK("omapfb", "ick", &dss_ick_3430es2, CK_3430ES2),
44dc9d02
RK		 246 CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
247 CLK(NULL, "cam_ick", &cam_ick, CK_343X),
6c8fe0b9 248 CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
44dc9d02
RK		 249 CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2),
250 CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2),
251 CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2),
44dc9d02
RK		 252 CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2),
253 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X),
254 CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X),
255 CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X),
39a80c7f 256 CLK("omap_wdt", "fck", &wdt2_fck, CK_343X),
44dc9d02
RK		 257 CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X),
258 CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2),
39a80c7f 259 CLK("omap_wdt", "ick", &wdt2_ick, CK_343X),
44dc9d02
RK		 260 CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X),
261 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X),
262 CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X),
263 CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X),
264 CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X),
265 CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X),
266 CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X),
267 CLK(NULL, "uart3_fck", &uart3_fck, CK_343X),
268 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X),
269 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X),
270 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X),
271 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X),
272 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X),
273 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X),
274 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X),
275 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X),
276 CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X),
277 CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X),
278 CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X),
279 CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X),
280 CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X),
281 CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X),
282 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X),
283 CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X),
284 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X),
285 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X),
286 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X),
287 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X),
288 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X),
289 CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X),
290 CLK(NULL, "uart3_ick", &uart3_ick, CK_343X),
291 CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X),
292 CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X),
293 CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X),
294 CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X),
295 CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X),
296 CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X),
297 CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X),
298 CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X),
b820ce4e
RK		 299 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X),
300 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X),
301 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X),
302 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X),
303 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X),
304 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X),
44dc9d02
RK		 305 CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X),
306 CLK(NULL, "pclk_fck", &pclk_fck, CK_343X),
307 CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X),
308 CLK(NULL, "atclk_fck", &atclk_fck, CK_343X),
309 CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X),
310 CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X),
311 CLK(NULL, "sr1_fck", &sr1_fck, CK_343X),
312 CLK(NULL, "sr2_fck", &sr2_fck, CK_343X),
313 CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X),
314 CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X),
315 CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X),
316 CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X),
317};
318
542313cc
PW		 319/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
320#define DPLL_AUTOIDLE_DISABLE 0x0
321#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
322
323#define MAX_DPLL_WAIT_TRIES 1000000
02e19a96 324
4519c2bf
PW		 325#define MIN_SDRC_DLL_LOCK_FREQ 83000000
326
c9812d04
PW		 327#define CYCLES_PER_MHZ 1000000
328
329/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
330#define SDRC_MPURATE_SCALE 8
331
332/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
333#define SDRC_MPURATE_BASE_SHIFT 9
334
335/*
336 * SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
337 * 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
338 */
339#define SDRC_MPURATE_LOOPS 96
340
7a66a39b
RN		 341/*
342 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
343 * that are sourced by DPLL5, and both of these require this clock
344 * to be at 120 MHz for proper operation.
345 */
346#define DPLL5_FREQ_FOR_USBHOST 120000000
347
3c82e229
PW		 348/**
349 * omap3430es2_clk_ssi_find_idlest - return CM_IDLEST info for SSI
350 * @clk: struct clk * being enabled
351 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
352 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
353 *
354 * The OMAP3430ES2 SSI target CM_IDLEST bit is at a different shift
355 * from the CM_{I,F}CLKEN bit. Pass back the correct info via
356 * @idlest_reg and @idlest_bit. No return value.
357 */
358static void omap3430es2_clk_ssi_find_idlest(struct clk *clk,
359 void __iomem **idlest_reg,
360 u8 *idlest_bit)
361{
362 u32 r;
363
364 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
365 *idlest_reg = (__force void __iomem *)r;
366 *idlest_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT;
367}
368
369/**
370 * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
371 * @clk: struct clk * being enabled
372 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
373 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
374 *
375 * Some OMAP modules on OMAP3 ES2+ chips have both initiator and
376 * target IDLEST bits. For our purposes, we are concerned with the
377 * target IDLEST bits, which exist at a different bit position than
378 * the *CLKEN bit position for these modules (DSS and USBHOST) (The
379 * default find_idlest code assumes that they are at the same
380 * position.) No return value.
381 */
382static void omap3430es2_clk_dss_usbhost_find_idlest(struct clk *clk,
383 void __iomem **idlest_reg,
384 u8 *idlest_bit)
385{
386 u32 r;
387
388 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
389 *idlest_reg = (__force void __iomem *)r;
390 /* USBHOST_IDLE has same shift */
391 *idlest_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT;
392}
393
394/**
395 * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
396 * @clk: struct clk * being enabled
397 * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into
398 * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into
399 *
400 * The OMAP3430ES2 HSOTGUSB target CM_IDLEST bit is at a different
401 * shift from the CM_{I,F}CLKEN bit. Pass back the correct info via
402 * @idlest_reg and @idlest_bit. No return value.
403 */
404static void omap3430es2_clk_hsotgusb_find_idlest(struct clk *clk,
405 void __iomem **idlest_reg,
406 u8 *idlest_bit)
407{
408 u32 r;
409
410 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
411 *idlest_reg = (__force void __iomem *)r;
412 *idlest_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT;
413}
414
02e19a96
PW		 415/**
416 * omap3_dpll_recalc - recalculate DPLL rate
417 * @clk: DPLL struct clk
418 *
419 * Recalculate and propagate the DPLL rate.
420 */
8b9dbc16 421static unsigned long omap3_dpll_recalc(struct clk *clk)
02e19a96 422{
8b9dbc16 423 return omap2_get_dpll_rate(clk);
02e19a96
PW		 424}
425
542313cc
PW		 426/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
427static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
428{
429 const struct dpll_data *dd;
ad67ef68 430 u32 v;
542313cc
PW		 431
432 dd = clk->dpll_data;
433
ad67ef68
PW		 434 v = __raw_readl(dd->control_reg);
435 v &= ~dd->enable_mask;
436 v |= clken_bits << __ffs(dd->enable_mask);
437 __raw_writel(v, dd->control_reg);
542313cc
PW		 438}
439
440/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
441static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
442{
443 const struct dpll_data *dd;
444 int i = 0;
445 int ret = -EINVAL;
542313cc
PW		 446
447 dd = clk->dpll_data;
448
c1bd7aaf 449 state <<= __ffs(dd->idlest_mask);
542313cc 450
c1bd7aaf 451 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
542313cc
PW		 452 i < MAX_DPLL_WAIT_TRIES) {
453 i++;
454 udelay(1);
455 }
456
457 if (i == MAX_DPLL_WAIT_TRIES) {
458 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
459 clk->name, (state) ? "locked" : "bypassed");
460 } else {
461 pr_debug("clock: %s transition to '%s' in %d loops\n",
462 clk->name, (state) ? "locked" : "bypassed", i);
463
464 ret = 0;
465 }
466
467 return ret;
468}
469
16c90f02
PW		 470/* From 3430 TRM ES2 4.7.6.2 */
471static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
472{
473 unsigned long fint;
474 u16 f = 0;
475
c0bf3132 476 fint = clk->dpll_data->clk_ref->rate / (n + 1);
16c90f02
PW		 477
478 pr_debug("clock: fint is %lu\n", fint);
479
480 if (fint >= 750000 && fint <= 1000000)
481 f = 0x3;
482 else if (fint > 1000000 && fint <= 1250000)
483 f = 0x4;
484 else if (fint > 1250000 && fint <= 1500000)
485 f = 0x5;
486 else if (fint > 1500000 && fint <= 1750000)
487 f = 0x6;
488 else if (fint > 1750000 && fint <= 2100000)
489 f = 0x7;
490 else if (fint > 7500000 && fint <= 10000000)
491 f = 0xB;
492 else if (fint > 10000000 && fint <= 12500000)
493 f = 0xC;
494 else if (fint > 12500000 && fint <= 15000000)
495 f = 0xD;
496 else if (fint > 15000000 && fint <= 17500000)
497 f = 0xE;
498 else if (fint > 17500000 && fint <= 21000000)
499 f = 0xF;
500 else
501 pr_debug("clock: unknown freqsel setting for %d\n", n);
502
503 return f;
504}
505
542313cc
PW		 506/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
507
508/*
509 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
510 * @clk: pointer to a DPLL struct clk
511 *
512 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
513 * readiness before returning. Will save and restore the DPLL's
514 * autoidle state across the enable, per the CDP code. If the DPLL
515 * locked successfully, return 0; if the DPLL did not lock in the time
516 * allotted, or DPLL3 was passed in, return -EINVAL.
517 */
518static int _omap3_noncore_dpll_lock(struct clk *clk)
519{
520 u8 ai;
521 int r;
522
523 if (clk == &dpll3_ck)
524 return -EINVAL;
525
526 pr_debug("clock: locking DPLL %s\n", clk->name);
527
528 ai = omap3_dpll_autoidle_read(clk);
529
416db864
PW		 530 omap3_dpll_deny_idle(clk);
531
542313cc
PW		 532 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
533
416db864
PW		 534 r = _omap3_wait_dpll_status(clk, 1);
535
536 if (ai)
542313cc 537 omap3_dpll_allow_idle(clk);
542313cc
PW		 538
539 return r;
540}
541
542/*
c0bf3132 543 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
542313cc
PW		 544 * @clk: pointer to a DPLL struct clk
545 *
546 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
547 * bypass mode, the DPLL's rate is set equal to its parent clock's
548 * rate. Waits for the DPLL to report readiness before returning.
549 * Will save and restore the DPLL's autoidle state across the enable,
550 * per the CDP code. If the DPLL entered bypass mode successfully,
551 * return 0; if the DPLL did not enter bypass in the time allotted, or
552 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
553 * return -EINVAL.
554 */
555static int _omap3_noncore_dpll_bypass(struct clk *clk)
556{
557 int r;
558 u8 ai;
559
560 if (clk == &dpll3_ck)
561 return -EINVAL;
562
563 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
564 return -EINVAL;
565
566 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
567 clk->name);
568
569 ai = omap3_dpll_autoidle_read(clk);
570
571 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
572
573 r = _omap3_wait_dpll_status(clk, 0);
574
575 if (ai)
576 omap3_dpll_allow_idle(clk);
577 else
578 omap3_dpll_deny_idle(clk);
579
580 return r;
581}
582
583/*
584 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
585 * @clk: pointer to a DPLL struct clk
586 *
587 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
588 * restore the DPLL's autoidle state across the stop, per the CDP
589 * code. If DPLL3 was passed in, or the DPLL does not support
590 * low-power stop, return -EINVAL; otherwise, return 0.
591 */
592static int _omap3_noncore_dpll_stop(struct clk *clk)
593{
594 u8 ai;
595
596 if (clk == &dpll3_ck)
597 return -EINVAL;
598
599 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
600 return -EINVAL;
601
602 pr_debug("clock: stopping DPLL %s\n", clk->name);
603
604 ai = omap3_dpll_autoidle_read(clk);
605
606 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
607
608 if (ai)
609 omap3_dpll_allow_idle(clk);
610 else
611 omap3_dpll_deny_idle(clk);
612
613 return 0;
614}
615
616/**
617 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
618 * @clk: pointer to a DPLL struct clk
619 *
620 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
621 * The choice of modes depends on the DPLL's programmed rate: if it is
622 * the same as the DPLL's parent clock, it will enter bypass;
623 * otherwise, it will enter lock. This code will wait for the DPLL to
624 * indicate readiness before returning, unless the DPLL takes too long
625 * to enter the target state. Intended to be used as the struct clk's
626 * enable function. If DPLL3 was passed in, or the DPLL does not
627 * support low-power stop, or if the DPLL took too long to enter
628 * bypass or lock, return -EINVAL; otherwise, return 0.
629 */
630static int omap3_noncore_dpll_enable(struct clk *clk)
631{
632 int r;
c0bf3132 633 struct dpll_data *dd;
542313cc
PW		 634
635 if (clk == &dpll3_ck)
636 return -EINVAL;
637
c0bf3132
RK		 638 dd = clk->dpll_data;
639 if (!dd)
640 return -EINVAL;
641
642 if (clk->rate == dd->clk_bypass->rate) {
643 WARN_ON(clk->parent != dd->clk_bypass);
542313cc 644 r = _omap3_noncore_dpll_bypass(clk);
c0bf3132
RK		 645 } else {
646 WARN_ON(clk->parent != dd->clk_ref);
542313cc 647 r = _omap3_noncore_dpll_lock(clk);
c0bf3132
RK		 648 }
649 /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */
650 if (!r)
651 clk->rate = omap2_get_dpll_rate(clk);
542313cc
PW		 652
653 return r;
654}
655
656/**
657 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
658 * @clk: pointer to a DPLL struct clk
659 *
660 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
661 * The choice of modes depends on the DPLL's programmed rate: if it is
662 * the same as the DPLL's parent clock, it will enter bypass;
663 * otherwise, it will enter lock. This code will wait for the DPLL to
664 * indicate readiness before returning, unless the DPLL takes too long
665 * to enter the target state. Intended to be used as the struct clk's
666 * enable function. If DPLL3 was passed in, or the DPLL does not
667 * support low-power stop, or if the DPLL took too long to enter
668 * bypass or lock, return -EINVAL; otherwise, return 0.
669 */
670static void omap3_noncore_dpll_disable(struct clk *clk)
671{
672 if (clk == &dpll3_ck)
673 return;
674
675 _omap3_noncore_dpll_stop(clk);
676}
677
16c90f02
PW		 678
679/* Non-CORE DPLL rate set code */
680
681/*
682 * omap3_noncore_dpll_program - set non-core DPLL M,N values directly
683 * @clk: struct clk * of DPLL to set
684 * @m: DPLL multiplier to set
685 * @n: DPLL divider to set
686 * @freqsel: FREQSEL value to set
687 *
688 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
689 * lock.. Returns -EINVAL upon error, or 0 upon success.
690 */
691static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
692{
693 struct dpll_data *dd = clk->dpll_data;
694 u32 v;
695
696 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
697 _omap3_noncore_dpll_bypass(clk);
698
f0587b63
PW		 699 /* Set jitter correction */
700 v = __raw_readl(dd->control_reg);
701 v &= ~dd->freqsel_mask;
702 v |= freqsel << __ffs(dd->freqsel_mask);
703 __raw_writel(v, dd->control_reg);
704
705 /* Set DPLL multiplier, divider */
16c90f02
PW		 706 v = __raw_readl(dd->mult_div1_reg);
707 v &= ~(dd->mult_mask | dd->div1_mask);
16c90f02 708 v |= m << __ffs(dd->mult_mask);
f0587b63 709 v |= (n - 1) << __ffs(dd->div1_mask);
16c90f02
PW		 710 __raw_writel(v, dd->mult_div1_reg);
711
712 /* We let the clock framework set the other output dividers later */
713
714 /* REVISIT: Set ramp-up delay? */
715
716 _omap3_noncore_dpll_lock(clk);
717
718 return 0;
719}
720
721/**
722 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
723 * @clk: struct clk * of DPLL to set
724 * @rate: rounded target rate
725 *
c0bf3132
RK		 726 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
727 * low-power bypass, and the target rate is the bypass source clock
728 * rate, then configure the DPLL for bypass. Otherwise, round the
729 * target rate if it hasn't been done already, then program and lock
730 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
16c90f02
PW		 731 */
732static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
733{
c0bf3132 734 struct clk *new_parent = NULL;
16c90f02
PW		 735 u16 freqsel;
736 struct dpll_data *dd;
c0bf3132 737 int ret;
16c90f02
PW		 738
739 if (!clk || !rate)
740 return -EINVAL;
741
742 dd = clk->dpll_data;
743 if (!dd)
744 return -EINVAL;
745
746 if (rate == omap2_get_dpll_rate(clk))
747 return 0;
748
c0bf3132
RK		 749 /*
750 * Ensure both the bypass and ref clocks are enabled prior to
751 * doing anything; we need the bypass clock running to reprogram
752 * the DPLL.
753 */
754 omap2_clk_enable(dd->clk_bypass);
755 omap2_clk_enable(dd->clk_ref);
16c90f02 756
c0bf3132
RK		 757 if (dd->clk_bypass->rate == rate &&
758 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
759 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
760
761 ret = _omap3_noncore_dpll_bypass(clk);
762 if (!ret)
763 new_parent = dd->clk_bypass;
764 } else {
765 if (dd->last_rounded_rate != rate)
766 omap2_dpll_round_rate(clk, rate);
16c90f02 767
c0bf3132
RK		 768 if (dd->last_rounded_rate == 0)
769 return -EINVAL;
16c90f02 770
c0bf3132
RK		 771 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n);
772 if (!freqsel)
773 WARN_ON(1);
774
775 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
776 clk->name, rate);
777
778 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
779 dd->last_rounded_n, freqsel);
780 if (!ret)
781 new_parent = dd->clk_ref;
782 }
783 if (!ret) {
784 /*
785 * Switch the parent clock in the heirarchy, and make sure
786 * that the new parent's usecount is correct. Note: we
787 * enable the new parent before disabling the old to avoid
788 * any unnecessary hardware disable->enable transitions.
789 */
790 if (clk->usecount) {
791 omap2_clk_enable(new_parent);
792 omap2_clk_disable(clk->parent);
793 }
794 clk_reparent(clk, new_parent);
795 clk->rate = rate;
796 }
797 omap2_clk_disable(dd->clk_ref);
798 omap2_clk_disable(dd->clk_bypass);
16c90f02 799
16c90f02
PW		 800 return 0;
801}
802
803static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
804{
805 /*
806 * According to the 12-5 CDP code from TI, "Limitation 2.5"
807 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
808 * on DPLL4.
809 */
810 if (omap_rev() == OMAP3430_REV_ES1_0) {
811 printk(KERN_ERR "clock: DPLL4 cannot change rate due to "
812 "silicon 'Limitation 2.5' on 3430ES1.\n");
813 return -EINVAL;
814 }
815 return omap3_noncore_dpll_set_rate(clk, rate);
816}
817
0eafd472
PW		 818
819/*
820 * CORE DPLL (DPLL3) rate programming functions
821 *
822 * These call into SRAM code to do the actual CM writes, since the SDRAM
823 * is clocked from DPLL3.
824 */
825
826/**
827 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
828 * @clk: struct clk * of DPLL to set
829 * @rate: rounded target rate
830 *
831 * Program the DPLL M2 divider with the rounded target rate. Returns
832 * -EINVAL upon error, or 0 upon success.
833 */
834static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
835{
836 u32 new_div = 0;
4519c2bf 837 u32 unlock_dll = 0;
c9812d04
PW		 838 u32 c;
839 unsigned long validrate, sdrcrate, mpurate;
58cda884
JP		 840 struct omap_sdrc_params *sdrc_cs0;
841 struct omap_sdrc_params *sdrc_cs1;
842 int ret;
0eafd472
PW		 843
844 if (!clk || !rate)
845 return -EINVAL;
846
847 if (clk != &dpll3_m2_ck)
848 return -EINVAL;
849
0eafd472
PW		 850 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
851 if (validrate != rate)
852 return -EINVAL;
853
854 sdrcrate = sdrc_ick.rate;
855 if (rate > clk->rate)
3afec633 856 sdrcrate <<= ((rate / clk->rate) >> 1);
0eafd472 857 else
3afec633 858 sdrcrate >>= ((clk->rate / rate) >> 1);
0eafd472 859
58cda884
JP		 860 ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
861 if (ret)
0eafd472
PW		 862 return -EINVAL;
863
4519c2bf
PW		 864 if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
865 pr_debug("clock: will unlock SDRC DLL\n");
866 unlock_dll = 1;
867 }
868
c9812d04
PW		 869 /*
870 * XXX This only needs to be done when the CPU frequency changes
871 */
872 mpurate = arm_fck.rate / CYCLES_PER_MHZ;
873 c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
874 c += 1; /* for safety */
875 c *= SDRC_MPURATE_LOOPS;
876 c >>= SDRC_MPURATE_SCALE;
877 if (c == 0)
878 c = 1;
879
b7aee4bf
PW		 880 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
881 validrate);
58cda884
JP		 882 pr_debug("clock: SDRC CS0 timing params used:"
883 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
884 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
885 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
886 if (sdrc_cs1)
887 pr_debug("clock: SDRC CS1 timing params used: "
888 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
889 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
890 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
891
892 if (sdrc_cs1)
893 omap3_configure_core_dpll(
894 new_div, unlock_dll, c, rate > clk->rate,
895 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
896 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
897 sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
898 sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
899 else
900 omap3_configure_core_dpll(
901 new_div, unlock_dll, c, rate > clk->rate,
902 sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
903 sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
904 0, 0, 0, 0);
0eafd472 905
0eafd472
PW		 906 return 0;
907}
908
909
548d8495
RK		 910static const struct clkops clkops_noncore_dpll_ops = {
911 .enable = &omap3_noncore_dpll_enable,
912 .disable = &omap3_noncore_dpll_disable,
913};
914
16c90f02
PW		 915/* DPLL autoidle read/set code */
916
917
542313cc
PW		 918/**
919 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
920 * @clk: struct clk * of the DPLL to read
921 *
922 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
923 * -EINVAL if passed a null pointer or if the struct clk does not
924 * appear to refer to a DPLL.
925 */
926static u32 omap3_dpll_autoidle_read(struct clk *clk)
927{
928 const struct dpll_data *dd;
929 u32 v;
930
931 if (!clk || !clk->dpll_data)
932 return -EINVAL;
933
934 dd = clk->dpll_data;
935
ad67ef68 936 v = __raw_readl(dd->autoidle_reg);
542313cc
PW		 937 v &= dd->autoidle_mask;
938 v >>= __ffs(dd->autoidle_mask);
939
940 return v;
941}
942
943/**
944 * omap3_dpll_allow_idle - enable DPLL autoidle bits
945 * @clk: struct clk * of the DPLL to operate on
946 *
947 * Enable DPLL automatic idle control. This automatic idle mode
948 * switching takes effect only when the DPLL is locked, at least on
949 * OMAP3430. The DPLL will enter low-power stop when its downstream
950 * clocks are gated. No return value.
951 */
952static void omap3_dpll_allow_idle(struct clk *clk)
953{
954 const struct dpll_data *dd;
ad67ef68 955 u32 v;
542313cc
PW		 956
957 if (!clk || !clk->dpll_data)
958 return;
959
960 dd = clk->dpll_data;
961
962 /*
963 * REVISIT: CORE DPLL can optionally enter low-power bypass
964 * by writing 0x5 instead of 0x1. Add some mechanism to
965 * optionally enter this mode.
966 */
ad67ef68
PW		 967 v = __raw_readl(dd->autoidle_reg);
968 v &= ~dd->autoidle_mask;
969 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
970 __raw_writel(v, dd->autoidle_reg);
542313cc
PW		 971}
972
973/**
974 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
975 * @clk: struct clk * of the DPLL to operate on
976 *
977 * Disable DPLL automatic idle control. No return value.
978 */
979static void omap3_dpll_deny_idle(struct clk *clk)
980{
981 const struct dpll_data *dd;
ad67ef68 982 u32 v;
542313cc
PW		 983
984 if (!clk || !clk->dpll_data)
985 return;
986
987 dd = clk->dpll_data;
988
ad67ef68
PW		 989 v = __raw_readl(dd->autoidle_reg);
990 v &= ~dd->autoidle_mask;
991 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
992 __raw_writel(v, dd->autoidle_reg);
542313cc
PW		 993}
994
995/* Clock control for DPLL outputs */
996
02e19a96
PW		 997/**
998 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
999 * @clk: DPLL output struct clk
1000 *
1001 * Using parent clock DPLL data, look up DPLL state. If locked, set our
1002 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
1003 */
8b9dbc16 1004static unsigned long omap3_clkoutx2_recalc(struct clk *clk)
02e19a96
PW		 1005{
1006 const struct dpll_data *dd;
8b9dbc16 1007 unsigned long rate;
02e19a96
PW		 1008 u32 v;
1009 struct clk *pclk;
1010
1011 /* Walk up the parents of clk, looking for a DPLL */
1012 pclk = clk->parent;
1013 while (pclk && !pclk->dpll_data)
1014 pclk = pclk->parent;
1015
1016 /* clk does not have a DPLL as a parent? */
1017 WARN_ON(!pclk);
1018
1019 dd = pclk->dpll_data;
1020
c0bf3132 1021 WARN_ON(!dd->enable_mask);
02e19a96
PW		 1022
1023 v = __raw_readl(dd->control_reg) & dd->enable_mask;
1024 v >>= __ffs(dd->enable_mask);
c0bf3132 1025 if (v != OMAP3XXX_EN_DPLL_LOCKED)
8b9dbc16 1026 rate = clk->parent->rate;
02e19a96 1027 else
8b9dbc16
RK		 1028 rate = clk->parent->rate * 2;
1029 return rate;
02e19a96
PW		 1030}
1031
542313cc
PW		 1032/* Common clock code */
1033
02e19a96
PW		 1034/*
1035 * As it is structured now, this will prevent an OMAP2/3 multiboot
1036 * kernel from compiling. This will need further attention.
1037 */
1038#if defined(CONFIG_ARCH_OMAP3)
1039
1040static struct clk_functions omap2_clk_functions = {
1041 .clk_enable = omap2_clk_enable,
1042 .clk_disable = omap2_clk_disable,
1043 .clk_round_rate = omap2_clk_round_rate,
1044 .clk_set_rate = omap2_clk_set_rate,
1045 .clk_set_parent = omap2_clk_set_parent,
1046 .clk_disable_unused = omap2_clk_disable_unused,
1047};
1048
1049/*
1050 * Set clocks for bypass mode for reboot to work.
1051 */
1052void omap2_clk_prepare_for_reboot(void)
1053{
1054 /* REVISIT: Not ready for 343x */
1055#if 0
1056 u32 rate;
1057
1058 if (vclk == NULL || sclk == NULL)
1059 return;
1060
1061 rate = clk_get_rate(sclk);
1062 clk_set_rate(vclk, rate);
1063#endif
1064}
1065
7a66a39b
RN		 1066static void omap3_clk_lock_dpll5(void)
1067{
1068 struct clk *dpll5_clk;
1069 struct clk *dpll5_m2_clk;
1070
1071 dpll5_clk = clk_get(NULL, "dpll5_ck");
1072 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
1073 clk_enable(dpll5_clk);
1074
1075 /* Enable autoidle to allow it to enter low power bypass */
1076 omap3_dpll_allow_idle(dpll5_clk);
1077
1078 /* Program dpll5_m2_clk divider for no division */
1079 dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
1080 clk_enable(dpll5_m2_clk);
1081 clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
1082
1083 clk_disable(dpll5_m2_clk);
1084 clk_disable(dpll5_clk);
1085 return;
1086}
1087
02e19a96
PW		 1088/* REVISIT: Move this init stuff out into clock.c */
1089
1090/*
1091 * Switch the MPU rate if specified on cmdline.
1092 * We cannot do this early until cmdline is parsed.
1093 */
1094static int __init omap2_clk_arch_init(void)
1095{
1096 if (!mpurate)
1097 return -EINVAL;
1098
1099 /* REVISIT: not yet ready for 343x */
11b66383
SP		 1100 if (clk_set_rate(&dpll1_ck, mpurate))
1101 printk(KERN_ERR "*** Unable to set MPU rate\n");
02e19a96
PW		 1102
1103 recalculate_root_clocks();
1104
11b66383 1105 printk(KERN_INFO "Switched to new clocking rate (Crystal/Core/MPU): "
02e19a96 1106 "%ld.%01ld/%ld/%ld MHz\n",
11b66383
SP		 1107 (osc_sys_ck.rate / 1000000), ((osc_sys_ck.rate / 100000) % 10),
1108 (core_ck.rate / 1000000), (arm_fck.rate / 1000000)) ;
1109
1110 calibrate_delay();
02e19a96
PW		 1111
1112 return 0;
1113}
1114arch_initcall(omap2_clk_arch_init);
1115
1116int __init omap2_clk_init(void)
1117{
1118 /* struct prcm_config *prcm; */
44dc9d02 1119 struct omap_clk *c;
02e19a96
PW		 1120 /* u32 clkrate; */
1121 u32 cpu_clkflg;
1122
02e19a96
PW		 1123 if (cpu_is_omap34xx()) {
1124 cpu_mask = RATE_IN_343X;
44dc9d02 1125 cpu_clkflg = CK_343X;
02e19a96
PW		 1126
1127 /*
1128 * Update this if there are further clock changes between ES2
1129 * and production parts
1130 */
84a34344 1131 if (omap_rev() == OMAP3430_REV_ES1_0) {
02e19a96 1132 /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
44dc9d02 1133 cpu_clkflg |= CK_3430ES1;
02e19a96
PW		 1134 } else {
1135 cpu_mask |= RATE_IN_3430ES2;
44dc9d02 1136 cpu_clkflg |= CK_3430ES2;
02e19a96
PW		 1137 }
1138 }
1139
1140 clk_init(&omap2_clk_functions);
1141
3f0a820c 1142 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
79716870 1143 clk_preinit(c->lk.clk);
3f0a820c 1144
44dc9d02
RK		 1145 for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
1146 if (c->cpu & cpu_clkflg) {
1147 clkdev_add(&c->lk);
1148 clk_register(c->lk.clk);
1149 omap2_init_clk_clkdm(c->lk.clk);
333943ba 1150 }
02e19a96
PW		 1151
1152 /* REVISIT: Not yet ready for OMAP3 */
1153#if 0
1154 /* Check the MPU rate set by bootloader */
1155 clkrate = omap2_get_dpll_rate_24xx(&dpll_ck);
1156 for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1157 if (!(prcm->flags & cpu_mask))
1158 continue;
1159 if (prcm->xtal_speed != sys_ck.rate)
1160 continue;
1161 if (prcm->dpll_speed <= clkrate)
1162 break;
1163 }
1164 curr_prcm_set = prcm;
1165#endif
1166
1167 recalculate_root_clocks();
1168
11b66383 1169 printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
02e19a96
PW		 1170 "%ld.%01ld/%ld/%ld MHz\n",
1171 (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3760d31f 1172 (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
02e19a96
PW		 1173
1174 /*
1175 * Only enable those clocks we will need, let the drivers
1176 * enable other clocks as necessary
1177 */
1178 clk_enable_init_clocks();
1179
7a66a39b
RN		 1180 /*
1181 * Lock DPLL5 and put it in autoidle.
1182 */
1183 if (omap_rev() >= OMAP3430_REV_ES2_0)
1184 omap3_clk_lock_dpll5();
1185
02e19a96
PW		 1186 /* Avoid sleeping during omap2_clk_prepare_for_reboot() */
1187 /* REVISIT: not yet ready for 343x */
1188#if 0
1189 vclk = clk_get(NULL, "virt_prcm_set");
1190 sclk = clk_get(NULL, "sys_ck");
1191#endif
1192 return 0;
1193}
1194
1195#endif
Linux 6.x block layer and io_uring tree(s)