[linux-2.6-block.git] / arch / arm / mach-mx3 / clock-imx35.c

/*
 * Copyright (C) 2009 by Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <asm/clkdev.h>

#include <mach/clock.h>
#include <mach/hardware.h>
#include <mach/common.h>

#define CCM_BASE	MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)

#define CCM_CCMR        0x00
#define CCM_PDR0        0x04
#define CCM_PDR1        0x08
#define CCM_PDR2        0x0C
#define CCM_PDR3        0x10
#define CCM_PDR4        0x14
#define CCM_RCSR        0x18
#define CCM_MPCTL       0x1C
#define CCM_PPCTL       0x20
#define CCM_ACMR        0x24
#define CCM_COSR        0x28
#define CCM_CGR0        0x2C
#define CCM_CGR1        0x30
#define CCM_CGR2        0x34
#define CCM_CGR3        0x38

#ifdef HAVE_SET_RATE_SUPPORT
static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
{
	u32 min_pre, temp_pre, old_err, err;

	min_pre = (div - 1) / maxpost + 1;
	old_err = 8;

	for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
		if (div > (temp_pre * maxpost))
			break;

		if (div < (temp_pre * temp_pre))
			continue;

		err = div % temp_pre;

		if (err == 0) {
			*pre = temp_pre;
			break;
		}

		err = temp_pre - err;

		if (err < old_err) {
			old_err = err;
			*pre = temp_pre;
		}
	}

	*post = (div + *pre - 1) / *pre;
}

/* get the best values for a 3-bit divider combined with a 6-bit divider */
static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post)
{
	if (div >= 512) {
		*pre = 8;
		*post = 64;
	} else if (div >= 64) {
		calc_dividers(div, pre, post, 64);
	} else if (div <= 8) {
		*pre = div;
		*post = 1;
	} else {
		*pre = 1;
		*post = div;
	}
}

/* get the best values for two cascaded 3-bit dividers */
static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
{
	if (div >= 64) {
		*pre = *post = 8;
	} else if (div > 8) {
		calc_dividers(div, pre, post, 8);
	} else {
		*pre = 1;
		*post = div;
	}
}
#endif

static unsigned long get_rate_mpll(void)
{
	ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL);

	return mxc_decode_pll(mpctl, 24000000);
}

static unsigned long get_rate_ppll(void)
{
	ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL);

	return mxc_decode_pll(ppctl, 24000000);
}

struct arm_ahb_div {
	unsigned char arm, ahb, sel;
};

static struct arm_ahb_div clk_consumer[] = {
	{ .arm = 1, .ahb = 4, .sel = 0},
	{ .arm = 1, .ahb = 3, .sel = 1},
	{ .arm = 2, .ahb = 2, .sel = 0},
	{ .arm = 0, .ahb = 0, .sel = 0},
	{ .arm = 0, .ahb = 0, .sel = 0},
	{ .arm = 0, .ahb = 0, .sel = 0},
	{ .arm = 4, .ahb = 1, .sel = 0},
	{ .arm = 1, .ahb = 5, .sel = 0},
	{ .arm = 1, .ahb = 8, .sel = 0},
	{ .arm = 1, .ahb = 6, .sel = 1},
	{ .arm = 2, .ahb = 4, .sel = 0},
	{ .arm = 0, .ahb = 0, .sel = 0},
	{ .arm = 0, .ahb = 0, .sel = 0},
	{ .arm = 0, .ahb = 0, .sel = 0},
	{ .arm = 4, .ahb = 2, .sel = 0},
	{ .arm = 0, .ahb = 0, .sel = 0},
};

static unsigned long get_rate_arm(void)
{
	unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
	struct arm_ahb_div *aad;
	unsigned long fref = get_rate_mpll();

	aad = &clk_consumer[(pdr0 >> 16) & 0xf];
	if (aad->sel)
		fref = fref * 2 / 3;

	return fref / aad->arm;
}

static unsigned long get_rate_ahb(struct clk *clk)
{
	unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
	struct arm_ahb_div *aad;
	unsigned long fref = get_rate_mpll();

	aad = &clk_consumer[(pdr0 >> 16) & 0xf];

	return fref / aad->ahb;
}

static unsigned long get_rate_ipg(struct clk *clk)
{
	return get_rate_ahb(NULL) >> 1;
}

static unsigned long get_3_3_div(unsigned long in)
{
	return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1);
}

static unsigned long get_rate_uart(struct clk *clk)
{
	unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
	unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
	unsigned long div = get_3_3_div(pdr4 >> 10);

	if (pdr3 & (1 << 14))
		return get_rate_arm() / div;
	else
		return get_rate_ppll() / div;
}

static unsigned long get_rate_sdhc(struct clk *clk)
{
	unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
	unsigned long div, rate;

	if (pdr3 & (1 << 6))
		rate = get_rate_arm();
	else
		rate = get_rate_ppll();

	switch (clk->id) {
	default:
	case 0:
		div = pdr3 & 0x3f;
		break;
	case 1:
		div = (pdr3 >> 8) & 0x3f;
		break;
	case 2:
		div = (pdr3 >> 16) & 0x3f;
		break;
	}

	return rate / get_3_3_div(div);
}

static unsigned long get_rate_mshc(struct clk *clk)
{
	unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1);
	unsigned long div1, div2, rate;

	if (pdr1 & (1 << 7))
		rate = get_rate_arm();
	else
		rate = get_rate_ppll();

	div1 = (pdr1 >> 29) & 0x7;
	div2 = (pdr1 >> 22) & 0x3f;

	return rate / ((div1 + 1) * (div2 + 1));
}

static unsigned long get_rate_ssi(struct clk *clk)
{
	unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
	unsigned long div1, div2, rate;

	if (pdr2 & (1 << 6))
		rate = get_rate_arm();
	else
		rate = get_rate_ppll();

	switch (clk->id) {
	default:
	case 0:
		div1 = pdr2 & 0x3f;
		div2 = (pdr2 >> 24) & 0x7;
		break;
	case 1:
		div1 = (pdr2 >> 8) & 0x3f;
		div2 = (pdr2 >> 27) & 0x7;
		break;
	}

	return rate / ((div1 + 1) * (div2 + 1));
}

static unsigned long get_rate_csi(struct clk *clk)
{
	unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
	unsigned long rate;

	if (pdr2 & (1 << 7))
		rate = get_rate_arm();
	else
		rate = get_rate_ppll();

	return rate / get_3_3_div((pdr2 >> 16) & 0x3f);
}

static unsigned long get_rate_otg(struct clk *clk)
{
	unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
	unsigned long rate;

	if (pdr4 & (1 << 9))
		rate = get_rate_arm();
	else
		rate = get_rate_ppll();

	return rate / get_3_3_div((pdr4 >> 22) & 0x3f);
}

static unsigned long get_rate_ipg_per(struct clk *clk)
{
	unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
	unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
	unsigned long div1, div2;

	if (pdr0 & (1 << 26)) {
		div1 = (pdr4 >> 19) & 0x7;
		div2 = (pdr4 >> 16) & 0x7;
		return get_rate_arm() / ((div1 + 1) * (div2 + 1));
	} else {
		div1 = (pdr0 >> 12) & 0x7;
		return get_rate_ahb(NULL) / div1;
	}
}

static int clk_cgr_enable(struct clk *clk)
{
	u32 reg;

	reg = __raw_readl(clk->enable_reg);
	reg |= 3 << clk->enable_shift;
	__raw_writel(reg, clk->enable_reg);

	return 0;
}

static void clk_cgr_disable(struct clk *clk)
{
	u32 reg;

	reg = __raw_readl(clk->enable_reg);
	reg &= ~(3 << clk->enable_shift);
	__raw_writel(reg, clk->enable_reg);
}

#define DEFINE_CLOCK(name, i, er, es, gr, sr)		\
	static struct clk name = {			\
		.id		= i,			\
		.enable_reg	= CCM_BASE + er,	\
		.enable_shift	= es,			\
		.get_rate	= gr,			\
		.set_rate	= sr,			\
		.enable		= clk_cgr_enable,	\
		.disable	= clk_cgr_disable,	\
	}

DEFINE_CLOCK(asrc_clk,   0, CCM_CGR0,  0, NULL, NULL);
DEFINE_CLOCK(ata_clk,    0, CCM_CGR0,  2, get_rate_ipg, NULL);
/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0,  4, NULL, NULL); */
DEFINE_CLOCK(can1_clk,   0, CCM_CGR0,  6, get_rate_ipg, NULL);
DEFINE_CLOCK(can2_clk,   1, CCM_CGR0,  8, get_rate_ipg, NULL);
DEFINE_CLOCK(cspi1_clk,  0, CCM_CGR0, 10, get_rate_ipg, NULL);
DEFINE_CLOCK(cspi2_clk,  1, CCM_CGR0, 12, get_rate_ipg, NULL);
DEFINE_CLOCK(ect_clk,    0, CCM_CGR0, 14, get_rate_ipg, NULL);
DEFINE_CLOCK(edio_clk,   0, CCM_CGR0, 16, NULL, NULL);
DEFINE_CLOCK(emi_clk,    0, CCM_CGR0, 18, get_rate_ipg, NULL);
DEFINE_CLOCK(epit1_clk,  0, CCM_CGR0, 20, get_rate_ipg_per, NULL);
DEFINE_CLOCK(epit2_clk,  1, CCM_CGR0, 22, get_rate_ipg_per, NULL);
DEFINE_CLOCK(esai_clk,   0, CCM_CGR0, 24, NULL, NULL);
DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL);

DEFINE_CLOCK(fec_clk,    0, CCM_CGR1,  0, get_rate_ipg, NULL);
DEFINE_CLOCK(gpio1_clk,  0, CCM_CGR1,  2, NULL, NULL);
DEFINE_CLOCK(gpio2_clk,  1, CCM_CGR1,  4, NULL, NULL);
DEFINE_CLOCK(gpio3_clk,  2, CCM_CGR1,  6, NULL, NULL);
DEFINE_CLOCK(gpt_clk,    0, CCM_CGR1,  8, get_rate_ipg, NULL);
DEFINE_CLOCK(i2c1_clk,   0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
DEFINE_CLOCK(i2c2_clk,   1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
DEFINE_CLOCK(i2c3_clk,   2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, NULL, NULL);
DEFINE_CLOCK(kpp_clk,    0, CCM_CGR1, 20, get_rate_ipg, NULL);
DEFINE_CLOCK(mlb_clk,    0, CCM_CGR1, 22, get_rate_ahb, NULL);
DEFINE_CLOCK(mshc_clk,   0, CCM_CGR1, 24, get_rate_mshc, NULL);
DEFINE_CLOCK(owire_clk,  0, CCM_CGR1, 26, get_rate_ipg_per, NULL);
DEFINE_CLOCK(pwm_clk,    0, CCM_CGR1, 28, get_rate_ipg_per, NULL);
DEFINE_CLOCK(rngc_clk,   0, CCM_CGR1, 30, get_rate_ipg, NULL);

DEFINE_CLOCK(rtc_clk,    0, CCM_CGR2,  0, get_rate_ipg, NULL);
DEFINE_CLOCK(rtic_clk,   0, CCM_CGR2,  2, get_rate_ahb, NULL);
DEFINE_CLOCK(scc_clk,    0, CCM_CGR2,  4, get_rate_ipg, NULL);
DEFINE_CLOCK(sdma_clk,   0, CCM_CGR2,  6, NULL, NULL);
DEFINE_CLOCK(spba_clk,   0, CCM_CGR2,  8, get_rate_ipg, NULL);
DEFINE_CLOCK(spdif_clk,  0, CCM_CGR2, 10, NULL, NULL);
DEFINE_CLOCK(ssi1_clk,   0, CCM_CGR2, 12, get_rate_ssi, NULL);
DEFINE_CLOCK(ssi2_clk,   1, CCM_CGR2, 14, get_rate_ssi, NULL);
DEFINE_CLOCK(uart1_clk,  0, CCM_CGR2, 16, get_rate_uart, NULL);
DEFINE_CLOCK(uart2_clk,  1, CCM_CGR2, 18, get_rate_uart, NULL);
DEFINE_CLOCK(uart3_clk,  2, CCM_CGR2, 20, get_rate_uart, NULL);
DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
DEFINE_CLOCK(wdog_clk,   0, CCM_CGR2, 24, NULL, NULL);
DEFINE_CLOCK(max_clk,    0, CCM_CGR2, 26, NULL, NULL);
DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);

DEFINE_CLOCK(csi_clk,    0, CCM_CGR3,  0, get_rate_csi, NULL);
DEFINE_CLOCK(iim_clk,    0, CCM_CGR3,  2, NULL, NULL);
DEFINE_CLOCK(gpu2d_clk,  0, CCM_CGR3,  4, NULL, NULL);

DEFINE_CLOCK(usbahb_clk, 0, 0,         0, get_rate_ahb, NULL);

static int clk_dummy_enable(struct clk *clk)
{
	return 0;
}

static void clk_dummy_disable(struct clk *clk)
{
}

static unsigned long get_rate_nfc(struct clk *clk)
{
	unsigned long div1;

	div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;

	return get_rate_ahb(NULL) / div1;
}

/* NAND Controller: It seems it can't be disabled */
static struct clk nfc_clk = {
	.id		= 0,
	.enable_reg	= 0,
	.enable_shift	= 0,
	.get_rate	= get_rate_nfc,
	.set_rate	= NULL, /* set_rate_nfc, */
	.enable		= clk_dummy_enable,
	.disable	= clk_dummy_disable
};

#define _REGISTER_CLOCK(d, n, c)	\
	{				\
		.dev_id = d,		\
		.con_id = n,		\
		.clk = &c,		\
	},

static struct clk_lookup lookups[] = {
	_REGISTER_CLOCK(NULL, "asrc", asrc_clk)
	_REGISTER_CLOCK(NULL, "ata", ata_clk)
	_REGISTER_CLOCK(NULL, "can", can1_clk)
	_REGISTER_CLOCK(NULL, "can", can2_clk)
	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
	_REGISTER_CLOCK(NULL, "ect", ect_clk)
	_REGISTER_CLOCK(NULL, "edio", edio_clk)
	_REGISTER_CLOCK(NULL, "emi", emi_clk)
	_REGISTER_CLOCK(NULL, "epit", epit1_clk)
	_REGISTER_CLOCK(NULL, "epit", epit2_clk)
	_REGISTER_CLOCK(NULL, "esai", esai_clk)
	_REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk)
	_REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk)
	_REGISTER_CLOCK(NULL, "sdhc", esdhc3_clk)
	_REGISTER_CLOCK("fec.0", NULL, fec_clk)
	_REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
	_REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
	_REGISTER_CLOCK(NULL, "gpio", gpio3_clk)
	_REGISTER_CLOCK("gpt.0", NULL, gpt_clk)
	_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
	_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
	_REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
	_REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk)
	_REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
	_REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
	_REGISTER_CLOCK(NULL, "kpp", kpp_clk)
	_REGISTER_CLOCK(NULL, "mlb", mlb_clk)
	_REGISTER_CLOCK(NULL, "mshc", mshc_clk)
	_REGISTER_CLOCK("mxc_w1", NULL, owire_clk)
	_REGISTER_CLOCK(NULL, "pwm", pwm_clk)
	_REGISTER_CLOCK(NULL, "rngc", rngc_clk)
	_REGISTER_CLOCK(NULL, "rtc", rtc_clk)
	_REGISTER_CLOCK(NULL, "rtic", rtic_clk)
	_REGISTER_CLOCK(NULL, "scc", scc_clk)
	_REGISTER_CLOCK(NULL, "sdma", sdma_clk)
	_REGISTER_CLOCK(NULL, "spba", spba_clk)
	_REGISTER_CLOCK(NULL, "spdif", spdif_clk)
	_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
	_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
	_REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
	_REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
	_REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
	_REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
	_REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
	_REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
	_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
	_REGISTER_CLOCK(NULL, "max", max_clk)
	_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
	_REGISTER_CLOCK(NULL, "csi", csi_clk)
	_REGISTER_CLOCK(NULL, "iim", iim_clk)
	_REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
	_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
};

int __init mx35_clocks_init()
{
	unsigned int ll = 0;

#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
	ll = (3 << 16);
#endif

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	/* Turn off all clocks except the ones we need to survive, namely:
	 * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
	 */
	__raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
	__raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
			CCM_BASE + CCM_CGR1);
	__raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
	__raw_writel(0, CCM_BASE + CCM_CGR3);

	mxc_timer_init(&gpt_clk,
			MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);

	return 0;
}
Commit	Line	Data
2cb536d1 SH	1	/*
	2	* Copyright (C) 2009 by Sascha Hauer, Pengutronix
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation; either version 2
	7	* of the License, or (at your option) any later version.
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program; if not, write to the Free Software
	15	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	16	* MA 02110-1301, USA.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/list.h>
	22	#include <linux/clk.h>
	23	#include <linux/io.h>
	24
	25	#include <asm/clkdev.h>
	26
	27	#include <mach/clock.h>
	28	#include <mach/hardware.h>
	29	#include <mach/common.h>
	30
6ef9af68	31	#define CCM_BASE MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)
2cb536d1 SH	32
	33	#define CCM_CCMR 0x00
	34	#define CCM_PDR0 0x04
	35	#define CCM_PDR1 0x08
	36	#define CCM_PDR2 0x0C
	37	#define CCM_PDR3 0x10
	38	#define CCM_PDR4 0x14
	39	#define CCM_RCSR 0x18
	40	#define CCM_MPCTL 0x1C
	41	#define CCM_PPCTL 0x20
	42	#define CCM_ACMR 0x24
	43	#define CCM_COSR 0x28
	44	#define CCM_CGR0 0x2C
	45	#define CCM_CGR1 0x30
	46	#define CCM_CGR2 0x34
	47	#define CCM_CGR3 0x38
	48
	49	#ifdef HAVE_SET_RATE_SUPPORT
	50	static void calc_dividers(u32 div, u32 pre, u32 post, u32 maxpost)
	51	{
	52	u32 min_pre, temp_pre, old_err, err;
	53
	54	min_pre = (div - 1) / maxpost + 1;
	55	old_err = 8;
	56
	57	for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
	58	if (div > (temp_pre * maxpost))
	59	break;
	60
	61	if (div < (temp_pre * temp_pre))
	62	continue;
	63
	64	err = div % temp_pre;
	65
	66	if (err == 0) {
	67	*pre = temp_pre;
	68	break;
	69	}
	70
	71	err = temp_pre - err;
	72
	73	if (err < old_err) {
	74	old_err = err;
	75	*pre = temp_pre;
	76	}
	77	}
	78
	79	post = (div + pre - 1) / *pre;
	80	}
	81
	82	/* get the best values for a 3-bit divider combined with a 6-bit divider */
	83	static void calc_dividers_3_6(u32 div, u32 pre, u32 post)
	84	{
	85	if (div >= 512) {
	86	*pre = 8;
	87	*post = 64;
	88	} else if (div >= 64) {
	89	calc_dividers(div, pre, post, 64);
	90	} else if (div <= 8) {
	91	*pre = div;
	92	*post = 1;
	93	} else {
	94	*pre = 1;
	95	*post = div;
96	}
97	}
98
99	/* get the best values for two cascaded 3-bit dividers */
100	static void calc_dividers_3_3(u32 div, u32 pre, u32 post)
101	{
102	if (div >= 64) {
103	pre = post = 8;
104	} else if (div > 8) {
105	calc_dividers(div, pre, post, 8);
106	} else {
107	*pre = 1;
108	*post = div;
109	}
110	}
111	#endif
112
113	static unsigned long get_rate_mpll(void)
114	{
115	ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL);
116
117	return mxc_decode_pll(mpctl, 24000000);
118	}
119
120	static unsigned long get_rate_ppll(void)
121	{
122	ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL);
123
124	return mxc_decode_pll(ppctl, 24000000);
125	}
126
127	struct arm_ahb_div {
128	unsigned char arm, ahb, sel;
129	};
130
131	static struct arm_ahb_div clk_consumer[] = {
132	{ .arm = 1, .ahb = 4, .sel = 0},
133	{ .arm = 1, .ahb = 3, .sel = 1},
134	{ .arm = 2, .ahb = 2, .sel = 0},
135	{ .arm = 0, .ahb = 0, .sel = 0},
136	{ .arm = 0, .ahb = 0, .sel = 0},
137	{ .arm = 0, .ahb = 0, .sel = 0},
138	{ .arm = 4, .ahb = 1, .sel = 0},
139	{ .arm = 1, .ahb = 5, .sel = 0},
140	{ .arm = 1, .ahb = 8, .sel = 0},
141	{ .arm = 1, .ahb = 6, .sel = 1},
142	{ .arm = 2, .ahb = 4, .sel = 0},
143	{ .arm = 0, .ahb = 0, .sel = 0},
144	{ .arm = 0, .ahb = 0, .sel = 0},
145	{ .arm = 0, .ahb = 0, .sel = 0},
146	{ .arm = 4, .ahb = 2, .sel = 0},
147	{ .arm = 0, .ahb = 0, .sel = 0},
148	};
149
2cb536d1 SH	150	static unsigned long get_rate_arm(void)
	151	{
	152	unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
	153	struct arm_ahb_div *aad;
	154	unsigned long fref = get_rate_mpll();
	155
d16caf69 SH	156	aad = &clk_consumer[(pdr0 >> 16) & 0xf];
	157	if (aad->sel)
	158	fref = fref * 2 / 3;
	159
2cb536d1 SH	160	return fref / aad->arm;
	161	}
	162
	163	static unsigned long get_rate_ahb(struct clk *clk)
	164	{
	165	unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
	166	struct arm_ahb_div *aad;
	167	unsigned long fref = get_rate_mpll();
	168
d16caf69	169	aad = &clk_consumer[(pdr0 >> 16) & 0xf];
2cb536d1 SH	170
	171	return fref / aad->ahb;
	172	}
	173
	174	static unsigned long get_rate_ipg(struct clk *clk)
	175	{
	176	return get_rate_ahb(NULL) >> 1;
	177	}
	178
	179	static unsigned long get_3_3_div(unsigned long in)
	180	{
	181	return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1);
	182	}
	183
	184	static unsigned long get_rate_uart(struct clk *clk)
	185	{
	186	unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
	187	unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
	188	unsigned long div = get_3_3_div(pdr4 >> 10);
	189
	190	if (pdr3 & (1 << 14))
	191	return get_rate_arm() / div;
	192	else
	193	return get_rate_ppll() / div;
	194	}
	195
	196	static unsigned long get_rate_sdhc(struct clk *clk)
	197	{
	198	unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
	199	unsigned long div, rate;
	200
	201	if (pdr3 & (1 << 6))
	202	rate = get_rate_arm();
	203	else
	204	rate = get_rate_ppll();
	205
	206	switch (clk->id) {
	207	default:
	208	case 0:
	209	div = pdr3 & 0x3f;
	210	break;
	211	case 1:
	212	div = (pdr3 >> 8) & 0x3f;
	213	break;
	214	case 2:
	215	div = (pdr3 >> 16) & 0x3f;
	216	break;
	217	}
	218
	219	return rate / get_3_3_div(div);
	220	}
	221
	222	static unsigned long get_rate_mshc(struct clk *clk)
	223	{
	224	unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1);
	225	unsigned long div1, div2, rate;
	226
	227	if (pdr1 & (1 << 7))
	228	rate = get_rate_arm();
	229	else
	230	rate = get_rate_ppll();
	231
	232	div1 = (pdr1 >> 29) & 0x7;
	233	div2 = (pdr1 >> 22) & 0x3f;
234
235	return rate / ((div1 + 1) * (div2 + 1));
236	}
237
238	static unsigned long get_rate_ssi(struct clk *clk)
239	{
240	unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
241	unsigned long div1, div2, rate;
242
243	if (pdr2 & (1 << 6))
244	rate = get_rate_arm();
245	else
246	rate = get_rate_ppll();
247
248	switch (clk->id) {
249	default:
250	case 0:
251	div1 = pdr2 & 0x3f;
252	div2 = (pdr2 >> 24) & 0x7;
253	break;
254	case 1:
255	div1 = (pdr2 >> 8) & 0x3f;
256	div2 = (pdr2 >> 27) & 0x7;
257	break;
258	}
259
260	return rate / ((div1 + 1) * (div2 + 1));
261	}
262
263	static unsigned long get_rate_csi(struct clk *clk)
264	{
265	unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
266	unsigned long rate;
267
268	if (pdr2 & (1 << 7))
269	rate = get_rate_arm();
270	else
271	rate = get_rate_ppll();
272
273	return rate / get_3_3_div((pdr2 >> 16) & 0x3f);
274	}
275
547270a3 SH	276	static unsigned long get_rate_otg(struct clk *clk)
	277	{
	278	unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
	279	unsigned long rate;
	280
	281	if (pdr4 & (1 << 9))
	282	rate = get_rate_arm();
	283	else
	284	rate = get_rate_ppll();
	285
	286	return rate / get_3_3_div((pdr4 >> 22) & 0x3f);
	287	}
	288
2cb536d1 SH	289	static unsigned long get_rate_ipg_per(struct clk *clk)
	290	{
	291	unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
	292	unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
	293	unsigned long div1, div2;
	294
	295	if (pdr0 & (1 << 26)) {
	296	div1 = (pdr4 >> 19) & 0x7;
	297	div2 = (pdr4 >> 16) & 0x7;
	298	return get_rate_arm() / ((div1 + 1) * (div2 + 1));
	299	} else {
	300	div1 = (pdr0 >> 12) & 0x7;
	301	return get_rate_ahb(NULL) / div1;
	302	}
	303	}
	304
	305	static int clk_cgr_enable(struct clk *clk)
	306	{
	307	u32 reg;
	308
	309	reg = __raw_readl(clk->enable_reg);
	310	reg \|= 3 << clk->enable_shift;
	311	__raw_writel(reg, clk->enable_reg);
	312
	313	return 0;
	314	}
	315
	316	static void clk_cgr_disable(struct clk *clk)
	317	{
	318	u32 reg;
	319
	320	reg = __raw_readl(clk->enable_reg);
	321	reg &= ~(3 << clk->enable_shift);
	322	__raw_writel(reg, clk->enable_reg);
	323	}
	324
	325	#define DEFINE_CLOCK(name, i, er, es, gr, sr) \
	326	static struct clk name = { \
	327	.id = i, \
	328	.enable_reg = CCM_BASE + er, \
	329	.enable_shift = es, \
	330	.get_rate = gr, \
	331	.set_rate = sr, \
	332	.enable = clk_cgr_enable, \
	333	.disable = clk_cgr_disable, \
	334	}
	335
	336	DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL);
	337	DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL);
4dc7be72	338	/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */
2cb536d1 SH	339	DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL);
	340	DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL);
	341	DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL);
	342	DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL);
	343	DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL);
	344	DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL);
	345	DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL);
	346	DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg_per, NULL);
	347	DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg_per, NULL);
	348	DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL);
	349	DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
	350	DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
	351	DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL);
	352
	353	DEFINE_CLOCK(fec_clk, 0, CCM_CGR1, 0, get_rate_ipg, NULL);
	354	DEFINE_CLOCK(gpio1_clk, 0, CCM_CGR1, 2, NULL, NULL);
	355	DEFINE_CLOCK(gpio2_clk, 1, CCM_CGR1, 4, NULL, NULL);
	356	DEFINE_CLOCK(gpio3_clk, 2, CCM_CGR1, 6, NULL, NULL);
	357	DEFINE_CLOCK(gpt_clk, 0, CCM_CGR1, 8, get_rate_ipg, NULL);
	358	DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
	359	DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
	360	DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
	361	DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
	362	DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, NULL, NULL);
	363	DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL);
	364	DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL);
	365	DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL);
	366	DEFINE_CLOCK(owire_clk, 0, CCM_CGR1, 26, get_rate_ipg_per, NULL);
	367	DEFINE_CLOCK(pwm_clk, 0, CCM_CGR1, 28, get_rate_ipg_per, NULL);
	368	DEFINE_CLOCK(rngc_clk, 0, CCM_CGR1, 30, get_rate_ipg, NULL);
	369
	370	DEFINE_CLOCK(rtc_clk, 0, CCM_CGR2, 0, get_rate_ipg, NULL);
	371	DEFINE_CLOCK(rtic_clk, 0, CCM_CGR2, 2, get_rate_ahb, NULL);
	372	DEFINE_CLOCK(scc_clk, 0, CCM_CGR2, 4, get_rate_ipg, NULL);
	373	DEFINE_CLOCK(sdma_clk, 0, CCM_CGR2, 6, NULL, NULL);
	374	DEFINE_CLOCK(spba_clk, 0, CCM_CGR2, 8, get_rate_ipg, NULL);
	375	DEFINE_CLOCK(spdif_clk, 0, CCM_CGR2, 10, NULL, NULL);
	376	DEFINE_CLOCK(ssi1_clk, 0, CCM_CGR2, 12, get_rate_ssi, NULL);
	377	DEFINE_CLOCK(ssi2_clk, 1, CCM_CGR2, 14, get_rate_ssi, NULL);
	378	DEFINE_CLOCK(uart1_clk, 0, CCM_CGR2, 16, get_rate_uart, NULL);
	379	DEFINE_CLOCK(uart2_clk, 1, CCM_CGR2, 18, get_rate_uart, NULL);
	380	DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL);
547270a3	381	DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
2cb536d1 SH	382	DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL);
2cb536d1 SH	383	DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL);
4dc7be72	384	DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
2cb536d1 SH	385
	386	DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL);
	387	DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL);
	388	DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL);
	389
3e9a23db HH	390	DEFINE_CLOCK(usbahb_clk, 0, 0, 0, get_rate_ahb, NULL);
3e9a23db HH	391
9e0afdf8 JB	392	static int clk_dummy_enable(struct clk *clk)
	393	{
	394	return 0;
	395	}
	396
	397	static void clk_dummy_disable(struct clk *clk)
	398	{
	399	}
	400
	401	static unsigned long get_rate_nfc(struct clk *clk)
	402	{
	403	unsigned long div1;
	404
	405	div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
	406
	407	return get_rate_ahb(NULL) / div1;
	408	}
	409
	410	/* NAND Controller: It seems it can't be disabled */
	411	static struct clk nfc_clk = {
	412	.id = 0,
	413	.enable_reg = 0,
	414	.enable_shift = 0,
	415	.get_rate = get_rate_nfc,
	416	.set_rate = NULL, /* set_rate_nfc, */
	417	.enable = clk_dummy_enable,
	418	.disable = clk_dummy_disable
	419	};
	420
2cb536d1 SH	421	#define _REGISTER_CLOCK(d, n, c) \
	422	{ \
	423	.dev_id = d, \
	424	.con_id = n, \
	425	.clk = &c, \
	426	},
	427
6b4bfb87	428	static struct clk_lookup lookups[] = {
2cb536d1 SH	429	_REGISTER_CLOCK(NULL, "asrc", asrc_clk)
2cb536d1 SH	430	_REGISTER_CLOCK(NULL, "ata", ata_clk)
2cb536d1 SH	431	_REGISTER_CLOCK(NULL, "can", can1_clk)
	432	_REGISTER_CLOCK(NULL, "can", can2_clk)
	433	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
	434	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
	435	_REGISTER_CLOCK(NULL, "ect", ect_clk)
	436	_REGISTER_CLOCK(NULL, "edio", edio_clk)
	437	_REGISTER_CLOCK(NULL, "emi", emi_clk)
	438	_REGISTER_CLOCK(NULL, "epit", epit1_clk)
	439	_REGISTER_CLOCK(NULL, "epit", epit2_clk)
	440	_REGISTER_CLOCK(NULL, "esai", esai_clk)
	441	_REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk)
	442	_REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk)
	443	_REGISTER_CLOCK(NULL, "sdhc", esdhc3_clk)
	444	_REGISTER_CLOCK("fec.0", NULL, fec_clk)
	445	_REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
	446	_REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
	447	_REGISTER_CLOCK(NULL, "gpio", gpio3_clk)
	448	_REGISTER_CLOCK("gpt.0", NULL, gpt_clk)
	449	_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
	450	_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
	451	_REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
	452	_REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk)
76b6ea0a SH	453	_REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
76b6ea0a SH	454	_REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
2cb536d1 SH	455	_REGISTER_CLOCK(NULL, "kpp", kpp_clk)
	456	_REGISTER_CLOCK(NULL, "mlb", mlb_clk)
	457	_REGISTER_CLOCK(NULL, "mshc", mshc_clk)
	458	_REGISTER_CLOCK("mxc_w1", NULL, owire_clk)
	459	_REGISTER_CLOCK(NULL, "pwm", pwm_clk)
	460	_REGISTER_CLOCK(NULL, "rngc", rngc_clk)
	461	_REGISTER_CLOCK(NULL, "rtc", rtc_clk)
	462	_REGISTER_CLOCK(NULL, "rtic", rtic_clk)
	463	_REGISTER_CLOCK(NULL, "scc", scc_clk)
	464	_REGISTER_CLOCK(NULL, "sdma", sdma_clk)
	465	_REGISTER_CLOCK(NULL, "spba", spba_clk)
	466	_REGISTER_CLOCK(NULL, "spdif", spdif_clk)
d8d982b1 SH	467	_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
d8d982b1 SH	468	_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
2cb536d1 SH	469	_REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
	470	_REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
	471	_REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
547270a3 SH	472	_REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
	473	_REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
	474	_REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
	475	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
3e9a23db	476	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
679bfef0	477	_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
2cb536d1	478	_REGISTER_CLOCK(NULL, "max", max_clk)
4dc7be72	479	_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
2cb536d1 SH	480	_REGISTER_CLOCK(NULL, "csi", csi_clk)
	481	_REGISTER_CLOCK(NULL, "iim", iim_clk)
	482	_REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
9e0afdf8	483	_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
2cb536d1 SH	484	};
	485
	486	int __init mx35_clocks_init()
	487	{
2cb536d1 SH	488	unsigned int ll = 0;
2cb536d1 SH	489
97adeda0	490	#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
2cb536d1 SH	491	ll = (3 << 16);
	492	#endif
	493
0a0300dc	494	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
2cb536d1 SH	495
	496	/* Turn off all clocks except the ones we need to survive, namely:
	497	* EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
	498	*/
	499	__raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
	500	__raw_writel((3 << 2) \| (3 << 4) \| (3 << 6) \| (3 << 8) \| (3 << 16),
	501	CCM_BASE + CCM_CGR1);
	502	__raw_writel((3 << 26) \| ll, CCM_BASE + CCM_CGR2);
	503	__raw_writel(0, CCM_BASE + CCM_CGR3);
	504
6ef9af68 UKK	505	mxc_timer_init(&gpt_clk,
6ef9af68 UKK	506	MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
2cb536d1 SH	507
	508	return 0;
	509	}
	510