Commit | Line | Data |
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1da177e4 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-ixp4xx/include/mach/system.h |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2002 Intel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | */ | |
11 | ||
a09e64fb | 12 | #include <mach/hardware.h> |
1da177e4 LT |
13 | |
14 | static inline void arch_idle(void) | |
15 | { | |
74c32e72 MP |
16 | /* ixp4xx does not implement the XScale PWRMODE register, |
17 | * so it must not call cpu_do_idle() here. | |
18 | */ | |
1da177e4 | 19 | #if 0 |
74c32e72 | 20 | cpu_do_idle(); |
1da177e4 LT |
21 | #endif |
22 | } | |
23 | ||
24 | ||
be093beb | 25 | static inline void arch_reset(char mode, const char *cmd) |
1da177e4 LT |
26 | { |
27 | if ( 1 && mode == 's') { | |
28 | /* Jump into ROM at address 0 */ | |
29 | cpu_reset(0); | |
30 | } else { | |
31 | /* Use on-chip reset capability */ | |
32 | ||
33 | /* set the "key" register to enable access to | |
34 | * "timer" and "enable" registers | |
35 | */ | |
36 | *IXP4XX_OSWK = IXP4XX_WDT_KEY; | |
37 | ||
38 | /* write 0 to the timer register for an immediate reset */ | |
39 | *IXP4XX_OSWT = 0; | |
40 | ||
41 | *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE; | |
42 | } | |
43 | } | |
44 |