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91cfbd4e TA |
1 | /* |
2 | * Exynos Generic power domain support. | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * | |
7 | * Implementation of Exynos specific power domain control which is used in | |
8 | * conjunction with runtime-pm. Support for both device-tree and non-device-tree | |
9 | * based power domain support is included. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/io.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/pm_domain.h> | |
c760569d | 20 | #include <linux/clk.h> |
91cfbd4e TA |
21 | #include <linux/delay.h> |
22 | #include <linux/of_address.h> | |
8a65d236 TF |
23 | #include <linux/of_platform.h> |
24 | #include <linux/sched.h> | |
91cfbd4e | 25 | |
b634e38f | 26 | #define INT_LOCAL_PWR_EN 0x7 |
c760569d P |
27 | #define MAX_CLK_PER_DOMAIN 4 |
28 | ||
91cfbd4e TA |
29 | /* |
30 | * Exynos specific wrapper around the generic power domain | |
31 | */ | |
32 | struct exynos_pm_domain { | |
33 | void __iomem *base; | |
34 | char const *name; | |
35 | bool is_off; | |
36 | struct generic_pm_domain pd; | |
c760569d P |
37 | struct clk *oscclk; |
38 | struct clk *clk[MAX_CLK_PER_DOMAIN]; | |
39 | struct clk *pclk[MAX_CLK_PER_DOMAIN]; | |
528eae6c | 40 | struct clk *asb_clk[MAX_CLK_PER_DOMAIN]; |
91cfbd4e TA |
41 | }; |
42 | ||
43 | static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) | |
44 | { | |
45 | struct exynos_pm_domain *pd; | |
46 | void __iomem *base; | |
47 | u32 timeout, pwr; | |
48 | char *op; | |
528eae6c | 49 | int i; |
91cfbd4e TA |
50 | |
51 | pd = container_of(domain, struct exynos_pm_domain, pd); | |
52 | base = pd->base; | |
53 | ||
528eae6c AH |
54 | for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { |
55 | if (IS_ERR(pd->asb_clk[i])) | |
56 | break; | |
57 | clk_prepare_enable(pd->asb_clk[i]); | |
58 | } | |
59 | ||
c760569d P |
60 | /* Set oscclk before powering off a domain*/ |
61 | if (!power_on) { | |
c760569d P |
62 | for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { |
63 | if (IS_ERR(pd->clk[i])) | |
64 | break; | |
65 | if (clk_set_parent(pd->clk[i], pd->oscclk)) | |
66 | pr_err("%s: error setting oscclk as parent to clock %d\n", | |
67 | pd->name, i); | |
68 | } | |
69 | } | |
70 | ||
b634e38f | 71 | pwr = power_on ? INT_LOCAL_PWR_EN : 0; |
91cfbd4e TA |
72 | __raw_writel(pwr, base); |
73 | ||
74 | /* Wait max 1ms */ | |
75 | timeout = 10; | |
76 | ||
b634e38f | 77 | while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) { |
91cfbd4e TA |
78 | if (!timeout) { |
79 | op = (power_on) ? "enable" : "disable"; | |
80 | pr_err("Power domain %s %s failed\n", domain->name, op); | |
81 | return -ETIMEDOUT; | |
82 | } | |
83 | timeout--; | |
84 | cpu_relax(); | |
85 | usleep_range(80, 100); | |
86 | } | |
c760569d P |
87 | |
88 | /* Restore clocks after powering on a domain*/ | |
89 | if (power_on) { | |
c760569d P |
90 | for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { |
91 | if (IS_ERR(pd->clk[i])) | |
92 | break; | |
93 | if (clk_set_parent(pd->clk[i], pd->pclk[i])) | |
94 | pr_err("%s: error setting parent to clock%d\n", | |
95 | pd->name, i); | |
96 | } | |
97 | } | |
98 | ||
528eae6c AH |
99 | for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { |
100 | if (IS_ERR(pd->asb_clk[i])) | |
101 | break; | |
102 | clk_disable_unprepare(pd->asb_clk[i]); | |
103 | } | |
104 | ||
91cfbd4e TA |
105 | return 0; |
106 | } | |
107 | ||
108 | static int exynos_pd_power_on(struct generic_pm_domain *domain) | |
109 | { | |
110 | return exynos_pd_power(domain, true); | |
111 | } | |
112 | ||
113 | static int exynos_pd_power_off(struct generic_pm_domain *domain) | |
114 | { | |
115 | return exynos_pd_power(domain, false); | |
116 | } | |
117 | ||
8eaa9e42 | 118 | static __init int exynos4_pm_init_power_domain(void) |
91cfbd4e | 119 | { |
8a65d236 | 120 | struct platform_device *pdev; |
91cfbd4e TA |
121 | struct device_node *np; |
122 | ||
123 | for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { | |
124 | struct exynos_pm_domain *pd; | |
c760569d P |
125 | int on, i; |
126 | struct device *dev; | |
91cfbd4e | 127 | |
8a65d236 | 128 | pdev = of_find_device_by_node(np); |
c760569d | 129 | dev = &pdev->dev; |
8a65d236 | 130 | |
91cfbd4e TA |
131 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); |
132 | if (!pd) { | |
133 | pr_err("%s: failed to allocate memory for domain\n", | |
134 | __func__); | |
135 | return -ENOMEM; | |
136 | } | |
137 | ||
70e9d7b5 | 138 | pd->pd.name = kstrdup(dev_name(dev), GFP_KERNEL); |
7add0ec0 | 139 | pd->name = pd->pd.name; |
91cfbd4e TA |
140 | pd->base = of_iomap(np, 0); |
141 | pd->pd.power_off = exynos_pd_power_off; | |
142 | pd->pd.power_on = exynos_pd_power_on; | |
2ed5f236 | 143 | |
528eae6c AH |
144 | for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { |
145 | char clk_name[8]; | |
146 | ||
147 | snprintf(clk_name, sizeof(clk_name), "asb%d", i); | |
148 | pd->asb_clk[i] = clk_get(dev, clk_name); | |
149 | if (IS_ERR(pd->asb_clk[i])) | |
150 | break; | |
151 | } | |
152 | ||
c760569d P |
153 | pd->oscclk = clk_get(dev, "oscclk"); |
154 | if (IS_ERR(pd->oscclk)) | |
155 | goto no_clk; | |
156 | ||
157 | for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) { | |
158 | char clk_name[8]; | |
159 | ||
160 | snprintf(clk_name, sizeof(clk_name), "clk%d", i); | |
161 | pd->clk[i] = clk_get(dev, clk_name); | |
162 | if (IS_ERR(pd->clk[i])) | |
163 | break; | |
164 | snprintf(clk_name, sizeof(clk_name), "pclk%d", i); | |
165 | pd->pclk[i] = clk_get(dev, clk_name); | |
166 | if (IS_ERR(pd->pclk[i])) { | |
167 | clk_put(pd->clk[i]); | |
168 | pd->clk[i] = ERR_PTR(-EINVAL); | |
169 | break; | |
170 | } | |
171 | } | |
172 | ||
173 | if (IS_ERR(pd->clk[0])) | |
174 | clk_put(pd->oscclk); | |
175 | ||
176 | no_clk: | |
b634e38f | 177 | on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN; |
2ed5f236 TF |
178 | |
179 | pm_genpd_init(&pd->pd, NULL, !on); | |
a4a8c2c4 | 180 | of_genpd_add_provider_simple(np, &pd->pd); |
91cfbd4e | 181 | } |
8a65d236 | 182 | |
0f780751 MS |
183 | /* Assign the child power domains to their parents */ |
184 | for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { | |
185 | struct generic_pm_domain *child_domain, *parent_domain; | |
186 | struct of_phandle_args args; | |
187 | ||
188 | args.np = np; | |
189 | args.args_count = 0; | |
190 | child_domain = of_genpd_get_from_provider(&args); | |
0b7dc0ff | 191 | if (IS_ERR(child_domain)) |
0f780751 MS |
192 | continue; |
193 | ||
194 | if (of_parse_phandle_with_args(np, "power-domains", | |
195 | "#power-domain-cells", 0, &args) != 0) | |
196 | continue; | |
197 | ||
198 | parent_domain = of_genpd_get_from_provider(&args); | |
0b7dc0ff | 199 | if (IS_ERR(parent_domain)) |
0f780751 MS |
200 | continue; |
201 | ||
202 | if (pm_genpd_add_subdomain(parent_domain, child_domain)) | |
203 | pr_warn("%s failed to add subdomain: %s\n", | |
204 | parent_domain->name, child_domain->name); | |
205 | else | |
206 | pr_info("%s has as child subdomain: %s.\n", | |
207 | parent_domain->name, child_domain->name); | |
208 | of_node_put(np); | |
209 | } | |
210 | ||
91cfbd4e TA |
211 | return 0; |
212 | } | |
91cfbd4e | 213 | arch_initcall(exynos4_pm_init_power_domain); |