[linux-2.6-block.git] / arch / arm / mach-exynos / pm_domains.c

/*
 * Exynos Generic power domain support.
 *
 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Implementation of Exynos specific power domain control which is used in
 * conjunction with runtime-pm. Support for both device-tree and non-device-tree
 * based power domain support is included.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/io.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <linux/pm_domain.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/sched.h>

#define INT_LOCAL_PWR_EN	0x7
#define MAX_CLK_PER_DOMAIN	4

/*
 * Exynos specific wrapper around the generic power domain
 */
struct exynos_pm_domain {
	void __iomem *base;
	char const *name;
	bool is_off;
	struct generic_pm_domain pd;
	struct clk *oscclk;
	struct clk *clk[MAX_CLK_PER_DOMAIN];
	struct clk *pclk[MAX_CLK_PER_DOMAIN];
	struct clk *asb_clk[MAX_CLK_PER_DOMAIN];
};

static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
{
	struct exynos_pm_domain *pd;
	void __iomem *base;
	u32 timeout, pwr;
	char *op;
	int i;

	pd = container_of(domain, struct exynos_pm_domain, pd);
	base = pd->base;

	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
		if (IS_ERR(pd->asb_clk[i]))
			break;
		clk_prepare_enable(pd->asb_clk[i]);
	}

	/* Set oscclk before powering off a domain*/
	if (!power_on) {
		for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
			if (IS_ERR(pd->clk[i]))
				break;
			if (clk_set_parent(pd->clk[i], pd->oscclk))
				pr_err("%s: error setting oscclk as parent to clock %d\n",
						pd->name, i);
		}
	}

	pwr = power_on ? INT_LOCAL_PWR_EN : 0;
	__raw_writel(pwr, base);

	/* Wait max 1ms */
	timeout = 10;

	while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
		if (!timeout) {
			op = (power_on) ? "enable" : "disable";
			pr_err("Power domain %s %s failed\n", domain->name, op);
			return -ETIMEDOUT;
		}
		timeout--;
		cpu_relax();
		usleep_range(80, 100);
	}

	/* Restore clocks after powering on a domain*/
	if (power_on) {
		for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
			if (IS_ERR(pd->clk[i]))
				break;
			if (clk_set_parent(pd->clk[i], pd->pclk[i]))
				pr_err("%s: error setting parent to clock%d\n",
						pd->name, i);
		}
	}

	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
		if (IS_ERR(pd->asb_clk[i]))
			break;
		clk_disable_unprepare(pd->asb_clk[i]);
	}

	return 0;
}

static int exynos_pd_power_on(struct generic_pm_domain *domain)
{
	return exynos_pd_power(domain, true);
}

static int exynos_pd_power_off(struct generic_pm_domain *domain)
{
	return exynos_pd_power(domain, false);
}

static __init int exynos4_pm_init_power_domain(void)
{
	struct platform_device *pdev;
	struct device_node *np;

	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
		struct exynos_pm_domain *pd;
		int on, i;
		struct device *dev;

		pdev = of_find_device_by_node(np);
		if (!pdev) {
			pr_err("%s: failed to find device for node %s\n",
					__func__, np->name);
			of_node_put(np);
			continue;
		}
		dev = &pdev->dev;

		pd = kzalloc(sizeof(*pd), GFP_KERNEL);
		if (!pd) {
			pr_err("%s: failed to allocate memory for domain\n",
					__func__);
			return -ENOMEM;
		}

		pd->pd.name = kstrdup(dev_name(dev), GFP_KERNEL);
		if (!pd->pd.name) {
			kfree(pd);
			of_node_put(np);
			return -ENOMEM;
		}

		pd->name = pd->pd.name;
		pd->base = of_iomap(np, 0);
		if (!pd->base) {
			dev_warn(&pdev->dev, "Failed to map memory\n");
			kfree(pd->pd.name);
			kfree(pd);
			of_node_put(np);
			continue;
		}

		pd->pd.power_off = exynos_pd_power_off;
		pd->pd.power_on = exynos_pd_power_on;

		for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
			char clk_name[8];

			snprintf(clk_name, sizeof(clk_name), "asb%d", i);
			pd->asb_clk[i] = clk_get(dev, clk_name);
			if (IS_ERR(pd->asb_clk[i]))
				break;
		}

		pd->oscclk = clk_get(dev, "oscclk");
		if (IS_ERR(pd->oscclk))
			goto no_clk;

		for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
			char clk_name[8];

			snprintf(clk_name, sizeof(clk_name), "clk%d", i);
			pd->clk[i] = clk_get(dev, clk_name);
			if (IS_ERR(pd->clk[i]))
				break;
			snprintf(clk_name, sizeof(clk_name), "pclk%d", i);
			pd->pclk[i] = clk_get(dev, clk_name);
			if (IS_ERR(pd->pclk[i])) {
				clk_put(pd->clk[i]);
				pd->clk[i] = ERR_PTR(-EINVAL);
				break;
			}
		}

		if (IS_ERR(pd->clk[0]))
			clk_put(pd->oscclk);

no_clk:
		on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;

		pm_genpd_init(&pd->pd, NULL, !on);
		of_genpd_add_provider_simple(np, &pd->pd);
	}

	/* Assign the child power domains to their parents */
	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
		struct generic_pm_domain *child_domain, *parent_domain;
		struct of_phandle_args args;

		args.np = np;
		args.args_count = 0;
		child_domain = of_genpd_get_from_provider(&args);
		if (IS_ERR(child_domain))
			continue;

		if (of_parse_phandle_with_args(np, "power-domains",
					 "#power-domain-cells", 0, &args) != 0)
			continue;

		parent_domain = of_genpd_get_from_provider(&args);
		if (IS_ERR(parent_domain))
			continue;

		if (pm_genpd_add_subdomain(parent_domain, child_domain))
			pr_warn("%s failed to add subdomain: %s\n",
				parent_domain->name, child_domain->name);
		else
			pr_info("%s has as child subdomain: %s.\n",
				parent_domain->name, child_domain->name);
		of_node_put(np);
	}

	return 0;
}
arch_initcall(exynos4_pm_init_power_domain);
Commit	Line	Data
91cfbd4e TA	1	/*
	2	* Exynos Generic power domain support.
	3	*
	4	* Copyright (c) 2012 Samsung Electronics Co., Ltd.
	5	* http://www.samsung.com
	6	*
	7	* Implementation of Exynos specific power domain control which is used in
	8	* conjunction with runtime-pm. Support for both device-tree and non-device-tree
	9	* based power domain support is included.
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
	14	*/
	15
	16	#include <linux/io.h>
	17	#include <linux/err.h>
	18	#include <linux/slab.h>
	19	#include <linux/pm_domain.h>
c760569d	20	#include <linux/clk.h>
91cfbd4e TA	21	#include <linux/delay.h>
91cfbd4e TA	22	#include <linux/of_address.h>
8a65d236 TF	23	#include <linux/of_platform.h>
8a65d236 TF	24	#include <linux/sched.h>
91cfbd4e	25
b634e38f	26	#define INT_LOCAL_PWR_EN 0x7
c760569d P	27	#define MAX_CLK_PER_DOMAIN 4
c760569d P	28
91cfbd4e TA	29	/*
	30	* Exynos specific wrapper around the generic power domain
	31	*/
	32	struct exynos_pm_domain {
	33	void __iomem *base;
	34	char const *name;
	35	bool is_off;
	36	struct generic_pm_domain pd;
c760569d P	37	struct clk *oscclk;
	38	struct clk *clk[MAX_CLK_PER_DOMAIN];
	39	struct clk *pclk[MAX_CLK_PER_DOMAIN];
528eae6c	40	struct clk *asb_clk[MAX_CLK_PER_DOMAIN];
91cfbd4e TA	41	};
	42
	43	static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on)
	44	{
	45	struct exynos_pm_domain *pd;
	46	void __iomem *base;
	47	u32 timeout, pwr;
	48	char *op;
528eae6c	49	int i;
91cfbd4e TA	50
	51	pd = container_of(domain, struct exynos_pm_domain, pd);
	52	base = pd->base;
	53
528eae6c AH	54	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	55	if (IS_ERR(pd->asb_clk[i]))
	56	break;
	57	clk_prepare_enable(pd->asb_clk[i]);
	58	}
	59
c760569d P	60	/* Set oscclk before powering off a domain*/
c760569d P	61	if (!power_on) {
c760569d P	62	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	63	if (IS_ERR(pd->clk[i]))
	64	break;
	65	if (clk_set_parent(pd->clk[i], pd->oscclk))
	66	pr_err("%s: error setting oscclk as parent to clock %d\n",
	67	pd->name, i);
	68	}
	69	}
	70
b634e38f	71	pwr = power_on ? INT_LOCAL_PWR_EN : 0;
91cfbd4e TA	72	__raw_writel(pwr, base);
	73
	74	/* Wait max 1ms */
	75	timeout = 10;
	76
b634e38f	77	while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) {
91cfbd4e TA	78	if (!timeout) {
	79	op = (power_on) ? "enable" : "disable";
	80	pr_err("Power domain %s %s failed\n", domain->name, op);
	81	return -ETIMEDOUT;
	82	}
	83	timeout--;
	84	cpu_relax();
	85	usleep_range(80, 100);
	86	}
c760569d P	87
	88	/* Restore clocks after powering on a domain*/
	89	if (power_on) {
c760569d P	90	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	91	if (IS_ERR(pd->clk[i]))
	92	break;
	93	if (clk_set_parent(pd->clk[i], pd->pclk[i]))
	94	pr_err("%s: error setting parent to clock%d\n",
	95	pd->name, i);
	96	}
	97	}
	98
528eae6c AH	99	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	100	if (IS_ERR(pd->asb_clk[i]))
	101	break;
	102	clk_disable_unprepare(pd->asb_clk[i]);
	103	}
	104
91cfbd4e TA	105	return 0;
	106	}
	107
	108	static int exynos_pd_power_on(struct generic_pm_domain *domain)
	109	{
	110	return exynos_pd_power(domain, true);
	111	}
	112
	113	static int exynos_pd_power_off(struct generic_pm_domain *domain)
	114	{
	115	return exynos_pd_power(domain, false);
	116	}
	117
8eaa9e42	118	static __init int exynos4_pm_init_power_domain(void)
91cfbd4e	119	{
8a65d236	120	struct platform_device *pdev;
91cfbd4e TA	121	struct device_node *np;
	122
	123	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
	124	struct exynos_pm_domain *pd;
c760569d P	125	int on, i;
c760569d P	126	struct device *dev;
91cfbd4e	127
8a65d236	128	pdev = of_find_device_by_node(np);
c88cad34 KK	129	if (!pdev) {
	130	pr_err("%s: failed to find device for node %s\n",
	131	__func__, np->name);
	132	of_node_put(np);
	133	continue;
	134	}
c760569d	135	dev = &pdev->dev;
8a65d236	136
91cfbd4e TA	137	pd = kzalloc(sizeof(*pd), GFP_KERNEL);
	138	if (!pd) {
	139	pr_err("%s: failed to allocate memory for domain\n",
	140	__func__);
	141	return -ENOMEM;
	142	}
	143
70e9d7b5	144	pd->pd.name = kstrdup(dev_name(dev), GFP_KERNEL);
c88cad34 KK	145	if (!pd->pd.name) {
	146	kfree(pd);
	147	of_node_put(np);
	148	return -ENOMEM;
	149	}
	150
7add0ec0	151	pd->name = pd->pd.name;
91cfbd4e	152	pd->base = of_iomap(np, 0);
ef2156cf KK	153	if (!pd->base) {
	154	dev_warn(&pdev->dev, "Failed to map memory\n");
	155	kfree(pd->pd.name);
	156	kfree(pd);
	157	of_node_put(np);
	158	continue;
	159	}
	160
91cfbd4e TA	161	pd->pd.power_off = exynos_pd_power_off;
91cfbd4e TA	162	pd->pd.power_on = exynos_pd_power_on;
2ed5f236	163
528eae6c AH	164	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	165	char clk_name[8];
	166
	167	snprintf(clk_name, sizeof(clk_name), "asb%d", i);
	168	pd->asb_clk[i] = clk_get(dev, clk_name);
	169	if (IS_ERR(pd->asb_clk[i]))
	170	break;
	171	}
	172
c760569d P	173	pd->oscclk = clk_get(dev, "oscclk");
	174	if (IS_ERR(pd->oscclk))
	175	goto no_clk;
	176
	177	for (i = 0; i < MAX_CLK_PER_DOMAIN; i++) {
	178	char clk_name[8];
	179
	180	snprintf(clk_name, sizeof(clk_name), "clk%d", i);
	181	pd->clk[i] = clk_get(dev, clk_name);
	182	if (IS_ERR(pd->clk[i]))
	183	break;
	184	snprintf(clk_name, sizeof(clk_name), "pclk%d", i);
	185	pd->pclk[i] = clk_get(dev, clk_name);
	186	if (IS_ERR(pd->pclk[i])) {
	187	clk_put(pd->clk[i]);
	188	pd->clk[i] = ERR_PTR(-EINVAL);
	189	break;
	190	}
	191	}
	192
	193	if (IS_ERR(pd->clk[0]))
	194	clk_put(pd->oscclk);
	195
	196	no_clk:
b634e38f	197	on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN;
2ed5f236 TF	198
2ed5f236 TF	199	pm_genpd_init(&pd->pd, NULL, !on);
a4a8c2c4	200	of_genpd_add_provider_simple(np, &pd->pd);
91cfbd4e	201	}
8a65d236	202
0f780751 MS	203	/* Assign the child power domains to their parents */
	204	for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") {
	205	struct generic_pm_domain child_domain, parent_domain;
	206	struct of_phandle_args args;
	207
	208	args.np = np;
	209	args.args_count = 0;
	210	child_domain = of_genpd_get_from_provider(&args);
0b7dc0ff	211	if (IS_ERR(child_domain))
0f780751 MS	212	continue;
	213
	214	if (of_parse_phandle_with_args(np, "power-domains",
	215	"#power-domain-cells", 0, &args) != 0)
	216	continue;
	217
	218	parent_domain = of_genpd_get_from_provider(&args);
0b7dc0ff	219	if (IS_ERR(parent_domain))
0f780751 MS	220	continue;
	221
	222	if (pm_genpd_add_subdomain(parent_domain, child_domain))
	223	pr_warn("%s failed to add subdomain: %s\n",
	224	parent_domain->name, child_domain->name);
	225	else
	226	pr_info("%s has as child subdomain: %s.\n",
	227	parent_domain->name, child_domain->name);
	228	of_node_put(np);
	229	}
	230
91cfbd4e TA	231	return 0;
91cfbd4e TA	232	}
91cfbd4e	233	arch_initcall(exynos4_pm_init_power_domain);