[linux-2.6-block.git] / arch / arm / mach-exynos / firmware.c

/*
 * Copyright (C) 2012 Samsung Electronics.
 * Kyungmin Park <kyungmin.park@samsung.com>
 * Tomasz Figa <t.figa@samsung.com>
 *
 * This program is free software,you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_address.h>

#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <asm/firmware.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/suspend.h>

#include <mach/map.h>

#include "common.h"
#include "smc.h"

#define EXYNOS_BOOT_ADDR	0x8
#define EXYNOS_BOOT_FLAG	0xc

static void exynos_save_cp15(void)
{
	/* Save Power control and Diagnostic registers */
	asm ("mrc p15, 0, %0, c15, c0, 0\n"
	     "mrc p15, 0, %1, c15, c0, 1\n"
	     : "=r" (cp15_save_power), "=r" (cp15_save_diag)
	     : : "cc");
}

static int exynos_do_idle(unsigned long mode)
{
	switch (mode) {
	case FW_DO_IDLE_AFTR:
		if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
			exynos_save_cp15();
		__raw_writel(virt_to_phys(exynos_cpu_resume_ns),
			     sysram_ns_base_addr + 0x24);
		__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
		if (soc_is_exynos3250()) {
			flush_cache_all();
			exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
				   SMC_POWERSTATE_IDLE, 0);
			exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
				   SMC_POWERSTATE_IDLE, 0);
		} else
			exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
		break;
	case FW_DO_IDLE_SLEEP:
		exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
	}
	return 0;
}

static int exynos_cpu_boot(int cpu)
{
	/*
	 * Exynos3250 doesn't need to send smc command for secondary CPU boot
	 * because Exynos3250 removes WFE in secure mode.
	 */
	if (soc_is_exynos3250())
		return 0;

	/*
	 * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
	 * But, Exynos4212 has only one secondary CPU so second parameter
	 * isn't used for informing secure firmware about CPU id.
	 */
	if (soc_is_exynos4212())
		cpu = 0;

	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
	return 0;
}

static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
{
	void __iomem *boot_reg;

	if (!sysram_ns_base_addr)
		return -ENODEV;

	boot_reg = sysram_ns_base_addr + 0x1c;

	/*
	 * Almost all Exynos-series of SoCs that run in secure mode don't need
	 * additional offset for every CPU, with Exynos4412 being the only
	 * exception.
	 */
	if (soc_is_exynos4412())
		boot_reg += 4 * cpu;

	__raw_writel(boot_addr, boot_reg);
	return 0;
}

static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr)
{
	void __iomem *boot_reg;

	if (!sysram_ns_base_addr)
		return -ENODEV;

	boot_reg = sysram_ns_base_addr + 0x1c;

	if (soc_is_exynos4412())
		boot_reg += 4 * cpu;

	*boot_addr = __raw_readl(boot_reg);
	return 0;
}

static int exynos_cpu_suspend(unsigned long arg)
{
	flush_cache_all();
	outer_flush_all();

	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);

	pr_info("Failed to suspend the system\n");
	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	return 1;
}

static int exynos_suspend(void)
{
	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
		exynos_save_cp15();

	writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	writel(virt_to_phys(exynos_cpu_resume_ns),
		sysram_ns_base_addr + EXYNOS_BOOT_ADDR);

	return cpu_suspend(0, exynos_cpu_suspend);
}

static int exynos_resume(void)
{
	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);

	return 0;
}

static const struct firmware_ops exynos_firmware_ops = {
	.do_idle		= IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL,
	.set_cpu_boot_addr	= exynos_set_cpu_boot_addr,
	.get_cpu_boot_addr	= exynos_get_cpu_boot_addr,
	.cpu_boot		= exynos_cpu_boot,
	.suspend		= IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL,
	.resume			= IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL,
};

static void exynos_l2_write_sec(unsigned long val, unsigned reg)
{
	static int l2cache_enabled;

	switch (reg) {
	case L2X0_CTRL:
		if (val & L2X0_CTRL_EN) {
			/*
			 * Before the cache can be enabled, due to firmware
			 * design, SMC_CMD_L2X0INVALL must be called.
			 */
			if (!l2cache_enabled) {
				exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
				l2cache_enabled = 1;
			}
		} else {
			l2cache_enabled = 0;
		}
		exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
		break;

	case L2X0_DEBUG_CTRL:
		exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
		break;

	default:
		WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
	}
}

static void exynos_l2_configure(const struct l2x0_regs *regs)
{
	exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
		   regs->prefetch_ctrl);
	exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
}

void __init exynos_firmware_init(void)
{
	struct device_node *nd;
	const __be32 *addr;

	nd = of_find_compatible_node(NULL, NULL,
					"samsung,secure-firmware");
	if (!nd)
		return;

	addr = of_get_address(nd, 0, NULL, NULL);
	if (!addr) {
		pr_err("%s: No address specified.\n", __func__);
		return;
	}

	pr_info("Running under secure firmware.\n");

	register_firmware_ops(&exynos_firmware_ops);

	/*
	 * Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
	 * running under secure firmware, require certain registers of L2
	 * cache controller to be written in secure mode. Here .write_sec
	 * callback is provided to perform necessary SMC calls.
	 */
	if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
	    read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
		outer_cache.write_sec = exynos_l2_write_sec;
		outer_cache.configure = exynos_l2_configure;
	}
}

#define REG_CPU_STATE_ADDR	(sysram_ns_base_addr + 0x28)
#define BOOT_MODE_MASK		0x1f

void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
{
	unsigned int tmp;

	tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);

	if (mode & BOOT_MODE_MASK)
		tmp &= ~BOOT_MODE_MASK;

	tmp |= mode;
	__raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
}

void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
{
	unsigned int tmp;

	tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
	tmp &= ~mode;
	__raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
}
Commit	Line	Data
bca28f8f TF	1	/*
	2	* Copyright (C) 2012 Samsung Electronics.
	3	* Kyungmin Park <kyungmin.park@samsung.com>
	4	* Tomasz Figa <t.figa@samsung.com>
	5	*
	6	* This program is free software,you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/kernel.h>
	12	#include <linux/io.h>
	13	#include <linux/init.h>
	14	#include <linux/of.h>
	15	#include <linux/of_address.h>
	16
2b9d9c32 TF	17	#include <asm/cacheflush.h>
2b9d9c32 TF	18	#include <asm/cputype.h>
bca28f8f	19	#include <asm/firmware.h>
5445b640	20	#include <asm/hardware/cache-l2x0.h>
2b9d9c32	21	#include <asm/suspend.h>
bca28f8f TF	22
	23	#include <mach/map.h>
	24
b3205dea	25	#include "common.h"
bca28f8f TF	26	#include "smc.h"
bca28f8f TF	27
2b9d9c32 TF	28	#define EXYNOS_BOOT_ADDR 0x8
	29	#define EXYNOS_BOOT_FLAG 0xc
	30
a135e201 BZ	31	static void exynos_save_cp15(void)
	32	{
	33	/* Save Power control and Diagnostic registers */
	34	asm ("mrc p15, 0, %0, c15, c0, 0\n"
	35	"mrc p15, 0, %1, c15, c0, 1\n"
	36	: "=r" (cp15_save_power), "=r" (cp15_save_diag)
	37	: : "cc");
	38	}
	39
0b7778a8	40	static int exynos_do_idle(unsigned long mode)
bca28f8f	41	{
0b7778a8 BZ	42	switch (mode) {
0b7778a8 BZ	43	case FW_DO_IDLE_AFTR:
a135e201 BZ	44	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
	45	exynos_save_cp15();
	46	__raw_writel(virt_to_phys(exynos_cpu_resume_ns),
	47	sysram_ns_base_addr + 0x24);
	48	__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
89366409	49	if (soc_is_exynos3250()) {
af997114	50	flush_cache_all();
89366409 BZ	51	exynos_smc(SMC_CMD_SAVE, OP_TYPE_CORE,
	52	SMC_POWERSTATE_IDLE, 0);
	53	exynos_smc(SMC_CMD_SHUTDOWN, OP_TYPE_CLUSTER,
	54	SMC_POWERSTATE_IDLE, 0);
	55	} else
	56	exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
0b7778a8 BZ	57	break;
	58	case FW_DO_IDLE_SLEEP:
	59	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
	60	}
bca28f8f TF	61	return 0;
	62	}
	63
	64	static int exynos_cpu_boot(int cpu)
	65	{
6457158a CC	66	/*
	67	* Exynos3250 doesn't need to send smc command for secondary CPU boot
	68	* because Exynos3250 removes WFE in secure mode.
	69	*/
	70	if (soc_is_exynos3250())
	71	return 0;
	72
989ff3fd KP	73	/*
	74	* The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
	75	* But, Exynos4212 has only one secondary CPU so second parameter
	76	* isn't used for informing secure firmware about CPU id.
	77	*/
	78	if (soc_is_exynos4212())
	79	cpu = 0;
	80
bca28f8f TF	81	exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
	82	return 0;
	83	}
	84
	85	static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
	86	{
b3205dea SK	87	void __iomem *boot_reg;
	88
	89	if (!sysram_ns_base_addr)
	90	return -ENODEV;
	91
fe388fac	92	boot_reg = sysram_ns_base_addr + 0x1c;
989ff3fd	93
35e75645 SK	94	/*
	95	* Almost all Exynos-series of SoCs that run in secure mode don't need
	96	* additional offset for every CPU, with Exynos4412 being the only
	97	* exception.
	98	*/
	99	if (soc_is_exynos4412())
	100	boot_reg += 4 * cpu;
bca28f8f TF	101
	102	__raw_writel(boot_addr, boot_reg);
	103	return 0;
	104	}
	105
1225ad72 BZ	106	static int exynos_get_cpu_boot_addr(int cpu, unsigned long *boot_addr)
	107	{
	108	void __iomem *boot_reg;
	109
	110	if (!sysram_ns_base_addr)
	111	return -ENODEV;
	112
	113	boot_reg = sysram_ns_base_addr + 0x1c;
	114
	115	if (soc_is_exynos4412())
	116	boot_reg += 4 * cpu;
	117
	118	*boot_addr = __raw_readl(boot_reg);
	119	return 0;
	120	}
	121
2b9d9c32 TF	122	static int exynos_cpu_suspend(unsigned long arg)
	123	{
	124	flush_cache_all();
	125	outer_flush_all();
	126
	127	exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
	128
	129	pr_info("Failed to suspend the system\n");
	130	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	131	return 1;
	132	}
	133
	134	static int exynos_suspend(void)
	135	{
a135e201 BZ	136	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
a135e201 BZ	137	exynos_save_cp15();
2b9d9c32 TF	138
	139	writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	140	writel(virt_to_phys(exynos_cpu_resume_ns),
	141	sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
	142
	143	return cpu_suspend(0, exynos_cpu_suspend);
	144	}
	145
	146	static int exynos_resume(void)
	147	{
	148	writel(0, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
	149
	150	return 0;
	151	}
	152
bca28f8f	153	static const struct firmware_ops exynos_firmware_ops = {
03c1b760	154	.do_idle = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_do_idle : NULL,
bca28f8f	155	.set_cpu_boot_addr = exynos_set_cpu_boot_addr,
1225ad72	156	.get_cpu_boot_addr = exynos_get_cpu_boot_addr,
bca28f8f	157	.cpu_boot = exynos_cpu_boot,
03c1b760 AB	158	.suspend = IS_ENABLED(CONFIG_PM_SLEEP) ? exynos_suspend : NULL,
03c1b760 AB	159	.resume = IS_ENABLED(CONFIG_EXYNOS_CPU_SUSPEND) ? exynos_resume : NULL,
bca28f8f TF	160	};
bca28f8f TF	161
5445b640 TF	162	static void exynos_l2_write_sec(unsigned long val, unsigned reg)
	163	{
	164	static int l2cache_enabled;
	165
	166	switch (reg) {
	167	case L2X0_CTRL:
	168	if (val & L2X0_CTRL_EN) {
	169	/*
	170	* Before the cache can be enabled, due to firmware
	171	* design, SMC_CMD_L2X0INVALL must be called.
	172	*/
	173	if (!l2cache_enabled) {
	174	exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
	175	l2cache_enabled = 1;
	176	}
	177	} else {
	178	l2cache_enabled = 0;
	179	}
	180	exynos_smc(SMC_CMD_L2X0CTRL, val, 0, 0);
	181	break;
	182
	183	case L2X0_DEBUG_CTRL:
	184	exynos_smc(SMC_CMD_L2X0DEBUG, val, 0, 0);
	185	break;
	186
	187	default:
	188	WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg);
	189	}
	190	}
	191
	192	static void exynos_l2_configure(const struct l2x0_regs *regs)
	193	{
	194	exynos_smc(SMC_CMD_L2X0SETUP1, regs->tag_latency, regs->data_latency,
	195	regs->prefetch_ctrl);
	196	exynos_smc(SMC_CMD_L2X0SETUP2, regs->pwr_ctrl, regs->aux_ctrl, 0);
	197	}
	198
bca28f8f TF	199	void __init exynos_firmware_init(void)
bca28f8f TF	200	{
4ee1cc79 TF	201	struct device_node *nd;
4ee1cc79 TF	202	const __be32 *addr;
bca28f8f	203
4ee1cc79 TF	204	nd = of_find_compatible_node(NULL, NULL,
	205	"samsung,secure-firmware");
	206	if (!nd)
	207	return;
bca28f8f	208
4ee1cc79 TF	209	addr = of_get_address(nd, 0, NULL, NULL);
	210	if (!addr) {
	211	pr_err("%s: No address specified.\n", __func__);
	212	return;
bca28f8f TF	213	}
	214
	215	pr_info("Running under secure firmware.\n");
	216
	217	register_firmware_ops(&exynos_firmware_ops);
5445b640 TF	218
	219	/*
	220	* Exynos 4 SoCs (based on Cortex A9 and equipped with L2C-310),
	221	* running under secure firmware, require certain registers of L2
	222	* cache controller to be written in secure mode. Here .write_sec
	223	* callback is provided to perform necessary SMC calls.
	224	*/
	225	if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
	226	read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
	227	outer_cache.write_sec = exynos_l2_write_sec;
	228	outer_cache.configure = exynos_l2_configure;
	229	}
bca28f8f	230	}
dc1b9448 BZ	231
	232	#define REG_CPU_STATE_ADDR (sysram_ns_base_addr + 0x28)
	233	#define BOOT_MODE_MASK 0x1f
	234
	235	void exynos_set_boot_flag(unsigned int cpu, unsigned int mode)
	236	{
	237	unsigned int tmp;
	238
	239	tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
	240
	241	if (mode & BOOT_MODE_MASK)
	242	tmp &= ~BOOT_MODE_MASK;
	243
	244	tmp \|= mode;
	245	__raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
	246	}
	247
	248	void exynos_clear_boot_flag(unsigned int cpu, unsigned int mode)
	249	{
	250	unsigned int tmp;
	251
	252	tmp = __raw_readl(REG_CPU_STATE_ADDR + cpu * 4);
	253	tmp &= ~mode;
	254	__raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4);
	255	}