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[ARM] 5592/1: ep93xx: cleanup platform header includes
[linux-2.6-block.git] / arch / arm / mach-ep93xx / core.c
CommitLineData
e7736d47
LB		 1/*
2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
3c9a071d 6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
e7736d47
LB		 7 *
8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9 * role in the ep93xx linux community.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 */
16
e7736d47
LB		 17#include <linux/kernel.h>
18#include <linux/init.h>
583ddafe 19#include <linux/platform_device.h>
e7736d47 20#include <linux/interrupt.h>
63890a0e 21#include <linux/dma-mapping.h>
e7736d47 22#include <linux/timex.h>
583ddafe
HS		 23#include <linux/io.h>
24#include <linux/gpio.h>
aee85fe8 25#include <linux/termios.h>
e7736d47 26#include <linux/amba/bus.h>
aee85fe8 27#include <linux/amba/serial.h>
d52a26a9
HS		 28#include <linux/i2c.h>
29#include <linux/i2c-gpio.h>
e7736d47 30
a09e64fb 31#include <mach/hardware.h>
e7736d47
LB		 32
33#include <asm/mach/map.h>
34#include <asm/mach/time.h>
35#include <asm/mach/irq.h>
36
37#include <asm/hardware/vic.h>
38
39
40/*************************************************************************
41 * Static I/O mappings that are needed for all EP93xx platforms
42 *************************************************************************/
43static struct map_desc ep93xx_io_desc[] __initdata = {
44 {
45 .virtual = EP93XX_AHB_VIRT_BASE,
46 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
47 .length = EP93XX_AHB_SIZE,
48 .type = MT_DEVICE,
49 }, {
50 .virtual = EP93XX_APB_VIRT_BASE,
51 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
52 .length = EP93XX_APB_SIZE,
53 .type = MT_DEVICE,
54 },
55};
56
57void __init ep93xx_map_io(void)
58{
59 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
60}
61
62
63/*************************************************************************
64 * Timer handling for EP93xx
65 *************************************************************************
66 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
67 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
68 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
69 * is free-running, and can't generate interrupts.
70 *
71 * The 508 kHz timers are ideal for use for the timer interrupt, as the
72 * most common values of HZ divide 508 kHz nicely. We pick one of the 16
73 * bit timers (timer 1) since we don't need more than 16 bits of reload
74 * value as long as HZ >= 8.
75 *
76 * The higher clock rate of timer 4 makes it a better choice than the
77 * other timers for use in gettimeoffset(), while the fact that it can't
78 * generate interrupts means we don't have to worry about not being able
79 * to use this timer for something else. We also use timer 4 for keeping
80 * track of lost jiffies.
81 */
82static unsigned int last_jiffy_time;
83
84#define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
85
d5565f76 86static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
e7736d47 87{
e7736d47 88 __raw_writel(1, EP93XX_TIMER1_CLEAR);
f869afab
LB		 89 while ((signed long)
90 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
e7736d47
LB		 91 >= TIMER4_TICKS_PER_JIFFY) {
92 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
0cd61b68 93 timer_tick();
e7736d47
LB		 94 }
95
e7736d47
LB		 96 return IRQ_HANDLED;
97}
98
99static struct irqaction ep93xx_timer_irq = {
100 .name = "ep93xx timer",
b30fabad 101 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
e7736d47
LB		 102 .handler = ep93xx_timer_interrupt,
103};
104
105static void __init ep93xx_timer_init(void)
106{
107 /* Enable periodic HZ timer. */
108 __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
a059e33c 109 __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
e7736d47
LB		 110 __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
111
112 /* Enable lost jiffy timer. */
113 __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
114
115 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
116}
117
118static unsigned long ep93xx_gettimeoffset(void)
119{
120 int offset;
121
122 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
123
124 /* Calculate (1000000 / 983040) * offset. */
125 return offset + (53 * offset / 3072);
126}
127
128struct sys_timer ep93xx_timer = {
129 .init = ep93xx_timer_init,
130 .offset = ep93xx_gettimeoffset,
131};
132
133
a8e19667
LB		 134/*************************************************************************
135 * GPIO handling for EP93xx
136 *************************************************************************/
271f5ca6
LB		 137static unsigned char gpio_int_unmasked[3];
138static unsigned char gpio_int_enabled[3];
4932e397
LB		 139static unsigned char gpio_int_type1[3];
140static unsigned char gpio_int_type2[3];
68ee3d83 141static unsigned char gpio_int_debounce[3];
bd20ff57 142
7ca72253
HVR		 143/* Port ordering is: A B F */
144static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
145static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
146static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
f69162ae 147static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
799a0600 148static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
7ca72253 149
b685004f 150void ep93xx_gpio_update_int_params(unsigned port)
bd20ff57 151{
7ca72253
HVR		 152 BUG_ON(port > 2);
153
154 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
bd20ff57 155
7ca72253
HVR		 156 __raw_writeb(gpio_int_type2[port],
157 EP93XX_GPIO_REG(int_type2_register_offset[port]));
bd20ff57 158
7ca72253
HVR		 159 __raw_writeb(gpio_int_type1[port],
160 EP93XX_GPIO_REG(int_type1_register_offset[port]));
bd20ff57 161
7ca72253
HVR		 162 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
163 EP93XX_GPIO_REG(int_en_register_offset[port]));
164}
bd20ff57 165
b685004f 166void ep93xx_gpio_int_mask(unsigned line)
a8e19667 167{
b685004f 168 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
a8e19667 169}
a8e19667 170
799a0600
HS		 171void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
172{
173 int line = irq_to_gpio(irq);
174 int port = line >> 3;
175 int port_mask = 1 << (line & 7);
176
177 if (enable)
68ee3d83 178 gpio_int_debounce[port] |= port_mask;
799a0600 179 else
68ee3d83 180 gpio_int_debounce[port] &= ~port_mask;
799a0600 181
68ee3d83 182 __raw_writeb(gpio_int_debounce[port],
799a0600
HS		 183 EP93XX_GPIO_REG(int_debounce_register_offset[port]));
184}
185EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
186
e7736d47
LB		 187/*************************************************************************
188 * EP93xx IRQ handling
189 *************************************************************************/
4932e397 190static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
bd20ff57
LB		 191{
192 unsigned char status;
193 int i;
194
195 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
196 for (i = 0; i < 8; i++) {
197 if (status & (1 << i)) {
7ca72253 198 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
d8aa0251 199 generic_handle_irq(gpio_irq);
bd20ff57
LB		 200 }
201 }
202
203 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
204 for (i = 0; i < 8; i++) {
205 if (status & (1 << i)) {
7ca72253
HVR		 206 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
207 desc = irq_desc + gpio_irq;
d8aa0251 208 generic_handle_irq(gpio_irq);
bd20ff57
LB		 209 }
210 }
211}
212
4932e397
LB		 213static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
214{
7ca72253
HVR		 215 /*
216 * map discontiguous hw irq range to continous sw irq range:
217 *
218 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
219 */
220 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
221 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
4932e397 222
d8aa0251 223 generic_handle_irq(gpio_irq);
4932e397
LB		 224}
225
3c9a071d
HVR		 226static void ep93xx_gpio_irq_ack(unsigned int irq)
227{
228 int line = irq_to_gpio(irq);
229 int port = line >> 3;
230 int port_mask = 1 << (line & 7);
231
6cab4860 232 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
3c9a071d 233 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
b685004f 234 ep93xx_gpio_update_int_params(port);
3c9a071d
HVR		 235 }
236
237 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
238}
239
4932e397 240static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
bd20ff57 241{
7ca72253 242 int line = irq_to_gpio(irq);
bd20ff57 243 int port = line >> 3;
7ca72253 244 int port_mask = 1 << (line & 7);
bd20ff57 245
6cab4860 246 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
3c9a071d
HVR		 247 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
248
7ca72253 249 gpio_int_unmasked[port] &= ~port_mask;
b685004f 250 ep93xx_gpio_update_int_params(port);
bd20ff57 251
7ca72253 252 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
bd20ff57
LB		 253}
254
4932e397 255static void ep93xx_gpio_irq_mask(unsigned int irq)
bd20ff57 256{
7ca72253 257 int line = irq_to_gpio(irq);
bd20ff57
LB		 258 int port = line >> 3;
259
271f5ca6 260 gpio_int_unmasked[port] &= ~(1 << (line & 7));
b685004f 261 ep93xx_gpio_update_int_params(port);
bd20ff57
LB		 262}
263
4932e397 264static void ep93xx_gpio_irq_unmask(unsigned int irq)
bd20ff57 265{
7ca72253 266 int line = irq_to_gpio(irq);
bd20ff57
LB		 267 int port = line >> 3;
268
271f5ca6 269 gpio_int_unmasked[port] |= 1 << (line & 7);
b685004f 270 ep93xx_gpio_update_int_params(port);
bd20ff57
LB		 271}
272
273
274/*
275 * gpio_int_type1 controls whether the interrupt is level (0) or
276 * edge (1) triggered, while gpio_int_type2 controls whether it
277 * triggers on low/falling (0) or high/rising (1).
278 */
4932e397 279static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
bd20ff57 280{
3c9a071d 281 struct irq_desc *desc = irq_desc + irq;
7ca72253
HVR		 282 const int gpio = irq_to_gpio(irq);
283 const int port = gpio >> 3;
284 const int port_mask = 1 << (gpio & 7);
bd20ff57 285
f8b6389b 286 gpio_direction_input(gpio);
bd20ff57 287
3c9a071d 288 switch (type) {
6cab4860 289 case IRQ_TYPE_EDGE_RISING:
7ca72253
HVR		 290 gpio_int_type1[port] |= port_mask;
291 gpio_int_type2[port] |= port_mask;
3c9a071d
HVR		 292 desc->handle_irq = handle_edge_irq;
293 break;
6cab4860 294 case IRQ_TYPE_EDGE_FALLING:
7ca72253
HVR		 295 gpio_int_type1[port] |= port_mask;
296 gpio_int_type2[port] &= ~port_mask;
3c9a071d
HVR		 297 desc->handle_irq = handle_edge_irq;
298 break;
6cab4860 299 case IRQ_TYPE_LEVEL_HIGH:
7ca72253
HVR		 300 gpio_int_type1[port] &= ~port_mask;
301 gpio_int_type2[port] |= port_mask;
3c9a071d
HVR		 302 desc->handle_irq = handle_level_irq;
303 break;
6cab4860 304 case IRQ_TYPE_LEVEL_LOW:
7ca72253
HVR		 305 gpio_int_type1[port] &= ~port_mask;
306 gpio_int_type2[port] &= ~port_mask;
3c9a071d
HVR		 307 desc->handle_irq = handle_level_irq;
308 break;
6cab4860 309 case IRQ_TYPE_EDGE_BOTH:
3c9a071d
HVR		 310 gpio_int_type1[port] |= port_mask;
311 /* set initial polarity based on current input level */
312 if (gpio_get_value(gpio))
313 gpio_int_type2[port] &= ~port_mask; /* falling */
314 else
315 gpio_int_type2[port] |= port_mask; /* rising */
316 desc->handle_irq = handle_edge_irq;
317 break;
318 default:
319 pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
320 type, gpio);
321 return -EINVAL;
4932e397 322 }
bd20ff57 323
3c9a071d
HVR		 324 gpio_int_enabled[port] |= port_mask;
325
326 desc->status &= ~IRQ_TYPE_SENSE_MASK;
327 desc->status |= type & IRQ_TYPE_SENSE_MASK;
328
b685004f 329 ep93xx_gpio_update_int_params(port);
bd20ff57
LB		 330
331 return 0;
332}
333
4932e397
LB		 334static struct irq_chip ep93xx_gpio_irq_chip = {
335 .name = "GPIO",
3c9a071d
HVR		 336 .ack = ep93xx_gpio_irq_ack,
337 .mask_ack = ep93xx_gpio_irq_mask_ack,
4932e397
LB		 338 .mask = ep93xx_gpio_irq_mask,
339 .unmask = ep93xx_gpio_irq_unmask,
340 .set_type = ep93xx_gpio_irq_type,
bd20ff57
LB		 341};
342
343
e7736d47
LB		 344void __init ep93xx_init_irq(void)
345{
7ca72253 346 int gpio_irq;
bd20ff57 347
c07f87f2
BD		 348 vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
349 vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
bd20ff57 350
7ca72253
HVR		 351 for (gpio_irq = gpio_to_irq(0);
352 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
353 set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
354 set_irq_handler(gpio_irq, handle_level_irq);
355 set_irq_flags(gpio_irq, IRQF_VALID);
bd20ff57 356 }
4932e397 357
bd20ff57 358 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
4932e397
LB		 359 set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
360 set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
361 set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
362 set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
363 set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
364 set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
365 set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
366 set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
e7736d47
LB		 367}
368
369
02239f0a
HS		 370/*************************************************************************
371 * EP93xx System Controller Software Locked register handling
372 *************************************************************************/
373
374/*
375 * syscon_swlock prevents anything else from writing to the syscon
376 * block while a software locked register is being written.
377 */
378static DEFINE_SPINLOCK(syscon_swlock);
379
380void ep93xx_syscon_swlocked_write(unsigned int val, unsigned int reg)
381{
382 unsigned long flags;
383
384 spin_lock_irqsave(&syscon_swlock, flags);
385
386 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
387 __raw_writel(val, reg);
388
389 spin_unlock_irqrestore(&syscon_swlock, flags);
390}
391EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
392
393void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
394{
395 unsigned long flags;
396 unsigned int val;
397
398 spin_lock_irqsave(&syscon_swlock, flags);
399
400 val = __raw_readl(EP93XX_SYSCON_DEVCFG);
401 val |= set_bits;
402 val &= ~clear_bits;
403 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
404 __raw_writel(val, EP93XX_SYSCON_DEVCFG);
405
406 spin_unlock_irqrestore(&syscon_swlock, flags);
407}
408EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
409
410
e7736d47
LB		 411/*************************************************************************
412 * EP93xx peripheral handling
413 *************************************************************************/
aee85fe8
LB		 414#define EP93XX_UART_MCR_OFFSET (0x0100)
415
416static void ep93xx_uart_set_mctrl(struct amba_device *dev,
417 void __iomem *base, unsigned int mctrl)
418{
419 unsigned int mcr;
420
421 mcr = 0;
422 if (!(mctrl & TIOCM_RTS))
423 mcr |= 2;
424 if (!(mctrl & TIOCM_DTR))
425 mcr |= 1;
426
427 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
428}
429
430static struct amba_pl010_data ep93xx_uart_data = {
431 .set_mctrl = ep93xx_uart_set_mctrl,
432};
433
434static struct amba_device uart1_device = {
435 .dev = {
1d559e29 436 .init_name = "apb:uart1",
aee85fe8
LB		 437 .platform_data = &ep93xx_uart_data,
438 },
439 .res = {
440 .start = EP93XX_UART1_PHYS_BASE,
441 .end = EP93XX_UART1_PHYS_BASE + 0x0fff,
442 .flags = IORESOURCE_MEM,
443 },
444 .irq = { IRQ_EP93XX_UART1, NO_IRQ },
445 .periphid = 0x00041010,
446};
447
448static struct amba_device uart2_device = {
449 .dev = {
1d559e29 450 .init_name = "apb:uart2",
aee85fe8
LB		 451 .platform_data = &ep93xx_uart_data,
452 },
453 .res = {
454 .start = EP93XX_UART2_PHYS_BASE,
455 .end = EP93XX_UART2_PHYS_BASE + 0x0fff,
456 .flags = IORESOURCE_MEM,
457 },
458 .irq = { IRQ_EP93XX_UART2, NO_IRQ },
459 .periphid = 0x00041010,
460};
461
462static struct amba_device uart3_device = {
463 .dev = {
1d559e29 464 .init_name = "apb:uart3",
aee85fe8
LB		 465 .platform_data = &ep93xx_uart_data,
466 },
467 .res = {
468 .start = EP93XX_UART3_PHYS_BASE,
469 .end = EP93XX_UART3_PHYS_BASE + 0x0fff,
470 .flags = IORESOURCE_MEM,
471 },
472 .irq = { IRQ_EP93XX_UART3, NO_IRQ },
473 .periphid = 0x00041010,
474};
475
41658132 476
38f7b009
HS		 477static struct resource ep93xx_rtc_resource[] = {
478 {
479 .start = EP93XX_RTC_PHYS_BASE,
480 .end = EP93XX_RTC_PHYS_BASE + 0x10c - 1,
481 .flags = IORESOURCE_MEM,
482 },
483};
484
41658132 485static struct platform_device ep93xx_rtc_device = {
38f7b009
HS		 486 .name = "ep93xx-rtc",
487 .id = -1,
488 .num_resources = ARRAY_SIZE(ep93xx_rtc_resource),
489 .resource = ep93xx_rtc_resource,
41658132
LB		 490};
491
492
1f64eb37
LB		 493static struct resource ep93xx_ohci_resources[] = {
494 [0] = {
495 .start = EP93XX_USB_PHYS_BASE,
496 .end = EP93XX_USB_PHYS_BASE + 0x0fff,
497 .flags = IORESOURCE_MEM,
498 },
499 [1] = {
500 .start = IRQ_EP93XX_USB,
501 .end = IRQ_EP93XX_USB,
502 .flags = IORESOURCE_IRQ,
503 },
504};
505
63890a0e 506
1f64eb37
LB		 507static struct platform_device ep93xx_ohci_device = {
508 .name = "ep93xx-ohci",
509 .id = -1,
510 .dev = {
63890a0e
MK		 511 .dma_mask = &ep93xx_ohci_device.dev.coherent_dma_mask,
512 .coherent_dma_mask = DMA_BIT_MASK(32),
1f64eb37
LB		 513 },
514 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
515 .resource = ep93xx_ohci_resources,
516};
517
a0a08fdc
HS		 518static struct ep93xx_eth_data ep93xx_eth_data;
519
520static struct resource ep93xx_eth_resource[] = {
521 {
522 .start = EP93XX_ETHERNET_PHYS_BASE,
523 .end = EP93XX_ETHERNET_PHYS_BASE + 0xffff,
524 .flags = IORESOURCE_MEM,
525 }, {
526 .start = IRQ_EP93XX_ETHERNET,
527 .end = IRQ_EP93XX_ETHERNET,
528 .flags = IORESOURCE_IRQ,
529 }
530};
531
532static struct platform_device ep93xx_eth_device = {
533 .name = "ep93xx-eth",
534 .id = -1,
535 .dev = {
536 .platform_data = &ep93xx_eth_data,
537 },
538 .num_resources = ARRAY_SIZE(ep93xx_eth_resource),
539 .resource = ep93xx_eth_resource,
540};
541
542void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
543{
544 if (copy_addr) {
545 memcpy(data->dev_addr,
546 (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
547 }
548
549 ep93xx_eth_data = *data;
550 platform_device_register(&ep93xx_eth_device);
551}
552
d52a26a9
HS		 553static struct i2c_gpio_platform_data ep93xx_i2c_data = {
554 .sda_pin = EP93XX_GPIO_LINE_EEDAT,
555 .sda_is_open_drain = 0,
556 .scl_pin = EP93XX_GPIO_LINE_EECLK,
557 .scl_is_open_drain = 0,
558 .udelay = 2,
559};
560
561static struct platform_device ep93xx_i2c_device = {
562 .name = "i2c-gpio",
563 .id = 0,
564 .dev.platform_data = &ep93xx_i2c_data,
565};
566
567void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
568{
569 i2c_register_board_info(0, devices, num);
570 platform_device_register(&ep93xx_i2c_device);
571}
572
b685004f 573extern void ep93xx_gpio_init(void);
1f64eb37 574
e7736d47
LB		 575void __init ep93xx_init_devices(void)
576{
02239f0a
HS		 577 /* Disallow access to MaverickCrunch initially */
578 ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
aee85fe8 579
b685004f
RM		 580 ep93xx_gpio_init();
581
aee85fe8
LB		 582 amba_device_register(&uart1_device, &iomem_resource);
583 amba_device_register(&uart2_device, &iomem_resource);
584 amba_device_register(&uart3_device, &iomem_resource);
41658132
LB		 585
586 platform_device_register(&ep93xx_rtc_device);
1f64eb37 587 platform_device_register(&ep93xx_ohci_device);
e7736d47 588}
Linux 6.x block layer and io_uring tree(s)