Commit | Line | Data |
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83f53220 | 1 | /* |
5526b3f7 | 2 | * Utility to set the DAVINCI MUX register from a table in mux.h |
83f53220 VB |
3 | * |
4 | * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> | |
5 | * | |
5526b3f7 KH |
6 | * Based on linux/arch/arm/plat-omap/mux.c: |
7 | * Copyright (C) 2003 - 2005 Nokia Corporation | |
8 | * | |
9 | * Written by Tony Lindgren | |
10 | * | |
83f53220 VB |
11 | * 2007 (c) MontaVista Software, Inc. This file is licensed under |
12 | * the terms of the GNU General Public License version 2. This program | |
13 | * is licensed "as is" without any warranty of any kind, whether express | |
14 | * or implied. | |
5526b3f7 KH |
15 | * |
16 | * Copyright (C) 2008 Texas Instruments. | |
83f53220 | 17 | */ |
a7ca2bcf JP |
18 | |
19 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
20 | ||
83f53220 | 21 | #include <linux/io.h> |
5526b3f7 | 22 | #include <linux/module.h> |
83f53220 VB |
23 | #include <linux/spinlock.h> |
24 | ||
a09e64fb | 25 | #include <mach/mux.h> |
0e585952 | 26 | #include <mach/common.h> |
83f53220 | 27 | |
779b0d53 CC |
28 | static void __iomem *pinmux_base; |
29 | ||
5526b3f7 KH |
30 | /* |
31 | * Sets the DAVINCI MUX register based on the table | |
32 | */ | |
31612d64 | 33 | int davinci_cfg_reg(const unsigned long index) |
83f53220 | 34 | { |
5526b3f7 | 35 | static DEFINE_SPINLOCK(mux_spin_lock); |
0e585952 | 36 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
5526b3f7 KH |
37 | unsigned long flags; |
38 | const struct mux_config *cfg; | |
39 | unsigned int reg_orig = 0, reg = 0; | |
40 | unsigned int mask, warn = 0; | |
41 | ||
779b0d53 CC |
42 | if (WARN_ON(!soc_info->pinmux_pins)) |
43 | return -ENODEV; | |
44 | ||
45 | if (!pinmux_base) { | |
46 | pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K); | |
47 | if (WARN_ON(!pinmux_base)) | |
48 | return -ENOMEM; | |
49 | } | |
5526b3f7 | 50 | |
0e585952 | 51 | if (index >= soc_info->pinmux_pins_num) { |
a7ca2bcf | 52 | pr_err("Invalid pin mux index: %lu (%lu)\n", |
0e585952 | 53 | index, soc_info->pinmux_pins_num); |
5526b3f7 KH |
54 | dump_stack(); |
55 | return -ENODEV; | |
56 | } | |
57 | ||
0e585952 | 58 | cfg = &soc_info->pinmux_pins[index]; |
5526b3f7 KH |
59 | |
60 | if (cfg->name == NULL) { | |
a7ca2bcf | 61 | pr_err("No entry for the specified index\n"); |
5526b3f7 KH |
62 | return -ENODEV; |
63 | } | |
64 | ||
65 | /* Update the mux register in question */ | |
66 | if (cfg->mask) { | |
67 | unsigned tmp1, tmp2; | |
68 | ||
69 | spin_lock_irqsave(&mux_spin_lock, flags); | |
779b0d53 | 70 | reg_orig = __raw_readl(pinmux_base + cfg->mux_reg); |
5526b3f7 KH |
71 | |
72 | mask = (cfg->mask << cfg->mask_offset); | |
73 | tmp1 = reg_orig & mask; | |
74 | reg = reg_orig & ~mask; | |
75 | ||
76 | tmp2 = (cfg->mode << cfg->mask_offset); | |
77 | reg |= tmp2; | |
78 | ||
79 | if (tmp1 != tmp2) | |
80 | warn = 1; | |
81 | ||
779b0d53 | 82 | __raw_writel(reg, pinmux_base + cfg->mux_reg); |
5526b3f7 KH |
83 | spin_unlock_irqrestore(&mux_spin_lock, flags); |
84 | } | |
85 | ||
86 | if (warn) { | |
87 | #ifdef CONFIG_DAVINCI_MUX_WARNINGS | |
a7ca2bcf | 88 | pr_warn("initialized %s\n", cfg->name); |
5526b3f7 KH |
89 | #endif |
90 | } | |
83f53220 | 91 | |
5526b3f7 KH |
92 | #ifdef CONFIG_DAVINCI_MUX_DEBUG |
93 | if (cfg->debug || warn) { | |
a7ca2bcf JP |
94 | pr_warn("Setting register %s\n", cfg->name); |
95 | pr_warn(" %s (0x%08x) = 0x%08x -> 0x%08x\n", | |
96 | cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg); | |
83f53220 | 97 | } |
5526b3f7 | 98 | #endif |
83f53220 | 99 | |
5526b3f7 | 100 | return 0; |
83f53220 | 101 | } |
5526b3f7 | 102 | EXPORT_SYMBOL(davinci_cfg_reg); |
c96b56c5 | 103 | |
31612d64 | 104 | int davinci_cfg_reg_list(const short pins[]) |
c96b56c5 SR |
105 | { |
106 | int i, error = -EINVAL; | |
107 | ||
108 | if (pins) | |
109 | for (i = 0; pins[i] >= 0; i++) { | |
110 | error = davinci_cfg_reg(pins[i]); | |
111 | if (error) | |
112 | break; | |
113 | } | |
114 | ||
115 | return error; | |
116 | } |