[linux-2.6-block.git] / arch / arm / mach-davinci / include / mach / mux.h

/*
 * Table of the DAVINCI register configurations for the PINMUX combinations
 *
 * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
 *
 * Based on linux/include/asm-arm/arch-omap/mux.h:
 * Copyright (C) 2003 - 2005 Nokia Corporation
 *
 * Written by Tony Lindgren
 *
 * 2007 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * Copyright (C) 2008 Texas Instruments.
 */

#ifndef __INC_MACH_MUX_H
#define __INC_MACH_MUX_H

struct mux_config {
	const char *name;
	const char *mux_reg_name;
	const unsigned char mux_reg;
	const unsigned char mask_offset;
	const unsigned char mask;
	const unsigned char mode;
	bool debug;
};

enum davinci_dm644x_index {
	/* ATA and HDDIR functions */
	DM644X_HDIREN,
	DM644X_ATAEN,
	DM644X_ATAEN_DISABLE,

	/* HPI functions */
	DM644X_HPIEN_DISABLE,

	/* AEAW functions */
	DM644X_AEAW,

	/* Memory Stick */
	DM644X_MSTK,

	/* I2C */
	DM644X_I2C,

	/* ASP function */
	DM644X_MCBSP,

	/* UART1 */
	DM644X_UART1,

	/* UART2 */
	DM644X_UART2,

	/* PWM0 */
	DM644X_PWM0,

	/* PWM1 */
	DM644X_PWM1,

	/* PWM2 */
	DM644X_PWM2,

	/* VLYNQ function */
	DM644X_VLYNQEN,
	DM644X_VLSCREN,
	DM644X_VLYNQWD,

	/* EMAC and MDIO function */
	DM644X_EMACEN,

	/* GPIO3V[0:16] pins */
	DM644X_GPIO3V,

	/* GPIO pins */
	DM644X_GPIO0,
	DM644X_GPIO3,
	DM644X_GPIO43_44,
	DM644X_GPIO46_47,

	/* VPBE */
	DM644X_RGB666,

	/* LCD */
	DM644X_LOEEN,
	DM644X_LFLDEN,
};

enum davinci_dm646x_index {
	/* ATA function */
	DM646X_ATAEN,

	/* AUDIO Clock */
	DM646X_AUDCK1,
	DM646X_AUDCK0,

	/* CRGEN Control */
	DM646X_CRGMUX,

	/* VPIF Control */
	DM646X_STSOMUX_DISABLE,
	DM646X_STSIMUX_DISABLE,
	DM646X_PTSOMUX_DISABLE,
	DM646X_PTSIMUX_DISABLE,

	/* TSIF Control */
	DM646X_STSOMUX,
	DM646X_STSIMUX,
	DM646X_PTSOMUX_PARALLEL,
	DM646X_PTSIMUX_PARALLEL,
	DM646X_PTSOMUX_SERIAL,
	DM646X_PTSIMUX_SERIAL,
};

enum davinci_dm355_index {
	/* MMC/SD 0 */
	DM355_MMCSD0,

	/* MMC/SD 1 */
	DM355_SD1_CLK,
	DM355_SD1_CMD,
	DM355_SD1_DATA3,
	DM355_SD1_DATA2,
	DM355_SD1_DATA1,
	DM355_SD1_DATA0,

	/* I2C */
	DM355_I2C_SDA,
	DM355_I2C_SCL,

	/* ASP0 function */
	DM355_MCBSP0_BDX,
	DM355_MCBSP0_X,
	DM355_MCBSP0_BFSX,
	DM355_MCBSP0_BDR,
	DM355_MCBSP0_R,
	DM355_MCBSP0_BFSR,

	/* SPI0 */
	DM355_SPI0_SDI,
	DM355_SPI0_SDENA0,
	DM355_SPI0_SDENA1,

	/* IRQ muxing */
	DM355_INT_EDMA_CC,
	DM355_INT_EDMA_TC0_ERR,
	DM355_INT_EDMA_TC1_ERR,

	/* EDMA event muxing */
	DM355_EVT8_ASP1_TX,
	DM355_EVT9_ASP1_RX,
	DM355_EVT26_MMC0_RX,
};

enum davinci_dm365_index {
	/* MMC/SD 0 */
	DM365_MMCSD0,

	/* MMC/SD 1 */
	DM365_SD1_CLK,
	DM365_SD1_CMD,
	DM365_SD1_DATA3,
	DM365_SD1_DATA2,
	DM365_SD1_DATA1,
	DM365_SD1_DATA0,

	/* I2C */
	DM365_I2C_SDA,
	DM365_I2C_SCL,

	/* AEMIF */
	DM365_AEMIF_AR,
	DM365_AEMIF_A3,
	DM365_AEMIF_A7,
	DM365_AEMIF_D15_8,
	DM365_AEMIF_CE0,

	/* ASP0 function */
	DM365_MCBSP0_BDX,
	DM365_MCBSP0_X,
	DM365_MCBSP0_BFSX,
	DM365_MCBSP0_BDR,
	DM365_MCBSP0_R,
	DM365_MCBSP0_BFSR,

	/* SPI0 */
	DM365_SPI0_SCLK,
	DM365_SPI0_SDI,
	DM365_SPI0_SDO,
	DM365_SPI0_SDENA0,
	DM365_SPI0_SDENA1,

	/* UART */
	DM365_UART0_RXD,
	DM365_UART0_TXD,
	DM365_UART1_RXD,
	DM365_UART1_TXD,
	DM365_UART1_RTS,
	DM365_UART1_CTS,

	/* EMAC */
	DM365_EMAC_TX_EN,
	DM365_EMAC_TX_CLK,
	DM365_EMAC_COL,
	DM365_EMAC_TXD3,
	DM365_EMAC_TXD2,
	DM365_EMAC_TXD1,
	DM365_EMAC_TXD0,
	DM365_EMAC_RXD3,
	DM365_EMAC_RXD2,
	DM365_EMAC_RXD1,
	DM365_EMAC_RXD0,
	DM365_EMAC_RX_CLK,
	DM365_EMAC_RX_DV,
	DM365_EMAC_RX_ER,
	DM365_EMAC_CRS,
	DM365_EMAC_MDIO,
	DM365_EMAC_MDCLK,

	/* IRQ muxing */
	DM365_INT_EDMA_CC,
	DM365_INT_EDMA_TC0_ERR,
	DM365_INT_EDMA_TC1_ERR,
	DM365_INT_PRTCSS,
	DM365_INT_EMAC_RXTHRESH,
	DM365_INT_EMAC_RXPULSE,
	DM365_INT_EMAC_TXPULSE,
	DM365_INT_EMAC_MISCPULSE,

	/* EDMA event muxing */
	DM365_EVT2_ASP_TX,
	DM365_EVT3_ASP_RX,
	DM365_EVT26_MMC0_RX,
};

#ifdef CONFIG_DAVINCI_MUX
/* setup pin muxing */
extern int davinci_cfg_reg(unsigned long reg_cfg);
#else
/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
#endif

#endif /* __INC_MACH_MUX_H */
Commit	Line	Data
83f53220	1	/*
5526b3f7	2	* Table of the DAVINCI register configurations for the PINMUX combinations
83f53220 VB	3	*
	4	* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
	5	*
5526b3f7 KH	6	* Based on linux/include/asm-arm/arch-omap/mux.h:
	7	* Copyright (C) 2003 - 2005 Nokia Corporation
	8	*
	9	* Written by Tony Lindgren
	10	*
83f53220 VB	11	* 2007 (c) MontaVista Software, Inc. This file is licensed under
	12	* the terms of the GNU General Public License version 2. This program
	13	* is licensed "as is" without any warranty of any kind, whether express
	14	* or implied.
5526b3f7 KH	15	*
5526b3f7 KH	16	* Copyright (C) 2008 Texas Instruments.
83f53220	17	*/
5526b3f7 KH	18
	19	#ifndef __INC_MACH_MUX_H
	20	#define __INC_MACH_MUX_H
	21
5526b3f7 KH	22	struct mux_config {
	23	const char *name;
	24	const char *mux_reg_name;
	25	const unsigned char mux_reg;
	26	const unsigned char mask_offset;
	27	const unsigned char mask;
	28	const unsigned char mode;
	29	bool debug;
	30	};
	31
	32	enum davinci_dm644x_index {
	33	/* ATA and HDDIR functions */
	34	DM644X_HDIREN,
	35	DM644X_ATAEN,
	36	DM644X_ATAEN_DISABLE,
	37
	38	/* HPI functions */
	39	DM644X_HPIEN_DISABLE,
	40
	41	/* AEAW functions */
	42	DM644X_AEAW,
	43
	44	/* Memory Stick */
	45	DM644X_MSTK,
	46
	47	/* I2C */
	48	DM644X_I2C,
	49
	50	/* ASP function */
	51	DM644X_MCBSP,
	52
	53	/* UART1 */
	54	DM644X_UART1,
	55
	56	/* UART2 */
	57	DM644X_UART2,
	58
	59	/* PWM0 */
	60	DM644X_PWM0,
	61
	62	/* PWM1 */
	63	DM644X_PWM1,
	64
	65	/* PWM2 */
	66	DM644X_PWM2,
	67
	68	/* VLYNQ function */
	69	DM644X_VLYNQEN,
	70	DM644X_VLSCREN,
	71	DM644X_VLYNQWD,
	72
	73	/* EMAC and MDIO function */
	74	DM644X_EMACEN,
	75
	76	/* GPIO3V[0:16] pins */
	77	DM644X_GPIO3V,
	78
	79	/* GPIO pins */
	80	DM644X_GPIO0,
	81	DM644X_GPIO3,
	82	DM644X_GPIO43_44,
	83	DM644X_GPIO46_47,
	84
	85	/* VPBE */
86	DM644X_RGB666,
87
88	/* LCD */
89	DM644X_LOEEN,
90	DM644X_LFLDEN,
91	};
92
93	enum davinci_dm646x_index {
94	/* ATA function */
95	DM646X_ATAEN,
96
97	/* AUDIO Clock */
98	DM646X_AUDCK1,
99	DM646X_AUDCK0,
100
101	/* CRGEN Control */
102	DM646X_CRGMUX,
103
104	/* VPIF Control */
105	DM646X_STSOMUX_DISABLE,
106	DM646X_STSIMUX_DISABLE,
107	DM646X_PTSOMUX_DISABLE,
108	DM646X_PTSIMUX_DISABLE,
109
110	/* TSIF Control */
111	DM646X_STSOMUX,
112	DM646X_STSIMUX,
113	DM646X_PTSOMUX_PARALLEL,
114	DM646X_PTSIMUX_PARALLEL,
115	DM646X_PTSOMUX_SERIAL,
116	DM646X_PTSIMUX_SERIAL,
117	};
118
119	enum davinci_dm355_index {
120	/* MMC/SD 0 */
121	DM355_MMCSD0,
122
123	/* MMC/SD 1 */
124	DM355_SD1_CLK,
125	DM355_SD1_CMD,
126	DM355_SD1_DATA3,
127	DM355_SD1_DATA2,
128	DM355_SD1_DATA1,
129	DM355_SD1_DATA0,
130
131	/* I2C */
132	DM355_I2C_SDA,
133	DM355_I2C_SCL,
134
135	/* ASP0 function */
136	DM355_MCBSP0_BDX,
137	DM355_MCBSP0_X,
138	DM355_MCBSP0_BFSX,
139	DM355_MCBSP0_BDR,
140	DM355_MCBSP0_R,
141	DM355_MCBSP0_BFSR,
142
143	/* SPI0 */
144	DM355_SPI0_SDI,
145	DM355_SPI0_SDENA0,
146	DM355_SPI0_SDENA1,
147
148	/* IRQ muxing */
149	DM355_INT_EDMA_CC,
150	DM355_INT_EDMA_TC0_ERR,
151	DM355_INT_EDMA_TC1_ERR,
152
153	/* EDMA event muxing */
154	DM355_EVT8_ASP1_TX,
155	DM355_EVT9_ASP1_RX,
156	DM355_EVT26_MMC0_RX,
157	};
158
fb8fcb89 SP	159	enum davinci_dm365_index {
	160	/* MMC/SD 0 */
	161	DM365_MMCSD0,
	162
	163	/* MMC/SD 1 */
	164	DM365_SD1_CLK,
	165	DM365_SD1_CMD,
	166	DM365_SD1_DATA3,
	167	DM365_SD1_DATA2,
	168	DM365_SD1_DATA1,
	169	DM365_SD1_DATA0,
	170
	171	/* I2C */
	172	DM365_I2C_SDA,
	173	DM365_I2C_SCL,
	174
	175	/* AEMIF */
	176	DM365_AEMIF_AR,
	177	DM365_AEMIF_A3,
	178	DM365_AEMIF_A7,
	179	DM365_AEMIF_D15_8,
	180	DM365_AEMIF_CE0,
	181
	182	/* ASP0 function */
	183	DM365_MCBSP0_BDX,
	184	DM365_MCBSP0_X,
	185	DM365_MCBSP0_BFSX,
	186	DM365_MCBSP0_BDR,
	187	DM365_MCBSP0_R,
	188	DM365_MCBSP0_BFSR,
	189
	190	/* SPI0 */
	191	DM365_SPI0_SCLK,
	192	DM365_SPI0_SDI,
	193	DM365_SPI0_SDO,
	194	DM365_SPI0_SDENA0,
	195	DM365_SPI0_SDENA1,
	196
	197	/* UART */
	198	DM365_UART0_RXD,
	199	DM365_UART0_TXD,
	200	DM365_UART1_RXD,
	201	DM365_UART1_TXD,
	202	DM365_UART1_RTS,
	203	DM365_UART1_CTS,
	204
	205	/* EMAC */
	206	DM365_EMAC_TX_EN,
	207	DM365_EMAC_TX_CLK,
	208	DM365_EMAC_COL,
	209	DM365_EMAC_TXD3,
	210	DM365_EMAC_TXD2,
	211	DM365_EMAC_TXD1,
	212	DM365_EMAC_TXD0,
	213	DM365_EMAC_RXD3,
	214	DM365_EMAC_RXD2,
	215	DM365_EMAC_RXD1,
	216	DM365_EMAC_RXD0,
	217	DM365_EMAC_RX_CLK,
	218	DM365_EMAC_RX_DV,
	219	DM365_EMAC_RX_ER,
	220	DM365_EMAC_CRS,
	221	DM365_EMAC_MDIO,
	222	DM365_EMAC_MDCLK,
223
224	/* IRQ muxing */
225	DM365_INT_EDMA_CC,
226	DM365_INT_EDMA_TC0_ERR,
227	DM365_INT_EDMA_TC1_ERR,
228	DM365_INT_PRTCSS,
229	DM365_INT_EMAC_RXTHRESH,
230	DM365_INT_EMAC_RXPULSE,
231	DM365_INT_EMAC_TXPULSE,
232	DM365_INT_EMAC_MISCPULSE,
233
234	/* EDMA event muxing */
235	DM365_EVT2_ASP_TX,
236	DM365_EVT3_ASP_RX,
237	DM365_EVT26_MMC0_RX,
238	};
239
5526b3f7 KH	240	#ifdef CONFIG_DAVINCI_MUX
5526b3f7 KH	241	/* setup pin muxing */
5526b3f7 KH	242	extern int davinci_cfg_reg(unsigned long reg_cfg);
	243	#else
	244	/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
5526b3f7 KH	245	static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
	246	#endif
	247
	248	#endif /* __INC_MACH_MUX_H */