[linux-2.6-block.git] / arch / arm / mach-davinci / gpio.c

/*
 * TI DaVinci GPIO Support
 *
 * Copyright (c) 2006-2007 David Brownell
 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>

#include <mach/gpio.h>

#include <asm/mach/irq.h>

struct davinci_gpio_regs {
	u32	dir;
	u32	out_data;
	u32	set_data;
	u32	clr_data;
	u32	in_data;
	u32	set_rising;
	u32	clr_rising;
	u32	set_falling;
	u32	clr_falling;
	u32	intstat;
};

#define chip2controller(chip)	\
	container_of(chip, struct davinci_gpio_controller, chip)

static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
static void __iomem *gpio_base;

static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
{
	void __iomem *ptr;

	if (gpio < 32 * 1)
		ptr = gpio_base + 0x10;
	else if (gpio < 32 * 2)
		ptr = gpio_base + 0x38;
	else if (gpio < 32 * 3)
		ptr = gpio_base + 0x60;
	else if (gpio < 32 * 4)
		ptr = gpio_base + 0x88;
	else if (gpio < 32 * 5)
		ptr = gpio_base + 0xb0;
	else
		ptr = NULL;
	return ptr;
}

static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
{
	struct davinci_gpio_regs __iomem *g;

	g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);

	return g;
}

static int __init davinci_gpio_irq_setup(void);

/*--------------------------------------------------------------------------*/

/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
static inline int __davinci_direction(struct gpio_chip *chip,
			unsigned offset, bool out, int value)
{
	struct davinci_gpio_controller *d = chip2controller(chip);
	struct davinci_gpio_regs __iomem *g = d->regs;
	unsigned long flags;
	u32 temp;
	u32 mask = 1 << offset;

	spin_lock_irqsave(&d->lock, flags);
	temp = __raw_readl(&g->dir);
	if (out) {
		temp &= ~mask;
		__raw_writel(mask, value ? &g->set_data : &g->clr_data);
	} else {
		temp |= mask;
	}
	__raw_writel(temp, &g->dir);
	spin_unlock_irqrestore(&d->lock, flags);

	return 0;
}

static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
{
	return __davinci_direction(chip, offset, false, 0);
}

static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
	return __davinci_direction(chip, offset, true, value);
}

/*
 * Read the pin's value (works even if it's set up as output);
 * returns zero/nonzero.
 *
 * Note that changes are synched to the GPIO clock, so reading values back
 * right after you've set them may give old values.
 */
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio_controller *d = chip2controller(chip);
	struct davinci_gpio_regs __iomem *g = d->regs;

	return (1 << offset) & __raw_readl(&g->in_data);
}

/*
 * Assuming the pin is muxed as a gpio output, set its output value.
 */
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct davinci_gpio_controller *d = chip2controller(chip);
	struct davinci_gpio_regs __iomem *g = d->regs;

	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
}

static int __init davinci_gpio_setup(void)
{
	int i, base;
	unsigned ngpio;
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	struct davinci_gpio_regs *regs;

	if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
		return 0;

	/*
	 * The gpio banks conceptually expose a segmented bitmap,
	 * and "ngpio" is one more than the largest zero-based
	 * bit index that's valid.
	 */
	ngpio = soc_info->gpio_num;
	if (ngpio == 0) {
		pr_err("GPIO setup:  how many GPIOs?\n");
		return -EINVAL;
	}

	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
		ngpio = DAVINCI_N_GPIO;

	gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
	if (WARN_ON(!gpio_base))
		return -ENOMEM;

	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
		chips[i].chip.label = "DaVinci";

		chips[i].chip.direction_input = davinci_direction_in;
		chips[i].chip.get = davinci_gpio_get;
		chips[i].chip.direction_output = davinci_direction_out;
		chips[i].chip.set = davinci_gpio_set;

		chips[i].chip.base = base;
		chips[i].chip.ngpio = ngpio - base;
		if (chips[i].chip.ngpio > 32)
			chips[i].chip.ngpio = 32;

		spin_lock_init(&chips[i].lock);

		regs = gpio2regs(base);
		chips[i].regs = regs;
		chips[i].set_data = &regs->set_data;
		chips[i].clr_data = &regs->clr_data;
		chips[i].in_data = &regs->in_data;

		gpiochip_add(&chips[i].chip);
	}

	soc_info->gpio_ctlrs = chips;
	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);

	davinci_gpio_irq_setup();
	return 0;
}
pure_initcall(davinci_gpio_setup);

/*--------------------------------------------------------------------------*/
/*
 * We expect irqs will normally be set up as input pins, but they can also be
 * used as output pins ... which is convenient for testing.
 *
 * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 * to their GPIOBNK0 irq, with a bit less overhead.
 *
 * All those INTC hookups (direct, plus several IRQ banks) can also
 * serve as EDMA event triggers.
 */

static void gpio_irq_disable(struct irq_data *d)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
	u32 mask = (u32) irq_data_get_irq_handler_data(d);

	__raw_writel(mask, &g->clr_falling);
	__raw_writel(mask, &g->clr_rising);
}

static void gpio_irq_enable(struct irq_data *d)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
	u32 mask = (u32) irq_data_get_irq_handler_data(d);
	unsigned status = irqd_get_trigger_type(d);

	status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
	if (!status)
		status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;

	if (status & IRQ_TYPE_EDGE_FALLING)
		__raw_writel(mask, &g->set_falling);
	if (status & IRQ_TYPE_EDGE_RISING)
		__raw_writel(mask, &g->set_rising);
}

static int gpio_irq_type(struct irq_data *d, unsigned trigger)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
	u32 mask = (u32) irq_data_get_irq_handler_data(d);

	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	return 0;
}

static struct irq_chip gpio_irqchip = {
	.name		= "GPIO",
	.irq_enable	= gpio_irq_enable,
	.irq_disable	= gpio_irq_disable,
	.irq_set_type	= gpio_irq_type,
	.flags		= IRQCHIP_SET_TYPE_MASKED,
};

static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct davinci_gpio_regs __iomem *g;
	u32 mask = 0xffff;
	struct davinci_gpio_controller *d;

	d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
	g = (struct davinci_gpio_regs __iomem *)d->regs;

	/* we only care about one bank */
	if (irq & 1)
		mask <<= 16;

	/* temporarily mask (level sensitive) parent IRQ */
	desc->irq_data.chip->irq_mask(&desc->irq_data);
	desc->irq_data.chip->irq_ack(&desc->irq_data);
	while (1) {
		u32		status;
		int		n;
		int		res;

		/* ack any irqs */
		status = __raw_readl(&g->intstat) & mask;
		if (!status)
			break;
		__raw_writel(status, &g->intstat);

		/* now demux them to the right lowlevel handler */
		n = d->irq_base;
		if (irq & 1) {
			n += 16;
			status >>= 16;
		}

		while (status) {
			res = ffs(status);
			n += res;
			generic_handle_irq(n - 1);
			status >>= res;
		}
	}
	desc->irq_data.chip->irq_unmask(&desc->irq_data);
	/* now it may re-trigger */
}

static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio_controller *d = chip2controller(chip);

	if (d->irq_base >= 0)
		return d->irq_base + offset;
	else
		return -ENODEV;
}

static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	/* NOTE:  we assume for now that only irqs in the first gpio_chip
	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	 */
	if (offset < soc_info->gpio_unbanked)
		return soc_info->gpio_irq + offset;
	else
		return -ENODEV;
}

static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
	u32 mask = (u32) irq_data_get_irq_handler_data(d);

	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
		     ? &g->set_falling : &g->clr_falling);
	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
		     ? &g->set_rising : &g->clr_rising);

	return 0;
}

/*
 * NOTE:  for suspend/resume, probably best to make a platform_device with
 * suspend_late/resume_resume calls hooking into results of the set_wake()
 * calls ... so if no gpios are wakeup events the clock can be disabled,
 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 * (dm6446) can be set appropriately for GPIOV33 pins.
 */

static int __init davinci_gpio_irq_setup(void)
{
	unsigned	gpio, irq, bank;
	struct clk	*clk;
	u32		binten = 0;
	unsigned	ngpio, bank_irq;
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	struct davinci_gpio_regs	__iomem *g;

	ngpio = soc_info->gpio_num;

	bank_irq = soc_info->gpio_irq;
	if (bank_irq == 0) {
		printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
		return -EINVAL;
	}

	clk = clk_get(NULL, "gpio");
	if (IS_ERR(clk)) {
		printk(KERN_ERR "Error %ld getting gpio clock?\n",
		       PTR_ERR(clk));
		return PTR_ERR(clk);
	}
	clk_enable(clk);

	/* Arrange gpio_to_irq() support, handling either direct IRQs or
	 * banked IRQs.  Having GPIOs in the first GPIO bank use direct
	 * IRQs, while the others use banked IRQs, would need some setup
	 * tweaks to recognize hardware which can do that.
	 */
	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
		chips[bank].chip.to_irq = gpio_to_irq_banked;
		chips[bank].irq_base = soc_info->gpio_unbanked
			? -EINVAL
			: (soc_info->intc_irq_num + gpio);
	}

	/*
	 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	 * controller only handling trigger modes.  We currently assume no
	 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	 */
	if (soc_info->gpio_unbanked) {
		static struct irq_chip gpio_irqchip_unbanked;

		/* pass "bank 0" GPIO IRQs to AINTC */
		chips[0].chip.to_irq = gpio_to_irq_unbanked;
		binten = BIT(0);

		/* AINTC handles mask/unmask; GPIO handles triggering */
		irq = bank_irq;
		gpio_irqchip_unbanked = *irq_get_chip(irq);
		gpio_irqchip_unbanked.name = "GPIO-AINTC";
		gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;

		/* default trigger: both edges */
		g = gpio2regs(0);
		__raw_writel(~0, &g->set_falling);
		__raw_writel(~0, &g->set_rising);

		/* set the direct IRQs up to use that irqchip */
		for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
			irq_set_chip(irq, &gpio_irqchip_unbanked);
			irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
			irq_set_chip_data(irq, (__force void *)g);
			irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
		}

		goto done;
	}

	/*
	 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	 * then chain through our own handler.
	 */
	for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
			gpio < ngpio;
			bank++, bank_irq++) {
		unsigned		i;

		/* disabled by default, enabled only as needed */
		g = gpio2regs(gpio);
		__raw_writel(~0, &g->clr_falling);
		__raw_writel(~0, &g->clr_rising);

		/* set up all irqs in this bank */
		irq_set_chained_handler(bank_irq, gpio_irq_handler);

		/*
		 * Each chip handles 32 gpios, and each irq bank consists of 16
		 * gpio irqs. Pass the irq bank's corresponding controller to
		 * the chained irq handler.
		 */
		irq_set_handler_data(bank_irq, &chips[gpio / 32]);

		for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
			irq_set_chip(irq, &gpio_irqchip);
			irq_set_chip_data(irq, (__force void *)g);
			irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
			irq_set_handler(irq, handle_simple_irq);
			set_irq_flags(irq, IRQF_VALID);
		}

		binten |= BIT(bank);
	}

done:
	/* BINTEN -- per-bank interrupt enable. genirq would also let these
	 * bits be set/cleared dynamically.
	 */
	__raw_writel(binten, gpio_base + 0x08);

	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));

	return 0;
}
Commit	Line	Data
3d9edf09 VB	1	/*
	2	* TI DaVinci GPIO Support
	3	*
dce1115b	4	* Copyright (c) 2006-2007 David Brownell
3d9edf09 VB	5	* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
	13	#include <linux/errno.h>
	14	#include <linux/kernel.h>
3d9edf09 VB	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
3d9edf09	18
a09e64fb	19	#include <mach/gpio.h>
3d9edf09 VB	20
	21	#include <asm/mach/irq.h>
	22
c12f415a CC	23	struct davinci_gpio_regs {
	24	u32 dir;
	25	u32 out_data;
	26	u32 set_data;
	27	u32 clr_data;
	28	u32 in_data;
	29	u32 set_rising;
	30	u32 clr_rising;
	31	u32 set_falling;
	32	u32 clr_falling;
	33	u32 intstat;
	34	};
	35
ba4a984e	36	#define chip2controller(chip) \
99e9e52d	37	container_of(chip, struct davinci_gpio_controller, chip)
ba4a984e	38
99e9e52d	39	static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
b8d44293	40	static void __iomem *gpio_base;
3d9edf09	41
99e9e52d	42	static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
3d9edf09	43	{
c12f415a	44	void __iomem *ptr;
c12f415a CC	45
c12f415a CC	46	if (gpio < 32 * 1)
b8d44293	47	ptr = gpio_base + 0x10;
c12f415a	48	else if (gpio < 32 * 2)
b8d44293	49	ptr = gpio_base + 0x38;
c12f415a	50	else if (gpio < 32 * 3)
b8d44293	51	ptr = gpio_base + 0x60;
c12f415a	52	else if (gpio < 32 * 4)
b8d44293	53	ptr = gpio_base + 0x88;
c12f415a	54	else if (gpio < 32 * 5)
b8d44293	55	ptr = gpio_base + 0xb0;
c12f415a CC	56	else
	57	ptr = NULL;
	58	return ptr;
3d9edf09 VB	59	}
3d9edf09 VB	60
99e9e52d	61	static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
21ce873d	62	{
99e9e52d	63	struct davinci_gpio_regs __iomem *g;
21ce873d	64
6845664a	65	g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
21ce873d KH	66
	67	return g;
	68	}
	69
dc756026	70	static int __init davinci_gpio_irq_setup(void);
dce1115b DB	71
	72	/--------------------------------------------------------------------------/
	73
5b3a05ca	74	/* board setup code MUST setup pinmux and enable the GPIO clock. */
ba4a984e CC	75	static inline int __davinci_direction(struct gpio_chip *chip,
ba4a984e CC	76	unsigned offset, bool out, int value)
3d9edf09	77	{
99e9e52d CC	78	struct davinci_gpio_controller *d = chip2controller(chip);
99e9e52d CC	79	struct davinci_gpio_regs __iomem *g = d->regs;
b27b6d03	80	unsigned long flags;
dce1115b	81	u32 temp;
ba4a984e	82	u32 mask = 1 << offset;
3d9edf09	83
b27b6d03	84	spin_lock_irqsave(&d->lock, flags);
dce1115b	85	temp = __raw_readl(&g->dir);
ba4a984e CC	86	if (out) {
	87	temp &= ~mask;
	88	__raw_writel(mask, value ? &g->set_data : &g->clr_data);
	89	} else {
	90	temp \|= mask;
	91	}
dce1115b	92	__raw_writel(temp, &g->dir);
b27b6d03	93	spin_unlock_irqrestore(&d->lock, flags);
3d9edf09	94
dce1115b DB	95	return 0;
dce1115b DB	96	}
3d9edf09	97
ba4a984e CC	98	static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
	99	{
	100	return __davinci_direction(chip, offset, false, 0);
	101	}
	102
	103	static int
	104	davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
	105	{
	106	return __davinci_direction(chip, offset, true, value);
	107	}
	108
3d9edf09 VB	109	/*
	110	* Read the pin's value (works even if it's set up as output);
	111	* returns zero/nonzero.
	112	*
	113	* Note that changes are synched to the GPIO clock, so reading values back
	114	* right after you've set them may give old values.
	115	*/
dce1115b	116	static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
3d9edf09	117	{
99e9e52d CC	118	struct davinci_gpio_controller *d = chip2controller(chip);
99e9e52d CC	119	struct davinci_gpio_regs __iomem *g = d->regs;
3d9edf09	120
dce1115b	121	return (1 << offset) & __raw_readl(&g->in_data);
3d9edf09	122	}
3d9edf09	123
dce1115b DB	124	/*
	125	* Assuming the pin is muxed as a gpio output, set its output value.
	126	*/
	127	static void
	128	davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3d9edf09	129	{
99e9e52d CC	130	struct davinci_gpio_controller *d = chip2controller(chip);
99e9e52d CC	131	struct davinci_gpio_regs __iomem *g = d->regs;
3d9edf09	132
dce1115b DB	133	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
	134	}
	135
	136	static int __init davinci_gpio_setup(void)
	137	{
	138	int i, base;
a994955c MG	139	unsigned ngpio;
a994955c MG	140	struct davinci_soc_info *soc_info = &davinci_soc_info;
c12f415a	141	struct davinci_gpio_regs *regs;
dce1115b	142
686b634a CC	143	if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
	144	return 0;
	145
a994955c MG	146	/*
a994955c MG	147	* The gpio banks conceptually expose a segmented bitmap,
474dad54 DB	148	* and "ngpio" is one more than the largest zero-based
	149	* bit index that's valid.
	150	*/
a994955c MG	151	ngpio = soc_info->gpio_num;
a994955c MG	152	if (ngpio == 0) {
474dad54 DB	153	pr_err("GPIO setup: how many GPIOs?\n");
	154	return -EINVAL;
	155	}
	156
	157	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
	158	ngpio = DAVINCI_N_GPIO;
	159
b8d44293 CC	160	gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
	161	if (WARN_ON(!gpio_base))
	162	return -ENOMEM;
	163
474dad54	164	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
dce1115b DB	165	chips[i].chip.label = "DaVinci";
	166
	167	chips[i].chip.direction_input = davinci_direction_in;
	168	chips[i].chip.get = davinci_gpio_get;
	169	chips[i].chip.direction_output = davinci_direction_out;
	170	chips[i].chip.set = davinci_gpio_set;
	171
	172	chips[i].chip.base = base;
474dad54	173	chips[i].chip.ngpio = ngpio - base;
dce1115b DB	174	if (chips[i].chip.ngpio > 32)
	175	chips[i].chip.ngpio = 32;
	176
b27b6d03 CC	177	spin_lock_init(&chips[i].lock);
b27b6d03 CC	178
c12f415a CC	179	regs = gpio2regs(base);
	180	chips[i].regs = regs;
	181	chips[i].set_data = &regs->set_data;
	182	chips[i].clr_data = &regs->clr_data;
	183	chips[i].in_data = &regs->in_data;
dce1115b DB	184
	185	gpiochip_add(&chips[i].chip);
	186	}
3d9edf09	187
c12f415a CC	188	soc_info->gpio_ctlrs = chips;
	189	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
	190
dc756026	191	davinci_gpio_irq_setup();
3d9edf09 VB	192	return 0;
3d9edf09 VB	193	}
dce1115b	194	pure_initcall(davinci_gpio_setup);
3d9edf09	195
dce1115b	196	/--------------------------------------------------------------------------/
3d9edf09 VB	197	/*
	198	* We expect irqs will normally be set up as input pins, but they can also be
	199	* used as output pins ... which is convenient for testing.
	200	*
474dad54	201	* NOTE: The first few GPIOs also have direct INTC hookups in addition
7a36071e	202	* to their GPIOBNK0 irq, with a bit less overhead.
3d9edf09	203	*
474dad54	204	* All those INTC hookups (direct, plus several IRQ banks) can also
3d9edf09 VB	205	* serve as EDMA event triggers.
	206	*/
	207
23265442	208	static void gpio_irq_disable(struct irq_data *d)
3d9edf09	209	{
23265442	210	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
6845664a	211	u32 mask = (u32) irq_data_get_irq_handler_data(d);
3d9edf09 VB	212
	213	__raw_writel(mask, &g->clr_falling);
	214	__raw_writel(mask, &g->clr_rising);
	215	}
	216
23265442	217	static void gpio_irq_enable(struct irq_data *d)
3d9edf09	218	{
23265442	219	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
6845664a	220	u32 mask = (u32) irq_data_get_irq_handler_data(d);
5093aec8	221	unsigned status = irqd_get_trigger_type(d);
3d9edf09	222
df4aab46 DB	223	status &= IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	224	if (!status)
	225	status = IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	226
	227	if (status & IRQ_TYPE_EDGE_FALLING)
3d9edf09	228	__raw_writel(mask, &g->set_falling);
df4aab46	229	if (status & IRQ_TYPE_EDGE_RISING)
3d9edf09 VB	230	__raw_writel(mask, &g->set_rising);
	231	}
	232
23265442	233	static int gpio_irq_type(struct irq_data *d, unsigned trigger)
3d9edf09	234	{
23265442	235	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
6845664a	236	u32 mask = (u32) irq_data_get_irq_handler_data(d);
3d9edf09 VB	237
	238	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	239	return -EINVAL;
	240
3d9edf09 VB	241	return 0;
	242	}
	243
	244	static struct irq_chip gpio_irqchip = {
	245	.name = "GPIO",
23265442 LB	246	.irq_enable = gpio_irq_enable,
	247	.irq_disable = gpio_irq_disable,
	248	.irq_set_type = gpio_irq_type,
5093aec8	249	.flags = IRQCHIP_SET_TYPE_MASKED,
3d9edf09 VB	250	};
	251
	252	static void
	253	gpio_irq_handler(unsigned irq, struct irq_desc *desc)
	254	{
74164016	255	struct davinci_gpio_regs __iomem *g;
3d9edf09	256	u32 mask = 0xffff;
f299bb95	257	struct davinci_gpio_controller *d;
3d9edf09	258
f299bb95 IY	259	d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
f299bb95 IY	260	g = (struct davinci_gpio_regs __iomem *)d->regs;
74164016	261
3d9edf09 VB	262	/* we only care about one bank */
	263	if (irq & 1)
	264	mask <<= 16;
	265
	266	/* temporarily mask (level sensitive) parent IRQ */
23265442 LB	267	desc->irq_data.chip->irq_mask(&desc->irq_data);
23265442 LB	268	desc->irq_data.chip->irq_ack(&desc->irq_data);
3d9edf09 VB	269	while (1) {
3d9edf09 VB	270	u32 status;
3d9edf09 VB	271	int n;
	272	int res;
	273
	274	/* ack any irqs */
	275	status = __raw_readl(&g->intstat) & mask;
	276	if (!status)
	277	break;
	278	__raw_writel(status, &g->intstat);
3d9edf09 VB	279
3d9edf09 VB	280	/* now demux them to the right lowlevel handler */
f299bb95 IY	281	n = d->irq_base;
	282	if (irq & 1) {
	283	n += 16;
	284	status >>= 16;
	285	}
	286
3d9edf09 VB	287	while (status) {
	288	res = ffs(status);
	289	n += res;
d8aa0251	290	generic_handle_irq(n - 1);
3d9edf09 VB	291	status >>= res;
	292	}
	293	}
23265442	294	desc->irq_data.chip->irq_unmask(&desc->irq_data);
3d9edf09 VB	295	/* now it may re-trigger */
	296	}
	297
7a36071e DB	298	static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
7a36071e DB	299	{
99e9e52d	300	struct davinci_gpio_controller *d = chip2controller(chip);
7a36071e DB	301
	302	if (d->irq_base >= 0)
	303	return d->irq_base + offset;
	304	else
	305	return -ENODEV;
	306	}
	307
	308	static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
	309	{
	310	struct davinci_soc_info *soc_info = &davinci_soc_info;
	311
	312	/* NOTE: we assume for now that only irqs in the first gpio_chip
	313	* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	314	*/
	315	if (offset < soc_info->gpio_unbanked)
	316	return soc_info->gpio_irq + offset;
	317	else
	318	return -ENODEV;
	319	}
	320
23265442	321	static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
7a36071e	322	{
23265442	323	struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
6845664a	324	u32 mask = (u32) irq_data_get_irq_handler_data(d);
7a36071e DB	325
	326	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	327	return -EINVAL;
	328
	329	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
	330	? &g->set_falling : &g->clr_falling);
	331	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
	332	? &g->set_rising : &g->clr_rising);
	333
	334	return 0;
	335	}
	336
3d9edf09	337	/*
474dad54 DB	338	* NOTE: for suspend/resume, probably best to make a platform_device with
474dad54 DB	339	* suspend_late/resume_resume calls hooking into results of the set_wake()
3d9edf09 VB	340	* calls ... so if no gpios are wakeup events the clock can be disabled,
3d9edf09 VB	341	* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
474dad54	342	* (dm6446) can be set appropriately for GPIOV33 pins.
3d9edf09 VB	343	*/
	344
	345	static int __init davinci_gpio_irq_setup(void)
	346	{
	347	unsigned gpio, irq, bank;
	348	struct clk *clk;
474dad54	349	u32 binten = 0;
a994955c MG	350	unsigned ngpio, bank_irq;
a994955c MG	351	struct davinci_soc_info *soc_info = &davinci_soc_info;
99e9e52d	352	struct davinci_gpio_regs __iomem *g;
a994955c MG	353
a994955c MG	354	ngpio = soc_info->gpio_num;
474dad54	355
a994955c MG	356	bank_irq = soc_info->gpio_irq;
a994955c MG	357	if (bank_irq == 0) {
474dad54 DB	358	printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
	359	return -EINVAL;
	360	}
3d9edf09 VB	361
	362	clk = clk_get(NULL, "gpio");
	363	if (IS_ERR(clk)) {
	364	printk(KERN_ERR "Error %ld getting gpio clock?\n",
	365	PTR_ERR(clk));
474dad54	366	return PTR_ERR(clk);
3d9edf09	367	}
3d9edf09 VB	368	clk_enable(clk);
3d9edf09 VB	369
7a36071e DB	370	/* Arrange gpio_to_irq() support, handling either direct IRQs or
	371	* banked IRQs. Having GPIOs in the first GPIO bank use direct
	372	* IRQs, while the others use banked IRQs, would need some setup
	373	* tweaks to recognize hardware which can do that.
	374	*/
	375	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
	376	chips[bank].chip.to_irq = gpio_to_irq_banked;
	377	chips[bank].irq_base = soc_info->gpio_unbanked
	378	? -EINVAL
	379	: (soc_info->intc_irq_num + gpio);
	380	}
	381
	382	/*
	383	* AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	384	* controller only handling trigger modes. We currently assume no
	385	* IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	386	*/
	387	if (soc_info->gpio_unbanked) {
	388	static struct irq_chip gpio_irqchip_unbanked;
	389
	390	/* pass "bank 0" GPIO IRQs to AINTC */
	391	chips[0].chip.to_irq = gpio_to_irq_unbanked;
	392	binten = BIT(0);
	393
	394	/* AINTC handles mask/unmask; GPIO handles triggering */
	395	irq = bank_irq;
5093aec8	396	gpio_irqchip_unbanked = *irq_get_chip(irq);
7a36071e	397	gpio_irqchip_unbanked.name = "GPIO-AINTC";
23265442	398	gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
7a36071e DB	399
7a36071e DB	400	/* default trigger: both edges */
99e9e52d	401	g = gpio2regs(0);
7a36071e DB	402	__raw_writel(~0, &g->set_falling);
	403	__raw_writel(~0, &g->set_rising);
	404
	405	/* set the direct IRQs up to use that irqchip */
	406	for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
6845664a TG	407	irq_set_chip(irq, &gpio_irqchip_unbanked);
	408	irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
	409	irq_set_chip_data(irq, (__force void *)g);
5093aec8	410	irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
7a36071e DB	411	}
	412
	413	goto done;
	414	}
	415
	416	/*
	417	* Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	418	* then chain through our own handler.
	419	*/
474dad54 DB	420	for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
	421	gpio < ngpio;
	422	bank++, bank_irq++) {
3d9edf09 VB	423	unsigned i;
3d9edf09 VB	424
7a36071e	425	/* disabled by default, enabled only as needed */
99e9e52d	426	g = gpio2regs(gpio);
3d9edf09 VB	427	__raw_writel(~0, &g->clr_falling);
	428	__raw_writel(~0, &g->clr_rising);
	429
	430	/* set up all irqs in this bank */
6845664a	431	irq_set_chained_handler(bank_irq, gpio_irq_handler);
f299bb95 IY	432
	433	/*
	434	* Each chip handles 32 gpios, and each irq bank consists of 16
	435	* gpio irqs. Pass the irq bank's corresponding controller to
	436	* the chained irq handler.
	437	*/
	438	irq_set_handler_data(bank_irq, &chips[gpio / 32]);
3d9edf09	439
474dad54	440	for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
6845664a TG	441	irq_set_chip(irq, &gpio_irqchip);
	442	irq_set_chip_data(irq, (__force void *)g);
	443	irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
	444	irq_set_handler(irq, handle_simple_irq);
3d9edf09 VB	445	set_irq_flags(irq, IRQF_VALID);
3d9edf09 VB	446	}
474dad54 DB	447
474dad54 DB	448	binten \|= BIT(bank);
3d9edf09 VB	449	}
3d9edf09 VB	450
7a36071e	451	done:
3d9edf09 VB	452	/* BINTEN -- per-bank interrupt enable. genirq would also let these
	453	* bits be set/cleared dynamically.
	454	*/
b8d44293	455	__raw_writel(binten, gpio_base + 0x08);
3d9edf09 VB	456
	457	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
	458
	459	return 0;
	460	}