[linux-2.6-block.git] / arch / arm / mach-davinci / gpio.c

/*
 * TI DaVinci GPIO Support
 *
 * Copyright (c) 2006-2007 David Brownell
 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>

#include <mach/gpio.h>

#include <asm/mach/irq.h>

struct davinci_gpio_regs {
	u32	dir;
	u32	out_data;
	u32	set_data;
	u32	clr_data;
	u32	in_data;
	u32	set_rising;
	u32	clr_rising;
	u32	set_falling;
	u32	clr_falling;
	u32	intstat;
};

static DEFINE_SPINLOCK(gpio_lock);

#define chip2controller(chip)	\
	container_of(chip, struct davinci_gpio_controller, chip)

static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];

static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
{
	void __iomem *ptr;
	void __iomem *base = davinci_soc_info.gpio_base;

	if (gpio < 32 * 1)
		ptr = base + 0x10;
	else if (gpio < 32 * 2)
		ptr = base + 0x38;
	else if (gpio < 32 * 3)
		ptr = base + 0x60;
	else if (gpio < 32 * 4)
		ptr = base + 0x88;
	else if (gpio < 32 * 5)
		ptr = base + 0xb0;
	else
		ptr = NULL;
	return ptr;
}

static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
{
	struct davinci_gpio_regs __iomem *g;

	g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);

	return g;
}

static int __init davinci_gpio_irq_setup(void);

/*--------------------------------------------------------------------------*/

/*
 * board setup code *MUST* set PINMUX0 and PINMUX1 as
 * needed, and enable the GPIO clock.
 */

static inline int __davinci_direction(struct gpio_chip *chip,
			unsigned offset, bool out, int value)
{
	struct davinci_gpio_controller *d = chip2controller(chip);
	struct davinci_gpio_regs __iomem *g = d->regs;
	u32 temp;
	u32 mask = 1 << offset;

	spin_lock(&gpio_lock);
	temp = __raw_readl(&g->dir);
	if (out) {
		temp &= ~mask;
		__raw_writel(mask, value ? &g->set_data : &g->clr_data);
	} else {
		temp |= mask;
	}
	__raw_writel(temp, &g->dir);
	spin_unlock(&gpio_lock);

	return 0;
}

static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
{
	return __davinci_direction(chip, offset, false, 0);
}

static int
davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
{
	return __davinci_direction(chip, offset, true, value);
}

/*
 * Read the pin's value (works even if it's set up as output);
 * returns zero/nonzero.
 *
 * Note that changes are synched to the GPIO clock, so reading values back
 * right after you've set them may give old values.
 */
static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio_controller *d = chip2controller(chip);
	struct davinci_gpio_regs __iomem *g = d->regs;

	return (1 << offset) & __raw_readl(&g->in_data);
}

/*
 * Assuming the pin is muxed as a gpio output, set its output value.
 */
static void
davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct davinci_gpio_controller *d = chip2controller(chip);
	struct davinci_gpio_regs __iomem *g = d->regs;

	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
}

static int __init davinci_gpio_setup(void)
{
	int i, base;
	unsigned ngpio;
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	struct davinci_gpio_regs *regs;

	if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
		return 0;

	/*
	 * The gpio banks conceptually expose a segmented bitmap,
	 * and "ngpio" is one more than the largest zero-based
	 * bit index that's valid.
	 */
	ngpio = soc_info->gpio_num;
	if (ngpio == 0) {
		pr_err("GPIO setup:  how many GPIOs?\n");
		return -EINVAL;
	}

	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
		ngpio = DAVINCI_N_GPIO;

	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
		chips[i].chip.label = "DaVinci";

		chips[i].chip.direction_input = davinci_direction_in;
		chips[i].chip.get = davinci_gpio_get;
		chips[i].chip.direction_output = davinci_direction_out;
		chips[i].chip.set = davinci_gpio_set;

		chips[i].chip.base = base;
		chips[i].chip.ngpio = ngpio - base;
		if (chips[i].chip.ngpio > 32)
			chips[i].chip.ngpio = 32;

		regs = gpio2regs(base);
		chips[i].regs = regs;
		chips[i].set_data = &regs->set_data;
		chips[i].clr_data = &regs->clr_data;
		chips[i].in_data = &regs->in_data;

		gpiochip_add(&chips[i].chip);
	}

	soc_info->gpio_ctlrs = chips;
	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);

	davinci_gpio_irq_setup();
	return 0;
}
pure_initcall(davinci_gpio_setup);

/*--------------------------------------------------------------------------*/
/*
 * We expect irqs will normally be set up as input pins, but they can also be
 * used as output pins ... which is convenient for testing.
 *
 * NOTE:  The first few GPIOs also have direct INTC hookups in addition
 * to their GPIOBNK0 irq, with a bit less overhead.
 *
 * All those INTC hookups (direct, plus several IRQ banks) can also
 * serve as EDMA event triggers.
 */

static void gpio_irq_disable(unsigned irq)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
	u32 mask = (u32) get_irq_data(irq);

	__raw_writel(mask, &g->clr_falling);
	__raw_writel(mask, &g->clr_rising);
}

static void gpio_irq_enable(unsigned irq)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
	u32 mask = (u32) get_irq_data(irq);
	unsigned status = irq_desc[irq].status;

	status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
	if (!status)
		status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;

	if (status & IRQ_TYPE_EDGE_FALLING)
		__raw_writel(mask, &g->set_falling);
	if (status & IRQ_TYPE_EDGE_RISING)
		__raw_writel(mask, &g->set_rising);
}

static int gpio_irq_type(unsigned irq, unsigned trigger)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
	u32 mask = (u32) get_irq_data(irq);

	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
	irq_desc[irq].status |= trigger;

	/* don't enable the IRQ if it's currently disabled */
	if (irq_desc[irq].depth == 0) {
		__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
			     ? &g->set_falling : &g->clr_falling);
		__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
			     ? &g->set_rising : &g->clr_rising);
	}
	return 0;
}

static struct irq_chip gpio_irqchip = {
	.name		= "GPIO",
	.enable		= gpio_irq_enable,
	.disable	= gpio_irq_disable,
	.set_type	= gpio_irq_type,
};

static void
gpio_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
	u32 mask = 0xffff;

	/* we only care about one bank */
	if (irq & 1)
		mask <<= 16;

	/* temporarily mask (level sensitive) parent IRQ */
	desc->chip->mask(irq);
	desc->chip->ack(irq);
	while (1) {
		u32		status;
		int		n;
		int		res;

		/* ack any irqs */
		status = __raw_readl(&g->intstat) & mask;
		if (!status)
			break;
		__raw_writel(status, &g->intstat);
		if (irq & 1)
			status >>= 16;

		/* now demux them to the right lowlevel handler */
		n = (int)get_irq_data(irq);
		while (status) {
			res = ffs(status);
			n += res;
			generic_handle_irq(n - 1);
			status >>= res;
		}
	}
	desc->chip->unmask(irq);
	/* now it may re-trigger */
}

static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_gpio_controller *d = chip2controller(chip);

	if (d->irq_base >= 0)
		return d->irq_base + offset;
	else
		return -ENODEV;
}

static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
{
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	/* NOTE:  we assume for now that only irqs in the first gpio_chip
	 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	 */
	if (offset < soc_info->gpio_unbanked)
		return soc_info->gpio_irq + offset;
	else
		return -ENODEV;
}

static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
{
	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
	u32 mask = (u32) get_irq_data(irq);

	if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		return -EINVAL;

	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
		     ? &g->set_falling : &g->clr_falling);
	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
		     ? &g->set_rising : &g->clr_rising);

	return 0;
}

/*
 * NOTE:  for suspend/resume, probably best to make a platform_device with
 * suspend_late/resume_resume calls hooking into results of the set_wake()
 * calls ... so if no gpios are wakeup events the clock can be disabled,
 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
 * (dm6446) can be set appropriately for GPIOV33 pins.
 */

static int __init davinci_gpio_irq_setup(void)
{
	unsigned	gpio, irq, bank;
	struct clk	*clk;
	u32		binten = 0;
	unsigned	ngpio, bank_irq;
	struct davinci_soc_info *soc_info = &davinci_soc_info;
	struct davinci_gpio_regs	__iomem *g;

	ngpio = soc_info->gpio_num;

	bank_irq = soc_info->gpio_irq;
	if (bank_irq == 0) {
		printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
		return -EINVAL;
	}

	clk = clk_get(NULL, "gpio");
	if (IS_ERR(clk)) {
		printk(KERN_ERR "Error %ld getting gpio clock?\n",
		       PTR_ERR(clk));
		return PTR_ERR(clk);
	}
	clk_enable(clk);

	/* Arrange gpio_to_irq() support, handling either direct IRQs or
	 * banked IRQs.  Having GPIOs in the first GPIO bank use direct
	 * IRQs, while the others use banked IRQs, would need some setup
	 * tweaks to recognize hardware which can do that.
	 */
	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
		chips[bank].chip.to_irq = gpio_to_irq_banked;
		chips[bank].irq_base = soc_info->gpio_unbanked
			? -EINVAL
			: (soc_info->intc_irq_num + gpio);
	}

	/*
	 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	 * controller only handling trigger modes.  We currently assume no
	 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	 */
	if (soc_info->gpio_unbanked) {
		static struct irq_chip gpio_irqchip_unbanked;

		/* pass "bank 0" GPIO IRQs to AINTC */
		chips[0].chip.to_irq = gpio_to_irq_unbanked;
		binten = BIT(0);

		/* AINTC handles mask/unmask; GPIO handles triggering */
		irq = bank_irq;
		gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
		gpio_irqchip_unbanked.name = "GPIO-AINTC";
		gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;

		/* default trigger: both edges */
		g = gpio2regs(0);
		__raw_writel(~0, &g->set_falling);
		__raw_writel(~0, &g->set_rising);

		/* set the direct IRQs up to use that irqchip */
		for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
			set_irq_chip(irq, &gpio_irqchip_unbanked);
			set_irq_data(irq, (void *) __gpio_mask(gpio));
			set_irq_chip_data(irq, (__force void *) g);
			irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
		}

		goto done;
	}

	/*
	 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	 * then chain through our own handler.
	 */
	for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
			gpio < ngpio;
			bank++, bank_irq++) {
		unsigned		i;

		/* disabled by default, enabled only as needed */
		g = gpio2regs(gpio);
		__raw_writel(~0, &g->clr_falling);
		__raw_writel(~0, &g->clr_rising);

		/* set up all irqs in this bank */
		set_irq_chained_handler(bank_irq, gpio_irq_handler);
		set_irq_chip_data(bank_irq, (__force void *) g);
		set_irq_data(bank_irq, (void *) irq);

		for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
			set_irq_chip(irq, &gpio_irqchip);
			set_irq_chip_data(irq, (__force void *) g);
			set_irq_data(irq, (void *) __gpio_mask(gpio));
			set_irq_handler(irq, handle_simple_irq);
			set_irq_flags(irq, IRQF_VALID);
		}

		binten |= BIT(bank);
	}

done:
	/* BINTEN -- per-bank interrupt enable. genirq would also let these
	 * bits be set/cleared dynamically.
	 */
	__raw_writel(binten, soc_info->gpio_base + 0x08);

	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));

	return 0;
}
Commit	Line	Data
3d9edf09 VB	1	/*
	2	* TI DaVinci GPIO Support
	3	*
dce1115b	4	* Copyright (c) 2006-2007 David Brownell
3d9edf09 VB	5	* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
	13	#include <linux/errno.h>
	14	#include <linux/kernel.h>
3d9edf09 VB	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
3d9edf09	18
a09e64fb	19	#include <mach/gpio.h>
3d9edf09 VB	20
	21	#include <asm/mach/irq.h>
	22
c12f415a CC	23	struct davinci_gpio_regs {
	24	u32 dir;
	25	u32 out_data;
	26	u32 set_data;
	27	u32 clr_data;
	28	u32 in_data;
	29	u32 set_rising;
	30	u32 clr_rising;
	31	u32 set_falling;
	32	u32 clr_falling;
	33	u32 intstat;
	34	};
	35
dce1115b	36	static DEFINE_SPINLOCK(gpio_lock);
3d9edf09	37
ba4a984e	38	#define chip2controller(chip) \
99e9e52d	39	container_of(chip, struct davinci_gpio_controller, chip)
ba4a984e	40
99e9e52d	41	static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
3d9edf09	42
99e9e52d	43	static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
3d9edf09	44	{
c12f415a CC	45	void __iomem *ptr;
	46	void __iomem *base = davinci_soc_info.gpio_base;
	47
	48	if (gpio < 32 * 1)
	49	ptr = base + 0x10;
	50	else if (gpio < 32 * 2)
	51	ptr = base + 0x38;
	52	else if (gpio < 32 * 3)
	53	ptr = base + 0x60;
	54	else if (gpio < 32 * 4)
	55	ptr = base + 0x88;
	56	else if (gpio < 32 * 5)
	57	ptr = base + 0xb0;
	58	else
	59	ptr = NULL;
	60	return ptr;
3d9edf09 VB	61	}
3d9edf09 VB	62
99e9e52d	63	static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
21ce873d	64	{
99e9e52d	65	struct davinci_gpio_regs __iomem *g;
21ce873d	66
99e9e52d	67	g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
21ce873d KH	68
	69	return g;
	70	}
	71
dc756026	72	static int __init davinci_gpio_irq_setup(void);
dce1115b DB	73
	74	/--------------------------------------------------------------------------/
	75
3d9edf09	76	/*
dce1115b DB	77	* board setup code MUST set PINMUX0 and PINMUX1 as
dce1115b DB	78	* needed, and enable the GPIO clock.
3d9edf09	79	*/
dce1115b	80
ba4a984e CC	81	static inline int __davinci_direction(struct gpio_chip *chip,
ba4a984e CC	82	unsigned offset, bool out, int value)
3d9edf09	83	{
99e9e52d CC	84	struct davinci_gpio_controller *d = chip2controller(chip);
99e9e52d CC	85	struct davinci_gpio_regs __iomem *g = d->regs;
dce1115b	86	u32 temp;
ba4a984e	87	u32 mask = 1 << offset;
3d9edf09	88
dce1115b DB	89	spin_lock(&gpio_lock);
dce1115b DB	90	temp = __raw_readl(&g->dir);
ba4a984e CC	91	if (out) {
	92	temp &= ~mask;
	93	__raw_writel(mask, value ? &g->set_data : &g->clr_data);
	94	} else {
	95	temp \|= mask;
	96	}
dce1115b DB	97	__raw_writel(temp, &g->dir);
dce1115b DB	98	spin_unlock(&gpio_lock);
3d9edf09	99
dce1115b DB	100	return 0;
dce1115b DB	101	}
3d9edf09	102
ba4a984e CC	103	static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
	104	{
	105	return __davinci_direction(chip, offset, false, 0);
	106	}
	107
	108	static int
	109	davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
	110	{
	111	return __davinci_direction(chip, offset, true, value);
	112	}
	113
3d9edf09 VB	114	/*
	115	* Read the pin's value (works even if it's set up as output);
	116	* returns zero/nonzero.
	117	*
	118	* Note that changes are synched to the GPIO clock, so reading values back
	119	* right after you've set them may give old values.
	120	*/
dce1115b	121	static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
3d9edf09	122	{
99e9e52d CC	123	struct davinci_gpio_controller *d = chip2controller(chip);
99e9e52d CC	124	struct davinci_gpio_regs __iomem *g = d->regs;
3d9edf09	125
dce1115b	126	return (1 << offset) & __raw_readl(&g->in_data);
3d9edf09	127	}
3d9edf09	128
dce1115b DB	129	/*
	130	* Assuming the pin is muxed as a gpio output, set its output value.
	131	*/
	132	static void
	133	davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3d9edf09	134	{
99e9e52d CC	135	struct davinci_gpio_controller *d = chip2controller(chip);
99e9e52d CC	136	struct davinci_gpio_regs __iomem *g = d->regs;
3d9edf09	137
dce1115b DB	138	__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
	139	}
	140
	141	static int __init davinci_gpio_setup(void)
	142	{
	143	int i, base;
a994955c MG	144	unsigned ngpio;
a994955c MG	145	struct davinci_soc_info *soc_info = &davinci_soc_info;
c12f415a	146	struct davinci_gpio_regs *regs;
dce1115b	147
686b634a CC	148	if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
	149	return 0;
	150
a994955c MG	151	/*
a994955c MG	152	* The gpio banks conceptually expose a segmented bitmap,
474dad54 DB	153	* and "ngpio" is one more than the largest zero-based
	154	* bit index that's valid.
	155	*/
a994955c MG	156	ngpio = soc_info->gpio_num;
a994955c MG	157	if (ngpio == 0) {
474dad54 DB	158	pr_err("GPIO setup: how many GPIOs?\n");
	159	return -EINVAL;
	160	}
	161
	162	if (WARN_ON(DAVINCI_N_GPIO < ngpio))
	163	ngpio = DAVINCI_N_GPIO;
	164
	165	for (i = 0, base = 0; base < ngpio; i++, base += 32) {
dce1115b DB	166	chips[i].chip.label = "DaVinci";
	167
	168	chips[i].chip.direction_input = davinci_direction_in;
	169	chips[i].chip.get = davinci_gpio_get;
	170	chips[i].chip.direction_output = davinci_direction_out;
	171	chips[i].chip.set = davinci_gpio_set;
	172
	173	chips[i].chip.base = base;
474dad54	174	chips[i].chip.ngpio = ngpio - base;
dce1115b DB	175	if (chips[i].chip.ngpio > 32)
	176	chips[i].chip.ngpio = 32;
	177
c12f415a CC	178	regs = gpio2regs(base);
	179	chips[i].regs = regs;
	180	chips[i].set_data = &regs->set_data;
	181	chips[i].clr_data = &regs->clr_data;
	182	chips[i].in_data = &regs->in_data;
dce1115b DB	183
	184	gpiochip_add(&chips[i].chip);
	185	}
3d9edf09	186
c12f415a CC	187	soc_info->gpio_ctlrs = chips;
	188	soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
	189
dc756026	190	davinci_gpio_irq_setup();
3d9edf09 VB	191	return 0;
3d9edf09 VB	192	}
dce1115b	193	pure_initcall(davinci_gpio_setup);
3d9edf09	194
dce1115b	195	/--------------------------------------------------------------------------/
3d9edf09 VB	196	/*
	197	* We expect irqs will normally be set up as input pins, but they can also be
	198	* used as output pins ... which is convenient for testing.
	199	*
474dad54	200	* NOTE: The first few GPIOs also have direct INTC hookups in addition
7a36071e	201	* to their GPIOBNK0 irq, with a bit less overhead.
3d9edf09	202	*
474dad54	203	* All those INTC hookups (direct, plus several IRQ banks) can also
3d9edf09 VB	204	* serve as EDMA event triggers.
	205	*/
	206
	207	static void gpio_irq_disable(unsigned irq)
	208	{
99e9e52d	209	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
7a36071e	210	u32 mask = (u32) get_irq_data(irq);
3d9edf09 VB	211
	212	__raw_writel(mask, &g->clr_falling);
	213	__raw_writel(mask, &g->clr_rising);
	214	}
	215
	216	static void gpio_irq_enable(unsigned irq)
	217	{
99e9e52d	218	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
7a36071e	219	u32 mask = (u32) get_irq_data(irq);
df4aab46	220	unsigned status = irq_desc[irq].status;
3d9edf09	221
df4aab46 DB	222	status &= IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	223	if (!status)
	224	status = IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING;
	225
	226	if (status & IRQ_TYPE_EDGE_FALLING)
3d9edf09	227	__raw_writel(mask, &g->set_falling);
df4aab46	228	if (status & IRQ_TYPE_EDGE_RISING)
3d9edf09 VB	229	__raw_writel(mask, &g->set_rising);
	230	}
	231
	232	static int gpio_irq_type(unsigned irq, unsigned trigger)
	233	{
99e9e52d	234	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
7a36071e	235	u32 mask = (u32) get_irq_data(irq);
3d9edf09 VB	236
	237	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	238	return -EINVAL;
	239
	240	irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
	241	irq_desc[irq].status \|= trigger;
	242
df4aab46 DB	243	/* don't enable the IRQ if it's currently disabled */
	244	if (irq_desc[irq].depth == 0) {
	245	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
	246	? &g->set_falling : &g->clr_falling);
	247	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
	248	? &g->set_rising : &g->clr_rising);
	249	}
3d9edf09 VB	250	return 0;
	251	}
	252
	253	static struct irq_chip gpio_irqchip = {
	254	.name = "GPIO",
	255	.enable = gpio_irq_enable,
	256	.disable = gpio_irq_disable,
	257	.set_type = gpio_irq_type,
	258	};
	259
	260	static void
	261	gpio_irq_handler(unsigned irq, struct irq_desc *desc)
	262	{
99e9e52d	263	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
3d9edf09 VB	264	u32 mask = 0xffff;
	265
	266	/* we only care about one bank */
	267	if (irq & 1)
	268	mask <<= 16;
	269
	270	/* temporarily mask (level sensitive) parent IRQ */
dc756026	271	desc->chip->mask(irq);
3d9edf09 VB	272	desc->chip->ack(irq);
	273	while (1) {
	274	u32 status;
3d9edf09 VB	275	int n;
	276	int res;
	277
	278	/* ack any irqs */
	279	status = __raw_readl(&g->intstat) & mask;
	280	if (!status)
	281	break;
	282	__raw_writel(status, &g->intstat);
	283	if (irq & 1)
	284	status >>= 16;
	285
	286	/* now demux them to the right lowlevel handler */
	287	n = (int)get_irq_data(irq);
3d9edf09 VB	288	while (status) {
	289	res = ffs(status);
	290	n += res;
d8aa0251	291	generic_handle_irq(n - 1);
3d9edf09 VB	292	status >>= res;
	293	}
	294	}
	295	desc->chip->unmask(irq);
	296	/* now it may re-trigger */
	297	}
	298
7a36071e DB	299	static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
7a36071e DB	300	{
99e9e52d	301	struct davinci_gpio_controller *d = chip2controller(chip);
7a36071e DB	302
	303	if (d->irq_base >= 0)
	304	return d->irq_base + offset;
	305	else
	306	return -ENODEV;
	307	}
	308
	309	static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
	310	{
	311	struct davinci_soc_info *soc_info = &davinci_soc_info;
	312
	313	/* NOTE: we assume for now that only irqs in the first gpio_chip
	314	* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
	315	*/
	316	if (offset < soc_info->gpio_unbanked)
	317	return soc_info->gpio_irq + offset;
	318	else
	319	return -ENODEV;
	320	}
	321
	322	static int gpio_irq_type_unbanked(unsigned irq, unsigned trigger)
	323	{
99e9e52d	324	struct davinci_gpio_regs __iomem *g = irq2regs(irq);
7a36071e DB	325	u32 mask = (u32) get_irq_data(irq);
	326
	327	if (trigger & ~(IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
	328	return -EINVAL;
	329
	330	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
	331	? &g->set_falling : &g->clr_falling);
	332	__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
	333	? &g->set_rising : &g->clr_rising);
	334
	335	return 0;
	336	}
	337
3d9edf09	338	/*
474dad54 DB	339	* NOTE: for suspend/resume, probably best to make a platform_device with
474dad54 DB	340	* suspend_late/resume_resume calls hooking into results of the set_wake()
3d9edf09 VB	341	* calls ... so if no gpios are wakeup events the clock can be disabled,
3d9edf09 VB	342	* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
474dad54	343	* (dm6446) can be set appropriately for GPIOV33 pins.
3d9edf09 VB	344	*/
	345
	346	static int __init davinci_gpio_irq_setup(void)
	347	{
	348	unsigned gpio, irq, bank;
	349	struct clk *clk;
474dad54	350	u32 binten = 0;
a994955c MG	351	unsigned ngpio, bank_irq;
a994955c MG	352	struct davinci_soc_info *soc_info = &davinci_soc_info;
99e9e52d	353	struct davinci_gpio_regs __iomem *g;
a994955c MG	354
a994955c MG	355	ngpio = soc_info->gpio_num;
474dad54	356
a994955c MG	357	bank_irq = soc_info->gpio_irq;
a994955c MG	358	if (bank_irq == 0) {
474dad54 DB	359	printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
	360	return -EINVAL;
	361	}
3d9edf09 VB	362
	363	clk = clk_get(NULL, "gpio");
	364	if (IS_ERR(clk)) {
	365	printk(KERN_ERR "Error %ld getting gpio clock?\n",
	366	PTR_ERR(clk));
474dad54	367	return PTR_ERR(clk);
3d9edf09	368	}
3d9edf09 VB	369	clk_enable(clk);
3d9edf09 VB	370
7a36071e DB	371	/* Arrange gpio_to_irq() support, handling either direct IRQs or
	372	* banked IRQs. Having GPIOs in the first GPIO bank use direct
	373	* IRQs, while the others use banked IRQs, would need some setup
	374	* tweaks to recognize hardware which can do that.
	375	*/
	376	for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
	377	chips[bank].chip.to_irq = gpio_to_irq_banked;
	378	chips[bank].irq_base = soc_info->gpio_unbanked
	379	? -EINVAL
	380	: (soc_info->intc_irq_num + gpio);
	381	}
	382
	383	/*
	384	* AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
	385	* controller only handling trigger modes. We currently assume no
	386	* IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
	387	*/
	388	if (soc_info->gpio_unbanked) {
	389	static struct irq_chip gpio_irqchip_unbanked;
	390
	391	/* pass "bank 0" GPIO IRQs to AINTC */
	392	chips[0].chip.to_irq = gpio_to_irq_unbanked;
	393	binten = BIT(0);
	394
	395	/* AINTC handles mask/unmask; GPIO handles triggering */
	396	irq = bank_irq;
	397	gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
	398	gpio_irqchip_unbanked.name = "GPIO-AINTC";
	399	gpio_irqchip_unbanked.set_type = gpio_irq_type_unbanked;
	400
	401	/* default trigger: both edges */
99e9e52d	402	g = gpio2regs(0);
7a36071e DB	403	__raw_writel(~0, &g->set_falling);
	404	__raw_writel(~0, &g->set_rising);
	405
	406	/* set the direct IRQs up to use that irqchip */
	407	for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
	408	set_irq_chip(irq, &gpio_irqchip_unbanked);
	409	set_irq_data(irq, (void *) __gpio_mask(gpio));
21ce873d	410	set_irq_chip_data(irq, (__force void *) g);
7a36071e DB	411	irq_desc[irq].status \|= IRQ_TYPE_EDGE_BOTH;
	412	}
	413
	414	goto done;
	415	}
	416
	417	/*
	418	* Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
	419	* then chain through our own handler.
	420	*/
474dad54 DB	421	for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
	422	gpio < ngpio;
	423	bank++, bank_irq++) {
3d9edf09 VB	424	unsigned i;
3d9edf09 VB	425
7a36071e	426	/* disabled by default, enabled only as needed */
99e9e52d	427	g = gpio2regs(gpio);
3d9edf09 VB	428	__raw_writel(~0, &g->clr_falling);
	429	__raw_writel(~0, &g->clr_rising);
	430
	431	/* set up all irqs in this bank */
474dad54	432	set_irq_chained_handler(bank_irq, gpio_irq_handler);
21ce873d KH	433	set_irq_chip_data(bank_irq, (__force void *) g);
21ce873d KH	434	set_irq_data(bank_irq, (void *) irq);
3d9edf09	435
474dad54	436	for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
3d9edf09	437	set_irq_chip(irq, &gpio_irqchip);
21ce873d	438	set_irq_chip_data(irq, (__force void *) g);
7a36071e	439	set_irq_data(irq, (void *) __gpio_mask(gpio));
3d9edf09 VB	440	set_irq_handler(irq, handle_simple_irq);
	441	set_irq_flags(irq, IRQF_VALID);
	442	}
474dad54 DB	443
474dad54 DB	444	binten \|= BIT(bank);
3d9edf09 VB	445	}
3d9edf09 VB	446
7a36071e	447	done:
3d9edf09 VB	448	/* BINTEN -- per-bank interrupt enable. genirq would also let these
	449	* bits be set/cleared dynamically.
	450	*/
a994955c	451	__raw_writel(binten, soc_info->gpio_base + 0x08);
3d9edf09 VB	452
	453	printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
	454
	455	return 0;
	456	}