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Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
[linux-2.6-block.git] / arch / arm / mach-davinci / da850.c
CommitLineData
e1a8d7e2
SR		 1/*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
e1a8d7e2
SR		 14#include <linux/init.h>
15#include <linux/clk.h>
16#include <linux/platform_device.h>
683b1e1f 17#include <linux/cpufreq.h>
35f9acd8 18#include <linux/regulator/consumer.h>
e1a8d7e2
SR		 19
20#include <asm/mach/map.h>
21
e1a8d7e2 22#include <mach/psc.h>
e1a8d7e2
SR		 23#include <mach/irqs.h>
24#include <mach/cputype.h>
25#include <mach/common.h>
26#include <mach/time.h>
27#include <mach/da8xx.h>
683b1e1f 28#include <mach/cpufreq.h>
044ca015 29#include <mach/pm.h>
e1a8d7e2
SR		 30
31#include "clock.h"
32#include "mux.h"
33
5d36a332
SN		 34/* SoC specific clock flags */
35#define DA850_CLK_ASYNC3 BIT(16)
36
e1a8d7e2
SR		 37#define DA850_PLL1_BASE 0x01e1a000
38#define DA850_TIMER64P2_BASE 0x01f0c000
39#define DA850_TIMER64P3_BASE 0x01f0d000
40
41#define DA850_REF_FREQ 24000000
42
5d36a332 43#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
7aad472b 44#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
683b1e1f
SN		 45#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
46
47static int da850_set_armrate(struct clk *clk, unsigned long rate);
48static int da850_round_armrate(struct clk *clk, unsigned long rate);
49static int da850_set_pll0rate(struct clk *clk, unsigned long armrate);
5d36a332 50
e1a8d7e2
SR		 51static struct pll_data pll0_data = {
52 .num = 1,
53 .phys_base = DA8XX_PLL0_BASE,
54 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
55};
56
57static struct clk ref_clk = {
58 .name = "ref_clk",
59 .rate = DA850_REF_FREQ,
60};
61
62static struct clk pll0_clk = {
63 .name = "pll0",
64 .parent = &ref_clk,
65 .pll_data = &pll0_data,
66 .flags = CLK_PLL,
683b1e1f 67 .set_rate = da850_set_pll0rate,
e1a8d7e2
SR		 68};
69
70static struct clk pll0_aux_clk = {
71 .name = "pll0_aux_clk",
72 .parent = &pll0_clk,
73 .flags = CLK_PLL | PRE_PLL,
74};
75
76static struct clk pll0_sysclk2 = {
77 .name = "pll0_sysclk2",
78 .parent = &pll0_clk,
79 .flags = CLK_PLL,
80 .div_reg = PLLDIV2,
81};
82
83static struct clk pll0_sysclk3 = {
84 .name = "pll0_sysclk3",
85 .parent = &pll0_clk,
86 .flags = CLK_PLL,
87 .div_reg = PLLDIV3,
88};
89
90static struct clk pll0_sysclk4 = {
91 .name = "pll0_sysclk4",
92 .parent = &pll0_clk,
93 .flags = CLK_PLL,
94 .div_reg = PLLDIV4,
95};
96
97static struct clk pll0_sysclk5 = {
98 .name = "pll0_sysclk5",
99 .parent = &pll0_clk,
100 .flags = CLK_PLL,
101 .div_reg = PLLDIV5,
102};
103
104static struct clk pll0_sysclk6 = {
105 .name = "pll0_sysclk6",
106 .parent = &pll0_clk,
107 .flags = CLK_PLL,
108 .div_reg = PLLDIV6,
109};
110
111static struct clk pll0_sysclk7 = {
112 .name = "pll0_sysclk7",
113 .parent = &pll0_clk,
114 .flags = CLK_PLL,
115 .div_reg = PLLDIV7,
116};
117
118static struct pll_data pll1_data = {
119 .num = 2,
120 .phys_base = DA850_PLL1_BASE,
121 .flags = PLL_HAS_POSTDIV,
122};
123
124static struct clk pll1_clk = {
125 .name = "pll1",
126 .parent = &ref_clk,
127 .pll_data = &pll1_data,
128 .flags = CLK_PLL,
129};
130
131static struct clk pll1_aux_clk = {
132 .name = "pll1_aux_clk",
133 .parent = &pll1_clk,
134 .flags = CLK_PLL | PRE_PLL,
135};
136
137static struct clk pll1_sysclk2 = {
138 .name = "pll1_sysclk2",
139 .parent = &pll1_clk,
140 .flags = CLK_PLL,
141 .div_reg = PLLDIV2,
142};
143
144static struct clk pll1_sysclk3 = {
145 .name = "pll1_sysclk3",
146 .parent = &pll1_clk,
147 .flags = CLK_PLL,
148 .div_reg = PLLDIV3,
149};
150
151static struct clk pll1_sysclk4 = {
152 .name = "pll1_sysclk4",
153 .parent = &pll1_clk,
154 .flags = CLK_PLL,
155 .div_reg = PLLDIV4,
156};
157
158static struct clk pll1_sysclk5 = {
159 .name = "pll1_sysclk5",
160 .parent = &pll1_clk,
161 .flags = CLK_PLL,
162 .div_reg = PLLDIV5,
163};
164
165static struct clk pll1_sysclk6 = {
166 .name = "pll0_sysclk6",
167 .parent = &pll0_clk,
168 .flags = CLK_PLL,
169 .div_reg = PLLDIV6,
170};
171
172static struct clk pll1_sysclk7 = {
173 .name = "pll1_sysclk7",
174 .parent = &pll1_clk,
175 .flags = CLK_PLL,
176 .div_reg = PLLDIV7,
177};
178
179static struct clk i2c0_clk = {
180 .name = "i2c0",
181 .parent = &pll0_aux_clk,
182};
183
184static struct clk timerp64_0_clk = {
185 .name = "timer0",
186 .parent = &pll0_aux_clk,
187};
188
189static struct clk timerp64_1_clk = {
190 .name = "timer1",
191 .parent = &pll0_aux_clk,
192};
193
194static struct clk arm_rom_clk = {
195 .name = "arm_rom",
196 .parent = &pll0_sysclk2,
197 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
198 .flags = ALWAYS_ENABLED,
199};
200
201static struct clk tpcc0_clk = {
202 .name = "tpcc0",
203 .parent = &pll0_sysclk2,
204 .lpsc = DA8XX_LPSC0_TPCC,
205 .flags = ALWAYS_ENABLED | CLK_PSC,
206};
207
208static struct clk tptc0_clk = {
209 .name = "tptc0",
210 .parent = &pll0_sysclk2,
211 .lpsc = DA8XX_LPSC0_TPTC0,
212 .flags = ALWAYS_ENABLED,
213};
214
215static struct clk tptc1_clk = {
216 .name = "tptc1",
217 .parent = &pll0_sysclk2,
218 .lpsc = DA8XX_LPSC0_TPTC1,
219 .flags = ALWAYS_ENABLED,
220};
221
222static struct clk tpcc1_clk = {
223 .name = "tpcc1",
224 .parent = &pll0_sysclk2,
225 .lpsc = DA850_LPSC1_TPCC1,
789a785e 226 .gpsc = 1,
e1a8d7e2 227 .flags = CLK_PSC | ALWAYS_ENABLED,
e1a8d7e2
SR		 228};
229
230static struct clk tptc2_clk = {
231 .name = "tptc2",
232 .parent = &pll0_sysclk2,
233 .lpsc = DA850_LPSC1_TPTC2,
789a785e 234 .gpsc = 1,
e1a8d7e2 235 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 236};
237
238static struct clk uart0_clk = {
239 .name = "uart0",
240 .parent = &pll0_sysclk2,
241 .lpsc = DA8XX_LPSC0_UART0,
242};
243
244static struct clk uart1_clk = {
245 .name = "uart1",
246 .parent = &pll0_sysclk2,
247 .lpsc = DA8XX_LPSC1_UART1,
789a785e 248 .gpsc = 1,
5d36a332 249 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 250};
251
252static struct clk uart2_clk = {
253 .name = "uart2",
254 .parent = &pll0_sysclk2,
255 .lpsc = DA8XX_LPSC1_UART2,
789a785e 256 .gpsc = 1,
5d36a332 257 .flags = DA850_CLK_ASYNC3,
e1a8d7e2
SR		 258};
259
260static struct clk aintc_clk = {
261 .name = "aintc",
262 .parent = &pll0_sysclk4,
263 .lpsc = DA8XX_LPSC0_AINTC,
264 .flags = ALWAYS_ENABLED,
265};
266
267static struct clk gpio_clk = {
268 .name = "gpio",
269 .parent = &pll0_sysclk4,
270 .lpsc = DA8XX_LPSC1_GPIO,
789a785e 271 .gpsc = 1,
e1a8d7e2
SR		 272};
273
274static struct clk i2c1_clk = {
275 .name = "i2c1",
276 .parent = &pll0_sysclk4,
277 .lpsc = DA8XX_LPSC1_I2C,
789a785e 278 .gpsc = 1,
e1a8d7e2
SR		 279};
280
281static struct clk emif3_clk = {
282 .name = "emif3",
283 .parent = &pll0_sysclk5,
284 .lpsc = DA8XX_LPSC1_EMIF3C,
789a785e 285 .gpsc = 1,
e1a8d7e2 286 .flags = ALWAYS_ENABLED,
e1a8d7e2
SR		 287};
288
289static struct clk arm_clk = {
290 .name = "arm",
291 .parent = &pll0_sysclk6,
292 .lpsc = DA8XX_LPSC0_ARM,
293 .flags = ALWAYS_ENABLED,
683b1e1f
SN		 294 .set_rate = da850_set_armrate,
295 .round_rate = da850_round_armrate,
e1a8d7e2
SR		 296};
297
298static struct clk rmii_clk = {
299 .name = "rmii",
300 .parent = &pll0_sysclk7,
301};
302
5a4b1315
SR		 303static struct clk emac_clk = {
304 .name = "emac",
305 .parent = &pll0_sysclk4,
306 .lpsc = DA8XX_LPSC1_CPGMAC,
789a785e 307 .gpsc = 1,
5a4b1315
SR		 308};
309
491214e1
C		 310static struct clk mcasp_clk = {
311 .name = "mcasp",
312 .parent = &pll0_sysclk2,
313 .lpsc = DA8XX_LPSC1_McASP0,
789a785e 314 .gpsc = 1,
51157ed8 315 .flags = DA850_CLK_ASYNC3,
491214e1
C		 316};
317
5cbdf276
SR		 318static struct clk lcdc_clk = {
319 .name = "lcdc",
320 .parent = &pll0_sysclk2,
321 .lpsc = DA8XX_LPSC1_LCDC,
789a785e 322 .gpsc = 1,
5cbdf276
SR		 323};
324
700691f2
SR		 325static struct clk mmcsd_clk = {
326 .name = "mmcsd",
327 .parent = &pll0_sysclk2,
328 .lpsc = DA8XX_LPSC0_MMC_SD,
329};
330
38beb929
SR		 331static struct clk aemif_clk = {
332 .name = "aemif",
333 .parent = &pll0_sysclk3,
334 .lpsc = DA8XX_LPSC0_EMIF25,
335 .flags = ALWAYS_ENABLED,
336};
337
08aca087 338static struct clk_lookup da850_clks[] = {
e1a8d7e2
SR		 339 CLK(NULL, "ref", &ref_clk),
340 CLK(NULL, "pll0", &pll0_clk),
341 CLK(NULL, "pll0_aux", &pll0_aux_clk),
342 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
343 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
344 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
345 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
346 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
347 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
348 CLK(NULL, "pll1", &pll1_clk),
349 CLK(NULL, "pll1_aux", &pll1_aux_clk),
350 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
351 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
352 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
353 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
354 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
355 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
356 CLK("i2c_davinci.1", NULL, &i2c0_clk),
357 CLK(NULL, "timer0", &timerp64_0_clk),
358 CLK("watchdog", NULL, &timerp64_1_clk),
359 CLK(NULL, "arm_rom", &arm_rom_clk),
360 CLK(NULL, "tpcc0", &tpcc0_clk),
361 CLK(NULL, "tptc0", &tptc0_clk),
362 CLK(NULL, "tptc1", &tptc1_clk),
363 CLK(NULL, "tpcc1", &tpcc1_clk),
364 CLK(NULL, "tptc2", &tptc2_clk),
365 CLK(NULL, "uart0", &uart0_clk),
366 CLK(NULL, "uart1", &uart1_clk),
367 CLK(NULL, "uart2", &uart2_clk),
368 CLK(NULL, "aintc", &aintc_clk),
369 CLK(NULL, "gpio", &gpio_clk),
370 CLK("i2c_davinci.2", NULL, &i2c1_clk),
371 CLK(NULL, "emif3", &emif3_clk),
372 CLK(NULL, "arm", &arm_clk),
373 CLK(NULL, "rmii", &rmii_clk),
5a4b1315 374 CLK("davinci_emac.1", NULL, &emac_clk),
491214e1 375 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
5cbdf276 376 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
700691f2 377 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
38beb929 378 CLK(NULL, "aemif", &aemif_clk),
e1a8d7e2
SR		 379 CLK(NULL, NULL, NULL),
380};
381
382/*
383 * Device specific mux setup
384 *
385 * soc description mux mode mode mux dbg
386 * reg offset mask mode
387 */
388static const struct mux_config da850_pins[] = {
389#ifdef CONFIG_DAVINCI_MUX
390 /* UART0 function */
391 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
392 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
393 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
394 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
395 /* UART1 function */
396 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
397 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
398 /* UART2 function */
399 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
400 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
401 /* I2C1 function */
402 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
403 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
404 /* I2C0 function */
405 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
406 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
5a4b1315
SR		 407 /* EMAC function */
408 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
409 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
410 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
411 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
412 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
413 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
414 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
415 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
416 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
417 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
418 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
419 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
420 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
421 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
422 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
53ca5c91
SR		 423 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
424 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
2206771c
C		 425 MUX_CFG(DA850, RMII_TXD_0, 14, 12, 15, 8, false)
426 MUX_CFG(DA850, RMII_TXD_1, 14, 8, 15, 8, false)
427 MUX_CFG(DA850, RMII_TXEN, 14, 16, 15, 8, false)
428 MUX_CFG(DA850, RMII_CRS_DV, 15, 4, 15, 8, false)
429 MUX_CFG(DA850, RMII_RXD_0, 14, 24, 15, 8, false)
430 MUX_CFG(DA850, RMII_RXD_1, 14, 20, 15, 8, false)
431 MUX_CFG(DA850, RMII_RXER, 14, 28, 15, 8, false)
432 MUX_CFG(DA850, RMII_MHZ_50_CLK, 15, 0, 15, 0, false)
491214e1
C		 433 /* McASP function */
434 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
435 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
436 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
437 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
438 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
439 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
440 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
441 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
442 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
443 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
444 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
445 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
446 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
447 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
448 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
449 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
450 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
451 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
452 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
453 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
454 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
455 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
456 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
5cbdf276
SR		 457 /* LCD function */
458 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
459 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
460 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
461 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
462 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
463 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
464 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
465 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
466 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
467 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
468 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
469 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
470 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
471 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
472 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
473 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
474 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
475 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
476 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
477 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
700691f2
SR		 478 /* MMC/SD0 function */
479 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
480 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
481 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
482 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
483 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
484 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
38beb929
SR		 485 /* EMIF2.5/EMIFA function */
486 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
487 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
488 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
489 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
490 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
491 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
492 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
493 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
494 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
495 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
496 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
497 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
498 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
499 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
7c5ec609
SR		 500 MUX_CFG(DA850, EMA_A_0, 12, 28, 15, 1, false)
501 MUX_CFG(DA850, EMA_A_3, 12, 16, 15, 1, false)
502 MUX_CFG(DA850, EMA_A_4, 12, 12, 15, 1, false)
503 MUX_CFG(DA850, EMA_A_5, 12, 8, 15, 1, false)
504 MUX_CFG(DA850, EMA_A_6, 12, 4, 15, 1, false)
505 MUX_CFG(DA850, EMA_A_7, 12, 0, 15, 1, false)
506 MUX_CFG(DA850, EMA_A_8, 11, 28, 15, 1, false)
507 MUX_CFG(DA850, EMA_A_9, 11, 24, 15, 1, false)
508 MUX_CFG(DA850, EMA_A_10, 11, 20, 15, 1, false)
509 MUX_CFG(DA850, EMA_A_11, 11, 16, 15, 1, false)
510 MUX_CFG(DA850, EMA_A_12, 11, 12, 15, 1, false)
511 MUX_CFG(DA850, EMA_A_13, 11, 8, 15, 1, false)
512 MUX_CFG(DA850, EMA_A_14, 11, 4, 15, 1, false)
513 MUX_CFG(DA850, EMA_A_15, 11, 0, 15, 1, false)
514 MUX_CFG(DA850, EMA_A_16, 10, 28, 15, 1, false)
515 MUX_CFG(DA850, EMA_A_17, 10, 24, 15, 1, false)
516 MUX_CFG(DA850, EMA_A_18, 10, 20, 15, 1, false)
517 MUX_CFG(DA850, EMA_A_19, 10, 16, 15, 1, false)
518 MUX_CFG(DA850, EMA_A_20, 10, 12, 15, 1, false)
519 MUX_CFG(DA850, EMA_A_21, 10, 8, 15, 1, false)
520 MUX_CFG(DA850, EMA_A_22, 10, 4, 15, 1, false)
521 MUX_CFG(DA850, EMA_A_23, 10, 0, 15, 1, false)
522 MUX_CFG(DA850, EMA_D_8, 8, 28, 15, 1, false)
523 MUX_CFG(DA850, EMA_D_9, 8, 24, 15, 1, false)
524 MUX_CFG(DA850, EMA_D_10, 8, 20, 15, 1, false)
525 MUX_CFG(DA850, EMA_D_11, 8, 16, 15, 1, false)
526 MUX_CFG(DA850, EMA_D_12, 8, 12, 15, 1, false)
527 MUX_CFG(DA850, EMA_D_13, 8, 8, 15, 1, false)
528 MUX_CFG(DA850, EMA_D_14, 8, 4, 15, 1, false)
529 MUX_CFG(DA850, EMA_D_15, 8, 0, 15, 1, false)
530 MUX_CFG(DA850, EMA_BA_1, 5, 24, 15, 1, false)
531 MUX_CFG(DA850, EMA_CLK, 6, 0, 15, 1, false)
532 MUX_CFG(DA850, EMA_WAIT_1, 6, 24, 15, 1, false)
533 MUX_CFG(DA850, NEMA_CS_2, 7, 0, 15, 1, false)
5cbdf276 534 /* GPIO function */
2206771c 535 MUX_CFG(DA850, GPIO2_6, 6, 4, 15, 8, false)
7761ef67 536 MUX_CFG(DA850, GPIO2_8, 5, 28, 15, 8, false)
5cbdf276 537 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
700691f2
SR		 538 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
539 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
044ca015 540 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
e1a8d7e2
SR		 541#endif
542};
543
544const short da850_uart0_pins[] __initdata = {
545 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
546 -1
547};
548
549const short da850_uart1_pins[] __initdata = {
550 DA850_UART1_RXD, DA850_UART1_TXD,
551 -1
552};
553
554const short da850_uart2_pins[] __initdata = {
555 DA850_UART2_RXD, DA850_UART2_TXD,
556 -1
557};
558
559const short da850_i2c0_pins[] __initdata = {
560 DA850_I2C0_SDA, DA850_I2C0_SCL,
561 -1
562};
563
564const short da850_i2c1_pins[] __initdata = {
565 DA850_I2C1_SCL, DA850_I2C1_SDA,
566 -1
567};
568
5a4b1315
SR		 569const short da850_cpgmac_pins[] __initdata = {
570 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
571 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
572 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
53ca5c91
SR		 573 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
574 DA850_MDIO_D,
5a4b1315
SR		 575 -1
576};
577
2206771c
C		 578const short da850_rmii_pins[] __initdata = {
579 DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
580 DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
581 DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
582 DA850_MDIO_D,
583 -1
584};
585
491214e1
C		 586const short da850_mcasp_pins[] __initdata = {
587 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
588 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
589 DA850_AXR_11, DA850_AXR_12,
590 -1
591};
592
5cbdf276 593const short da850_lcdcntl_pins[] __initdata = {
7761ef67
SR		 594 DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3,
595 DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7,
596 DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11,
597 DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15,
598 DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS,
5cbdf276
SR		 599 -1
600};
601
700691f2
SR		 602const short da850_mmcsd0_pins[] __initdata = {
603 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
604 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
605 DA850_GPIO4_0, DA850_GPIO4_1,
606 -1
607};
608
38beb929
SR		 609const short da850_nand_pins[] __initdata = {
610 DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
611 DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
612 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
613 DA850_NEMA_WE, DA850_NEMA_OE,
614 -1
615};
616
7c5ec609
SR		 617const short da850_nor_pins[] __initdata = {
618 DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2,
619 DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1,
620 DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5,
621 DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9,
622 DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13,
623 DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1,
624 DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5,
625 DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9,
626 DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13,
627 DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17,
628 DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21,
629 DA850_EMA_A_22, DA850_EMA_A_23,
630 -1
631};
632
e1a8d7e2
SR		 633/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
634static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
635 [IRQ_DA8XX_COMMTX] = 7,
636 [IRQ_DA8XX_COMMRX] = 7,
637 [IRQ_DA8XX_NINT] = 7,
638 [IRQ_DA8XX_EVTOUT0] = 7,
639 [IRQ_DA8XX_EVTOUT1] = 7,
640 [IRQ_DA8XX_EVTOUT2] = 7,
641 [IRQ_DA8XX_EVTOUT3] = 7,
642 [IRQ_DA8XX_EVTOUT4] = 7,
643 [IRQ_DA8XX_EVTOUT5] = 7,
644 [IRQ_DA8XX_EVTOUT6] = 7,
645 [IRQ_DA8XX_EVTOUT6] = 7,
646 [IRQ_DA8XX_EVTOUT7] = 7,
647 [IRQ_DA8XX_CCINT0] = 7,
648 [IRQ_DA8XX_CCERRINT] = 7,
649 [IRQ_DA8XX_TCERRINT0] = 7,
650 [IRQ_DA8XX_AEMIFINT] = 7,
651 [IRQ_DA8XX_I2CINT0] = 7,
652 [IRQ_DA8XX_MMCSDINT0] = 7,
653 [IRQ_DA8XX_MMCSDINT1] = 7,
654 [IRQ_DA8XX_ALLINT0] = 7,
655 [IRQ_DA8XX_RTC] = 7,
656 [IRQ_DA8XX_SPINT0] = 7,
657 [IRQ_DA8XX_TINT12_0] = 7,
658 [IRQ_DA8XX_TINT34_0] = 7,
659 [IRQ_DA8XX_TINT12_1] = 7,
660 [IRQ_DA8XX_TINT34_1] = 7,
661 [IRQ_DA8XX_UARTINT0] = 7,
662 [IRQ_DA8XX_KEYMGRINT] = 7,
663 [IRQ_DA8XX_SECINT] = 7,
664 [IRQ_DA8XX_SECKEYERR] = 7,
665 [IRQ_DA850_MPUADDRERR0] = 7,
666 [IRQ_DA850_MPUPROTERR0] = 7,
667 [IRQ_DA850_IOPUADDRERR0] = 7,
668 [IRQ_DA850_IOPUPROTERR0] = 7,
669 [IRQ_DA850_IOPUADDRERR1] = 7,
670 [IRQ_DA850_IOPUPROTERR1] = 7,
671 [IRQ_DA850_IOPUADDRERR2] = 7,
672 [IRQ_DA850_IOPUPROTERR2] = 7,
673 [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7,
674 [IRQ_DA850_BOOTCFG_PROT_ERR] = 7,
675 [IRQ_DA850_MPUADDRERR1] = 7,
676 [IRQ_DA850_MPUPROTERR1] = 7,
677 [IRQ_DA850_IOPUADDRERR3] = 7,
678 [IRQ_DA850_IOPUPROTERR3] = 7,
679 [IRQ_DA850_IOPUADDRERR4] = 7,
680 [IRQ_DA850_IOPUPROTERR4] = 7,
681 [IRQ_DA850_IOPUADDRERR5] = 7,
682 [IRQ_DA850_IOPUPROTERR5] = 7,
683 [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
684 [IRQ_DA8XX_CHIPINT0] = 7,
685 [IRQ_DA8XX_CHIPINT1] = 7,
686 [IRQ_DA8XX_CHIPINT2] = 7,
687 [IRQ_DA8XX_CHIPINT3] = 7,
688 [IRQ_DA8XX_TCERRINT1] = 7,
689 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
690 [IRQ_DA8XX_C0_RX_PULSE] = 7,
691 [IRQ_DA8XX_C0_TX_PULSE] = 7,
692 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
693 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
694 [IRQ_DA8XX_C1_RX_PULSE] = 7,
695 [IRQ_DA8XX_C1_TX_PULSE] = 7,
696 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
697 [IRQ_DA8XX_MEMERR] = 7,
698 [IRQ_DA8XX_GPIO0] = 7,
699 [IRQ_DA8XX_GPIO1] = 7,
700 [IRQ_DA8XX_GPIO2] = 7,
701 [IRQ_DA8XX_GPIO3] = 7,
702 [IRQ_DA8XX_GPIO4] = 7,
703 [IRQ_DA8XX_GPIO5] = 7,
704 [IRQ_DA8XX_GPIO6] = 7,
705 [IRQ_DA8XX_GPIO7] = 7,
706 [IRQ_DA8XX_GPIO8] = 7,
707 [IRQ_DA8XX_I2CINT1] = 7,
708 [IRQ_DA8XX_LCDINT] = 7,
709 [IRQ_DA8XX_UARTINT1] = 7,
710 [IRQ_DA8XX_MCASPINT] = 7,
711 [IRQ_DA8XX_ALLINT1] = 7,
712 [IRQ_DA8XX_SPINT1] = 7,
713 [IRQ_DA8XX_UHPI_INT1] = 7,
714 [IRQ_DA8XX_USB_INT] = 7,
715 [IRQ_DA8XX_IRQN] = 7,
716 [IRQ_DA8XX_RWAKEUP] = 7,
717 [IRQ_DA8XX_UARTINT2] = 7,
718 [IRQ_DA8XX_DFTSSINT] = 7,
719 [IRQ_DA8XX_EHRPWM0] = 7,
720 [IRQ_DA8XX_EHRPWM0TZ] = 7,
721 [IRQ_DA8XX_EHRPWM1] = 7,
722 [IRQ_DA8XX_EHRPWM1TZ] = 7,
723 [IRQ_DA850_SATAINT] = 7,
724 [IRQ_DA850_TINT12_2] = 7,
725 [IRQ_DA850_TINT34_2] = 7,
726 [IRQ_DA850_TINTALL_2] = 7,
727 [IRQ_DA8XX_ECAP0] = 7,
728 [IRQ_DA8XX_ECAP1] = 7,
729 [IRQ_DA8XX_ECAP2] = 7,
730 [IRQ_DA850_MMCSDINT0_1] = 7,
731 [IRQ_DA850_MMCSDINT1_1] = 7,
732 [IRQ_DA850_T12CMPINT0_2] = 7,
733 [IRQ_DA850_T12CMPINT1_2] = 7,
734 [IRQ_DA850_T12CMPINT2_2] = 7,
735 [IRQ_DA850_T12CMPINT3_2] = 7,
736 [IRQ_DA850_T12CMPINT4_2] = 7,
737 [IRQ_DA850_T12CMPINT5_2] = 7,
738 [IRQ_DA850_T12CMPINT6_2] = 7,
739 [IRQ_DA850_T12CMPINT7_2] = 7,
740 [IRQ_DA850_T12CMPINT0_3] = 7,
741 [IRQ_DA850_T12CMPINT1_3] = 7,
742 [IRQ_DA850_T12CMPINT2_3] = 7,
743 [IRQ_DA850_T12CMPINT3_3] = 7,
744 [IRQ_DA850_T12CMPINT4_3] = 7,
745 [IRQ_DA850_T12CMPINT5_3] = 7,
746 [IRQ_DA850_T12CMPINT6_3] = 7,
747 [IRQ_DA850_T12CMPINT7_3] = 7,
748 [IRQ_DA850_RPIINT] = 7,
749 [IRQ_DA850_VPIFINT] = 7,
750 [IRQ_DA850_CCINT1] = 7,
751 [IRQ_DA850_CCERRINT1] = 7,
752 [IRQ_DA850_TCERRINT2] = 7,
753 [IRQ_DA850_TINT12_3] = 7,
754 [IRQ_DA850_TINT34_3] = 7,
755 [IRQ_DA850_TINTALL_3] = 7,
756 [IRQ_DA850_MCBSP0RINT] = 7,
757 [IRQ_DA850_MCBSP0XINT] = 7,
758 [IRQ_DA850_MCBSP1RINT] = 7,
759 [IRQ_DA850_MCBSP1XINT] = 7,
760 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
761};
762
763static struct map_desc da850_io_desc[] = {
764 {
765 .virtual = IO_VIRT,
766 .pfn = __phys_to_pfn(IO_PHYS),
767 .length = IO_SIZE,
768 .type = MT_DEVICE
769 },
770 {
771 .virtual = DA8XX_CP_INTC_VIRT,
772 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
773 .length = DA8XX_CP_INTC_SIZE,
774 .type = MT_DEVICE
775 },
60cd02e1
SN		 776 {
777 .virtual = SRAM_VIRT,
778 .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
779 .length = SZ_8K,
780 .type = MT_DEVICE
781 },
e1a8d7e2
SR		 782};
783
784static void __iomem *da850_psc_bases[] = {
785 IO_ADDRESS(DA8XX_PSC0_BASE),
786 IO_ADDRESS(DA8XX_PSC1_BASE),
787};
788
789/* Contents of JTAG ID register used to identify exact cpu type */
790static struct davinci_id da850_ids[] = {
791 {
792 .variant = 0x0,
793 .part_no = 0xb7d1,
794 .manufacturer = 0x017, /* 0x02f >> 1 */
795 .cpu_id = DAVINCI_CPU_ID_DA850,
796 .name = "da850/omap-l138",
797 },
798};
799
800static struct davinci_timer_instance da850_timer_instance[4] = {
801 {
802 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
803 .bottom_irq = IRQ_DA8XX_TINT12_0,
804 .top_irq = IRQ_DA8XX_TINT34_0,
805 },
806 {
807 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
808 .bottom_irq = IRQ_DA8XX_TINT12_1,
809 .top_irq = IRQ_DA8XX_TINT34_1,
810 },
811 {
812 .base = IO_ADDRESS(DA850_TIMER64P2_BASE),
813 .bottom_irq = IRQ_DA850_TINT12_2,
814 .top_irq = IRQ_DA850_TINT34_2,
815 },
816 {
817 .base = IO_ADDRESS(DA850_TIMER64P3_BASE),
818 .bottom_irq = IRQ_DA850_TINT12_3,
819 .top_irq = IRQ_DA850_TINT34_3,
820 },
821};
822
823/*
824 * T0_BOT: Timer 0, bottom : Used for clock_event
825 * T0_TOP: Timer 0, top : Used for clocksource
826 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
827 */
828static struct davinci_timer_info da850_timer_info = {
829 .timers = da850_timer_instance,
830 .clockevent_id = T0_BOT,
831 .clocksource_id = T0_TOP,
832};
833
5d36a332
SN		 834static void da850_set_async3_src(int pllnum)
835{
836 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
08aca087 837 struct clk_lookup *c;
5d36a332
SN		 838 unsigned int v;
839 int ret;
840
08aca087
KH		 841 for (c = da850_clks; c->clk; c++) {
842 clk = c->clk;
5d36a332
SN		 843 if (clk->flags & DA850_CLK_ASYNC3) {
844 ret = clk_set_parent(clk, newparent);
845 WARN(ret, "DA850: unable to re-parent clock %s",
846 clk->name);
847 }
848 }
849
d2de0582 850 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
5d36a332
SN		 851 if (pllnum)
852 v |= CFGCHIP3_ASYNC3_CLKSRC;
853 else
854 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
d2de0582 855 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
5d36a332
SN		 856}
857
683b1e1f
SN		 858#ifdef CONFIG_CPU_FREQ
859/*
860 * Notes:
861 * According to the TRM, minimum PLLM results in maximum power savings.
862 * The OPP definitions below should keep the PLLM as low as possible.
863 *
864 * The output of the PLLM must be between 400 to 600 MHz.
865 * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
866 */
867struct da850_opp {
868 unsigned int freq; /* in KHz */
869 unsigned int prediv;
870 unsigned int mult;
871 unsigned int postdiv;
35f9acd8
SN		 872 unsigned int cvdd_min; /* in uV */
873 unsigned int cvdd_max; /* in uV */
683b1e1f
SN		 874};
875
876static const struct da850_opp da850_opp_300 = {
877 .freq = 300000,
878 .prediv = 1,
879 .mult = 25,
880 .postdiv = 2,
35f9acd8
SN		 881 .cvdd_min = 1140000,
882 .cvdd_max = 1320000,
683b1e1f
SN		 883};
884
885static const struct da850_opp da850_opp_200 = {
886 .freq = 200000,
887 .prediv = 1,
888 .mult = 25,
889 .postdiv = 3,
35f9acd8
SN		 890 .cvdd_min = 1050000,
891 .cvdd_max = 1160000,
683b1e1f
SN		 892};
893
894static const struct da850_opp da850_opp_96 = {
895 .freq = 96000,
896 .prediv = 1,
897 .mult = 20,
898 .postdiv = 5,
35f9acd8
SN		 899 .cvdd_min = 950000,
900 .cvdd_max = 1050000,
683b1e1f
SN		 901};
902
903#define OPP(freq) \
904 { \
905 .index = (unsigned int) &da850_opp_##freq, \
906 .frequency = freq * 1000, \
907 }
908
909static struct cpufreq_frequency_table da850_freq_table[] = {
910 OPP(300),
911 OPP(200),
912 OPP(96),
913 {
914 .index = 0,
915 .frequency = CPUFREQ_TABLE_END,
916 },
917};
918
13d5e27a
SN		 919#ifdef CONFIG_REGULATOR
920static struct regulator *cvdd;
921
922static int da850_set_voltage(unsigned int index)
923{
924 struct da850_opp *opp;
925
926 if (!cvdd)
927 return -ENODEV;
928
929 opp = (struct da850_opp *) da850_freq_table[index].index;
930
931 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
932}
933
934static int da850_regulator_init(void)
935{
936 cvdd = regulator_get(NULL, "cvdd");
937 if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;"
938 " voltage scaling unsupported\n")) {
939 return PTR_ERR(cvdd);
940 }
941
942 return 0;
943}
944#endif
945
683b1e1f
SN		 946static struct davinci_cpufreq_config cpufreq_info = {
947 .freq_table = &da850_freq_table[0],
13d5e27a
SN		 948#ifdef CONFIG_REGULATOR
949 .init = da850_regulator_init,
950 .set_voltage = da850_set_voltage,
951#endif
683b1e1f
SN		 952};
953
954static struct platform_device da850_cpufreq_device = {
955 .name = "cpufreq-davinci",
956 .dev = {
957 .platform_data = &cpufreq_info,
958 },
959};
960
961int __init da850_register_cpufreq(void)
962{
963 return platform_device_register(&da850_cpufreq_device);
964}
965
966static int da850_round_armrate(struct clk *clk, unsigned long rate)
967{
968 int i, ret = 0, diff;
969 unsigned int best = (unsigned int) -1;
970
971 rate /= 1000; /* convert to kHz */
972
973 for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
974 diff = da850_freq_table[i].frequency - rate;
975 if (diff < 0)
976 diff = -diff;
977
978 if (diff < best) {
979 best = diff;
980 ret = da850_freq_table[i].frequency;
981 }
982 }
983
984 return ret * 1000;
985}
986
987static int da850_set_armrate(struct clk *clk, unsigned long index)
988{
989 struct clk *pllclk = &pll0_clk;
990
991 return clk_set_rate(pllclk, index);
992}
993
994static int da850_set_pll0rate(struct clk *clk, unsigned long index)
995{
996 unsigned int prediv, mult, postdiv;
997 struct da850_opp *opp;
998 struct pll_data *pll = clk->pll_data;
683b1e1f
SN		 999 int ret;
1000
1001 opp = (struct da850_opp *) da850_freq_table[index].index;
1002 prediv = opp->prediv;
1003 mult = opp->mult;
1004 postdiv = opp->postdiv;
1005
683b1e1f
SN		 1006 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1007 if (WARN_ON(ret))
1008 return ret;
1009
1010 return 0;
1011}
1012#else
1013int __init da850_register_cpufreq(void)
1014{
1015 return 0;
1016}
1017
1018static int da850_set_armrate(struct clk *clk, unsigned long rate)
1019{
1020 return -EINVAL;
1021}
1022
1023static int da850_set_pll0rate(struct clk *clk, unsigned long armrate)
1024{
1025 return -EINVAL;
1026}
1027
1028static int da850_round_armrate(struct clk *clk, unsigned long rate)
1029{
1030 return clk->rate;
1031}
1032#endif
1033
044ca015
SN		 1034int da850_register_pm(struct platform_device *pdev)
1035{
1036 int ret;
1037 struct davinci_pm_config *pdata = pdev->dev.platform_data;
1038
1039 ret = davinci_cfg_reg(DA850_RTC_ALARM);
1040 if (ret)
1041 return ret;
1042
1043 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1044 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1045 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1046
1047 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1048 if (!pdata->cpupll_reg_base)
1049 return -ENOMEM;
1050
1051 pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
1052 if (!pdata->ddrpll_reg_base) {
1053 ret = -ENOMEM;
1054 goto no_ddrpll_mem;
1055 }
1056
1057 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1058 if (!pdata->ddrpsc_reg_base) {
1059 ret = -ENOMEM;
1060 goto no_ddrpsc_mem;
1061 }
1062
1063 return platform_device_register(pdev);
1064
1065no_ddrpsc_mem:
1066 iounmap(pdata->ddrpll_reg_base);
1067no_ddrpll_mem:
1068 iounmap(pdata->cpupll_reg_base);
1069 return ret;
1070}
35f9acd8 1071
e1a8d7e2
SR		 1072static struct davinci_soc_info davinci_soc_info_da850 = {
1073 .io_desc = da850_io_desc,
1074 .io_desc_num = ARRAY_SIZE(da850_io_desc),
e1a8d7e2
SR		 1075 .ids = da850_ids,
1076 .ids_num = ARRAY_SIZE(da850_ids),
1077 .cpu_clks = da850_clks,
1078 .psc_bases = da850_psc_bases,
1079 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
e1a8d7e2
SR		 1080 .pinmux_pins = da850_pins,
1081 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
1082 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
1083 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
1084 .intc_irq_prios = da850_default_priorities,
1085 .intc_irq_num = DA850_N_CP_INTC_IRQ,
1086 .timer_info = &da850_timer_info,
1087 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
5a8d5441 1088 .gpio_num = 144,
e1a8d7e2
SR		 1089 .gpio_irq = IRQ_DA8XX_GPIO0,
1090 .serial_dev = &da8xx_serial_device,
1091 .emac_pdata = &da8xx_emac_pdata,
60cd02e1
SN		 1092 .sram_dma = DA8XX_ARM_RAM_BASE,
1093 .sram_len = SZ_8K,
e1a8d7e2
SR		 1094};
1095
1096void __init da850_init(void)
1097{
7aad472b
SN		 1098 unsigned int v;
1099
d2de0582
SN		 1100 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1101 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1102 return;
1103
1104 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1105 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
6a28adef
SN		 1106 return;
1107
cd874448 1108 davinci_soc_info_da850.jtag_id_base =
d2de0582
SN		 1109 DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
1110 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
6a28adef 1111
e1a8d7e2 1112 davinci_common_init(&davinci_soc_info_da850);
5d36a332
SN		 1113
1114 /*
1115 * Move the clock source of Async3 domain to PLL1 SYSCLK2.
1116 * This helps keeping the peripherals on this domain insulated
1117 * from CPU frequency changes caused by DVFS. The firmware sets
1118 * both PLL0 and PLL1 to the same frequency so, there should not
1119 * be any noticible change even in non-DVFS use cases.
1120 */
1121 da850_set_async3_src(1);
7aad472b
SN		 1122
1123 /* Unlock writing to PLL0 registers */
1124 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1125 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1126 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1127
1128 /* Unlock writing to PLL1 registers */
1129 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1130 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1131 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
e1a8d7e2 1132}
Linux 6.x block layer and io_uring tree(s)