[linux-2.6-block.git] / arch / arm / mach-davinci / board-dm644x-evm.c

/*
 * TI DaVinci EVM board support
 *
 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
 *
 * 2007 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/memory.h>

#include <linux/i2c.h>
#include <linux/i2c/pcf857x.h>
#include <linux/i2c/at24.h>
#include <linux/etherdevice.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/io.h>
#include <linux/phy.h>
#include <linux/clk.h>

#include <asm/setup.h>
#include <asm/mach-types.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>

#include <mach/dm644x.h>
#include <mach/common.h>
#include <mach/i2c.h>
#include <mach/serial.h>
#include <mach/mux.h>
#include <mach/psc.h>
#include <mach/nand.h>
#include <mach/mmc.h>
#include <mach/emac.h>

#define DM644X_EVM_PHY_MASK		(0x2)
#define DM644X_EVM_MDIO_FREQUENCY	(2200000) /* PHY bus frequency */

#define DAVINCI_CFC_ATA_BASE		  0x01C66000

#define DAVINCI_ASYNC_EMIF_CONTROL_BASE   0x01e00000
#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE  0x02000000
#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE  0x04000000
#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE  0x06000000
#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE  0x08000000

#define LXT971_PHY_ID	(0x001378e2)
#define LXT971_PHY_MASK	(0xfffffff0)

static struct mtd_partition davinci_evm_norflash_partitions[] = {
	/* bootloader (UBL, U-Boot, etc) in first 5 sectors */
	{
		.name		= "bootloader",
		.offset		= 0,
		.size		= 5 * SZ_64K,
		.mask_flags	= MTD_WRITEABLE, /* force read-only */
	},
	/* bootloader params in the next 1 sectors */
	{
		.name		= "params",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_64K,
		.mask_flags	= 0,
	},
	/* kernel */
	{
		.name		= "kernel",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_2M,
		.mask_flags	= 0
	},
	/* file system */
	{
		.name		= "filesystem",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0
	}
};

static struct physmap_flash_data davinci_evm_norflash_data = {
	.width		= 2,
	.parts		= davinci_evm_norflash_partitions,
	.nr_parts	= ARRAY_SIZE(davinci_evm_norflash_partitions),
};

/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
 * limits addresses to 16M, so using addresses past 16M will wrap */
static struct resource davinci_evm_norflash_resource = {
	.start		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
	.end		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
	.flags		= IORESOURCE_MEM,
};

static struct platform_device davinci_evm_norflash_device = {
	.name		= "physmap-flash",
	.id		= 0,
	.dev		= {
		.platform_data	= &davinci_evm_norflash_data,
	},
	.num_resources	= 1,
	.resource	= &davinci_evm_norflash_resource,
};

/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
 * It may used instead of the (default) NOR chip to boot, using TI's
 * tools to install the secondary boot loader (UBL) and U-Boot.
 */
struct mtd_partition davinci_evm_nandflash_partition[] = {
	/* Bootloader layout depends on whose u-boot is installed, but we
	 * can hide all the details.
	 *  - block 0 for u-boot environment ... in mainline u-boot
	 *  - block 1 for UBL (plus up to four backup copies in blocks 2..5)
	 *  - blocks 6...? for u-boot
	 *  - blocks 16..23 for u-boot environment ... in TI's u-boot
	 */
	{
		.name		= "bootloader",
		.offset		= 0,
		.size		= SZ_256K + SZ_128K,
		.mask_flags	= MTD_WRITEABLE,	/* force read-only */
	},
	/* Kernel */
	{
		.name		= "kernel",
		.offset		= MTDPART_OFS_APPEND,
		.size		= SZ_4M,
		.mask_flags	= 0,
	},
	/* File system (older GIT kernels started this on the 5MB mark) */
	{
		.name		= "filesystem",
		.offset		= MTDPART_OFS_APPEND,
		.size		= MTDPART_SIZ_FULL,
		.mask_flags	= 0,
	}
	/* A few blocks at end hold a flash BBT ... created by TI's CCS
	 * using flashwriter_nand.out, but ignored by TI's versions of
	 * Linux and u-boot.  We boot faster by using them.
	 */
};

static struct davinci_nand_pdata davinci_evm_nandflash_data = {
	.parts		= davinci_evm_nandflash_partition,
	.nr_parts	= ARRAY_SIZE(davinci_evm_nandflash_partition),
	.ecc_mode	= NAND_ECC_HW,
	.options	= NAND_USE_FLASH_BBT,
};

static struct resource davinci_evm_nandflash_resource[] = {
	{
		.start		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
		.end		= DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= DAVINCI_ASYNC_EMIF_CONTROL_BASE,
		.end		= DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
		.flags		= IORESOURCE_MEM,
	},
};

static struct platform_device davinci_evm_nandflash_device = {
	.name		= "davinci_nand",
	.id		= 0,
	.dev		= {
		.platform_data	= &davinci_evm_nandflash_data,
	},
	.num_resources	= ARRAY_SIZE(davinci_evm_nandflash_resource),
	.resource	= davinci_evm_nandflash_resource,
};

static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);

static struct platform_device davinci_fb_device = {
	.name		= "davincifb",
	.id		= -1,
	.dev = {
		.dma_mask		= &davinci_fb_dma_mask,
		.coherent_dma_mask      = DMA_BIT_MASK(32),
	},
	.num_resources = 0,
};

static struct platform_device rtc_dev = {
	.name           = "rtc_davinci_evm",
	.id             = -1,
};

static struct resource ide_resources[] = {
	{
		.start          = DAVINCI_CFC_ATA_BASE,
		.end            = DAVINCI_CFC_ATA_BASE + 0x7ff,
		.flags          = IORESOURCE_MEM,
	},
	{
		.start          = IRQ_IDE,
		.end            = IRQ_IDE,
		.flags          = IORESOURCE_IRQ,
	},
};

static u64 ide_dma_mask = DMA_BIT_MASK(32);

static struct platform_device ide_dev = {
	.name           = "palm_bk3710",
	.id             = -1,
	.resource       = ide_resources,
	.num_resources  = ARRAY_SIZE(ide_resources),
	.dev = {
		.dma_mask		= &ide_dma_mask,
		.coherent_dma_mask      = DMA_BIT_MASK(32),
	},
};

/*----------------------------------------------------------------------*/

/*
 * I2C GPIO expanders
 */

#define PCF_Uxx_BASE(x)	(DAVINCI_N_GPIO + ((x) * 8))


/* U2 -- LEDs */

static struct gpio_led evm_leds[] = {
	{ .name = "DS8", .active_low = 1,
		.default_trigger = "heartbeat", },
	{ .name = "DS7", .active_low = 1, },
	{ .name = "DS6", .active_low = 1, },
	{ .name = "DS5", .active_low = 1, },
	{ .name = "DS4", .active_low = 1, },
	{ .name = "DS3", .active_low = 1, },
	{ .name = "DS2", .active_low = 1,
		.default_trigger = "mmc0", },
	{ .name = "DS1", .active_low = 1,
		.default_trigger = "ide-disk", },
};

static const struct gpio_led_platform_data evm_led_data = {
	.num_leds	= ARRAY_SIZE(evm_leds),
	.leds		= evm_leds,
};

static struct platform_device *evm_led_dev;

static int
evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
{
	struct gpio_led *leds = evm_leds;
	int status;

	while (ngpio--) {
		leds->gpio = gpio++;
		leds++;
	}

	/* what an extremely annoying way to be forced to handle
	 * device unregistration ...
	 */
	evm_led_dev = platform_device_alloc("leds-gpio", 0);
	platform_device_add_data(evm_led_dev,
			&evm_led_data, sizeof evm_led_data);

	evm_led_dev->dev.parent = &client->dev;
	status = platform_device_add(evm_led_dev);
	if (status < 0) {
		platform_device_put(evm_led_dev);
		evm_led_dev = NULL;
	}
	return status;
}

static int
evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
{
	if (evm_led_dev) {
		platform_device_unregister(evm_led_dev);
		evm_led_dev = NULL;
	}
	return 0;
}

static struct pcf857x_platform_data pcf_data_u2 = {
	.gpio_base	= PCF_Uxx_BASE(0),
	.setup		= evm_led_setup,
	.teardown	= evm_led_teardown,
};


/* U18 - A/V clock generator and user switch */

static int sw_gpio;

static ssize_t
sw_show(struct device *d, struct device_attribute *a, char *buf)
{
	char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";

	strcpy(buf, s);
	return strlen(s);
}

static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);

static int
evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
{
	int	status;

	/* export dip switch option */
	sw_gpio = gpio + 7;
	status = gpio_request(sw_gpio, "user_sw");
	if (status == 0)
		status = gpio_direction_input(sw_gpio);
	if (status == 0)
		status = device_create_file(&client->dev, &dev_attr_user_sw);
	else
		gpio_free(sw_gpio);
	if (status != 0)
		sw_gpio = -EINVAL;

	/* audio PLL:  48 kHz (vs 44.1 or 32), single rate (vs double) */
	gpio_request(gpio + 3, "pll_fs2");
	gpio_direction_output(gpio + 3, 0);

	gpio_request(gpio + 2, "pll_fs1");
	gpio_direction_output(gpio + 2, 0);

	gpio_request(gpio + 1, "pll_sr");
	gpio_direction_output(gpio + 1, 0);

	return 0;
}

static int
evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
{
	gpio_free(gpio + 1);
	gpio_free(gpio + 2);
	gpio_free(gpio + 3);

	if (sw_gpio > 0) {
		device_remove_file(&client->dev, &dev_attr_user_sw);
		gpio_free(sw_gpio);
	}
	return 0;
}

static struct pcf857x_platform_data pcf_data_u18 = {
	.gpio_base	= PCF_Uxx_BASE(1),
	.n_latch	= (1 << 3) | (1 << 2) | (1 << 1),
	.setup		= evm_u18_setup,
	.teardown	= evm_u18_teardown,
};


/* U35 - various I/O signals used to manage USB, CF, ATA, etc */

static int
evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
{
	/* p0 = nDRV_VBUS (initial:  don't supply it) */
	gpio_request(gpio + 0, "nDRV_VBUS");
	gpio_direction_output(gpio + 0, 1);

	/* p1 = VDDIMX_EN */
	gpio_request(gpio + 1, "VDDIMX_EN");
	gpio_direction_output(gpio + 1, 1);

	/* p2 = VLYNQ_EN */
	gpio_request(gpio + 2, "VLYNQ_EN");
	gpio_direction_output(gpio + 2, 1);

	/* p3 = n3V3_CF_RESET (initial: stay in reset) */
	gpio_request(gpio + 3, "nCF_RESET");
	gpio_direction_output(gpio + 3, 0);

	/* (p4 unused) */

	/* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
	gpio_request(gpio + 5, "WLAN_RESET");
	gpio_direction_output(gpio + 5, 1);

	/* p6 = nATA_SEL (initial: select) */
	gpio_request(gpio + 6, "nATA_SEL");
	gpio_direction_output(gpio + 6, 0);

	/* p7 = nCF_SEL (initial: deselect) */
	gpio_request(gpio + 7, "nCF_SEL");
	gpio_direction_output(gpio + 7, 1);

	/* irlml6401 switches over 1A, in under 8 msec;
	 * now it can be managed by nDRV_VBUS ...
	 */
	setup_usb(500, 8);

	return 0;
}

static int
evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
{
	gpio_free(gpio + 7);
	gpio_free(gpio + 6);
	gpio_free(gpio + 5);
	gpio_free(gpio + 3);
	gpio_free(gpio + 2);
	gpio_free(gpio + 1);
	gpio_free(gpio + 0);
	return 0;
}

static struct pcf857x_platform_data pcf_data_u35 = {
	.gpio_base	= PCF_Uxx_BASE(2),
	.setup		= evm_u35_setup,
	.teardown	= evm_u35_teardown,
};

/*----------------------------------------------------------------------*/

/* Most of this EEPROM is unused, but U-Boot uses some data:
 *  - 0x7f00, 6 bytes Ethernet Address
 *  - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
 *  - ... newer boards may have more
 */

static struct at24_platform_data eeprom_info = {
	.byte_len	= (256*1024) / 8,
	.page_size	= 64,
	.flags		= AT24_FLAG_ADDR16,
	.setup          = davinci_get_mac_addr,
	.context	= (void *)0x7f00,
};

/*
 * MSP430 supports RTC, card detection, input from IR remote, and
 * a bit more.  It triggers interrupts on GPIO(7) from pressing
 * buttons on the IR remote, and for card detect switches.
 */
static struct i2c_client *dm6446evm_msp;

static int dm6446evm_msp_probe(struct i2c_client *client,
		const struct i2c_device_id *id)
{
	dm6446evm_msp = client;
	return 0;
}

static int dm6446evm_msp_remove(struct i2c_client *client)
{
	dm6446evm_msp = NULL;
	return 0;
}

static const struct i2c_device_id dm6446evm_msp_ids[] = {
	{ "dm6446evm_msp", 0, },
	{ /* end of list */ },
};

static struct i2c_driver dm6446evm_msp_driver = {
	.driver.name	= "dm6446evm_msp",
	.id_table	= dm6446evm_msp_ids,
	.probe		= dm6446evm_msp_probe,
	.remove		= dm6446evm_msp_remove,
};

static int dm6444evm_msp430_get_pins(void)
{
	static const char txbuf[2] = { 2, 4, };
	char buf[4];
	struct i2c_msg msg[2] = {
		{
			.addr = dm6446evm_msp->addr,
			.flags = 0,
			.len = 2,
			.buf = (void __force *)txbuf,
		},
		{
			.addr = dm6446evm_msp->addr,
			.flags = I2C_M_RD,
			.len = 4,
			.buf = buf,
		},
	};
	int status;

	if (!dm6446evm_msp)
		return -ENXIO;

	/* Command 4 == get input state, returns port 2 and port3 data
	 *   S Addr W [A] len=2 [A] cmd=4 [A]
	 *   RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
	 */
	status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
	if (status < 0)
		return status;

	dev_dbg(&dm6446evm_msp->dev,
		"PINS: %02x %02x %02x %02x\n",
		buf[0], buf[1], buf[2], buf[3]);

	return (buf[3] << 8) | buf[2];
}

static int dm6444evm_mmc_get_cd(int module)
{
	int status = dm6444evm_msp430_get_pins();

	return (status < 0) ? status : !(status & BIT(1));
}

static int dm6444evm_mmc_get_ro(int module)
{
	int status = dm6444evm_msp430_get_pins();

	return (status < 0) ? status : status & BIT(6 + 8);
}

static struct davinci_mmc_config dm6446evm_mmc_config = {
	.get_cd		= dm6444evm_mmc_get_cd,
	.get_ro		= dm6444evm_mmc_get_ro,
	.wires		= 4,
	.version	= MMC_CTLR_VERSION_1
};

static struct i2c_board_info __initdata i2c_info[] =  {
	{
		I2C_BOARD_INFO("dm6446evm_msp", 0x23),
	},
	{
		I2C_BOARD_INFO("pcf8574", 0x38),
		.platform_data	= &pcf_data_u2,
	},
	{
		I2C_BOARD_INFO("pcf8574", 0x39),
		.platform_data	= &pcf_data_u18,
	},
	{
		I2C_BOARD_INFO("pcf8574", 0x3a),
		.platform_data	= &pcf_data_u35,
	},
	{
		I2C_BOARD_INFO("24c256", 0x50),
		.platform_data	= &eeprom_info,
	},
	/* ALSO:
	 * - tvl320aic33 audio codec (0x1b)
	 * - tvp5146 video decoder (0x5d)
	 */
};

/* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
 * which requires 100 usec of idle bus after i2c writes sent to it.
 */
static struct davinci_i2c_platform_data i2c_pdata = {
	.bus_freq	= 20 /* kHz */,
	.bus_delay	= 100 /* usec */,
};

static void __init evm_init_i2c(void)
{
	davinci_init_i2c(&i2c_pdata);
	i2c_add_driver(&dm6446evm_msp_driver);
	i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
}

static struct platform_device *davinci_evm_devices[] __initdata = {
	&davinci_fb_device,
	&rtc_dev,
};

static struct davinci_uart_config uart_config __initdata = {
	.enabled_uarts = (1 << 0),
};

static void __init
davinci_evm_map_io(void)
{
	dm644x_init();
}

static int davinci_phy_fixup(struct phy_device *phydev)
{
	unsigned int control;
	/* CRITICAL: Fix for increasing PHY signal drive strength for
	 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
	 * signal strength was low causing  TX to fail randomly. The
	 * fix is to Set bit 11 (Increased MII drive strength) of PHY
	 * register 26 (Digital Config register) on this phy. */
	control = phy_read(phydev, 26);
	phy_write(phydev, 26, (control | 0x800));
	return 0;
}

#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
#define HAS_ATA 1
#else
#define HAS_ATA 0
#endif

#if defined(CONFIG_MTD_PHYSMAP) || \
    defined(CONFIG_MTD_PHYSMAP_MODULE)
#define HAS_NOR 1
#else
#define HAS_NOR 0
#endif

#if defined(CONFIG_MTD_NAND_DAVINCI) || \
    defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
#define HAS_NAND 1
#else
#define HAS_NAND 0
#endif

static __init void davinci_evm_init(void)
{
	struct clk *aemif_clk;
	struct davinci_soc_info *soc_info = &davinci_soc_info;

	aemif_clk = clk_get(NULL, "aemif");
	clk_enable(aemif_clk);

	if (HAS_ATA) {
		if (HAS_NAND || HAS_NOR)
			pr_warning("WARNING: both IDE and Flash are "
				"enabled, but they share AEMIF pins.\n"
				"\tDisable IDE for NAND/NOR support.\n");
		davinci_cfg_reg(DM644X_HPIEN_DISABLE);
		davinci_cfg_reg(DM644X_ATAEN);
		davinci_cfg_reg(DM644X_HDIREN);
		platform_device_register(&ide_dev);
	} else if (HAS_NAND || HAS_NOR) {
		davinci_cfg_reg(DM644X_HPIEN_DISABLE);
		davinci_cfg_reg(DM644X_ATAEN_DISABLE);

		/* only one device will be jumpered and detected */
		if (HAS_NAND) {
			platform_device_register(&davinci_evm_nandflash_device);
			evm_leds[7].default_trigger = "nand-disk";
			if (HAS_NOR)
				pr_warning("WARNING: both NAND and NOR flash "
					"are enabled; disable one of them.\n");
		} else if (HAS_NOR)
			platform_device_register(&davinci_evm_norflash_device);
	}

	platform_add_devices(davinci_evm_devices,
			     ARRAY_SIZE(davinci_evm_devices));
	evm_init_i2c();

	davinci_setup_mmc(0, &dm6446evm_mmc_config);

	davinci_serial_init(&uart_config);

	soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK;
	soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY;

	/* Register the fixup for PHY on DaVinci */
	phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
					davinci_phy_fixup);

}

static __init void davinci_evm_irq_init(void)
{
	davinci_irq_init();
}

MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
	/* Maintainer: MontaVista Software <source@mvista.com> */
	.phys_io      = IO_PHYS,
	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
	.boot_params  = (DAVINCI_DDR_BASE + 0x100),
	.map_io	      = davinci_evm_map_io,
	.init_irq     = davinci_evm_irq_init,
	.timer	      = &davinci_timer,
	.init_machine = davinci_evm_init,
MACHINE_END
Commit	Line	Data
7c6337e2 KH	1	/*
	2	* TI DaVinci EVM board support
	3	*
	4	* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
	5	*
	6	* 2007 (c) MontaVista Software, Inc. This file is licensed under
	7	* the terms of the GNU General Public License version 2. This program
	8	* is licensed "as is" without any warranty of any kind, whether express
	9	* or implied.
	10	*/
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/init.h>
	14	#include <linux/dma-mapping.h>
	15	#include <linux/platform_device.h>
7bff3c4c DB	16	#include <linux/gpio.h>
7bff3c4c DB	17	#include <linux/leds.h>
d0e47fba	18	#include <linux/memory.h>
7bff3c4c DB	19
	20	#include <linux/i2c.h>
	21	#include <linux/i2c/pcf857x.h>
	22	#include <linux/i2c/at24.h>
ac7b75b5	23	#include <linux/etherdevice.h>
7c6337e2	24	#include <linux/mtd/mtd.h>
d0e47fba	25	#include <linux/mtd/nand.h>
7c6337e2 KH	26	#include <linux/mtd/partitions.h>
7c6337e2 KH	27	#include <linux/mtd/physmap.h>
fced80c7	28	#include <linux/io.h>
d0e47fba KH	29	#include <linux/phy.h>
d0e47fba KH	30	#include <linux/clk.h>
7c6337e2 KH	31
7c6337e2 KH	32	#include <asm/setup.h>
7c6337e2	33	#include <asm/mach-types.h>
7c6337e2 KH	34
	35	#include <asm/mach/arch.h>
	36	#include <asm/mach/map.h>
	37	#include <asm/mach/flash.h>
	38
d0e47fba	39	#include <mach/dm644x.h>
a09e64fb	40	#include <mach/common.h>
7bff3c4c	41	#include <mach/i2c.h>
d0e47fba KH	42	#include <mach/serial.h>
	43	#include <mach/mux.h>
	44	#include <mach/psc.h>
	45	#include <mach/nand.h>
2dbf56ae	46	#include <mach/mmc.h>
b14dc0f9	47	#include <mach/emac.h>
d0e47fba KH	48
	49	#define DM644X_EVM_PHY_MASK (0x2)
	50	#define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
7c6337e2	51
f5c122da	52	#define DAVINCI_CFC_ATA_BASE 0x01C66000
f5c122da	53
d0e47fba KH	54	#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
	55	#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
	56	#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
	57	#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
	58	#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
7c6337e2	59
d0e47fba KH	60	#define LXT971_PHY_ID (0x001378e2)
d0e47fba KH	61	#define LXT971_PHY_MASK (0xfffffff0)
7c6337e2	62
7bff3c4c	63	static struct mtd_partition davinci_evm_norflash_partitions[] = {
d0e47fba	64	/* bootloader (UBL, U-Boot, etc) in first 5 sectors */
7c6337e2 KH	65	{
	66	.name = "bootloader",
	67	.offset = 0,
d0e47fba	68	.size = 5 * SZ_64K,
7c6337e2 KH	69	.mask_flags = MTD_WRITEABLE, /* force read-only */
	70	},
	71	/* bootloader params in the next 1 sectors */
	72	{
	73	.name = "params",
	74	.offset = MTDPART_OFS_APPEND,
	75	.size = SZ_64K,
	76	.mask_flags = 0,
	77	},
	78	/* kernel */
	79	{
	80	.name = "kernel",
	81	.offset = MTDPART_OFS_APPEND,
	82	.size = SZ_2M,
	83	.mask_flags = 0
	84	},
	85	/* file system */
	86	{
	87	.name = "filesystem",
	88	.offset = MTDPART_OFS_APPEND,
	89	.size = MTDPART_SIZ_FULL,
	90	.mask_flags = 0
	91	}
	92	};
	93
7bff3c4c	94	static struct physmap_flash_data davinci_evm_norflash_data = {
7c6337e2	95	.width = 2,
7bff3c4c DB	96	.parts = davinci_evm_norflash_partitions,
7bff3c4c DB	97	.nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions),
7c6337e2 KH	98	};
	99
	100	/* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
	101	* limits addresses to 16M, so using addresses past 16M will wrap */
7bff3c4c DB	102	static struct resource davinci_evm_norflash_resource = {
	103	.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
	104	.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
7c6337e2 KH	105	.flags = IORESOURCE_MEM,
	106	};
	107
7bff3c4c	108	static struct platform_device davinci_evm_norflash_device = {
7c6337e2 KH	109	.name = "physmap-flash",
	110	.id = 0,
	111	.dev = {
7bff3c4c	112	.platform_data = &davinci_evm_norflash_data,
7c6337e2 KH	113	},
7c6337e2 KH	114	.num_resources = 1,
7bff3c4c DB	115	.resource = &davinci_evm_norflash_resource,
	116	};
	117
3e9c18e1 DB	118	/* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
	119	* It may used instead of the (default) NOR chip to boot, using TI's
	120	* tools to install the secondary boot loader (UBL) and U-Boot.
	121	*/
d0e47fba	122	struct mtd_partition davinci_evm_nandflash_partition[] = {
3e9c18e1 DB	123	/* Bootloader layout depends on whose u-boot is installed, but we
	124	* can hide all the details.
	125	* - block 0 for u-boot environment ... in mainline u-boot
	126	* - block 1 for UBL (plus up to four backup copies in blocks 2..5)
	127	* - blocks 6...? for u-boot
	128	* - blocks 16..23 for u-boot environment ... in TI's u-boot
	129	*/
	130	{
	131	.name = "bootloader",
	132	.offset = 0,
	133	.size = SZ_256K + SZ_128K,
	134	.mask_flags = MTD_WRITEABLE, /* force read-only */
	135	},
	136	/* Kernel */
d0e47fba	137	{
3e9c18e1 DB	138	.name = "kernel",
	139	.offset = MTDPART_OFS_APPEND,
	140	.size = SZ_4M,
	141	.mask_flags = 0,
	142	},
	143	/* File system (older GIT kernels started this on the 5MB mark) */
	144	{
	145	.name = "filesystem",
	146	.offset = MTDPART_OFS_APPEND,
d0e47fba KH	147	.size = MTDPART_SIZ_FULL,
	148	.mask_flags = 0,
	149	}
3e9c18e1 DB	150	/* A few blocks at end hold a flash BBT ... created by TI's CCS
	151	* using flashwriter_nand.out, but ignored by TI's versions of
	152	* Linux and u-boot. We boot faster by using them.
	153	*/
d0e47fba	154	};
7bff3c4c	155
d0e47fba KH	156	static struct davinci_nand_pdata davinci_evm_nandflash_data = {
	157	.parts = davinci_evm_nandflash_partition,
	158	.nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
	159	.ecc_mode = NAND_ECC_HW,
3e9c18e1	160	.options = NAND_USE_FLASH_BBT,
d0e47fba KH	161	};
	162
	163	static struct resource davinci_evm_nandflash_resource[] = {
	164	{
	165	.start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
	166	.end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
	167	.flags = IORESOURCE_MEM,
	168	}, {
	169	.start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
	170	.end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
	171	.flags = IORESOURCE_MEM,
	172	},
	173	};
	174
	175	static struct platform_device davinci_evm_nandflash_device = {
	176	.name = "davinci_nand",
	177	.id = 0,
	178	.dev = {
	179	.platform_data = &davinci_evm_nandflash_data,
	180	},
	181	.num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
	182	.resource = davinci_evm_nandflash_resource,
	183	};
	184
3e9c18e1	185	static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
d0e47fba KH	186
	187	static struct platform_device davinci_fb_device = {
	188	.name = "davincifb",
	189	.id = -1,
	190	.dev = {
	191	.dma_mask = &davinci_fb_dma_mask,
3e9c18e1	192	.coherent_dma_mask = DMA_BIT_MASK(32),
d0e47fba KH	193	},
	194	.num_resources = 0,
	195	};
	196
	197	static struct platform_device rtc_dev = {
	198	.name = "rtc_davinci_evm",
	199	.id = -1,
	200	};
7bff3c4c DB	201
	202	static struct resource ide_resources[] = {
	203	{
	204	.start = DAVINCI_CFC_ATA_BASE,
	205	.end = DAVINCI_CFC_ATA_BASE + 0x7ff,
	206	.flags = IORESOURCE_MEM,
	207	},
	208	{
	209	.start = IRQ_IDE,
	210	.end = IRQ_IDE,
	211	.flags = IORESOURCE_IRQ,
	212	},
	213	};
	214
a029b706	215	static u64 ide_dma_mask = DMA_BIT_MASK(32);
7bff3c4c DB	216
	217	static struct platform_device ide_dev = {
	218	.name = "palm_bk3710",
	219	.id = -1,
	220	.resource = ide_resources,
	221	.num_resources = ARRAY_SIZE(ide_resources),
	222	.dev = {
	223	.dma_mask = &ide_dma_mask,
a029b706	224	.coherent_dma_mask = DMA_BIT_MASK(32),
7bff3c4c DB	225	},
	226	};
	227
7bff3c4c DB	228	/----------------------------------------------------------------------/
	229
	230	/*
	231	* I2C GPIO expanders
	232	*/
	233
	234	#define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
	235
	236
	237	/* U2 -- LEDs */
	238
	239	static struct gpio_led evm_leds[] = {
	240	{ .name = "DS8", .active_low = 1,
	241	.default_trigger = "heartbeat", },
	242	{ .name = "DS7", .active_low = 1, },
	243	{ .name = "DS6", .active_low = 1, },
	244	{ .name = "DS5", .active_low = 1, },
	245	{ .name = "DS4", .active_low = 1, },
	246	{ .name = "DS3", .active_low = 1, },
	247	{ .name = "DS2", .active_low = 1,
	248	.default_trigger = "mmc0", },
	249	{ .name = "DS1", .active_low = 1,
	250	.default_trigger = "ide-disk", },
	251	};
	252
	253	static const struct gpio_led_platform_data evm_led_data = {
	254	.num_leds = ARRAY_SIZE(evm_leds),
	255	.leds = evm_leds,
	256	};
	257
	258	static struct platform_device *evm_led_dev;
	259
	260	static int
	261	evm_led_setup(struct i2c_client client, int gpio, unsigned ngpio, void c)
	262	{
	263	struct gpio_led *leds = evm_leds;
	264	int status;
	265
	266	while (ngpio--) {
	267	leds->gpio = gpio++;
	268	leds++;
	269	}
	270
	271	/* what an extremely annoying way to be forced to handle
	272	* device unregistration ...
	273	*/
	274	evm_led_dev = platform_device_alloc("leds-gpio", 0);
	275	platform_device_add_data(evm_led_dev,
	276	&evm_led_data, sizeof evm_led_data);
	277
	278	evm_led_dev->dev.parent = &client->dev;
	279	status = platform_device_add(evm_led_dev);
	280	if (status < 0) {
	281	platform_device_put(evm_led_dev);
	282	evm_led_dev = NULL;
	283	}
	284	return status;
	285	}
	286
	287	static int
	288	evm_led_teardown(struct i2c_client client, int gpio, unsigned ngpio, void c)
	289	{
	290	if (evm_led_dev) {
	291	platform_device_unregister(evm_led_dev);
292	evm_led_dev = NULL;
293	}
294	return 0;
295	}
296
297	static struct pcf857x_platform_data pcf_data_u2 = {
298	.gpio_base = PCF_Uxx_BASE(0),
299	.setup = evm_led_setup,
300	.teardown = evm_led_teardown,
301	};
302
303
304	/* U18 - A/V clock generator and user switch */
305
306	static int sw_gpio;
307
308	static ssize_t
309	sw_show(struct device d, struct device_attribute a, char *buf)
310	{
311	char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
312
313	strcpy(buf, s);
314	return strlen(s);
315	}
316
317	static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
318
319	static int
320	evm_u18_setup(struct i2c_client client, int gpio, unsigned ngpio, void c)
321	{
322	int status;
323
324	/* export dip switch option */
325	sw_gpio = gpio + 7;
326	status = gpio_request(sw_gpio, "user_sw");
327	if (status == 0)
328	status = gpio_direction_input(sw_gpio);
329	if (status == 0)
330	status = device_create_file(&client->dev, &dev_attr_user_sw);
331	else
332	gpio_free(sw_gpio);
333	if (status != 0)
334	sw_gpio = -EINVAL;
335
336	/* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
337	gpio_request(gpio + 3, "pll_fs2");
338	gpio_direction_output(gpio + 3, 0);
339
340	gpio_request(gpio + 2, "pll_fs1");
341	gpio_direction_output(gpio + 2, 0);
342
343	gpio_request(gpio + 1, "pll_sr");
344	gpio_direction_output(gpio + 1, 0);
345
346	return 0;
347	}
348
349	static int
350	evm_u18_teardown(struct i2c_client client, int gpio, unsigned ngpio, void c)
351	{
352	gpio_free(gpio + 1);
353	gpio_free(gpio + 2);
354	gpio_free(gpio + 3);
355
356	if (sw_gpio > 0) {
357	device_remove_file(&client->dev, &dev_attr_user_sw);
358	gpio_free(sw_gpio);
359	}
360	return 0;
361	}
362
363	static struct pcf857x_platform_data pcf_data_u18 = {
364	.gpio_base = PCF_Uxx_BASE(1),
365	.n_latch = (1 << 3) \| (1 << 2) \| (1 << 1),
366	.setup = evm_u18_setup,
367	.teardown = evm_u18_teardown,
7c6337e2 KH	368	};
7c6337e2 KH	369
7bff3c4c DB	370
	371	/* U35 - various I/O signals used to manage USB, CF, ATA, etc */
	372
	373	static int
	374	evm_u35_setup(struct i2c_client client, int gpio, unsigned ngpio, void c)
	375	{
	376	/* p0 = nDRV_VBUS (initial: don't supply it) */
	377	gpio_request(gpio + 0, "nDRV_VBUS");
	378	gpio_direction_output(gpio + 0, 1);
	379
	380	/* p1 = VDDIMX_EN */
	381	gpio_request(gpio + 1, "VDDIMX_EN");
	382	gpio_direction_output(gpio + 1, 1);
	383
	384	/* p2 = VLYNQ_EN */
	385	gpio_request(gpio + 2, "VLYNQ_EN");
	386	gpio_direction_output(gpio + 2, 1);
	387
	388	/* p3 = n3V3_CF_RESET (initial: stay in reset) */
	389	gpio_request(gpio + 3, "nCF_RESET");
	390	gpio_direction_output(gpio + 3, 0);
	391
	392	/* (p4 unused) */
	393
	394	/* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
	395	gpio_request(gpio + 5, "WLAN_RESET");
	396	gpio_direction_output(gpio + 5, 1);
	397
	398	/* p6 = nATA_SEL (initial: select) */
	399	gpio_request(gpio + 6, "nATA_SEL");
	400	gpio_direction_output(gpio + 6, 0);
	401
	402	/* p7 = nCF_SEL (initial: deselect) */
	403	gpio_request(gpio + 7, "nCF_SEL");
	404	gpio_direction_output(gpio + 7, 1);
	405
d0e47fba KH	406	/* irlml6401 switches over 1A, in under 8 msec;
	407	* now it can be managed by nDRV_VBUS ...
	408	*/
34f32c97 DB	409	setup_usb(500, 8);
34f32c97 DB	410
7bff3c4c DB	411	return 0;
	412	}
	413
	414	static int
	415	evm_u35_teardown(struct i2c_client client, int gpio, unsigned ngpio, void c)
	416	{
	417	gpio_free(gpio + 7);
	418	gpio_free(gpio + 6);
	419	gpio_free(gpio + 5);
	420	gpio_free(gpio + 3);
	421	gpio_free(gpio + 2);
	422	gpio_free(gpio + 1);
	423	gpio_free(gpio + 0);
	424	return 0;
	425	}
	426
	427	static struct pcf857x_platform_data pcf_data_u35 = {
	428	.gpio_base = PCF_Uxx_BASE(2),
	429	.setup = evm_u35_setup,
	430	.teardown = evm_u35_teardown,
	431	};
	432
	433	/----------------------------------------------------------------------/
	434
	435	/* Most of this EEPROM is unused, but U-Boot uses some data:
	436	* - 0x7f00, 6 bytes Ethernet Address
	437	* - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
	438	* - ... newer boards may have more
	439	*/
d0e47fba	440
7bff3c4c DB	441	static struct at24_platform_data eeprom_info = {
	442	.byte_len = (256*1024) / 8,
	443	.page_size = 64,
	444	.flags = AT24_FLAG_ADDR16,
b14dc0f9 MG	445	.setup = davinci_get_mac_addr,
b14dc0f9 MG	446	.context = (void *)0x7f00,
d0e47fba KH	447	};
d0e47fba KH	448
d0e47fba KH	449	/*
	450	* MSP430 supports RTC, card detection, input from IR remote, and
	451	* a bit more. It triggers interrupts on GPIO(7) from pressing
	452	* buttons on the IR remote, and for card detect switches.
	453	*/
	454	static struct i2c_client *dm6446evm_msp;
	455
	456	static int dm6446evm_msp_probe(struct i2c_client *client,
	457	const struct i2c_device_id *id)
	458	{
	459	dm6446evm_msp = client;
	460	return 0;
	461	}
	462
	463	static int dm6446evm_msp_remove(struct i2c_client *client)
	464	{
	465	dm6446evm_msp = NULL;
	466	return 0;
	467	}
	468
	469	static const struct i2c_device_id dm6446evm_msp_ids[] = {
	470	{ "dm6446evm_msp", 0, },
	471	{ /* end of list */ },
	472	};
	473
	474	static struct i2c_driver dm6446evm_msp_driver = {
	475	.driver.name = "dm6446evm_msp",
	476	.id_table = dm6446evm_msp_ids,
	477	.probe = dm6446evm_msp_probe,
	478	.remove = dm6446evm_msp_remove,
7bff3c4c DB	479	};
7bff3c4c DB	480
d0e47fba KH	481	static int dm6444evm_msp430_get_pins(void)
	482	{
	483	static const char txbuf[2] = { 2, 4, };
	484	char buf[4];
	485	struct i2c_msg msg[2] = {
	486	{
	487	.addr = dm6446evm_msp->addr,
	488	.flags = 0,
	489	.len = 2,
	490	.buf = (void __force *)txbuf,
	491	},
	492	{
	493	.addr = dm6446evm_msp->addr,
	494	.flags = I2C_M_RD,
	495	.len = 4,
	496	.buf = buf,
	497	},
	498	};
	499	int status;
	500
	501	if (!dm6446evm_msp)
	502	return -ENXIO;
	503
	504	/* Command 4 == get input state, returns port 2 and port3 data
	505	* S Addr W [A] len=2 [A] cmd=4 [A]
	506	* RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
	507	*/
	508	status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
	509	if (status < 0)
	510	return status;
	511
	512	dev_dbg(&dm6446evm_msp->dev,
	513	"PINS: %02x %02x %02x %02x\n",
	514	buf[0], buf[1], buf[2], buf[3]);
	515
	516	return (buf[3] << 8) \| buf[2];
	517	}
	518
2dbf56ae KH	519	static int dm6444evm_mmc_get_cd(int module)
	520	{
	521	int status = dm6444evm_msp430_get_pins();
	522
	523	return (status < 0) ? status : !(status & BIT(1));
	524	}
	525
	526	static int dm6444evm_mmc_get_ro(int module)
	527	{
	528	int status = dm6444evm_msp430_get_pins();
	529
	530	return (status < 0) ? status : status & BIT(6 + 8);
	531	}
	532
	533	static struct davinci_mmc_config dm6446evm_mmc_config = {
	534	.get_cd = dm6444evm_mmc_get_cd,
	535	.get_ro = dm6444evm_mmc_get_ro,
	536	.wires = 4,
	537	.version = MMC_CTLR_VERSION_1
	538	};
	539
7bff3c4c	540	static struct i2c_board_info __initdata i2c_info[] = {
d0e47fba KH	541	{
	542	I2C_BOARD_INFO("dm6446evm_msp", 0x23),
	543	},
7bff3c4c DB	544	{
	545	I2C_BOARD_INFO("pcf8574", 0x38),
	546	.platform_data = &pcf_data_u2,
	547	},
	548	{
	549	I2C_BOARD_INFO("pcf8574", 0x39),
	550	.platform_data = &pcf_data_u18,
	551	},
	552	{
	553	I2C_BOARD_INFO("pcf8574", 0x3a),
	554	.platform_data = &pcf_data_u35,
	555	},
	556	{
	557	I2C_BOARD_INFO("24c256", 0x50),
	558	.platform_data = &eeprom_info,
	559	},
	560	/* ALSO:
	561	* - tvl320aic33 audio codec (0x1b)
7bff3c4c DB	562	* - tvp5146 video decoder (0x5d)
	563	*/
	564	};
	565
	566	/* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
	567	* which requires 100 usec of idle bus after i2c writes sent to it.
	568	*/
	569	static struct davinci_i2c_platform_data i2c_pdata = {
	570	.bus_freq = 20 /* kHz */,
	571	.bus_delay = 100 /* usec */,
	572	};
	573
	574	static void __init evm_init_i2c(void)
	575	{
	576	davinci_init_i2c(&i2c_pdata);
d0e47fba	577	i2c_add_driver(&dm6446evm_msp_driver);
7bff3c4c DB	578	i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
	579	}
	580
7c6337e2	581	static struct platform_device *davinci_evm_devices[] __initdata = {
d0e47fba KH	582	&davinci_fb_device,
	583	&rtc_dev,
	584	};
	585
	586	static struct davinci_uart_config uart_config __initdata = {
	587	.enabled_uarts = (1 << 0),
7c6337e2 KH	588	};
	589
	590	static void __init
	591	davinci_evm_map_io(void)
	592	{
d0e47fba	593	dm644x_init();
7c6337e2 KH	594	}
7c6337e2 KH	595
d0e47fba	596	static int davinci_phy_fixup(struct phy_device *phydev)
7c6337e2	597	{
d0e47fba KH	598	unsigned int control;
	599	/* CRITICAL: Fix for increasing PHY signal drive strength for
	600	* TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
	601	* signal strength was low causing TX to fail randomly. The
	602	* fix is to Set bit 11 (Increased MII drive strength) of PHY
	603	* register 26 (Digital Config register) on this phy. */
	604	control = phy_read(phydev, 26);
	605	phy_write(phydev, 26, (control \| 0x800));
	606	return 0;
	607	}
	608
7bff3c4c DB	609	#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) \|\| \
7bff3c4c DB	610	defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
d0e47fba KH	611	#define HAS_ATA 1
	612	#else
	613	#define HAS_ATA 0
	614	#endif
	615
7bff3c4c DB	616	#if defined(CONFIG_MTD_PHYSMAP) \|\| \
7bff3c4c DB	617	defined(CONFIG_MTD_PHYSMAP_MODULE)
d0e47fba KH	618	#define HAS_NOR 1
	619	#else
	620	#define HAS_NOR 0
7bff3c4c	621	#endif
d0e47fba KH	622
	623	#if defined(CONFIG_MTD_NAND_DAVINCI) \|\| \
	624	defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
	625	#define HAS_NAND 1
	626	#else
	627	#define HAS_NAND 0
7c6337e2 KH	628	#endif
7c6337e2 KH	629
d0e47fba KH	630	static __init void davinci_evm_init(void)
	631	{
	632	struct clk *aemif_clk;
972412b6	633	struct davinci_soc_info *soc_info = &davinci_soc_info;
d0e47fba KH	634
	635	aemif_clk = clk_get(NULL, "aemif");
	636	clk_enable(aemif_clk);
	637
	638	if (HAS_ATA) {
	639	if (HAS_NAND \|\| HAS_NOR)
	640	pr_warning("WARNING: both IDE and Flash are "
	641	"enabled, but they share AEMIF pins.\n"
	642	"\tDisable IDE for NAND/NOR support.\n");
	643	davinci_cfg_reg(DM644X_HPIEN_DISABLE);
	644	davinci_cfg_reg(DM644X_ATAEN);
	645	davinci_cfg_reg(DM644X_HDIREN);
	646	platform_device_register(&ide_dev);
	647	} else if (HAS_NAND \|\| HAS_NOR) {
	648	davinci_cfg_reg(DM644X_HPIEN_DISABLE);
	649	davinci_cfg_reg(DM644X_ATAEN_DISABLE);
	650
	651	/* only one device will be jumpered and detected */
	652	if (HAS_NAND) {
	653	platform_device_register(&davinci_evm_nandflash_device);
	654	evm_leds[7].default_trigger = "nand-disk";
	655	if (HAS_NOR)
	656	pr_warning("WARNING: both NAND and NOR flash "
	657	"are enabled; disable one of them.\n");
	658	} else if (HAS_NOR)
	659	platform_device_register(&davinci_evm_norflash_device);
	660	}
	661
7c6337e2 KH	662	platform_add_devices(davinci_evm_devices,
7c6337e2 KH	663	ARRAY_SIZE(davinci_evm_devices));
7bff3c4c	664	evm_init_i2c();
d0e47fba	665
2dbf56ae KH	666	davinci_setup_mmc(0, &dm6446evm_mmc_config);
2dbf56ae KH	667
d0e47fba KH	668	davinci_serial_init(&uart_config);
d0e47fba KH	669
972412b6 MG	670	soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK;
972412b6 MG	671	soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY;
ac7b75b5	672
d0e47fba KH	673	/* Register the fixup for PHY on DaVinci */
	674	phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
	675	davinci_phy_fixup);
	676
7c6337e2 KH	677	}
	678
	679	static __init void davinci_evm_irq_init(void)
	680	{
	681	davinci_irq_init();
	682	}
	683
d0e47fba	684	MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
7c6337e2 KH	685	/* Maintainer: MontaVista Software <source@mvista.com> */
7c6337e2 KH	686	.phys_io = IO_PHYS,
ac7643e4	687	.io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
7c6337e2 KH	688	.boot_params = (DAVINCI_DDR_BASE + 0x100),
	689	.map_io = davinci_evm_map_io,
	690	.init_irq = davinci_evm_irq_init,
	691	.timer = &davinci_timer,
	692	.init_machine = davinci_evm_init,
	693	MACHINE_END