Commit | Line | Data |
---|---|---|
7c6337e2 KH |
1 | /* |
2 | * TI DaVinci EVM board support | |
3 | * | |
4 | * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com> | |
5 | * | |
6 | * 2007 (c) MontaVista Software, Inc. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | */ | |
11 | #include <linux/kernel.h> | |
7c6337e2 KH |
12 | #include <linux/init.h> |
13 | #include <linux/dma-mapping.h> | |
14 | #include <linux/platform_device.h> | |
7bff3c4c | 15 | #include <linux/gpio.h> |
7bff3c4c DB |
16 | #include <linux/i2c.h> |
17 | #include <linux/i2c/pcf857x.h> | |
18 | #include <linux/i2c/at24.h> | |
7c6337e2 | 19 | #include <linux/mtd/mtd.h> |
d0e47fba | 20 | #include <linux/mtd/nand.h> |
7c6337e2 KH |
21 | #include <linux/mtd/partitions.h> |
22 | #include <linux/mtd/physmap.h> | |
d0e47fba KH |
23 | #include <linux/phy.h> |
24 | #include <linux/clk.h> | |
ab8e8df8 MK |
25 | #include <linux/videodev2.h> |
26 | ||
27 | #include <media/tvp514x.h> | |
7c6337e2 | 28 | |
7c6337e2 | 29 | #include <asm/mach-types.h> |
7c6337e2 | 30 | #include <asm/mach/arch.h> |
7c6337e2 | 31 | |
d0e47fba | 32 | #include <mach/dm644x.h> |
a09e64fb | 33 | #include <mach/common.h> |
7bff3c4c | 34 | #include <mach/i2c.h> |
d0e47fba KH |
35 | #include <mach/serial.h> |
36 | #include <mach/mux.h> | |
d0e47fba | 37 | #include <mach/nand.h> |
2dbf56ae | 38 | #include <mach/mmc.h> |
355fb4e3 | 39 | #include <mach/usb.h> |
d0e47fba KH |
40 | |
41 | #define DM644X_EVM_PHY_MASK (0x2) | |
42 | #define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */ | |
7c6337e2 | 43 | |
f5c122da | 44 | #define DAVINCI_CFC_ATA_BASE 0x01C66000 |
f5c122da | 45 | |
d0e47fba KH |
46 | #define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000 |
47 | #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 | |
48 | #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 | |
49 | #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000 | |
50 | #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000 | |
7c6337e2 | 51 | |
d0e47fba KH |
52 | #define LXT971_PHY_ID (0x001378e2) |
53 | #define LXT971_PHY_MASK (0xfffffff0) | |
7c6337e2 | 54 | |
7bff3c4c | 55 | static struct mtd_partition davinci_evm_norflash_partitions[] = { |
d0e47fba | 56 | /* bootloader (UBL, U-Boot, etc) in first 5 sectors */ |
7c6337e2 KH |
57 | { |
58 | .name = "bootloader", | |
59 | .offset = 0, | |
d0e47fba | 60 | .size = 5 * SZ_64K, |
7c6337e2 KH |
61 | .mask_flags = MTD_WRITEABLE, /* force read-only */ |
62 | }, | |
63 | /* bootloader params in the next 1 sectors */ | |
64 | { | |
65 | .name = "params", | |
66 | .offset = MTDPART_OFS_APPEND, | |
67 | .size = SZ_64K, | |
68 | .mask_flags = 0, | |
69 | }, | |
70 | /* kernel */ | |
71 | { | |
72 | .name = "kernel", | |
73 | .offset = MTDPART_OFS_APPEND, | |
74 | .size = SZ_2M, | |
75 | .mask_flags = 0 | |
76 | }, | |
77 | /* file system */ | |
78 | { | |
79 | .name = "filesystem", | |
80 | .offset = MTDPART_OFS_APPEND, | |
81 | .size = MTDPART_SIZ_FULL, | |
82 | .mask_flags = 0 | |
83 | } | |
84 | }; | |
85 | ||
7bff3c4c | 86 | static struct physmap_flash_data davinci_evm_norflash_data = { |
7c6337e2 | 87 | .width = 2, |
7bff3c4c DB |
88 | .parts = davinci_evm_norflash_partitions, |
89 | .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions), | |
7c6337e2 KH |
90 | }; |
91 | ||
92 | /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF | |
93 | * limits addresses to 16M, so using addresses past 16M will wrap */ | |
7bff3c4c DB |
94 | static struct resource davinci_evm_norflash_resource = { |
95 | .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, | |
96 | .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, | |
7c6337e2 KH |
97 | .flags = IORESOURCE_MEM, |
98 | }; | |
99 | ||
7bff3c4c | 100 | static struct platform_device davinci_evm_norflash_device = { |
7c6337e2 KH |
101 | .name = "physmap-flash", |
102 | .id = 0, | |
103 | .dev = { | |
7bff3c4c | 104 | .platform_data = &davinci_evm_norflash_data, |
7c6337e2 KH |
105 | }, |
106 | .num_resources = 1, | |
7bff3c4c DB |
107 | .resource = &davinci_evm_norflash_resource, |
108 | }; | |
109 | ||
3e9c18e1 DB |
110 | /* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks). |
111 | * It may used instead of the (default) NOR chip to boot, using TI's | |
112 | * tools to install the secondary boot loader (UBL) and U-Boot. | |
113 | */ | |
d0e47fba | 114 | struct mtd_partition davinci_evm_nandflash_partition[] = { |
3e9c18e1 DB |
115 | /* Bootloader layout depends on whose u-boot is installed, but we |
116 | * can hide all the details. | |
117 | * - block 0 for u-boot environment ... in mainline u-boot | |
118 | * - block 1 for UBL (plus up to four backup copies in blocks 2..5) | |
119 | * - blocks 6...? for u-boot | |
120 | * - blocks 16..23 for u-boot environment ... in TI's u-boot | |
121 | */ | |
122 | { | |
123 | .name = "bootloader", | |
124 | .offset = 0, | |
125 | .size = SZ_256K + SZ_128K, | |
126 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | |
127 | }, | |
128 | /* Kernel */ | |
d0e47fba | 129 | { |
3e9c18e1 DB |
130 | .name = "kernel", |
131 | .offset = MTDPART_OFS_APPEND, | |
132 | .size = SZ_4M, | |
133 | .mask_flags = 0, | |
134 | }, | |
135 | /* File system (older GIT kernels started this on the 5MB mark) */ | |
136 | { | |
137 | .name = "filesystem", | |
138 | .offset = MTDPART_OFS_APPEND, | |
d0e47fba KH |
139 | .size = MTDPART_SIZ_FULL, |
140 | .mask_flags = 0, | |
141 | } | |
3e9c18e1 DB |
142 | /* A few blocks at end hold a flash BBT ... created by TI's CCS |
143 | * using flashwriter_nand.out, but ignored by TI's versions of | |
144 | * Linux and u-boot. We boot faster by using them. | |
145 | */ | |
d0e47fba | 146 | }; |
7bff3c4c | 147 | |
d0e47fba KH |
148 | static struct davinci_nand_pdata davinci_evm_nandflash_data = { |
149 | .parts = davinci_evm_nandflash_partition, | |
150 | .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition), | |
151 | .ecc_mode = NAND_ECC_HW, | |
3e9c18e1 | 152 | .options = NAND_USE_FLASH_BBT, |
d0e47fba KH |
153 | }; |
154 | ||
155 | static struct resource davinci_evm_nandflash_resource[] = { | |
156 | { | |
157 | .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, | |
158 | .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1, | |
159 | .flags = IORESOURCE_MEM, | |
160 | }, { | |
161 | .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE, | |
162 | .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, | |
163 | .flags = IORESOURCE_MEM, | |
164 | }, | |
165 | }; | |
166 | ||
167 | static struct platform_device davinci_evm_nandflash_device = { | |
168 | .name = "davinci_nand", | |
169 | .id = 0, | |
170 | .dev = { | |
171 | .platform_data = &davinci_evm_nandflash_data, | |
172 | }, | |
173 | .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource), | |
174 | .resource = davinci_evm_nandflash_resource, | |
175 | }; | |
176 | ||
3e9c18e1 | 177 | static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32); |
d0e47fba KH |
178 | |
179 | static struct platform_device davinci_fb_device = { | |
180 | .name = "davincifb", | |
181 | .id = -1, | |
182 | .dev = { | |
183 | .dma_mask = &davinci_fb_dma_mask, | |
3e9c18e1 | 184 | .coherent_dma_mask = DMA_BIT_MASK(32), |
d0e47fba KH |
185 | }, |
186 | .num_resources = 0, | |
187 | }; | |
188 | ||
ab8e8df8 MK |
189 | static struct tvp514x_platform_data tvp5146_pdata = { |
190 | .clk_polarity = 0, | |
191 | .hs_polarity = 1, | |
192 | .vs_polarity = 1 | |
193 | }; | |
194 | ||
195 | #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) | |
196 | /* Inputs available at the TVP5146 */ | |
197 | static struct v4l2_input tvp5146_inputs[] = { | |
198 | { | |
199 | .index = 0, | |
200 | .name = "Composite", | |
201 | .type = V4L2_INPUT_TYPE_CAMERA, | |
202 | .std = TVP514X_STD_ALL, | |
203 | }, | |
204 | { | |
205 | .index = 1, | |
206 | .name = "S-Video", | |
207 | .type = V4L2_INPUT_TYPE_CAMERA, | |
208 | .std = TVP514X_STD_ALL, | |
209 | }, | |
210 | }; | |
211 | ||
212 | /* | |
213 | * this is the route info for connecting each input to decoder | |
214 | * ouput that goes to vpfe. There is a one to one correspondence | |
215 | * with tvp5146_inputs | |
216 | */ | |
217 | static struct vpfe_route tvp5146_routes[] = { | |
218 | { | |
219 | .input = INPUT_CVBS_VI2B, | |
220 | .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, | |
221 | }, | |
222 | { | |
223 | .input = INPUT_SVIDEO_VI2C_VI1C, | |
224 | .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, | |
225 | }, | |
226 | }; | |
227 | ||
228 | static struct vpfe_subdev_info vpfe_sub_devs[] = { | |
229 | { | |
230 | .name = "tvp5146", | |
231 | .grp_id = 0, | |
232 | .num_inputs = ARRAY_SIZE(tvp5146_inputs), | |
233 | .inputs = tvp5146_inputs, | |
234 | .routes = tvp5146_routes, | |
235 | .can_route = 1, | |
236 | .ccdc_if_params = { | |
237 | .if_type = VPFE_BT656, | |
238 | .hdpol = VPFE_PINPOL_POSITIVE, | |
239 | .vdpol = VPFE_PINPOL_POSITIVE, | |
240 | }, | |
241 | .board_info = { | |
242 | I2C_BOARD_INFO("tvp5146", 0x5d), | |
243 | .platform_data = &tvp5146_pdata, | |
244 | }, | |
245 | }, | |
246 | }; | |
247 | ||
248 | static struct vpfe_config vpfe_cfg = { | |
249 | .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), | |
250 | .sub_devs = vpfe_sub_devs, | |
251 | .card_name = "DM6446 EVM", | |
252 | .ccdc = "DM6446 CCDC", | |
253 | }; | |
254 | ||
d0e47fba KH |
255 | static struct platform_device rtc_dev = { |
256 | .name = "rtc_davinci_evm", | |
257 | .id = -1, | |
258 | }; | |
7bff3c4c DB |
259 | |
260 | static struct resource ide_resources[] = { | |
261 | { | |
262 | .start = DAVINCI_CFC_ATA_BASE, | |
263 | .end = DAVINCI_CFC_ATA_BASE + 0x7ff, | |
264 | .flags = IORESOURCE_MEM, | |
265 | }, | |
266 | { | |
267 | .start = IRQ_IDE, | |
268 | .end = IRQ_IDE, | |
269 | .flags = IORESOURCE_IRQ, | |
270 | }, | |
271 | }; | |
272 | ||
a029b706 | 273 | static u64 ide_dma_mask = DMA_BIT_MASK(32); |
7bff3c4c DB |
274 | |
275 | static struct platform_device ide_dev = { | |
276 | .name = "palm_bk3710", | |
277 | .id = -1, | |
278 | .resource = ide_resources, | |
279 | .num_resources = ARRAY_SIZE(ide_resources), | |
280 | .dev = { | |
281 | .dma_mask = &ide_dma_mask, | |
a029b706 | 282 | .coherent_dma_mask = DMA_BIT_MASK(32), |
7bff3c4c DB |
283 | }, |
284 | }; | |
285 | ||
61aa0732 | 286 | static struct snd_platform_data dm644x_evm_snd_data; |
25acf553 | 287 | |
7bff3c4c DB |
288 | /*----------------------------------------------------------------------*/ |
289 | ||
290 | /* | |
291 | * I2C GPIO expanders | |
292 | */ | |
293 | ||
294 | #define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8)) | |
295 | ||
296 | ||
297 | /* U2 -- LEDs */ | |
298 | ||
299 | static struct gpio_led evm_leds[] = { | |
300 | { .name = "DS8", .active_low = 1, | |
301 | .default_trigger = "heartbeat", }, | |
302 | { .name = "DS7", .active_low = 1, }, | |
303 | { .name = "DS6", .active_low = 1, }, | |
304 | { .name = "DS5", .active_low = 1, }, | |
305 | { .name = "DS4", .active_low = 1, }, | |
306 | { .name = "DS3", .active_low = 1, }, | |
307 | { .name = "DS2", .active_low = 1, | |
308 | .default_trigger = "mmc0", }, | |
309 | { .name = "DS1", .active_low = 1, | |
310 | .default_trigger = "ide-disk", }, | |
311 | }; | |
312 | ||
313 | static const struct gpio_led_platform_data evm_led_data = { | |
314 | .num_leds = ARRAY_SIZE(evm_leds), | |
315 | .leds = evm_leds, | |
316 | }; | |
317 | ||
318 | static struct platform_device *evm_led_dev; | |
319 | ||
320 | static int | |
321 | evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c) | |
322 | { | |
323 | struct gpio_led *leds = evm_leds; | |
324 | int status; | |
325 | ||
326 | while (ngpio--) { | |
327 | leds->gpio = gpio++; | |
328 | leds++; | |
329 | } | |
330 | ||
331 | /* what an extremely annoying way to be forced to handle | |
332 | * device unregistration ... | |
333 | */ | |
334 | evm_led_dev = platform_device_alloc("leds-gpio", 0); | |
335 | platform_device_add_data(evm_led_dev, | |
336 | &evm_led_data, sizeof evm_led_data); | |
337 | ||
338 | evm_led_dev->dev.parent = &client->dev; | |
339 | status = platform_device_add(evm_led_dev); | |
340 | if (status < 0) { | |
341 | platform_device_put(evm_led_dev); | |
342 | evm_led_dev = NULL; | |
343 | } | |
344 | return status; | |
345 | } | |
346 | ||
347 | static int | |
348 | evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c) | |
349 | { | |
350 | if (evm_led_dev) { | |
351 | platform_device_unregister(evm_led_dev); | |
352 | evm_led_dev = NULL; | |
353 | } | |
354 | return 0; | |
355 | } | |
356 | ||
357 | static struct pcf857x_platform_data pcf_data_u2 = { | |
358 | .gpio_base = PCF_Uxx_BASE(0), | |
359 | .setup = evm_led_setup, | |
360 | .teardown = evm_led_teardown, | |
361 | }; | |
362 | ||
363 | ||
364 | /* U18 - A/V clock generator and user switch */ | |
365 | ||
366 | static int sw_gpio; | |
367 | ||
368 | static ssize_t | |
369 | sw_show(struct device *d, struct device_attribute *a, char *buf) | |
370 | { | |
371 | char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n"; | |
372 | ||
373 | strcpy(buf, s); | |
374 | return strlen(s); | |
375 | } | |
376 | ||
377 | static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL); | |
378 | ||
379 | static int | |
380 | evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c) | |
381 | { | |
382 | int status; | |
383 | ||
384 | /* export dip switch option */ | |
385 | sw_gpio = gpio + 7; | |
386 | status = gpio_request(sw_gpio, "user_sw"); | |
387 | if (status == 0) | |
388 | status = gpio_direction_input(sw_gpio); | |
389 | if (status == 0) | |
390 | status = device_create_file(&client->dev, &dev_attr_user_sw); | |
391 | else | |
392 | gpio_free(sw_gpio); | |
393 | if (status != 0) | |
394 | sw_gpio = -EINVAL; | |
395 | ||
396 | /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */ | |
397 | gpio_request(gpio + 3, "pll_fs2"); | |
398 | gpio_direction_output(gpio + 3, 0); | |
399 | ||
400 | gpio_request(gpio + 2, "pll_fs1"); | |
401 | gpio_direction_output(gpio + 2, 0); | |
402 | ||
403 | gpio_request(gpio + 1, "pll_sr"); | |
404 | gpio_direction_output(gpio + 1, 0); | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
409 | static int | |
410 | evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c) | |
411 | { | |
412 | gpio_free(gpio + 1); | |
413 | gpio_free(gpio + 2); | |
414 | gpio_free(gpio + 3); | |
415 | ||
416 | if (sw_gpio > 0) { | |
417 | device_remove_file(&client->dev, &dev_attr_user_sw); | |
418 | gpio_free(sw_gpio); | |
419 | } | |
420 | return 0; | |
421 | } | |
422 | ||
423 | static struct pcf857x_platform_data pcf_data_u18 = { | |
424 | .gpio_base = PCF_Uxx_BASE(1), | |
425 | .n_latch = (1 << 3) | (1 << 2) | (1 << 1), | |
426 | .setup = evm_u18_setup, | |
427 | .teardown = evm_u18_teardown, | |
7c6337e2 KH |
428 | }; |
429 | ||
7bff3c4c DB |
430 | |
431 | /* U35 - various I/O signals used to manage USB, CF, ATA, etc */ | |
432 | ||
433 | static int | |
434 | evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c) | |
435 | { | |
436 | /* p0 = nDRV_VBUS (initial: don't supply it) */ | |
437 | gpio_request(gpio + 0, "nDRV_VBUS"); | |
438 | gpio_direction_output(gpio + 0, 1); | |
439 | ||
440 | /* p1 = VDDIMX_EN */ | |
441 | gpio_request(gpio + 1, "VDDIMX_EN"); | |
442 | gpio_direction_output(gpio + 1, 1); | |
443 | ||
444 | /* p2 = VLYNQ_EN */ | |
445 | gpio_request(gpio + 2, "VLYNQ_EN"); | |
446 | gpio_direction_output(gpio + 2, 1); | |
447 | ||
448 | /* p3 = n3V3_CF_RESET (initial: stay in reset) */ | |
449 | gpio_request(gpio + 3, "nCF_RESET"); | |
450 | gpio_direction_output(gpio + 3, 0); | |
451 | ||
452 | /* (p4 unused) */ | |
453 | ||
454 | /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */ | |
455 | gpio_request(gpio + 5, "WLAN_RESET"); | |
456 | gpio_direction_output(gpio + 5, 1); | |
457 | ||
458 | /* p6 = nATA_SEL (initial: select) */ | |
459 | gpio_request(gpio + 6, "nATA_SEL"); | |
460 | gpio_direction_output(gpio + 6, 0); | |
461 | ||
462 | /* p7 = nCF_SEL (initial: deselect) */ | |
463 | gpio_request(gpio + 7, "nCF_SEL"); | |
464 | gpio_direction_output(gpio + 7, 1); | |
465 | ||
d0e47fba KH |
466 | /* irlml6401 switches over 1A, in under 8 msec; |
467 | * now it can be managed by nDRV_VBUS ... | |
468 | */ | |
355fb4e3 | 469 | davinci_setup_usb(1000, 8); |
34f32c97 | 470 | |
7bff3c4c DB |
471 | return 0; |
472 | } | |
473 | ||
474 | static int | |
475 | evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c) | |
476 | { | |
477 | gpio_free(gpio + 7); | |
478 | gpio_free(gpio + 6); | |
479 | gpio_free(gpio + 5); | |
480 | gpio_free(gpio + 3); | |
481 | gpio_free(gpio + 2); | |
482 | gpio_free(gpio + 1); | |
483 | gpio_free(gpio + 0); | |
484 | return 0; | |
485 | } | |
486 | ||
487 | static struct pcf857x_platform_data pcf_data_u35 = { | |
488 | .gpio_base = PCF_Uxx_BASE(2), | |
489 | .setup = evm_u35_setup, | |
490 | .teardown = evm_u35_teardown, | |
491 | }; | |
492 | ||
493 | /*----------------------------------------------------------------------*/ | |
494 | ||
495 | /* Most of this EEPROM is unused, but U-Boot uses some data: | |
496 | * - 0x7f00, 6 bytes Ethernet Address | |
497 | * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL) | |
498 | * - ... newer boards may have more | |
499 | */ | |
d0e47fba | 500 | |
7bff3c4c DB |
501 | static struct at24_platform_data eeprom_info = { |
502 | .byte_len = (256*1024) / 8, | |
503 | .page_size = 64, | |
504 | .flags = AT24_FLAG_ADDR16, | |
b14dc0f9 MG |
505 | .setup = davinci_get_mac_addr, |
506 | .context = (void *)0x7f00, | |
d0e47fba KH |
507 | }; |
508 | ||
d0e47fba KH |
509 | /* |
510 | * MSP430 supports RTC, card detection, input from IR remote, and | |
511 | * a bit more. It triggers interrupts on GPIO(7) from pressing | |
512 | * buttons on the IR remote, and for card detect switches. | |
513 | */ | |
514 | static struct i2c_client *dm6446evm_msp; | |
515 | ||
516 | static int dm6446evm_msp_probe(struct i2c_client *client, | |
517 | const struct i2c_device_id *id) | |
518 | { | |
519 | dm6446evm_msp = client; | |
520 | return 0; | |
521 | } | |
522 | ||
523 | static int dm6446evm_msp_remove(struct i2c_client *client) | |
524 | { | |
525 | dm6446evm_msp = NULL; | |
526 | return 0; | |
527 | } | |
528 | ||
529 | static const struct i2c_device_id dm6446evm_msp_ids[] = { | |
530 | { "dm6446evm_msp", 0, }, | |
531 | { /* end of list */ }, | |
532 | }; | |
533 | ||
534 | static struct i2c_driver dm6446evm_msp_driver = { | |
535 | .driver.name = "dm6446evm_msp", | |
536 | .id_table = dm6446evm_msp_ids, | |
537 | .probe = dm6446evm_msp_probe, | |
538 | .remove = dm6446evm_msp_remove, | |
7bff3c4c DB |
539 | }; |
540 | ||
d0e47fba KH |
541 | static int dm6444evm_msp430_get_pins(void) |
542 | { | |
543 | static const char txbuf[2] = { 2, 4, }; | |
544 | char buf[4]; | |
545 | struct i2c_msg msg[2] = { | |
546 | { | |
547 | .addr = dm6446evm_msp->addr, | |
548 | .flags = 0, | |
549 | .len = 2, | |
550 | .buf = (void __force *)txbuf, | |
551 | }, | |
552 | { | |
553 | .addr = dm6446evm_msp->addr, | |
554 | .flags = I2C_M_RD, | |
555 | .len = 4, | |
556 | .buf = buf, | |
557 | }, | |
558 | }; | |
559 | int status; | |
560 | ||
561 | if (!dm6446evm_msp) | |
562 | return -ENXIO; | |
563 | ||
564 | /* Command 4 == get input state, returns port 2 and port3 data | |
565 | * S Addr W [A] len=2 [A] cmd=4 [A] | |
566 | * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P | |
567 | */ | |
568 | status = i2c_transfer(dm6446evm_msp->adapter, msg, 2); | |
569 | if (status < 0) | |
570 | return status; | |
571 | ||
572 | dev_dbg(&dm6446evm_msp->dev, | |
573 | "PINS: %02x %02x %02x %02x\n", | |
574 | buf[0], buf[1], buf[2], buf[3]); | |
575 | ||
576 | return (buf[3] << 8) | buf[2]; | |
577 | } | |
578 | ||
2dbf56ae KH |
579 | static int dm6444evm_mmc_get_cd(int module) |
580 | { | |
581 | int status = dm6444evm_msp430_get_pins(); | |
582 | ||
583 | return (status < 0) ? status : !(status & BIT(1)); | |
584 | } | |
585 | ||
586 | static int dm6444evm_mmc_get_ro(int module) | |
587 | { | |
588 | int status = dm6444evm_msp430_get_pins(); | |
589 | ||
590 | return (status < 0) ? status : status & BIT(6 + 8); | |
591 | } | |
592 | ||
593 | static struct davinci_mmc_config dm6446evm_mmc_config = { | |
594 | .get_cd = dm6444evm_mmc_get_cd, | |
595 | .get_ro = dm6444evm_mmc_get_ro, | |
596 | .wires = 4, | |
597 | .version = MMC_CTLR_VERSION_1 | |
598 | }; | |
599 | ||
7bff3c4c | 600 | static struct i2c_board_info __initdata i2c_info[] = { |
d0e47fba KH |
601 | { |
602 | I2C_BOARD_INFO("dm6446evm_msp", 0x23), | |
603 | }, | |
7bff3c4c DB |
604 | { |
605 | I2C_BOARD_INFO("pcf8574", 0x38), | |
606 | .platform_data = &pcf_data_u2, | |
607 | }, | |
608 | { | |
609 | I2C_BOARD_INFO("pcf8574", 0x39), | |
610 | .platform_data = &pcf_data_u18, | |
611 | }, | |
612 | { | |
613 | I2C_BOARD_INFO("pcf8574", 0x3a), | |
614 | .platform_data = &pcf_data_u35, | |
615 | }, | |
616 | { | |
617 | I2C_BOARD_INFO("24c256", 0x50), | |
618 | .platform_data = &eeprom_info, | |
619 | }, | |
1a7ff8ff C |
620 | { |
621 | I2C_BOARD_INFO("tlv320aic33", 0x1b), | |
622 | }, | |
7bff3c4c DB |
623 | }; |
624 | ||
625 | /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz), | |
626 | * which requires 100 usec of idle bus after i2c writes sent to it. | |
627 | */ | |
628 | static struct davinci_i2c_platform_data i2c_pdata = { | |
629 | .bus_freq = 20 /* kHz */, | |
630 | .bus_delay = 100 /* usec */, | |
631 | }; | |
632 | ||
633 | static void __init evm_init_i2c(void) | |
634 | { | |
635 | davinci_init_i2c(&i2c_pdata); | |
d0e47fba | 636 | i2c_add_driver(&dm6446evm_msp_driver); |
7bff3c4c DB |
637 | i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); |
638 | } | |
639 | ||
7c6337e2 | 640 | static struct platform_device *davinci_evm_devices[] __initdata = { |
d0e47fba KH |
641 | &davinci_fb_device, |
642 | &rtc_dev, | |
643 | }; | |
644 | ||
645 | static struct davinci_uart_config uart_config __initdata = { | |
646 | .enabled_uarts = (1 << 0), | |
7c6337e2 KH |
647 | }; |
648 | ||
649 | static void __init | |
650 | davinci_evm_map_io(void) | |
651 | { | |
ab8e8df8 MK |
652 | /* setup input configuration for VPFE input devices */ |
653 | dm644x_set_vpfe_config(&vpfe_cfg); | |
d0e47fba | 654 | dm644x_init(); |
7c6337e2 KH |
655 | } |
656 | ||
d0e47fba | 657 | static int davinci_phy_fixup(struct phy_device *phydev) |
7c6337e2 | 658 | { |
d0e47fba KH |
659 | unsigned int control; |
660 | /* CRITICAL: Fix for increasing PHY signal drive strength for | |
661 | * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY | |
662 | * signal strength was low causing TX to fail randomly. The | |
663 | * fix is to Set bit 11 (Increased MII drive strength) of PHY | |
664 | * register 26 (Digital Config register) on this phy. */ | |
665 | control = phy_read(phydev, 26); | |
666 | phy_write(phydev, 26, (control | 0x800)); | |
667 | return 0; | |
668 | } | |
669 | ||
7bff3c4c DB |
670 | #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ |
671 | defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE) | |
d0e47fba KH |
672 | #define HAS_ATA 1 |
673 | #else | |
674 | #define HAS_ATA 0 | |
675 | #endif | |
676 | ||
7bff3c4c DB |
677 | #if defined(CONFIG_MTD_PHYSMAP) || \ |
678 | defined(CONFIG_MTD_PHYSMAP_MODULE) | |
d0e47fba KH |
679 | #define HAS_NOR 1 |
680 | #else | |
681 | #define HAS_NOR 0 | |
7bff3c4c | 682 | #endif |
d0e47fba KH |
683 | |
684 | #if defined(CONFIG_MTD_NAND_DAVINCI) || \ | |
685 | defined(CONFIG_MTD_NAND_DAVINCI_MODULE) | |
686 | #define HAS_NAND 1 | |
687 | #else | |
688 | #define HAS_NAND 0 | |
7c6337e2 KH |
689 | #endif |
690 | ||
d0e47fba KH |
691 | static __init void davinci_evm_init(void) |
692 | { | |
693 | struct clk *aemif_clk; | |
972412b6 | 694 | struct davinci_soc_info *soc_info = &davinci_soc_info; |
d0e47fba KH |
695 | |
696 | aemif_clk = clk_get(NULL, "aemif"); | |
697 | clk_enable(aemif_clk); | |
698 | ||
699 | if (HAS_ATA) { | |
700 | if (HAS_NAND || HAS_NOR) | |
701 | pr_warning("WARNING: both IDE and Flash are " | |
702 | "enabled, but they share AEMIF pins.\n" | |
703 | "\tDisable IDE for NAND/NOR support.\n"); | |
704 | davinci_cfg_reg(DM644X_HPIEN_DISABLE); | |
705 | davinci_cfg_reg(DM644X_ATAEN); | |
706 | davinci_cfg_reg(DM644X_HDIREN); | |
707 | platform_device_register(&ide_dev); | |
708 | } else if (HAS_NAND || HAS_NOR) { | |
709 | davinci_cfg_reg(DM644X_HPIEN_DISABLE); | |
710 | davinci_cfg_reg(DM644X_ATAEN_DISABLE); | |
711 | ||
712 | /* only one device will be jumpered and detected */ | |
713 | if (HAS_NAND) { | |
714 | platform_device_register(&davinci_evm_nandflash_device); | |
715 | evm_leds[7].default_trigger = "nand-disk"; | |
716 | if (HAS_NOR) | |
717 | pr_warning("WARNING: both NAND and NOR flash " | |
718 | "are enabled; disable one of them.\n"); | |
719 | } else if (HAS_NOR) | |
720 | platform_device_register(&davinci_evm_norflash_device); | |
721 | } | |
722 | ||
7c6337e2 KH |
723 | platform_add_devices(davinci_evm_devices, |
724 | ARRAY_SIZE(davinci_evm_devices)); | |
7bff3c4c | 725 | evm_init_i2c(); |
d0e47fba | 726 | |
2dbf56ae KH |
727 | davinci_setup_mmc(0, &dm6446evm_mmc_config); |
728 | ||
d0e47fba | 729 | davinci_serial_init(&uart_config); |
25acf553 | 730 | dm644x_init_asp(&dm644x_evm_snd_data); |
d0e47fba | 731 | |
972412b6 MG |
732 | soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK; |
733 | soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY; | |
ac7b75b5 | 734 | |
d0e47fba KH |
735 | /* Register the fixup for PHY on DaVinci */ |
736 | phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK, | |
737 | davinci_phy_fixup); | |
738 | ||
7c6337e2 KH |
739 | } |
740 | ||
741 | static __init void davinci_evm_irq_init(void) | |
742 | { | |
743 | davinci_irq_init(); | |
744 | } | |
745 | ||
d0e47fba | 746 | MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") |
7c6337e2 KH |
747 | /* Maintainer: MontaVista Software <source@mvista.com> */ |
748 | .phys_io = IO_PHYS, | |
ac7643e4 | 749 | .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, |
7c6337e2 KH |
750 | .boot_params = (DAVINCI_DDR_BASE + 0x100), |
751 | .map_io = davinci_evm_map_io, | |
752 | .init_irq = davinci_evm_irq_init, | |
753 | .timer = &davinci_timer, | |
754 | .init_machine = davinci_evm_init, | |
755 | MACHINE_END |