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[linux-block.git] / arch / arm / mach-at91 / at91sam9rl_devices.c
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877d7720
AV		 1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9#include <asm/mach/arch.h>
10#include <asm/mach/map.h>
11
c6686ff9 12#include <linux/dma-mapping.h>
877d7720 13#include <linux/platform_device.h>
f230d3f5 14#include <linux/i2c-gpio.h>
877d7720 15
f230d3f5 16#include <linux/fb.h>
877d7720
AV		 17#include <video/atmel_lcdc.h>
18
a09e64fb
RK		 19#include <mach/board.h>
20#include <mach/gpio.h>
21#include <mach/at91sam9rl.h>
22#include <mach/at91sam9rl_matrix.h>
23#include <mach/at91sam9_smc.h>
877d7720
AV		 24
25#include "generic.h"
26
877d7720 27
ba45ca43
NF		 28/* --------------------------------------------------------------------
29 * USB HS Device (Gadget)
30 * -------------------------------------------------------------------- */
31
32#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
33
34static struct resource usba_udc_resources[] = {
35 [0] = {
36 .start = AT91SAM9RL_UDPHS_FIFO,
37 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
38 .flags = IORESOURCE_MEM,
39 },
40 [1] = {
41 .start = AT91SAM9RL_BASE_UDPHS,
42 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [2] = {
46 .start = AT91SAM9RL_ID_UDPHS,
47 .end = AT91SAM9RL_ID_UDPHS,
48 .flags = IORESOURCE_IRQ,
49 },
50};
51
52#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
53 [idx] = { \
54 .name = nam, \
55 .index = idx, \
56 .fifo_size = maxpkt, \
57 .nr_banks = maxbk, \
58 .can_dma = dma, \
59 .can_isoc = isoc, \
60 }
61
62static struct usba_ep_data usba_udc_ep[] __initdata = {
63 EP("ep0", 0, 64, 1, 0, 0),
64 EP("ep1", 1, 1024, 2, 1, 1),
65 EP("ep2", 2, 1024, 2, 1, 1),
66 EP("ep3", 3, 1024, 3, 1, 0),
67 EP("ep4", 4, 1024, 3, 1, 0),
68 EP("ep5", 5, 1024, 3, 1, 1),
69 EP("ep6", 6, 1024, 3, 1, 1),
70};
71
72#undef EP
73
74/*
75 * pdata doesn't have room for any endpoints, so we need to
76 * append room for the ones we need right after it.
77 */
78static struct {
79 struct usba_platform_data pdata;
80 struct usba_ep_data ep[7];
81} usba_udc_data;
82
83static struct platform_device at91_usba_udc_device = {
84 .name = "atmel_usba_udc",
85 .id = -1,
86 .dev = {
87 .platform_data = &usba_udc_data.pdata,
88 },
89 .resource = usba_udc_resources,
90 .num_resources = ARRAY_SIZE(usba_udc_resources),
91};
92
93void __init at91_add_device_usba(struct usba_platform_data *data)
94{
95 /*
96 * Invalid pins are 0 on AT91, but the usba driver is shared
97 * with AVR32, which use negative values instead. Once/if
98 * gpio_is_valid() is ported to AT91, revisit this code.
99 */
100 usba_udc_data.pdata.vbus_pin = -EINVAL;
101 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
102 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
103
104 if (data && data->vbus_pin > 0) {
105 at91_set_gpio_input(data->vbus_pin, 0);
106 at91_set_deglitch(data->vbus_pin, 1);
107 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
108 }
109
110 /* Pullup pin is handled internally by USB device peripheral */
111
112 /* Clocks */
113 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
114 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
115
116 platform_device_register(&at91_usba_udc_device);
117}
118#else
119void __init at91_add_device_usba(struct usba_platform_data *data) {}
120#endif
121
122
877d7720
AV		 123/* --------------------------------------------------------------------
124 * MMC / SD
125 * -------------------------------------------------------------------- */
126
127#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
c6686ff9 128static u64 mmc_dmamask = DMA_BIT_MASK(32);
877d7720
AV		 129static struct at91_mmc_data mmc_data;
130
131static struct resource mmc_resources[] = {
132 [0] = {
133 .start = AT91SAM9RL_BASE_MCI,
134 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
135 .flags = IORESOURCE_MEM,
136 },
137 [1] = {
138 .start = AT91SAM9RL_ID_MCI,
139 .end = AT91SAM9RL_ID_MCI,
140 .flags = IORESOURCE_IRQ,
141 },
142};
143
144static struct platform_device at91sam9rl_mmc_device = {
145 .name = "at91_mci",
146 .id = -1,
147 .dev = {
148 .dma_mask = &mmc_dmamask,
c6686ff9 149 .coherent_dma_mask = DMA_BIT_MASK(32),
877d7720
AV		 150 .platform_data = &mmc_data,
151 },
152 .resource = mmc_resources,
153 .num_resources = ARRAY_SIZE(mmc_resources),
154};
155
156void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
157{
158 if (!data)
159 return;
160
161 /* input/irq */
162 if (data->det_pin) {
163 at91_set_gpio_input(data->det_pin, 1);
164 at91_set_deglitch(data->det_pin, 1);
165 }
166 if (data->wp_pin)
167 at91_set_gpio_input(data->wp_pin, 1);
168 if (data->vcc_pin)
169 at91_set_gpio_output(data->vcc_pin, 0);
170
171 /* CLK */
172 at91_set_A_periph(AT91_PIN_PA2, 0);
173
174 /* CMD */
175 at91_set_A_periph(AT91_PIN_PA1, 1);
176
177 /* DAT0, maybe DAT1..DAT3 */
178 at91_set_A_periph(AT91_PIN_PA0, 1);
179 if (data->wire4) {
180 at91_set_A_periph(AT91_PIN_PA3, 1);
181 at91_set_A_periph(AT91_PIN_PA4, 1);
182 at91_set_A_periph(AT91_PIN_PA5, 1);
183 }
184
185 mmc_data = *data;
186 platform_device_register(&at91sam9rl_mmc_device);
187}
188#else
189void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
190#endif
191
192
193/* --------------------------------------------------------------------
194 * NAND / SmartMedia
195 * -------------------------------------------------------------------- */
196
f6ed6f78 197#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 198static struct atmel_nand_data nand_data;
877d7720
AV		 199
200#define NAND_BASE AT91_CHIPSELECT_3
201
202static struct resource nand_resources[] = {
d7a2415f 203 [0] = {
877d7720
AV		 204 .start = NAND_BASE,
205 .end = NAND_BASE + SZ_256M - 1,
206 .flags = IORESOURCE_MEM,
d7a2415f
AV		 207 },
208 [1] = {
209 .start = AT91_BASE_SYS + AT91_ECC,
210 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
211 .flags = IORESOURCE_MEM,
877d7720
AV		 212 }
213};
214
3c3796cc
HS		 215static struct platform_device atmel_nand_device = {
216 .name = "atmel_nand",
877d7720
AV		 217 .id = -1,
218 .dev = {
219 .platform_data = &nand_data,
220 },
221 .resource = nand_resources,
222 .num_resources = ARRAY_SIZE(nand_resources),
223};
224
3c3796cc 225void __init at91_add_device_nand(struct atmel_nand_data *data)
877d7720
AV		 226{
227 unsigned long csa;
228
229 if (!data)
230 return;
231
232 csa = at91_sys_read(AT91_MATRIX_EBICSA);
233 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
234
877d7720
AV		 235 /* enable pin */
236 if (data->enable_pin)
237 at91_set_gpio_output(data->enable_pin, 1);
238
239 /* ready/busy pin */
240 if (data->rdy_pin)
241 at91_set_gpio_input(data->rdy_pin, 1);
242
243 /* card detect pin */
244 if (data->det_pin)
245 at91_set_gpio_input(data->det_pin, 1);
246
247 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
248 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
249
250 nand_data = *data;
3c3796cc 251 platform_device_register(&atmel_nand_device);
877d7720
AV		 252}
253
254#else
3c3796cc 255void __init at91_add_device_nand(struct atmel_nand_data *data) {}
877d7720
AV		 256#endif
257
258
259/* --------------------------------------------------------------------
260 * TWI (i2c)
261 * -------------------------------------------------------------------- */
262
f230d3f5
AV		 263/*
264 * Prefer the GPIO code since the TWI controller isn't robust
265 * (gets overruns and underruns under load) and can only issue
266 * repeated STARTs in one scenario (the driver doesn't yet handle them).
267 */
268#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
269
270static struct i2c_gpio_platform_data pdata = {
271 .sda_pin = AT91_PIN_PA23,
272 .sda_is_open_drain = 1,
273 .scl_pin = AT91_PIN_PA24,
274 .scl_is_open_drain = 1,
275 .udelay = 2, /* ~100 kHz */
276};
277
278static struct platform_device at91sam9rl_twi_device = {
279 .name = "i2c-gpio",
280 .id = -1,
281 .dev.platform_data = &pdata,
282};
283
284void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
285{
286 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
287 at91_set_multi_drive(AT91_PIN_PA23, 1);
288
289 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
290 at91_set_multi_drive(AT91_PIN_PA24, 1);
291
292 i2c_register_board_info(0, devices, nr_devices);
293 platform_device_register(&at91sam9rl_twi_device);
294}
295
296#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
877d7720
AV		 297
298static struct resource twi_resources[] = {
299 [0] = {
300 .start = AT91SAM9RL_BASE_TWI0,
301 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
302 .flags = IORESOURCE_MEM,
303 },
304 [1] = {
305 .start = AT91SAM9RL_ID_TWI0,
306 .end = AT91SAM9RL_ID_TWI0,
307 .flags = IORESOURCE_IRQ,
308 },
309};
310
311static struct platform_device at91sam9rl_twi_device = {
312 .name = "at91_i2c",
313 .id = -1,
314 .resource = twi_resources,
315 .num_resources = ARRAY_SIZE(twi_resources),
316};
317
f230d3f5 318void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
877d7720
AV		 319{
320 /* pins used for TWI interface */
321 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
322 at91_set_multi_drive(AT91_PIN_PA23, 1);
323
324 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
325 at91_set_multi_drive(AT91_PIN_PA24, 1);
326
f230d3f5 327 i2c_register_board_info(0, devices, nr_devices);
877d7720
AV		 328 platform_device_register(&at91sam9rl_twi_device);
329}
330#else
f230d3f5 331void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
877d7720
AV		 332#endif
333
334
335/* --------------------------------------------------------------------
336 * SPI
337 * -------------------------------------------------------------------- */
338
339#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 340static u64 spi_dmamask = DMA_BIT_MASK(32);
877d7720
AV		 341
342static struct resource spi_resources[] = {
343 [0] = {
344 .start = AT91SAM9RL_BASE_SPI,
345 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
346 .flags = IORESOURCE_MEM,
347 },
348 [1] = {
349 .start = AT91SAM9RL_ID_SPI,
350 .end = AT91SAM9RL_ID_SPI,
351 .flags = IORESOURCE_IRQ,
352 },
353};
354
355static struct platform_device at91sam9rl_spi_device = {
356 .name = "atmel_spi",
357 .id = 0,
358 .dev = {
359 .dma_mask = &spi_dmamask,
c6686ff9 360 .coherent_dma_mask = DMA_BIT_MASK(32),
877d7720
AV		 361 },
362 .resource = spi_resources,
363 .num_resources = ARRAY_SIZE(spi_resources),
364};
365
366static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
367
368
369void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
370{
371 int i;
372 unsigned long cs_pin;
373
374 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
375 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
376 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
377
378 /* Enable SPI chip-selects */
379 for (i = 0; i < nr_devices; i++) {
380 if (devices[i].controller_data)
381 cs_pin = (unsigned long) devices[i].controller_data;
382 else
383 cs_pin = spi_standard_cs[devices[i].chip_select];
384
385 /* enable chip-select pin */
386 at91_set_gpio_output(cs_pin, 1);
387
388 /* pass chip-select pin to driver */
389 devices[i].controller_data = (void *) cs_pin;
390 }
391
392 spi_register_board_info(devices, nr_devices);
393 platform_device_register(&at91sam9rl_spi_device);
394}
395#else
396void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
397#endif
398
399
400/* --------------------------------------------------------------------
401 * LCD Controller
402 * -------------------------------------------------------------------- */
403
404#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
c6686ff9 405static u64 lcdc_dmamask = DMA_BIT_MASK(32);
877d7720
AV		 406static struct atmel_lcdfb_info lcdc_data;
407
408static struct resource lcdc_resources[] = {
409 [0] = {
410 .start = AT91SAM9RL_LCDC_BASE,
411 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
412 .flags = IORESOURCE_MEM,
413 },
414 [1] = {
415 .start = AT91SAM9RL_ID_LCDC,
416 .end = AT91SAM9RL_ID_LCDC,
417 .flags = IORESOURCE_IRQ,
418 },
877d7720
AV		 419};
420
421static struct platform_device at91_lcdc_device = {
422 .name = "atmel_lcdfb",
423 .id = 0,
424 .dev = {
425 .dma_mask = &lcdc_dmamask,
c6686ff9 426 .coherent_dma_mask = DMA_BIT_MASK(32),
877d7720
AV		 427 .platform_data = &lcdc_data,
428 },
429 .resource = lcdc_resources,
430 .num_resources = ARRAY_SIZE(lcdc_resources),
431};
432
433void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
434{
435 if (!data) {
436 return;
437 }
438
439 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
440 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
441 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
442 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
443 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
444 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
445 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
446 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
447 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
448 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
449 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
450 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
451 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
452 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
453 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
454 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
455 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
456 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
457 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
458 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
459 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
460
461 lcdc_data = *data;
462 platform_device_register(&at91_lcdc_device);
463}
464#else
465void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
466#endif
467
468
e5f40bfa
AV		 469/* --------------------------------------------------------------------
470 * Timer/Counter block
471 * -------------------------------------------------------------------- */
472
473#ifdef CONFIG_ATMEL_TCLIB
474
475static struct resource tcb_resources[] = {
476 [0] = {
477 .start = AT91SAM9RL_BASE_TCB0,
478 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
479 .flags = IORESOURCE_MEM,
480 },
481 [1] = {
482 .start = AT91SAM9RL_ID_TC0,
483 .end = AT91SAM9RL_ID_TC0,
484 .flags = IORESOURCE_IRQ,
485 },
486 [2] = {
487 .start = AT91SAM9RL_ID_TC1,
488 .end = AT91SAM9RL_ID_TC1,
489 .flags = IORESOURCE_IRQ,
490 },
491 [3] = {
492 .start = AT91SAM9RL_ID_TC2,
493 .end = AT91SAM9RL_ID_TC2,
494 .flags = IORESOURCE_IRQ,
495 },
496};
497
498static struct platform_device at91sam9rl_tcb_device = {
499 .name = "atmel_tcb",
500 .id = 0,
501 .resource = tcb_resources,
502 .num_resources = ARRAY_SIZE(tcb_resources),
503};
504
505static void __init at91_add_device_tc(void)
506{
507 /* this chip has a separate clock and irq for each TC channel */
508 at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
509 at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
510 at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
511 platform_device_register(&at91sam9rl_tcb_device);
512}
513#else
514static void __init at91_add_device_tc(void) { }
515#endif
516
517
f7647e63
AV		 518/* --------------------------------------------------------------------
519 * Touchscreen
520 * -------------------------------------------------------------------- */
521
522#if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
523static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
524
525static struct resource tsadcc_resources[] = {
526 [0] = {
527 .start = AT91SAM9RL_BASE_TSC,
528 .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
529 .flags = IORESOURCE_MEM,
530 },
531 [1] = {
532 .start = AT91SAM9RL_ID_TSC,
533 .end = AT91SAM9RL_ID_TSC,
534 .flags = IORESOURCE_IRQ,
535 }
536};
537
538static struct platform_device at91sam9rl_tsadcc_device = {
539 .name = "atmel_tsadcc",
540 .id = -1,
541 .dev = {
542 .dma_mask = &tsadcc_dmamask,
543 .coherent_dma_mask = DMA_BIT_MASK(32),
544 },
545 .resource = tsadcc_resources,
546 .num_resources = ARRAY_SIZE(tsadcc_resources),
547};
548
549void __init at91_add_device_tsadcc(void)
550{
551 at91_set_A_periph(AT91_PIN_PA17, 0); /* AD0_XR */
552 at91_set_A_periph(AT91_PIN_PA18, 0); /* AD1_XL */
553 at91_set_A_periph(AT91_PIN_PA19, 0); /* AD2_YT */
554 at91_set_A_periph(AT91_PIN_PA20, 0); /* AD3_TB */
555
556 platform_device_register(&at91sam9rl_tsadcc_device);
557}
558#else
559void __init at91_add_device_tsadcc(void) {}
560#endif
561
562
884f5a6a
AV		 563/* --------------------------------------------------------------------
564 * RTC
565 * -------------------------------------------------------------------- */
566
567#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
568static struct platform_device at91sam9rl_rtc_device = {
569 .name = "at91_rtc",
570 .id = -1,
571 .num_resources = 0,
572};
573
574static void __init at91_add_device_rtc(void)
575{
576 platform_device_register(&at91sam9rl_rtc_device);
577}
578#else
579static void __init at91_add_device_rtc(void) {}
580#endif
581
582
583/* --------------------------------------------------------------------
584 * RTT
585 * -------------------------------------------------------------------- */
586
587static struct resource rtt_resources[] = {
588 {
589 .start = AT91_BASE_SYS + AT91_RTT,
590 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
591 .flags = IORESOURCE_MEM,
592 }
593};
594
595static struct platform_device at91sam9rl_rtt_device = {
596 .name = "at91_rtt",
4fd9212c 597 .id = 0,
884f5a6a
AV		 598 .resource = rtt_resources,
599 .num_resources = ARRAY_SIZE(rtt_resources),
600};
601
602static void __init at91_add_device_rtt(void)
603{
604 platform_device_register(&at91sam9rl_rtt_device);
605}
606
607
608/* --------------------------------------------------------------------
609 * Watchdog
610 * -------------------------------------------------------------------- */
611
2af29b78 612#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
884f5a6a
AV		 613static struct platform_device at91sam9rl_wdt_device = {
614 .name = "at91_wdt",
615 .id = -1,
616 .num_resources = 0,
617};
618
619static void __init at91_add_device_watchdog(void)
620{
621 platform_device_register(&at91sam9rl_wdt_device);
622}
623#else
624static void __init at91_add_device_watchdog(void) {}
625#endif
626
627
bb1ad68b
AV		 628/* --------------------------------------------------------------------
629 * PWM
630 * --------------------------------------------------------------------*/
631
632#if defined(CONFIG_ATMEL_PWM)
633static u32 pwm_mask;
634
635static struct resource pwm_resources[] = {
636 [0] = {
637 .start = AT91SAM9RL_BASE_PWMC,
638 .end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
639 .flags = IORESOURCE_MEM,
640 },
641 [1] = {
642 .start = AT91SAM9RL_ID_PWMC,
643 .end = AT91SAM9RL_ID_PWMC,
644 .flags = IORESOURCE_IRQ,
645 },
646};
647
648static struct platform_device at91sam9rl_pwm0_device = {
649 .name = "atmel_pwm",
650 .id = -1,
651 .dev = {
652 .platform_data = &pwm_mask,
653 },
654 .resource = pwm_resources,
655 .num_resources = ARRAY_SIZE(pwm_resources),
656};
657
658void __init at91_add_device_pwm(u32 mask)
659{
660 if (mask & (1 << AT91_PWM0))
661 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */
662
663 if (mask & (1 << AT91_PWM1))
664 at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */
665
666 if (mask & (1 << AT91_PWM2))
667 at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */
668
669 if (mask & (1 << AT91_PWM3))
670 at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */
671
672 pwm_mask = mask;
673
674 platform_device_register(&at91sam9rl_pwm0_device);
675}
676#else
677void __init at91_add_device_pwm(u32 mask) {}
678#endif
679
680
bfbc3266
AV		 681/* --------------------------------------------------------------------
682 * SSC -- Synchronous Serial Controller
683 * -------------------------------------------------------------------- */
684
685#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
686static u64 ssc0_dmamask = DMA_BIT_MASK(32);
687
688static struct resource ssc0_resources[] = {
689 [0] = {
690 .start = AT91SAM9RL_BASE_SSC0,
691 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
692 .flags = IORESOURCE_MEM,
693 },
694 [1] = {
695 .start = AT91SAM9RL_ID_SSC0,
696 .end = AT91SAM9RL_ID_SSC0,
697 .flags = IORESOURCE_IRQ,
698 },
699};
700
701static struct platform_device at91sam9rl_ssc0_device = {
702 .name = "ssc",
703 .id = 0,
704 .dev = {
705 .dma_mask = &ssc0_dmamask,
706 .coherent_dma_mask = DMA_BIT_MASK(32),
707 },
708 .resource = ssc0_resources,
709 .num_resources = ARRAY_SIZE(ssc0_resources),
710};
711
712static inline void configure_ssc0_pins(unsigned pins)
713{
714 if (pins & ATMEL_SSC_TF)
715 at91_set_A_periph(AT91_PIN_PC0, 1);
716 if (pins & ATMEL_SSC_TK)
717 at91_set_A_periph(AT91_PIN_PC1, 1);
718 if (pins & ATMEL_SSC_TD)
719 at91_set_A_periph(AT91_PIN_PA15, 1);
720 if (pins & ATMEL_SSC_RD)
721 at91_set_A_periph(AT91_PIN_PA16, 1);
722 if (pins & ATMEL_SSC_RK)
723 at91_set_B_periph(AT91_PIN_PA10, 1);
724 if (pins & ATMEL_SSC_RF)
725 at91_set_B_periph(AT91_PIN_PA22, 1);
726}
727
728static u64 ssc1_dmamask = DMA_BIT_MASK(32);
729
730static struct resource ssc1_resources[] = {
731 [0] = {
732 .start = AT91SAM9RL_BASE_SSC1,
733 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
734 .flags = IORESOURCE_MEM,
735 },
736 [1] = {
737 .start = AT91SAM9RL_ID_SSC1,
738 .end = AT91SAM9RL_ID_SSC1,
739 .flags = IORESOURCE_IRQ,
740 },
741};
742
743static struct platform_device at91sam9rl_ssc1_device = {
744 .name = "ssc",
745 .id = 1,
746 .dev = {
747 .dma_mask = &ssc1_dmamask,
748 .coherent_dma_mask = DMA_BIT_MASK(32),
749 },
750 .resource = ssc1_resources,
751 .num_resources = ARRAY_SIZE(ssc1_resources),
752};
753
754static inline void configure_ssc1_pins(unsigned pins)
755{
756 if (pins & ATMEL_SSC_TF)
757 at91_set_B_periph(AT91_PIN_PA29, 1);
758 if (pins & ATMEL_SSC_TK)
759 at91_set_B_periph(AT91_PIN_PA30, 1);
760 if (pins & ATMEL_SSC_TD)
761 at91_set_B_periph(AT91_PIN_PA13, 1);
762 if (pins & ATMEL_SSC_RD)
763 at91_set_B_periph(AT91_PIN_PA14, 1);
764 if (pins & ATMEL_SSC_RK)
765 at91_set_B_periph(AT91_PIN_PA9, 1);
766 if (pins & ATMEL_SSC_RF)
767 at91_set_B_periph(AT91_PIN_PA8, 1);
768}
769
770/*
bfbc3266
AV		 771 * SSC controllers are accessed through library code, instead of any
772 * kind of all-singing/all-dancing driver. For example one could be
773 * used by a particular I2S audio codec's driver, while another one
774 * on the same system might be used by a custom data capture driver.
775 */
776void __init at91_add_device_ssc(unsigned id, unsigned pins)
777{
778 struct platform_device *pdev;
779
780 /*
781 * NOTE: caller is responsible for passing information matching
782 * "pins" to whatever will be using each particular controller.
783 */
784 switch (id) {
785 case AT91SAM9RL_ID_SSC0:
786 pdev = &at91sam9rl_ssc0_device;
787 configure_ssc0_pins(pins);
788 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
789 break;
790 case AT91SAM9RL_ID_SSC1:
791 pdev = &at91sam9rl_ssc1_device;
792 configure_ssc1_pins(pins);
793 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
794 break;
795 default:
796 return;
797 }
798
799 platform_device_register(pdev);
800}
801
802#else
803void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
804#endif
805
806
877d7720
AV		 807/* --------------------------------------------------------------------
808 * UART
809 * -------------------------------------------------------------------- */
810
811#if defined(CONFIG_SERIAL_ATMEL)
812static struct resource dbgu_resources[] = {
813 [0] = {
814 .start = AT91_VA_BASE_SYS + AT91_DBGU,
815 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
816 .flags = IORESOURCE_MEM,
817 },
818 [1] = {
819 .start = AT91_ID_SYS,
820 .end = AT91_ID_SYS,
821 .flags = IORESOURCE_IRQ,
822 },
823};
824
825static struct atmel_uart_data dbgu_data = {
826 .use_dma_tx = 0,
827 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
828 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
829};
830
c6686ff9
AV		 831static u64 dbgu_dmamask = DMA_BIT_MASK(32);
832
877d7720
AV		 833static struct platform_device at91sam9rl_dbgu_device = {
834 .name = "atmel_usart",
835 .id = 0,
836 .dev = {
c6686ff9
AV		 837 .dma_mask = &dbgu_dmamask,
838 .coherent_dma_mask = DMA_BIT_MASK(32),
839 .platform_data = &dbgu_data,
877d7720
AV		 840 },
841 .resource = dbgu_resources,
842 .num_resources = ARRAY_SIZE(dbgu_resources),
843};
844
845static inline void configure_dbgu_pins(void)
846{
847 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
848 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
849}
850
851static struct resource uart0_resources[] = {
852 [0] = {
853 .start = AT91SAM9RL_BASE_US0,
854 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
855 .flags = IORESOURCE_MEM,
856 },
857 [1] = {
858 .start = AT91SAM9RL_ID_US0,
859 .end = AT91SAM9RL_ID_US0,
860 .flags = IORESOURCE_IRQ,
861 },
862};
863
864static struct atmel_uart_data uart0_data = {
865 .use_dma_tx = 1,
866 .use_dma_rx = 1,
867};
868
c6686ff9
AV		 869static u64 uart0_dmamask = DMA_BIT_MASK(32);
870
877d7720
AV		 871static struct platform_device at91sam9rl_uart0_device = {
872 .name = "atmel_usart",
873 .id = 1,
874 .dev = {
c6686ff9
AV		 875 .dma_mask = &uart0_dmamask,
876 .coherent_dma_mask = DMA_BIT_MASK(32),
877 .platform_data = &uart0_data,
877d7720
AV		 878 },
879 .resource = uart0_resources,
880 .num_resources = ARRAY_SIZE(uart0_resources),
881};
882
c8f385a6 883static inline void configure_usart0_pins(unsigned pins)
877d7720
AV		 884{
885 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
886 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
c8f385a6
AV		 887
888 if (pins & ATMEL_UART_RTS)
889 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
890 if (pins & ATMEL_UART_CTS)
891 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
892 if (pins & ATMEL_UART_DSR)
893 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
894 if (pins & ATMEL_UART_DTR)
895 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
896 if (pins & ATMEL_UART_DCD)
897 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
898 if (pins & ATMEL_UART_RI)
899 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
877d7720
AV		 900}
901
902static struct resource uart1_resources[] = {
903 [0] = {
904 .start = AT91SAM9RL_BASE_US1,
905 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
906 .flags = IORESOURCE_MEM,
907 },
908 [1] = {
909 .start = AT91SAM9RL_ID_US1,
910 .end = AT91SAM9RL_ID_US1,
911 .flags = IORESOURCE_IRQ,
912 },
913};
914
915static struct atmel_uart_data uart1_data = {
916 .use_dma_tx = 1,
917 .use_dma_rx = 1,
918};
919
c6686ff9
AV		 920static u64 uart1_dmamask = DMA_BIT_MASK(32);
921
877d7720
AV		 922static struct platform_device at91sam9rl_uart1_device = {
923 .name = "atmel_usart",
924 .id = 2,
925 .dev = {
c6686ff9
AV		 926 .dma_mask = &uart1_dmamask,
927 .coherent_dma_mask = DMA_BIT_MASK(32),
928 .platform_data = &uart1_data,
877d7720
AV		 929 },
930 .resource = uart1_resources,
931 .num_resources = ARRAY_SIZE(uart1_resources),
932};
933
c8f385a6 934static inline void configure_usart1_pins(unsigned pins)
877d7720
AV		 935{
936 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
937 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
c8f385a6
AV		 938
939 if (pins & ATMEL_UART_RTS)
940 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */
941 if (pins & ATMEL_UART_CTS)
942 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */
877d7720
AV		 943}
944
945static struct resource uart2_resources[] = {
946 [0] = {
947 .start = AT91SAM9RL_BASE_US2,
948 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
949 .flags = IORESOURCE_MEM,
950 },
951 [1] = {
952 .start = AT91SAM9RL_ID_US2,
953 .end = AT91SAM9RL_ID_US2,
954 .flags = IORESOURCE_IRQ,
955 },
956};
957
958static struct atmel_uart_data uart2_data = {
959 .use_dma_tx = 1,
960 .use_dma_rx = 1,
961};
962
c6686ff9
AV		 963static u64 uart2_dmamask = DMA_BIT_MASK(32);
964
877d7720
AV		 965static struct platform_device at91sam9rl_uart2_device = {
966 .name = "atmel_usart",
967 .id = 3,
968 .dev = {
c6686ff9
AV		 969 .dma_mask = &uart2_dmamask,
970 .coherent_dma_mask = DMA_BIT_MASK(32),
971 .platform_data = &uart2_data,
877d7720
AV		 972 },
973 .resource = uart2_resources,
974 .num_resources = ARRAY_SIZE(uart2_resources),
975};
976
c8f385a6 977static inline void configure_usart2_pins(unsigned pins)
877d7720
AV		 978{
979 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
980 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
c8f385a6
AV		 981
982 if (pins & ATMEL_UART_RTS)
983 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
984 if (pins & ATMEL_UART_CTS)
985 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
877d7720
AV		 986}
987
988static struct resource uart3_resources[] = {
989 [0] = {
990 .start = AT91SAM9RL_BASE_US3,
991 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
992 .flags = IORESOURCE_MEM,
993 },
994 [1] = {
995 .start = AT91SAM9RL_ID_US3,
996 .end = AT91SAM9RL_ID_US3,
997 .flags = IORESOURCE_IRQ,
998 },
999};
1000
1001static struct atmel_uart_data uart3_data = {
1002 .use_dma_tx = 1,
1003 .use_dma_rx = 1,
1004};
1005
c6686ff9
AV		 1006static u64 uart3_dmamask = DMA_BIT_MASK(32);
1007
877d7720
AV		 1008static struct platform_device at91sam9rl_uart3_device = {
1009 .name = "atmel_usart",
1010 .id = 4,
1011 .dev = {
c6686ff9
AV		 1012 .dma_mask = &uart3_dmamask,
1013 .coherent_dma_mask = DMA_BIT_MASK(32),
1014 .platform_data = &uart3_data,
877d7720
AV		 1015 },
1016 .resource = uart3_resources,
1017 .num_resources = ARRAY_SIZE(uart3_resources),
1018};
1019
c8f385a6 1020static inline void configure_usart3_pins(unsigned pins)
877d7720
AV		 1021{
1022 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
1023 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
c8f385a6
AV		 1024
1025 if (pins & ATMEL_UART_RTS)
1026 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */
1027 if (pins & ATMEL_UART_CTS)
1028 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
877d7720
AV		 1029}
1030
11aadac4 1031static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
877d7720
AV		 1032struct platform_device *atmel_default_console_device; /* the serial console device */
1033
c8f385a6
AV		 1034void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1035{
1036 struct platform_device *pdev;
1037
1038 switch (id) {
1039 case 0: /* DBGU */
1040 pdev = &at91sam9rl_dbgu_device;
1041 configure_dbgu_pins();
1042 at91_clock_associate("mck", &pdev->dev, "usart");
1043 break;
1044 case AT91SAM9RL_ID_US0:
1045 pdev = &at91sam9rl_uart0_device;
1046 configure_usart0_pins(pins);
1047 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1048 break;
1049 case AT91SAM9RL_ID_US1:
1050 pdev = &at91sam9rl_uart1_device;
1051 configure_usart1_pins(pins);
1052 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1053 break;
1054 case AT91SAM9RL_ID_US2:
1055 pdev = &at91sam9rl_uart2_device;
1056 configure_usart2_pins(pins);
1057 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1058 break;
1059 case AT91SAM9RL_ID_US3:
1060 pdev = &at91sam9rl_uart3_device;
1061 configure_usart3_pins(pins);
1062 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1063 break;
1064 default:
1065 return;
1066 }
1067 pdev->id = portnr; /* update to mapped ID */
1068
1069 if (portnr < ATMEL_MAX_UART)
1070 at91_uarts[portnr] = pdev;
1071}
1072
1073void __init at91_set_serial_console(unsigned portnr)
1074{
1075 if (portnr < ATMEL_MAX_UART)
1076 atmel_default_console_device = at91_uarts[portnr];
c8f385a6
AV		 1077}
1078
877d7720
AV		 1079void __init at91_add_device_serial(void)
1080{
1081 int i;
1082
1083 for (i = 0; i < ATMEL_MAX_UART; i++) {
1084 if (at91_uarts[i])
1085 platform_device_register(at91_uarts[i]);
1086 }
11aadac4
AV		 1087
1088 if (!atmel_default_console_device)
1089 printk(KERN_INFO "AT91: No default serial console defined.\n");
877d7720
AV		 1090}
1091#else
c8f385a6
AV		 1092void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1093void __init at91_set_serial_console(unsigned portnr) {}
877d7720
AV		 1094void __init at91_add_device_serial(void) {}
1095#endif
1096
1097
1098/* -------------------------------------------------------------------- */
1099
1100/*
1101 * These devices are always present and don't need any board-specific
1102 * setup.
1103 */
1104static int __init at91_add_standard_devices(void)
1105{
884f5a6a
AV		 1106 at91_add_device_rtc();
1107 at91_add_device_rtt();
1108 at91_add_device_watchdog();
e5f40bfa 1109 at91_add_device_tc();
877d7720
AV		 1110 return 0;
1111}
1112
1113arch_initcall(at91_add_standard_devices);
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