[linux-2.6-block.git] / arch / arm / include / asm / dma-mapping.h

#ifndef ASMARM_DMA_MAPPING_H
#define ASMARM_DMA_MAPPING_H

#ifdef __KERNEL__

#include <linux/mm_types.h>
#include <linux/scatterlist.h>
#include <linux/dma-attrs.h>
#include <linux/dma-debug.h>

#include <asm-generic/dma-coherent.h>
#include <asm/memory.h>

#include <xen/xen.h>
#include <asm/xen/hypervisor.h>

#define DMA_ERROR_CODE	(~0)
extern struct dma_map_ops arm_dma_ops;
extern struct dma_map_ops arm_coherent_dma_ops;

static inline struct dma_map_ops *__generic_dma_ops(struct device *dev)
{
	if (dev && dev->archdata.dma_ops)
		return dev->archdata.dma_ops;
	return &arm_dma_ops;
}

static inline struct dma_map_ops *get_dma_ops(struct device *dev)
{
	if (xen_initial_domain())
		return xen_dma_ops;
	else
		return __generic_dma_ops(dev);
}

static inline void set_dma_ops(struct device *dev, struct dma_map_ops *ops)
{
	BUG_ON(!dev);
	dev->archdata.dma_ops = ops;
}

#include <asm-generic/dma-mapping-common.h>

static inline int dma_set_mask(struct device *dev, u64 mask)
{
	return get_dma_ops(dev)->set_dma_mask(dev, mask);
}

#ifdef __arch_page_to_dma
#error Please update to __arch_pfn_to_dma
#endif

/*
 * dma_to_pfn/pfn_to_dma/dma_to_virt/virt_to_dma are architecture private
 * functions used internally by the DMA-mapping API to provide DMA
 * addresses. They must not be used by drivers.
 */
#ifndef __arch_pfn_to_dma
static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
{
	return (dma_addr_t)__pfn_to_bus(pfn);
}

static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
{
	return __bus_to_pfn(addr);
}

static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
{
	return (void *)__bus_to_virt((unsigned long)addr);
}

static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
{
	return (dma_addr_t)__virt_to_bus((unsigned long)(addr));
}

#else
static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
{
	return __arch_pfn_to_dma(dev, pfn);
}

static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
{
	return __arch_dma_to_pfn(dev, addr);
}

static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
{
	return __arch_dma_to_virt(dev, addr);
}

static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
{
	return __arch_virt_to_dma(dev, addr);
}
#endif

/* The ARM override for dma_max_pfn() */
static inline unsigned long dma_max_pfn(struct device *dev)
{
	return PHYS_PFN_OFFSET + dma_to_pfn(dev, *dev->dma_mask);
}
#define dma_max_pfn(dev) dma_max_pfn(dev)

static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
{
	unsigned int offset = paddr & ~PAGE_MASK;
	return pfn_to_dma(dev, __phys_to_pfn(paddr)) + offset;
}

static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr)
{
	unsigned int offset = dev_addr & ~PAGE_MASK;
	return __pfn_to_phys(dma_to_pfn(dev, dev_addr)) + offset;
}

static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
{
	u64 limit, mask;

	if (!dev->dma_mask)
		return 0;

	mask = *dev->dma_mask;

	limit = (mask + 1) & ~mask;
	if (limit && size > limit)
		return 0;

	if ((addr | (addr + size - 1)) & ~mask)
		return 0;

	return 1;
}

static inline void dma_mark_clean(void *addr, size_t size) { }

/*
 * DMA errors are defined by all-bits-set in the DMA address.
 */
static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
	debug_dma_mapping_error(dev, dma_addr);
	return dma_addr == DMA_ERROR_CODE;
}

/*
 * Dummy noncoherent implementation.  We don't provide a dma_cache_sync
 * function so drivers using this API are highlighted with build warnings.
 */
static inline void *dma_alloc_noncoherent(struct device *dev, size_t size,
		dma_addr_t *handle, gfp_t gfp)
{
	return NULL;
}

static inline void dma_free_noncoherent(struct device *dev, size_t size,
		void *cpu_addr, dma_addr_t handle)
{
}

extern int dma_supported(struct device *dev, u64 mask);

extern int arm_dma_set_mask(struct device *dev, u64 dma_mask);

/**
 * arm_dma_alloc - allocate consistent memory for DMA
 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
 * @size: required memory size
 * @handle: bus-specific DMA address
 * @attrs: optinal attributes that specific mapping properties
 *
 * Allocate some memory for a device for performing DMA.  This function
 * allocates pages, and will return the CPU-viewed address, and sets @handle
 * to be the device-viewed address.
 */
extern void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
			   gfp_t gfp, struct dma_attrs *attrs);

#define dma_alloc_coherent(d, s, h, f) dma_alloc_attrs(d, s, h, f, NULL)

static inline void *dma_alloc_attrs(struct device *dev, size_t size,
				       dma_addr_t *dma_handle, gfp_t flag,
				       struct dma_attrs *attrs)
{
	struct dma_map_ops *ops = get_dma_ops(dev);
	void *cpu_addr;
	BUG_ON(!ops);

	cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs);
	debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
	return cpu_addr;
}

/**
 * arm_dma_free - free memory allocated by arm_dma_alloc
 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
 * @size: size of memory originally requested in dma_alloc_coherent
 * @cpu_addr: CPU-view address returned from dma_alloc_coherent
 * @handle: device-view address returned from dma_alloc_coherent
 * @attrs: optinal attributes that specific mapping properties
 *
 * Free (and unmap) a DMA buffer previously allocated by
 * arm_dma_alloc().
 *
 * References to memory and mappings associated with cpu_addr/handle
 * during and after this call executing are illegal.
 */
extern void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
			 dma_addr_t handle, struct dma_attrs *attrs);

#define dma_free_coherent(d, s, c, h) dma_free_attrs(d, s, c, h, NULL)

static inline void dma_free_attrs(struct device *dev, size_t size,
				     void *cpu_addr, dma_addr_t dma_handle,
				     struct dma_attrs *attrs)
{
	struct dma_map_ops *ops = get_dma_ops(dev);
	BUG_ON(!ops);

	debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
	ops->free(dev, size, cpu_addr, dma_handle, attrs);
}

/**
 * arm_dma_mmap - map a coherent DMA allocation into user space
 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
 * @vma: vm_area_struct describing requested user mapping
 * @cpu_addr: kernel CPU-view address returned from dma_alloc_coherent
 * @handle: device-view address returned from dma_alloc_coherent
 * @size: size of memory originally requested in dma_alloc_coherent
 * @attrs: optinal attributes that specific mapping properties
 *
 * Map a coherent DMA buffer previously allocated by dma_alloc_coherent
 * into user space.  The coherent DMA buffer must not be freed by the
 * driver until the user space mapping has been released.
 */
extern int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
			void *cpu_addr, dma_addr_t dma_addr, size_t size,
			struct dma_attrs *attrs);

static inline void *dma_alloc_writecombine(struct device *dev, size_t size,
				       dma_addr_t *dma_handle, gfp_t flag)
{
	DEFINE_DMA_ATTRS(attrs);
	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	return dma_alloc_attrs(dev, size, dma_handle, flag, &attrs);
}

static inline void dma_free_writecombine(struct device *dev, size_t size,
				     void *cpu_addr, dma_addr_t dma_handle)
{
	DEFINE_DMA_ATTRS(attrs);
	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	return dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs);
}

/*
 * This can be called during early boot to increase the size of the atomic
 * coherent DMA pool above the default value of 256KiB. It must be called
 * before postcore_initcall.
 */
extern void __init init_dma_coherent_pool_size(unsigned long size);

/*
 * For SA-1111, IXP425, and ADI systems  the dma-mapping functions are "magic"
 * and utilize bounce buffers as needed to work around limited DMA windows.
 *
 * On the SA-1111, a bug limits DMA to only certain regions of RAM.
 * On the IXP425, the PCI inbound window is 64MB (256MB total RAM)
 * On some ADI engineering systems, PCI inbound window is 32MB (12MB total RAM)
 *
 * The following are helper functions used by the dmabounce subystem
 *
 */

/**
 * dmabounce_register_dev
 *
 * @dev: valid struct device pointer
 * @small_buf_size: size of buffers to use with small buffer pool
 * @large_buf_size: size of buffers to use with large buffer pool (can be 0)
 * @needs_bounce_fn: called to determine whether buffer needs bouncing
 *
 * This function should be called by low-level platform code to register
 * a device as requireing DMA buffer bouncing. The function will allocate
 * appropriate DMA pools for the device.
 */
extern int dmabounce_register_dev(struct device *, unsigned long,
		unsigned long, int (*)(struct device *, dma_addr_t, size_t));

/**
 * dmabounce_unregister_dev
 *
 * @dev: valid struct device pointer
 *
 * This function should be called by low-level platform code when device
 * that was previously registered with dmabounce_register_dev is removed
 * from the system.
 *
 */
extern void dmabounce_unregister_dev(struct device *);


/*
 * The scatter list versions of the above methods.
 */
extern int arm_dma_map_sg(struct device *, struct scatterlist *, int,
		enum dma_data_direction, struct dma_attrs *attrs);
extern void arm_dma_unmap_sg(struct device *, struct scatterlist *, int,
		enum dma_data_direction, struct dma_attrs *attrs);
extern void arm_dma_sync_sg_for_cpu(struct device *, struct scatterlist *, int,
		enum dma_data_direction);
extern void arm_dma_sync_sg_for_device(struct device *, struct scatterlist *, int,
		enum dma_data_direction);
extern int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
		void *cpu_addr, dma_addr_t dma_addr, size_t size,
		struct dma_attrs *attrs);

#endif /* __KERNEL__ */
#endif
Commit	Line	Data
1da177e4 LT	1	#ifndef ASMARM_DMA_MAPPING_H
	2	#define ASMARM_DMA_MAPPING_H
	3
	4	#ifdef __KERNEL__
	5
98ed7d4b	6	#include <linux/mm_types.h>
dee9ba82	7	#include <linux/scatterlist.h>
f99d6034	8	#include <linux/dma-attrs.h>
24056f52	9	#include <linux/dma-debug.h>
1da177e4	10
1fe53268	11	#include <asm-generic/dma-coherent.h>
98ed7d4b RK	12	#include <asm/memory.h>
98ed7d4b RK	13
c7e9bc54 SS	14	#include <xen/xen.h>
	15	#include <asm/xen/hypervisor.h>
	16
553ac788	17	#define DMA_ERROR_CODE (~0)
2dc6a016	18	extern struct dma_map_ops arm_dma_ops;
dd37e940	19	extern struct dma_map_ops arm_coherent_dma_ops;
2dc6a016	20
c7e9bc54	21	static inline struct dma_map_ops __generic_dma_ops(struct device dev)
2dc6a016 MS	22	{
	23	if (dev && dev->archdata.dma_ops)
	24	return dev->archdata.dma_ops;
	25	return &arm_dma_ops;
	26	}
	27
c7e9bc54 SS	28	static inline struct dma_map_ops get_dma_ops(struct device dev)
	29	{
	30	if (xen_initial_domain())
	31	return xen_dma_ops;
	32	else
	33	return __generic_dma_ops(dev);
	34	}
	35
2dc6a016 MS	36	static inline void set_dma_ops(struct device dev, struct dma_map_ops ops)
	37	{
	38	BUG_ON(!dev);
	39	dev->archdata.dma_ops = ops;
	40	}
	41
	42	#include <asm-generic/dma-mapping-common.h>
	43
	44	static inline int dma_set_mask(struct device *dev, u64 mask)
	45	{
	46	return get_dma_ops(dev)->set_dma_mask(dev, mask);
	47	}
553ac788	48
9eedd963 RK	49	#ifdef __arch_page_to_dma
	50	#error Please update to __arch_pfn_to_dma
	51	#endif
	52
98ed7d4b	53	/*
9eedd963 RK	54	* dma_to_pfn/pfn_to_dma/dma_to_virt/virt_to_dma are architecture private
	55	* functions used internally by the DMA-mapping API to provide DMA
	56	* addresses. They must not be used by drivers.
98ed7d4b	57	*/
9eedd963 RK	58	#ifndef __arch_pfn_to_dma
9eedd963 RK	59	static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
58edb515	60	{
9eedd963	61	return (dma_addr_t)__pfn_to_bus(pfn);
58edb515	62	}
98ed7d4b	63
9eedd963	64	static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
ef1baed8	65	{
9eedd963	66	return __bus_to_pfn(addr);
ef1baed8 RK	67	}
ef1baed8 RK	68
98ed7d4b RK	69	static inline void dma_to_virt(struct device dev, dma_addr_t addr)
98ed7d4b RK	70	{
01f461a3	71	return (void *)__bus_to_virt((unsigned long)addr);
98ed7d4b RK	72	}
	73
	74	static inline dma_addr_t virt_to_dma(struct device dev, void addr)
	75	{
	76	return (dma_addr_t)__virt_to_bus((unsigned long)(addr));
	77	}
26ba47b1	78
98ed7d4b	79	#else
9eedd963	80	static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
98ed7d4b	81	{
9eedd963	82	return __arch_pfn_to_dma(dev, pfn);
98ed7d4b RK	83	}
98ed7d4b RK	84
9eedd963	85	static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
ef1baed8	86	{
9eedd963	87	return __arch_dma_to_pfn(dev, addr);
ef1baed8 RK	88	}
ef1baed8 RK	89
98ed7d4b RK	90	static inline void dma_to_virt(struct device dev, dma_addr_t addr)
	91	{
	92	return __arch_dma_to_virt(dev, addr);
	93	}
	94
	95	static inline dma_addr_t virt_to_dma(struct device dev, void addr)
	96	{
	97	return __arch_virt_to_dma(dev, addr);
	98	}
	99	#endif
1fe53268	100
26ba47b1 SS	101	/* The ARM override for dma_max_pfn() */
	102	static inline unsigned long dma_max_pfn(struct device *dev)
	103	{
	104	return PHYS_PFN_OFFSET + dma_to_pfn(dev, *dev->dma_mask);
	105	}
	106	#define dma_max_pfn(dev) dma_max_pfn(dev)
	107
fbd989b1 SS	108	static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
	109	{
	110	unsigned int offset = paddr & ~PAGE_MASK;
	111	return pfn_to_dma(dev, __phys_to_pfn(paddr)) + offset;
	112	}
	113
	114	static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dev_addr)
	115	{
	116	unsigned int offset = dev_addr & ~PAGE_MASK;
	117	return __pfn_to_phys(dma_to_pfn(dev, dev_addr)) + offset;
	118	}
	119
	120	static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
	121	{
	122	u64 limit, mask;
	123
	124	if (!dev->dma_mask)
	125	return 0;
	126
	127	mask = *dev->dma_mask;
	128
	129	limit = (mask + 1) & ~mask;
	130	if (limit && size > limit)
	131	return 0;
	132
	133	if ((addr \| (addr + size - 1)) & ~mask)
	134	return 0;
	135
	136	return 1;
	137	}
	138
	139	static inline void dma_mark_clean(void *addr, size_t size) { }
	140
1da177e4 LT	141	/*
	142	* DMA errors are defined by all-bits-set in the DMA address.
	143	*/
8d8bb39b	144	static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
1da177e4	145	{
a0157573	146	debug_dma_mapping_error(dev, dma_addr);
553ac788	147	return dma_addr == DMA_ERROR_CODE;
1da177e4 LT	148	}
1da177e4 LT	149
f454aa6b RK	150	/*
	151	* Dummy noncoherent implementation. We don't provide a dma_cache_sync
	152	* function so drivers using this API are highlighted with build warnings.
	153	*/
3216a97b RK	154	static inline void dma_alloc_noncoherent(struct device dev, size_t size,
3216a97b RK	155	dma_addr_t *handle, gfp_t gfp)
f454aa6b RK	156	{
	157	return NULL;
	158	}
	159
3216a97b RK	160	static inline void dma_free_noncoherent(struct device *dev, size_t size,
3216a97b RK	161	void *cpu_addr, dma_addr_t handle)
f454aa6b RK	162	{
	163	}
	164
15237e1f MS	165	extern int dma_supported(struct device *dev, u64 mask);
15237e1f MS	166
87b54e78 GC	167	extern int arm_dma_set_mask(struct device *dev, u64 dma_mask);
87b54e78 GC	168
1da177e4	169	/**
f99d6034	170	* arm_dma_alloc - allocate consistent memory for DMA
1da177e4 LT	171	* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
	172	* @size: required memory size
	173	* @handle: bus-specific DMA address
f99d6034	174	* @attrs: optinal attributes that specific mapping properties
1da177e4	175	*
f99d6034 MS	176	* Allocate some memory for a device for performing DMA. This function
	177	* allocates pages, and will return the CPU-viewed address, and sets @handle
	178	* to be the device-viewed address.
1da177e4	179	*/
f99d6034 MS	180	extern void arm_dma_alloc(struct device dev, size_t size, dma_addr_t *handle,
	181	gfp_t gfp, struct dma_attrs *attrs);
	182
	183	#define dma_alloc_coherent(d, s, h, f) dma_alloc_attrs(d, s, h, f, NULL)
	184
	185	static inline void dma_alloc_attrs(struct device dev, size_t size,
	186	dma_addr_t *dma_handle, gfp_t flag,
	187	struct dma_attrs *attrs)
	188	{
	189	struct dma_map_ops *ops = get_dma_ops(dev);
	190	void *cpu_addr;
	191	BUG_ON(!ops);
	192
	193	cpu_addr = ops->alloc(dev, size, dma_handle, flag, attrs);
	194	debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
	195	return cpu_addr;
	196	}
1da177e4 LT	197
1da177e4 LT	198	/**
f99d6034	199	* arm_dma_free - free memory allocated by arm_dma_alloc
1da177e4 LT	200	* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
	201	* @size: size of memory originally requested in dma_alloc_coherent
	202	* @cpu_addr: CPU-view address returned from dma_alloc_coherent
	203	* @handle: device-view address returned from dma_alloc_coherent
f99d6034	204	* @attrs: optinal attributes that specific mapping properties
1da177e4 LT	205	*
1da177e4 LT	206	* Free (and unmap) a DMA buffer previously allocated by
f99d6034	207	* arm_dma_alloc().
1da177e4 LT	208	*
	209	* References to memory and mappings associated with cpu_addr/handle
	210	* during and after this call executing are illegal.
	211	*/
f99d6034 MS	212	extern void arm_dma_free(struct device dev, size_t size, void cpu_addr,
	213	dma_addr_t handle, struct dma_attrs *attrs);
	214
	215	#define dma_free_coherent(d, s, c, h) dma_free_attrs(d, s, c, h, NULL)
	216
	217	static inline void dma_free_attrs(struct device *dev, size_t size,
	218	void *cpu_addr, dma_addr_t dma_handle,
	219	struct dma_attrs *attrs)
	220	{
	221	struct dma_map_ops *ops = get_dma_ops(dev);
	222	BUG_ON(!ops);
	223
	224	debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
	225	ops->free(dev, size, cpu_addr, dma_handle, attrs);
	226	}
1da177e4 LT	227
1da177e4 LT	228	/**
f99d6034	229	* arm_dma_mmap - map a coherent DMA allocation into user space
1da177e4 LT	230	* @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
	231	* @vma: vm_area_struct describing requested user mapping
	232	* @cpu_addr: kernel CPU-view address returned from dma_alloc_coherent
	233	* @handle: device-view address returned from dma_alloc_coherent
	234	* @size: size of memory originally requested in dma_alloc_coherent
f99d6034	235	* @attrs: optinal attributes that specific mapping properties
1da177e4 LT	236	*
	237	* Map a coherent DMA buffer previously allocated by dma_alloc_coherent
	238	* into user space. The coherent DMA buffer must not be freed by the
	239	* driver until the user space mapping has been released.
	240	*/
f99d6034 MS	241	extern int arm_dma_mmap(struct device dev, struct vm_area_struct vma,
	242	void *cpu_addr, dma_addr_t dma_addr, size_t size,
	243	struct dma_attrs *attrs);
1da177e4	244
f99d6034 MS	245	static inline void dma_alloc_writecombine(struct device dev, size_t size,
	246	dma_addr_t *dma_handle, gfp_t flag)
	247	{
	248	DEFINE_DMA_ATTRS(attrs);
	249	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	250	return dma_alloc_attrs(dev, size, dma_handle, flag, &attrs);
	251	}
1da177e4	252
f99d6034 MS	253	static inline void dma_free_writecombine(struct device *dev, size_t size,
	254	void *cpu_addr, dma_addr_t dma_handle)
	255	{
	256	DEFINE_DMA_ATTRS(attrs);
	257	dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
	258	return dma_free_attrs(dev, size, cpu_addr, dma_handle, &attrs);
	259	}
	260
6e5267aa MS	261	/*
	262	* This can be called during early boot to increase the size of the atomic
	263	* coherent DMA pool above the default value of 256KiB. It must be called
	264	* before postcore_initcall.
	265	*/
	266	extern void __init init_dma_coherent_pool_size(unsigned long size);
	267
8c8a0ec5 RK	268	/*
	269	* For SA-1111, IXP425, and ADI systems the dma-mapping functions are "magic"
	270	* and utilize bounce buffers as needed to work around limited DMA windows.
	271	*
	272	* On the SA-1111, a bug limits DMA to only certain regions of RAM.
	273	* On the IXP425, the PCI inbound window is 64MB (256MB total RAM)
	274	* On some ADI engineering systems, PCI inbound window is 32MB (12MB total RAM)
	275	*
	276	* The following are helper functions used by the dmabounce subystem
	277	*
	278	*/
	279
	280	/**
	281	* dmabounce_register_dev
	282	*
	283	* @dev: valid struct device pointer
	284	* @small_buf_size: size of buffers to use with small buffer pool
	285	* @large_buf_size: size of buffers to use with large buffer pool (can be 0)
0703ed2a	286	* @needs_bounce_fn: called to determine whether buffer needs bouncing
8c8a0ec5 RK	287	*
	288	* This function should be called by low-level platform code to register
	289	* a device as requireing DMA buffer bouncing. The function will allocate
	290	* appropriate DMA pools for the device.
8c8a0ec5	291	*/
3216a97b	292	extern int dmabounce_register_dev(struct device *, unsigned long,
0703ed2a	293	unsigned long, int ()(struct device , dma_addr_t, size_t));
8c8a0ec5 RK	294
	295	/**
	296	* dmabounce_unregister_dev
	297	*
	298	* @dev: valid struct device pointer
	299	*
	300	* This function should be called by low-level platform code when device
	301	* that was previously registered with dmabounce_register_dev is removed
	302	* from the system.
	303	*
	304	*/
	305	extern void dmabounce_unregister_dev(struct device *);
	306
8c8a0ec5	307
24056f52	308
afd1a321 RK	309	/*
afd1a321 RK	310	* The scatter list versions of the above methods.
1da177e4	311	*/
2dc6a016 MS	312	extern int arm_dma_map_sg(struct device , struct scatterlist , int,
	313	enum dma_data_direction, struct dma_attrs *attrs);
	314	extern void arm_dma_unmap_sg(struct device , struct scatterlist , int,
	315	enum dma_data_direction, struct dma_attrs *attrs);
	316	extern void arm_dma_sync_sg_for_cpu(struct device , struct scatterlist , int,
3216a97b	317	enum dma_data_direction);
2dc6a016	318	extern void arm_dma_sync_sg_for_device(struct device , struct scatterlist , int,
3216a97b	319	enum dma_data_direction);
dc2832e1 MS	320	extern int arm_dma_get_sgtable(struct device dev, struct sg_table sgt,
	321	void *cpu_addr, dma_addr_t dma_addr, size_t size,
	322	struct dma_attrs *attrs);
1da177e4	323
1da177e4 LT	324	#endif /* __KERNEL__ */
1da177e4 LT	325	#endif