[linux-2.6-block.git] / arch / arm / include / asm / bitops.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 1995, Russell King.
 * Various bits and pieces copyrights include:
 *  Linus Torvalds (test_bit).
 * Big endian support: Copyright 2001, Nicolas Pitre
 *  reworked by rmk.
 *
 * bit 0 is the LSB of an "unsigned long" quantity.
 *
 * Please note that the code in this file should never be included
 * from user space.  Many of these are not implemented in assembler
 * since they would be too costly.  Also, they require privileged
 * instructions (which are not available from user mode) to ensure
 * that they are atomic.
 */

#ifndef __ASM_ARM_BITOPS_H
#define __ASM_ARM_BITOPS_H

#ifdef __KERNEL__

#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif

#include <linux/compiler.h>
#include <linux/irqflags.h>
#include <asm/barrier.h>

/*
 * These functions are the basis of our bit ops.
 *
 * First, the atomic bitops. These use native endian.
 */
static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p)
{
	unsigned long flags;
	unsigned long mask = BIT_MASK(bit);

	p += BIT_WORD(bit);

	raw_local_irq_save(flags);
	*p |= mask;
	raw_local_irq_restore(flags);
}

static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
{
	unsigned long flags;
	unsigned long mask = BIT_MASK(bit);

	p += BIT_WORD(bit);

	raw_local_irq_save(flags);
	*p &= ~mask;
	raw_local_irq_restore(flags);
}

static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
{
	unsigned long flags;
	unsigned long mask = BIT_MASK(bit);

	p += BIT_WORD(bit);

	raw_local_irq_save(flags);
	*p ^= mask;
	raw_local_irq_restore(flags);
}

static inline int
____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
{
	unsigned long flags;
	unsigned int res;
	unsigned long mask = BIT_MASK(bit);

	p += BIT_WORD(bit);

	raw_local_irq_save(flags);
	res = *p;
	*p = res | mask;
	raw_local_irq_restore(flags);

	return (res & mask) != 0;
}

static inline int
____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
{
	unsigned long flags;
	unsigned int res;
	unsigned long mask = BIT_MASK(bit);

	p += BIT_WORD(bit);

	raw_local_irq_save(flags);
	res = *p;
	*p = res & ~mask;
	raw_local_irq_restore(flags);

	return (res & mask) != 0;
}

static inline int
____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
{
	unsigned long flags;
	unsigned int res;
	unsigned long mask = BIT_MASK(bit);

	p += BIT_WORD(bit);

	raw_local_irq_save(flags);
	res = *p;
	*p = res ^ mask;
	raw_local_irq_restore(flags);

	return (res & mask) != 0;
}

#include <asm-generic/bitops/non-atomic.h>

/*
 *  A note about Endian-ness.
 *  -------------------------
 *
 * When the ARM is put into big endian mode via CR15, the processor
 * merely swaps the order of bytes within words, thus:
 *
 *          ------------ physical data bus bits -----------
 *          D31 ... D24  D23 ... D16  D15 ... D8  D7 ... D0
 * little     byte 3       byte 2       byte 1      byte 0
 * big        byte 0       byte 1       byte 2      byte 3
 *
 * This means that reading a 32-bit word at address 0 returns the same
 * value irrespective of the endian mode bit.
 *
 * Peripheral devices should be connected with the data bus reversed in
 * "Big Endian" mode.  ARM Application Note 61 is applicable, and is
 * available from http://www.arm.com/.
 *
 * The following assumes that the data bus connectivity for big endian
 * mode has been followed.
 *
 * Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.
 */

/*
 * Native endian assembly bitops.  nr = 0 -> word 0 bit 0.
 */
extern void _set_bit(int nr, volatile unsigned long * p);
extern void _clear_bit(int nr, volatile unsigned long * p);
extern void _change_bit(int nr, volatile unsigned long * p);
extern int _test_and_set_bit(int nr, volatile unsigned long * p);
extern int _test_and_clear_bit(int nr, volatile unsigned long * p);
extern int _test_and_change_bit(int nr, volatile unsigned long * p);

/*
 * Little endian assembly bitops.  nr = 0 -> byte 0 bit 0.
 */
extern int _find_first_zero_bit_le(const unsigned long *p, unsigned size);
extern int _find_next_zero_bit_le(const unsigned long *p, int size, int offset);
extern int _find_first_bit_le(const unsigned long *p, unsigned size);
extern int _find_next_bit_le(const unsigned long *p, int size, int offset);

/*
 * Big endian assembly bitops.  nr = 0 -> byte 3 bit 0.
 */
extern int _find_first_zero_bit_be(const unsigned long *p, unsigned size);
extern int _find_next_zero_bit_be(const unsigned long *p, int size, int offset);
extern int _find_first_bit_be(const unsigned long *p, unsigned size);
extern int _find_next_bit_be(const unsigned long *p, int size, int offset);

#ifndef CONFIG_SMP
/*
 * The __* form of bitops are non-atomic and may be reordered.
 */
#define ATOMIC_BITOP(name,nr,p)			\
	(__builtin_constant_p(nr) ? ____atomic_##name(nr, p) : _##name(nr,p))
#else
#define ATOMIC_BITOP(name,nr,p)		_##name(nr,p)
#endif

/*
 * Native endian atomic definitions.
 */
#define set_bit(nr,p)			ATOMIC_BITOP(set_bit,nr,p)
#define clear_bit(nr,p)			ATOMIC_BITOP(clear_bit,nr,p)
#define change_bit(nr,p)		ATOMIC_BITOP(change_bit,nr,p)
#define test_and_set_bit(nr,p)		ATOMIC_BITOP(test_and_set_bit,nr,p)
#define test_and_clear_bit(nr,p)	ATOMIC_BITOP(test_and_clear_bit,nr,p)
#define test_and_change_bit(nr,p)	ATOMIC_BITOP(test_and_change_bit,nr,p)

#ifndef __ARMEB__
/*
 * These are the little endian, atomic definitions.
 */
#define find_first_zero_bit(p,sz)	_find_first_zero_bit_le(p,sz)
#define find_next_zero_bit(p,sz,off)	_find_next_zero_bit_le(p,sz,off)
#define find_first_bit(p,sz)		_find_first_bit_le(p,sz)
#define find_next_bit(p,sz,off)		_find_next_bit_le(p,sz,off)

#else
/*
 * These are the big endian, atomic definitions.
 */
#define find_first_zero_bit(p,sz)	_find_first_zero_bit_be(p,sz)
#define find_next_zero_bit(p,sz,off)	_find_next_zero_bit_be(p,sz,off)
#define find_first_bit(p,sz)		_find_first_bit_be(p,sz)
#define find_next_bit(p,sz,off)		_find_next_bit_be(p,sz,off)

#endif

#if __LINUX_ARM_ARCH__ < 5

#include <asm-generic/bitops/ffz.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/__ffs.h>
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/ffs.h>

#else

static inline int constant_fls(int x)
{
	int r = 32;

	if (!x)
		return 0;
	if (!(x & 0xffff0000u)) {
		x <<= 16;
		r -= 16;
	}
	if (!(x & 0xff000000u)) {
		x <<= 8;
		r -= 8;
	}
	if (!(x & 0xf0000000u)) {
		x <<= 4;
		r -= 4;
	}
	if (!(x & 0xc0000000u)) {
		x <<= 2;
		r -= 2;
	}
	if (!(x & 0x80000000u)) {
		x <<= 1;
		r -= 1;
	}
	return r;
}

/*
 * On ARMv5 and above those functions can be implemented around the
 * clz instruction for much better code efficiency.  __clz returns
 * the number of leading zeros, zero input will return 32, and
 * 0x80000000 will return 0.
 */
static inline unsigned int __clz(unsigned int x)
{
	unsigned int ret;

	asm("clz\t%0, %1" : "=r" (ret) : "r" (x));

	return ret;
}

/*
 * fls() returns zero if the input is zero, otherwise returns the bit
 * position of the last set bit, where the LSB is 1 and MSB is 32.
 */
static inline int fls(int x)
{
	if (__builtin_constant_p(x))
	       return constant_fls(x);

	return 32 - __clz(x);
}

/*
 * __fls() returns the bit position of the last bit set, where the
 * LSB is 0 and MSB is 31.  Zero input is undefined.
 */
static inline unsigned long __fls(unsigned long x)
{
	return fls(x) - 1;
}

/*
 * ffs() returns zero if the input was zero, otherwise returns the bit
 * position of the first set bit, where the LSB is 1 and MSB is 32.
 */
static inline int ffs(int x)
{
	return fls(x & -x);
}

/*
 * __ffs() returns the bit position of the first bit set, where the
 * LSB is 0 and MSB is 31.  Zero input is undefined.
 */
static inline unsigned long __ffs(unsigned long x)
{
	return ffs(x) - 1;
}

#define ffz(x) __ffs( ~(x) )

#endif

#include <asm-generic/bitops/fls64.h>

#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>

#ifdef __ARMEB__

static inline int find_first_zero_bit_le(const void *p, unsigned size)
{
	return _find_first_zero_bit_le(p, size);
}
#define find_first_zero_bit_le find_first_zero_bit_le

static inline int find_next_zero_bit_le(const void *p, int size, int offset)
{
	return _find_next_zero_bit_le(p, size, offset);
}
#define find_next_zero_bit_le find_next_zero_bit_le

static inline int find_next_bit_le(const void *p, int size, int offset)
{
	return _find_next_bit_le(p, size, offset);
}
#define find_next_bit_le find_next_bit_le

#endif

#include <asm-generic/bitops/le.h>

/*
 * Ext2 is defined to use little-endian byte ordering.
 */
#include <asm-generic/bitops/ext2-atomic-setbit.h>

#endif /* __KERNEL__ */

#endif /* _ARM_BITOPS_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4 LT	2	/*
	3	* Copyright 1995, Russell King.
	4	* Various bits and pieces copyrights include:
	5	* Linus Torvalds (test_bit).
	6	* Big endian support: Copyright 2001, Nicolas Pitre
	7	* reworked by rmk.
	8	*
	9	* bit 0 is the LSB of an "unsigned long" quantity.
	10	*
	11	* Please note that the code in this file should never be included
	12	* from user space. Many of these are not implemented in assembler
	13	* since they would be too costly. Also, they require privileged
	14	* instructions (which are not available from user mode) to ensure
	15	* that they are atomic.
	16	*/
	17
	18	#ifndef __ASM_ARM_BITOPS_H
	19	#define __ASM_ARM_BITOPS_H
	20
	21	#ifdef __KERNEL__
	22
0624517d JS	23	#ifndef _LINUX_BITOPS_H
	24	#error only <linux/bitops.h> can be included directly
	25	#endif
	26
8dc39b88	27	#include <linux/compiler.h>
9f97da78	28	#include <linux/irqflags.h>
030d0178	29	#include <asm/barrier.h>
1da177e4 LT	30
	31	/*
	32	* These functions are the basis of our bit ops.
	33	*
	34	* First, the atomic bitops. These use native endian.
	35	*/
	36	static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p)
	37	{
	38	unsigned long flags;
8901925d	39	unsigned long mask = BIT_MASK(bit);
1da177e4	40
8901925d	41	p += BIT_WORD(bit);
1da177e4	42
e7cc2c59	43	raw_local_irq_save(flags);
1da177e4	44	*p \|= mask;
e7cc2c59	45	raw_local_irq_restore(flags);
1da177e4 LT	46	}
	47
	48	static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
	49	{
	50	unsigned long flags;
8901925d	51	unsigned long mask = BIT_MASK(bit);
1da177e4	52
8901925d	53	p += BIT_WORD(bit);
1da177e4	54
e7cc2c59	55	raw_local_irq_save(flags);
1da177e4	56	*p &= ~mask;
e7cc2c59	57	raw_local_irq_restore(flags);
1da177e4 LT	58	}
	59
	60	static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
	61	{
	62	unsigned long flags;
8901925d	63	unsigned long mask = BIT_MASK(bit);
1da177e4	64
8901925d	65	p += BIT_WORD(bit);
1da177e4	66
e7cc2c59	67	raw_local_irq_save(flags);
1da177e4	68	*p ^= mask;
e7cc2c59	69	raw_local_irq_restore(flags);
1da177e4 LT	70	}
	71
	72	static inline int
	73	____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
	74	{
	75	unsigned long flags;
	76	unsigned int res;
8901925d	77	unsigned long mask = BIT_MASK(bit);
1da177e4	78
8901925d	79	p += BIT_WORD(bit);
1da177e4	80
e7cc2c59	81	raw_local_irq_save(flags);
1da177e4 LT	82	res = *p;
1da177e4 LT	83	*p = res \| mask;
e7cc2c59	84	raw_local_irq_restore(flags);
1da177e4	85
e9ac8291	86	return (res & mask) != 0;
1da177e4 LT	87	}
	88
	89	static inline int
	90	____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
	91	{
	92	unsigned long flags;
	93	unsigned int res;
8901925d	94	unsigned long mask = BIT_MASK(bit);
1da177e4	95
8901925d	96	p += BIT_WORD(bit);
1da177e4	97
e7cc2c59	98	raw_local_irq_save(flags);
1da177e4 LT	99	res = *p;
1da177e4 LT	100	*p = res & ~mask;
e7cc2c59	101	raw_local_irq_restore(flags);
1da177e4	102
e9ac8291	103	return (res & mask) != 0;
1da177e4 LT	104	}
	105
	106	static inline int
	107	____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
	108	{
	109	unsigned long flags;
	110	unsigned int res;
8901925d	111	unsigned long mask = BIT_MASK(bit);
1da177e4	112
8901925d	113	p += BIT_WORD(bit);
1da177e4	114
e7cc2c59	115	raw_local_irq_save(flags);
1da177e4 LT	116	res = *p;
1da177e4 LT	117	*p = res ^ mask;
e7cc2c59	118	raw_local_irq_restore(flags);
1da177e4	119
e9ac8291	120	return (res & mask) != 0;
1da177e4 LT	121	}
1da177e4 LT	122
b89c3b16	123	#include <asm-generic/bitops/non-atomic.h>
1da177e4 LT	124
	125	/*
	126	* A note about Endian-ness.
	127	* -------------------------
	128	*
	129	* When the ARM is put into big endian mode via CR15, the processor
	130	* merely swaps the order of bytes within words, thus:
	131	*
	132	* ------------ physical data bus bits -----------
	133	* D31 ... D24 D23 ... D16 D15 ... D8 D7 ... D0
	134	* little byte 3 byte 2 byte 1 byte 0
	135	* big byte 0 byte 1 byte 2 byte 3
	136	*
	137	* This means that reading a 32-bit word at address 0 returns the same
	138	* value irrespective of the endian mode bit.
	139	*
	140	* Peripheral devices should be connected with the data bus reversed in
	141	* "Big Endian" mode. ARM Application Note 61 is applicable, and is
	142	* available from http://www.arm.com/.
	143	*
	144	* The following assumes that the data bus connectivity for big endian
	145	* mode has been followed.
	146	*
	147	* Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.
	148	*/
	149
6323f0cc RK	150	/*
	151	* Native endian assembly bitops. nr = 0 -> word 0 bit 0.
	152	*/
	153	extern void _set_bit(int nr, volatile unsigned long * p);
	154	extern void _clear_bit(int nr, volatile unsigned long * p);
	155	extern void _change_bit(int nr, volatile unsigned long * p);
	156	extern int _test_and_set_bit(int nr, volatile unsigned long * p);
	157	extern int _test_and_clear_bit(int nr, volatile unsigned long * p);
	158	extern int _test_and_change_bit(int nr, volatile unsigned long * p);
	159
1da177e4 LT	160	/*
	161	* Little endian assembly bitops. nr = 0 -> byte 0 bit 0.
	162	*/
2d618fee MG	163	extern int _find_first_zero_bit_le(const unsigned long *p, unsigned size);
2d618fee MG	164	extern int _find_next_zero_bit_le(const unsigned long *p, int size, int offset);
1da177e4 LT	165	extern int _find_first_bit_le(const unsigned long *p, unsigned size);
	166	extern int _find_next_bit_le(const unsigned long *p, int size, int offset);
	167
	168	/*
	169	* Big endian assembly bitops. nr = 0 -> byte 3 bit 0.
	170	*/
2d618fee MG	171	extern int _find_first_zero_bit_be(const unsigned long *p, unsigned size);
2d618fee MG	172	extern int _find_next_zero_bit_be(const unsigned long *p, int size, int offset);
1da177e4 LT	173	extern int _find_first_bit_be(const unsigned long *p, unsigned size);
	174	extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
	175
e7ec0293	176	#ifndef CONFIG_SMP
1da177e4 LT	177	/*
	178	* The __* form of bitops are non-atomic and may be reordered.
	179	*/
6323f0cc RK	180	#define ATOMIC_BITOP(name,nr,p) \
6323f0cc RK	181	(__builtin_constant_p(nr) ? ____atomic_##name(nr, p) : _##name(nr,p))
e7ec0293	182	#else
6323f0cc	183	#define ATOMIC_BITOP(name,nr,p) _##name(nr,p)
e7ec0293	184	#endif
1da177e4	185
6323f0cc RK	186	/*
	187	* Native endian atomic definitions.
	188	*/
	189	#define set_bit(nr,p) ATOMIC_BITOP(set_bit,nr,p)
	190	#define clear_bit(nr,p) ATOMIC_BITOP(clear_bit,nr,p)
	191	#define change_bit(nr,p) ATOMIC_BITOP(change_bit,nr,p)
	192	#define test_and_set_bit(nr,p) ATOMIC_BITOP(test_and_set_bit,nr,p)
	193	#define test_and_clear_bit(nr,p) ATOMIC_BITOP(test_and_clear_bit,nr,p)
	194	#define test_and_change_bit(nr,p) ATOMIC_BITOP(test_and_change_bit,nr,p)
1da177e4 LT	195
	196	#ifndef __ARMEB__
	197	/*
	198	* These are the little endian, atomic definitions.
	199	*/
1da177e4 LT	200	#define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz)
	201	#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off)
	202	#define find_first_bit(p,sz) _find_first_bit_le(p,sz)
	203	#define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off)
	204
1da177e4	205	#else
1da177e4 LT	206	/*
	207	* These are the big endian, atomic definitions.
	208	*/
1da177e4 LT	209	#define find_first_zero_bit(p,sz) _find_first_zero_bit_be(p,sz)
	210	#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_be(p,sz,off)
	211	#define find_first_bit(p,sz) _find_first_bit_be(p,sz)
	212	#define find_next_bit(p,sz,off) _find_next_bit_be(p,sz,off)
	213
1da177e4 LT	214	#endif
	215
	216	#if __LINUX_ARM_ARCH__ < 5
	217
b89c3b16	218	#include <asm-generic/bitops/ffz.h>
94fc7336	219	#include <asm-generic/bitops/__fls.h>
b89c3b16 AM	220	#include <asm-generic/bitops/__ffs.h>
	221	#include <asm-generic/bitops/fls.h>
	222	#include <asm-generic/bitops/ffs.h>
1da177e4 LT	223
	224	#else
	225
93635133 AM	226	static inline int constant_fls(int x)
	227	{
	228	int r = 32;
	229
	230	if (!x)
	231	return 0;
	232	if (!(x & 0xffff0000u)) {
	233	x <<= 16;
	234	r -= 16;
	235	}
	236	if (!(x & 0xff000000u)) {
	237	x <<= 8;
	238	r -= 8;
	239	}
	240	if (!(x & 0xf0000000u)) {
	241	x <<= 4;
	242	r -= 4;
	243	}
	244	if (!(x & 0xc0000000u)) {
	245	x <<= 2;
	246	r -= 2;
	247	}
	248	if (!(x & 0x80000000u)) {
	249	x <<= 1;
	250	r -= 1;
	251	}
	252	return r;
	253	}
	254
1da177e4	255	/*
23f6620a RK	256	* On ARMv5 and above those functions can be implemented around the
	257	* clz instruction for much better code efficiency. __clz returns
	258	* the number of leading zeros, zero input will return 32, and
	259	* 0x80000000 will return 0.
1da177e4	260	*/
23f6620a RK	261	static inline unsigned int __clz(unsigned int x)
	262	{
	263	unsigned int ret;
	264
	265	asm("clz\t%0, %1" : "=r" (ret) : "r" (x));
1da177e4	266
23f6620a RK	267	return ret;
	268	}
	269
	270	/*
	271	* fls() returns zero if the input is zero, otherwise returns the bit
	272	* position of the last set bit, where the LSB is 1 and MSB is 32.
	273	*/
0c65f459 AM	274	static inline int fls(int x)
0c65f459 AM	275	{
94fc7336 NP	276	if (__builtin_constant_p(x))
	277	return constant_fls(x);
	278
23f6620a RK	279	return 32 - __clz(x);
	280	}
	281
	282	/*
	283	* __fls() returns the bit position of the last bit set, where the
	284	* LSB is 0 and MSB is 31. Zero input is undefined.
	285	*/
	286	static inline unsigned long __fls(unsigned long x)
	287	{
	288	return fls(x) - 1;
	289	}
	290
	291	/*
	292	* ffs() returns zero if the input was zero, otherwise returns the bit
	293	* position of the first set bit, where the LSB is 1 and MSB is 32.
	294	*/
	295	static inline int ffs(int x)
	296	{
	297	return fls(x & -x);
	298	}
	299
	300	/*
	301	* __ffs() returns the bit position of the first bit set, where the
	302	* LSB is 0 and MSB is 31. Zero input is undefined.
	303	*/
	304	static inline unsigned long __ffs(unsigned long x)
	305	{
	306	return ffs(x) - 1;
0c65f459 AM	307	}
0c65f459 AM	308
1da177e4 LT	309	#define ffz(x) __ffs( ~(x) )
	310
	311	#endif
	312
b89c3b16	313	#include <asm-generic/bitops/fls64.h>
1da177e4	314
b89c3b16 AM	315	#include <asm-generic/bitops/sched.h>
b89c3b16 AM	316	#include <asm-generic/bitops/hweight.h>
26333576	317	#include <asm-generic/bitops/lock.h>
1da177e4	318
04b18ff9	319	#ifdef __ARMEB__
f6b57e32 AM	320
	321	static inline int find_first_zero_bit_le(const void *p, unsigned size)
	322	{
	323	return _find_first_zero_bit_le(p, size);
	324	}
a2812e17	325	#define find_first_zero_bit_le find_first_zero_bit_le
f6b57e32 AM	326
	327	static inline int find_next_zero_bit_le(const void *p, int size, int offset)
	328	{
	329	return _find_next_zero_bit_le(p, size, offset);
	330	}
a2812e17	331	#define find_next_zero_bit_le find_next_zero_bit_le
f6b57e32 AM	332
	333	static inline int find_next_bit_le(const void *p, int size, int offset)
	334	{
	335	return _find_next_bit_le(p, size, offset);
	336	}
a2812e17	337	#define find_next_bit_le find_next_bit_le
f6b57e32	338
04b18ff9 AM	339	#endif
	340
	341	#include <asm-generic/bitops/le.h>
	342
1da177e4 LT	343	/*
1da177e4 LT	344	* Ext2 is defined to use little-endian byte ordering.
1da177e4	345	*/
148817ba	346	#include <asm-generic/bitops/ext2-atomic-setbit.h>
1da177e4	347
1da177e4 LT	348	#endif /* __KERNEL__ */
	349
	350	#endif /* _ARM_BITOPS_H */