[linux-2.6-block.git] / arch / arm / boot / dts / versatile-ab.dts

// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
/include/ "skeleton.dtsi"

/ {
	model = "ARM Versatile AB";
	compatible = "arm,versatile-ab";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&vic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		i2c0 = &i2c0;
	};

	chosen {
		stdout-path = &uart0;
	};

	memory {
		reg = <0x0 0x08000000>;
	};

	xtal24mhz: xtal24mhz@24M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
	};

	core-module@10000000 {
		compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
		reg = <0x10000000 0x200>;

		led@08.0 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x01>;
			label = "versatile:0";
			linux,default-trigger = "heartbeat";
			default-state = "on";
		};
		led@08.1 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x02>;
			label = "versatile:1";
			linux,default-trigger = "mmc0";
			default-state = "off";
		};
		led@08.2 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x04>;
			label = "versatile:2";
			linux,default-trigger = "cpu0";
			default-state = "off";
		};
		led@08.3 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x08>;
			label = "versatile:3";
			default-state = "off";
		};
		led@08.4 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x10>;
			label = "versatile:4";
			default-state = "off";
		};
		led@08.5 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x20>;
			label = "versatile:5";
			default-state = "off";
		};
		led@08.6 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x40>;
			label = "versatile:6";
			default-state = "off";
		};
		led@08.7 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x80>;
			label = "versatile:7";
			default-state = "off";
		};

		/* OSC1 on AB, OSC4 on PB */
		osc1: cm_aux_osc@24M {
			#clock-cells = <0>;
			compatible = "arm,versatile-cm-auxosc";
			clocks = <&xtal24mhz>;
		};

		/* The timer clock is the 24 MHz oscillator divided to 1MHz */
		timclk: timclk@1M {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <24>;
			clock-mult = <1>;
			clocks = <&xtal24mhz>;
		};

		pclk: pclk@24M {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <1>;
			clock-mult = <1>;
			clocks = <&xtal24mhz>;
		};
	};

	flash@34000000 {
		/* 64 MiB NOR flash in non-interleaved chips */
		compatible = "arm,versatile-flash", "cfi-flash";
		reg = <0x34000000 0x04000000>;
		bank-width = <4>;
	};

	i2c0: i2c@10002000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "arm,versatile-i2c";
		reg = <0x10002000 0x1000>;

		rtc@68 {
			compatible = "dallas,ds1338";
			reg = <0x68>;
		};
	};

	net@10010000 {
		compatible = "smsc,lan91c111";
		reg = <0x10010000 0x10000>;
		interrupts = <25>;
	};

	lcd@10008000 {
		compatible = "arm,versatile-lcd";
		reg = <0x10008000 0x1000>;
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		vic: intc@10140000 {
			compatible = "arm,versatile-vic";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x10140000 0x1000>;
			clear-mask = <0xffffffff>;
			valid-mask = <0xffffffff>;
		};

		sic: intc@10003000 {
			compatible = "arm,versatile-sic";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x10003000 0x1000>;
			interrupt-parent = <&vic>;
			interrupts = <31>; /* Cascaded to vic */
			clear-mask = <0xffffffff>;
			/*
			 * Valid interrupt lines mask according to
			 * table 4-36 page 4-50 of ARM DUI 0225D
			 */
			valid-mask = <0x0760031b>;
		};

		dma@10130000 {
			compatible = "arm,pl081", "arm,primecell";
			reg = <0x10130000 0x1000>;
			interrupts = <17>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		uart0: uart@101f1000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f1000 0x1000>;
			interrupts = <12>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart1: uart@101f2000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f2000 0x1000>;
			interrupts = <13>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart2: uart@101f3000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f3000 0x1000>;
			interrupts = <14>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		smc@10100000 {
			compatible = "arm,primecell";
			reg = <0x10100000 0x1000>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		mpmc@10110000 {
			compatible = "arm,primecell";
			reg = <0x10110000 0x1000>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		display@10120000 {
			compatible = "arm,pl110", "arm,primecell";
			reg = <0x10120000 0x1000>;
			interrupts = <16>;
			clocks = <&osc1>, <&pclk>;
			clock-names = "clcd", "apb_pclk";
		};

		sctl@101e0000 {
			compatible = "arm,primecell";
			reg = <0x101e0000 0x1000>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		watchdog@101e1000 {
			compatible = "arm,primecell";
			reg = <0x101e1000 0x1000>;
			interrupts = <0>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		timer@101e2000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x101e2000 0x1000>;
			interrupts = <4>;
			clocks = <&timclk>, <&timclk>, <&pclk>;
			clock-names = "timer0", "timer1", "apb_pclk";
		};

		timer@101e3000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x101e3000 0x1000>;
			interrupts = <5>;
			clocks = <&timclk>, <&timclk>, <&pclk>;
			clock-names = "timer0", "timer1", "apb_pclk";
		};

		gpio0: gpio@101e4000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x101e4000 0x1000>;
			gpio-controller;
			interrupts = <6>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		gpio1: gpio@101e5000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x101e5000 0x1000>;
			interrupts = <7>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		rtc@101e8000 {
			compatible = "arm,pl030", "arm,primecell";
			reg = <0x101e8000 0x1000>;
			interrupts = <10>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		sci@101f0000 {
			compatible = "arm,primecell";
			reg = <0x101f0000 0x1000>;
			interrupts = <15>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		ssp@101f4000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x101f4000 0x1000>;
			interrupts = <11>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "SSPCLK", "apb_pclk";
		};

		fpga {
			compatible = "arm,versatile-fpga", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x10000000 0x10000>;

			sysreg@0 {
				compatible = "arm,versatile-sysreg", "syscon";
				reg = <0x00000 0x1000>;
			};

			aaci@4000 {
				compatible = "arm,primecell";
				reg = <0x4000 0x1000>;
				interrupts = <24>;
				clocks = <&pclk>;
				clock-names = "apb_pclk";
			};
			mmc@5000 {
				compatible = "arm,pl180", "arm,primecell";
				reg = <0x5000 0x1000>;
				interrupts-extended = <&vic 22 &sic 1>;
				clocks = <&xtal24mhz>, <&pclk>;
				clock-names = "mclk", "apb_pclk";
			};
			kmi@6000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x6000 0x1000>;
				interrupt-parent = <&sic>;
				interrupts = <3>;
				clocks = <&xtal24mhz>, <&pclk>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};
			kmi@7000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x7000 0x1000>;
				interrupt-parent = <&sic>;
				interrupts = <4>;
				clocks = <&xtal24mhz>, <&pclk>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};
		};
	};
};
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
3ba7222a GL	2	/dts-v1/;
	3	/include/ "skeleton.dtsi"
	4
	5	/ {
	6	model = "ARM Versatile AB";
	7	compatible = "arm,versatile-ab";
	8	#address-cells = <1>;
	9	#size-cells = <1>;
	10	interrupt-parent = <&vic>;
	11
	12	aliases {
	13	serial0 = &uart0;
	14	serial1 = &uart1;
	15	serial2 = &uart2;
	16	i2c0 = &i2c0;
	17	};
	18
00388218 GL	19	chosen {
	20	stdout-path = &uart0;
	21	};
	22
3ba7222a GL	23	memory {
	24	reg = <0x0 0x08000000>;
	25	};
	26
2e452785 RH	27	xtal24mhz: xtal24mhz@24M {
	28	#clock-cells = <0>;
	29	compatible = "fixed-clock";
	30	clock-frequency = <24000000>;
	31	};
	32
	33	core-module@10000000 {
07ebfa59	34	compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
2e452785 RH	35	reg = <0x10000000 0x200>;
2e452785 RH	36
07ebfa59 LW	37	led@08.0 {
	38	compatible = "register-bit-led";
	39	offset = <0x08>;
	40	mask = <0x01>;
	41	label = "versatile:0";
	42	linux,default-trigger = "heartbeat";
	43	default-state = "on";
	44	};
	45	led@08.1 {
	46	compatible = "register-bit-led";
	47	offset = <0x08>;
	48	mask = <0x02>;
	49	label = "versatile:1";
	50	linux,default-trigger = "mmc0";
	51	default-state = "off";
	52	};
	53	led@08.2 {
	54	compatible = "register-bit-led";
	55	offset = <0x08>;
	56	mask = <0x04>;
	57	label = "versatile:2";
	58	linux,default-trigger = "cpu0";
	59	default-state = "off";
	60	};
	61	led@08.3 {
	62	compatible = "register-bit-led";
	63	offset = <0x08>;
	64	mask = <0x08>;
	65	label = "versatile:3";
	66	default-state = "off";
	67	};
	68	led@08.4 {
	69	compatible = "register-bit-led";
	70	offset = <0x08>;
	71	mask = <0x10>;
	72	label = "versatile:4";
	73	default-state = "off";
	74	};
	75	led@08.5 {
	76	compatible = "register-bit-led";
	77	offset = <0x08>;
	78	mask = <0x20>;
	79	label = "versatile:5";
	80	default-state = "off";
	81	};
	82	led@08.6 {
	83	compatible = "register-bit-led";
	84	offset = <0x08>;
	85	mask = <0x40>;
	86	label = "versatile:6";
	87	default-state = "off";
	88	};
	89	led@08.7 {
	90	compatible = "register-bit-led";
	91	offset = <0x08>;
	92	mask = <0x80>;
	93	label = "versatile:7";
	94	default-state = "off";
	95	};
	96
2e452785 RH	97	/* OSC1 on AB, OSC4 on PB */
	98	osc1: cm_aux_osc@24M {
	99	#clock-cells = <0>;
	100	compatible = "arm,versatile-cm-auxosc";
	101	clocks = <&xtal24mhz>;
	102	};
	103
	104	/* The timer clock is the 24 MHz oscillator divided to 1MHz */
	105	timclk: timclk@1M {
	106	#clock-cells = <0>;
	107	compatible = "fixed-factor-clock";
	108	clock-div = <24>;
	109	clock-mult = <1>;
	110	clocks = <&xtal24mhz>;
	111	};
	112
	113	pclk: pclk@24M {
	114	#clock-cells = <0>;
	115	compatible = "fixed-factor-clock";
	116	clock-div = <1>;
	117	clock-mult = <1>;
	118	clocks = <&xtal24mhz>;
	119	};
	120	};
	121
3ba7222a	122	flash@34000000 {
7bb73fd7 LW	123	/* 64 MiB NOR flash in non-interleaved chips */
	124	compatible = "arm,versatile-flash", "cfi-flash";
	125	reg = <0x34000000 0x04000000>;
3ba7222a GL	126	bank-width = <4>;
	127	};
	128
	129	i2c0: i2c@10002000 {
	130	#address-cells = <1>;
	131	#size-cells = <0>;
	132	compatible = "arm,versatile-i2c";
	133	reg = <0x10002000 0x1000>;
	134
	135	rtc@68 {
	136	compatible = "dallas,ds1338";
	137	reg = <0x68>;
	138	};
	139	};
	140
	141	net@10010000 {
	142	compatible = "smsc,lan91c111";
	143	reg = <0x10010000 0x10000>;
	144	interrupts = <25>;
	145	};
	146
	147	lcd@10008000 {
	148	compatible = "arm,versatile-lcd";
	149	reg = <0x10008000 0x1000>;
	150	};
	151
	152	amba {
2ef7d5f3	153	compatible = "simple-bus";
3ba7222a GL	154	#address-cells = <1>;
	155	#size-cells = <1>;
	156	ranges;
	157
	158	vic: intc@10140000 {
	159	compatible = "arm,versatile-vic";
	160	interrupt-controller;
	161	#interrupt-cells = <1>;
	162	reg = <0x10140000 0x1000>;
0ba6c5d2 RH	163	clear-mask = <0xffffffff>;
0ba6c5d2 RH	164	valid-mask = <0xffffffff>;
3ba7222a GL	165	};
	166
	167	sic: intc@10003000 {
	168	compatible = "arm,versatile-sic";
	169	interrupt-controller;
	170	#interrupt-cells = <1>;
	171	reg = <0x10003000 0x1000>;
	172	interrupt-parent = <&vic>;
	173	interrupts = <31>; /* Cascaded to vic */
0ba6c5d2	174	clear-mask = <0xffffffff>;
20f12758 LW	175	/*
	176	* Valid interrupt lines mask according to
	177	* table 4-36 page 4-50 of ARM DUI 0225D
	178	*/
	179	valid-mask = <0x0760031b>;
3ba7222a GL	180	};
	181
	182	dma@10130000 {
	183	compatible = "arm,pl081", "arm,primecell";
	184	reg = <0x10130000 0x1000>;
	185	interrupts = <17>;
2e452785 RH	186	clocks = <&pclk>;
2e452785 RH	187	clock-names = "apb_pclk";
3ba7222a GL	188	};
	189
	190	uart0: uart@101f1000 {
	191	compatible = "arm,pl011", "arm,primecell";
	192	reg = <0x101f1000 0x1000>;
	193	interrupts = <12>;
2e452785 RH	194	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	195	clock-names = "uartclk", "apb_pclk";
3ba7222a GL	196	};
	197
	198	uart1: uart@101f2000 {
	199	compatible = "arm,pl011", "arm,primecell";
	200	reg = <0x101f2000 0x1000>;
	201	interrupts = <13>;
2e452785 RH	202	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	203	clock-names = "uartclk", "apb_pclk";
3ba7222a GL	204	};
	205
	206	uart2: uart@101f3000 {
	207	compatible = "arm,pl011", "arm,primecell";
	208	reg = <0x101f3000 0x1000>;
	209	interrupts = <14>;
2e452785 RH	210	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	211	clock-names = "uartclk", "apb_pclk";
3ba7222a GL	212	};
	213
	214	smc@10100000 {
	215	compatible = "arm,primecell";
	216	reg = <0x10100000 0x1000>;
2e452785 RH	217	clocks = <&pclk>;
2e452785 RH	218	clock-names = "apb_pclk";
3ba7222a GL	219	};
	220
	221	mpmc@10110000 {
	222	compatible = "arm,primecell";
	223	reg = <0x10110000 0x1000>;
2e452785 RH	224	clocks = <&pclk>;
2e452785 RH	225	clock-names = "apb_pclk";
3ba7222a GL	226	};
	227
	228	display@10120000 {
	229	compatible = "arm,pl110", "arm,primecell";
	230	reg = <0x10120000 0x1000>;
	231	interrupts = <16>;
2e452785 RH	232	clocks = <&osc1>, <&pclk>;
2e452785 RH	233	clock-names = "clcd", "apb_pclk";
3ba7222a GL	234	};
	235
	236	sctl@101e0000 {
	237	compatible = "arm,primecell";
	238	reg = <0x101e0000 0x1000>;
2e452785 RH	239	clocks = <&pclk>;
2e452785 RH	240	clock-names = "apb_pclk";
3ba7222a GL	241	};
	242
	243	watchdog@101e1000 {
	244	compatible = "arm,primecell";
	245	reg = <0x101e1000 0x1000>;
	246	interrupts = <0>;
2e452785 RH	247	clocks = <&pclk>;
2e452785 RH	248	clock-names = "apb_pclk";
3ba7222a GL	249	};
3ba7222a GL	250
818270d5 RH	251	timer@101e2000 {
	252	compatible = "arm,sp804", "arm,primecell";
	253	reg = <0x101e2000 0x1000>;
	254	interrupts = <4>;
2e452785 RH	255	clocks = <&timclk>, <&timclk>, <&pclk>;
2e452785 RH	256	clock-names = "timer0", "timer1", "apb_pclk";
818270d5 RH	257	};
	258
	259	timer@101e3000 {
	260	compatible = "arm,sp804", "arm,primecell";
	261	reg = <0x101e3000 0x1000>;
	262	interrupts = <5>;
2e452785 RH	263	clocks = <&timclk>, <&timclk>, <&pclk>;
2e452785 RH	264	clock-names = "timer0", "timer1", "apb_pclk";
818270d5 RH	265	};
818270d5 RH	266
3ba7222a GL	267	gpio0: gpio@101e4000 {
	268	compatible = "arm,pl061", "arm,primecell";
	269	reg = <0x101e4000 0x1000>;
	270	gpio-controller;
	271	interrupts = <6>;
	272	#gpio-cells = <2>;
	273	interrupt-controller;
	274	#interrupt-cells = <2>;
2e452785 RH	275	clocks = <&pclk>;
2e452785 RH	276	clock-names = "apb_pclk";
3ba7222a GL	277	};
	278
	279	gpio1: gpio@101e5000 {
	280	compatible = "arm,pl061", "arm,primecell";
	281	reg = <0x101e5000 0x1000>;
	282	interrupts = <7>;
	283	gpio-controller;
	284	#gpio-cells = <2>;
	285	interrupt-controller;
	286	#interrupt-cells = <2>;
2e452785 RH	287	clocks = <&pclk>;
2e452785 RH	288	clock-names = "apb_pclk";
3ba7222a GL	289	};
	290
	291	rtc@101e8000 {
	292	compatible = "arm,pl030", "arm,primecell";
	293	reg = <0x101e8000 0x1000>;
	294	interrupts = <10>;
2e452785 RH	295	clocks = <&pclk>;
2e452785 RH	296	clock-names = "apb_pclk";
3ba7222a GL	297	};
	298
	299	sci@101f0000 {
	300	compatible = "arm,primecell";
	301	reg = <0x101f0000 0x1000>;
	302	interrupts = <15>;
2e452785 RH	303	clocks = <&pclk>;
2e452785 RH	304	clock-names = "apb_pclk";
3ba7222a GL	305	};
	306
	307	ssp@101f4000 {
	308	compatible = "arm,pl022", "arm,primecell";
	309	reg = <0x101f4000 0x1000>;
	310	interrupts = <11>;
2e452785 RH	311	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	312	clock-names = "SSPCLK", "apb_pclk";
3ba7222a GL	313	};
	314
	315	fpga {
	316	compatible = "arm,versatile-fpga", "simple-bus";
	317	#address-cells = <1>;
	318	#size-cells = <1>;
	319	ranges = <0 0x10000000 0x10000>;
	320
35a8578e RH	321	sysreg@0 {
	322	compatible = "arm,versatile-sysreg", "syscon";
	323	reg = <0x00000 0x1000>;
	324	};
	325
3ba7222a GL	326	aaci@4000 {
	327	compatible = "arm,primecell";
	328	reg = <0x4000 0x1000>;
	329	interrupts = <24>;
2e452785 RH	330	clocks = <&pclk>;
2e452785 RH	331	clock-names = "apb_pclk";
3ba7222a GL	332	};
3ba7222a GL	333	mmc@5000 {
04aa49f6	334	compatible = "arm,pl180", "arm,primecell";
20f12758 LW	335	reg = <0x5000 0x1000>;
20f12758 LW	336	interrupts-extended = <&vic 22 &sic 1>;
2e452785 RH	337	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	338	clock-names = "mclk", "apb_pclk";
3ba7222a GL	339	};
	340	kmi@6000 {
	341	compatible = "arm,pl050", "arm,primecell";
	342	reg = <0x6000 0x1000>;
	343	interrupt-parent = <&sic>;
	344	interrupts = <3>;
2e452785 RH	345	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	346	clock-names = "KMIREFCLK", "apb_pclk";
3ba7222a GL	347	};
	348	kmi@7000 {
	349	compatible = "arm,pl050", "arm,primecell";
	350	reg = <0x7000 0x1000>;
	351	interrupt-parent = <&sic>;
	352	interrupts = <4>;
2e452785 RH	353	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	354	clock-names = "KMIREFCLK", "apb_pclk";
3ba7222a GL	355	};
	356	};
	357	};
	358	};