Commit | Line | Data |
---|---|---|
ea566a4b MY |
1 | // SPDX-License-Identifier: GPL-2.0+ OR MIT |
2 | // | |
3 | // Device Tree Source for UniPhier PXs2 SoC | |
4 | // | |
5 | // Copyright (C) 2015-2016 Socionext Inc. | |
6 | // Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
a5e921b4 | 7 | |
d1194d49 | 8 | #include <dt-bindings/gpio/uniphier-gpio.h> |
fbd8d583 KH |
9 | #include <dt-bindings/thermal/thermal.h> |
10 | ||
a5e921b4 | 11 | / { |
77896e4d | 12 | compatible = "socionext,uniphier-pxs2"; |
8e2b908b MY |
13 | #address-cells = <1>; |
14 | #size-cells = <1>; | |
a5e921b4 MY |
15 | |
16 | cpus { | |
17 | #address-cells = <1>; | |
18 | #size-cells = <0>; | |
a5e921b4 | 19 | |
fbd8d583 | 20 | cpu0: cpu@0 { |
a5e921b4 MY |
21 | device_type = "cpu"; |
22 | compatible = "arm,cortex-a9"; | |
23 | reg = <0>; | |
7a8a6588 | 24 | clocks = <&sys_clk 32>; |
3bdba5ac | 25 | enable-method = "psci"; |
7c62f299 | 26 | next-level-cache = <&l2>; |
7a8a6588 | 27 | operating-points-v2 = <&cpu_opp>; |
fbd8d583 | 28 | #cooling-cells = <2>; |
a5e921b4 MY |
29 | }; |
30 | ||
fbd8d583 | 31 | cpu1: cpu@1 { |
a5e921b4 MY |
32 | device_type = "cpu"; |
33 | compatible = "arm,cortex-a9"; | |
34 | reg = <1>; | |
7a8a6588 | 35 | clocks = <&sys_clk 32>; |
3bdba5ac | 36 | enable-method = "psci"; |
7c62f299 | 37 | next-level-cache = <&l2>; |
7a8a6588 | 38 | operating-points-v2 = <&cpu_opp>; |
38dc27c8 | 39 | #cooling-cells = <2>; |
a5e921b4 MY |
40 | }; |
41 | ||
fbd8d583 | 42 | cpu2: cpu@2 { |
a5e921b4 MY |
43 | device_type = "cpu"; |
44 | compatible = "arm,cortex-a9"; | |
45 | reg = <2>; | |
7a8a6588 | 46 | clocks = <&sys_clk 32>; |
3bdba5ac | 47 | enable-method = "psci"; |
7c62f299 | 48 | next-level-cache = <&l2>; |
7a8a6588 | 49 | operating-points-v2 = <&cpu_opp>; |
38dc27c8 | 50 | #cooling-cells = <2>; |
a5e921b4 MY |
51 | }; |
52 | ||
fbd8d583 | 53 | cpu3: cpu@3 { |
a5e921b4 MY |
54 | device_type = "cpu"; |
55 | compatible = "arm,cortex-a9"; | |
56 | reg = <3>; | |
7a8a6588 | 57 | clocks = <&sys_clk 32>; |
3bdba5ac | 58 | enable-method = "psci"; |
7c62f299 | 59 | next-level-cache = <&l2>; |
7a8a6588 | 60 | operating-points-v2 = <&cpu_opp>; |
38dc27c8 | 61 | #cooling-cells = <2>; |
7a8a6588 MY |
62 | }; |
63 | }; | |
64 | ||
1658b84d | 65 | cpu_opp: opp-table { |
7a8a6588 MY |
66 | compatible = "operating-points-v2"; |
67 | opp-shared; | |
68 | ||
f21683ae | 69 | opp-100000000 { |
7a8a6588 MY |
70 | opp-hz = /bits/ 64 <100000000>; |
71 | clock-latency-ns = <300>; | |
72 | }; | |
f21683ae | 73 | opp-150000000 { |
7a8a6588 MY |
74 | opp-hz = /bits/ 64 <150000000>; |
75 | clock-latency-ns = <300>; | |
76 | }; | |
f21683ae | 77 | opp-200000000 { |
7a8a6588 MY |
78 | opp-hz = /bits/ 64 <200000000>; |
79 | clock-latency-ns = <300>; | |
80 | }; | |
f21683ae | 81 | opp-300000000 { |
7a8a6588 MY |
82 | opp-hz = /bits/ 64 <300000000>; |
83 | clock-latency-ns = <300>; | |
84 | }; | |
f21683ae | 85 | opp-400000000 { |
7a8a6588 MY |
86 | opp-hz = /bits/ 64 <400000000>; |
87 | clock-latency-ns = <300>; | |
88 | }; | |
f21683ae | 89 | opp-600000000 { |
7a8a6588 MY |
90 | opp-hz = /bits/ 64 <600000000>; |
91 | clock-latency-ns = <300>; | |
92 | }; | |
f21683ae | 93 | opp-800000000 { |
7a8a6588 MY |
94 | opp-hz = /bits/ 64 <800000000>; |
95 | clock-latency-ns = <300>; | |
96 | }; | |
f21683ae | 97 | opp-1200000000 { |
7a8a6588 MY |
98 | opp-hz = /bits/ 64 <1200000000>; |
99 | clock-latency-ns = <300>; | |
a5e921b4 MY |
100 | }; |
101 | }; | |
102 | ||
2752bcaa MY |
103 | psci { |
104 | compatible = "arm,psci-0.2"; | |
105 | method = "smc"; | |
106 | }; | |
107 | ||
a5e921b4 | 108 | clocks { |
2752bcaa MY |
109 | refclk: ref { |
110 | compatible = "fixed-clock"; | |
111 | #clock-cells = <0>; | |
112 | clock-frequency = <25000000>; | |
113 | }; | |
114 | ||
1658b84d | 115 | arm_timer_clk: arm-timer { |
a5e921b4 MY |
116 | #clock-cells = <0>; |
117 | compatible = "fixed-clock"; | |
118 | clock-frequency = <50000000>; | |
119 | }; | |
a5e921b4 MY |
120 | }; |
121 | ||
fbd8d583 KH |
122 | thermal-zones { |
123 | cpu-thermal { | |
124 | polling-delay-passive = <250>; /* 250ms */ | |
125 | polling-delay = <1000>; /* 1000ms */ | |
126 | thermal-sensors = <&pvtctl>; | |
127 | ||
128 | trips { | |
129 | cpu_crit: cpu-crit { | |
130 | temperature = <95000>; /* 95C */ | |
131 | hysteresis = <2000>; | |
132 | type = "critical"; | |
133 | }; | |
134 | cpu_alert: cpu-alert { | |
135 | temperature = <85000>; /* 85C */ | |
136 | hysteresis = <2000>; | |
137 | type = "passive"; | |
138 | }; | |
139 | }; | |
140 | ||
141 | cooling-maps { | |
142 | map { | |
143 | trip = <&cpu_alert>; | |
144 | cooling-device = <&cpu0 | |
145 | THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
146 | }; | |
147 | }; | |
148 | }; | |
149 | }; | |
150 | ||
2752bcaa MY |
151 | soc { |
152 | compatible = "simple-bus"; | |
629b557a | 153 | #address-cells = <1>; |
2752bcaa MY |
154 | #size-cells = <1>; |
155 | ranges; | |
156 | interrupt-parent = <&intc>; | |
a5e921b4 | 157 | |
2752bcaa MY |
158 | l2: l2-cache@500c0000 { |
159 | compatible = "socionext,uniphier-system-cache"; | |
160 | reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, | |
161 | <0x506c0000 0x400>; | |
162 | interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; | |
163 | cache-unified; | |
164 | cache-size = <(1280 * 1024)>; | |
165 | cache-sets = <512>; | |
166 | cache-line-size = <128>; | |
167 | cache-level = <2>; | |
168 | }; | |
a5e921b4 | 169 | |
92fa4f4c KH |
170 | spi0: spi@54006000 { |
171 | compatible = "socionext,uniphier-scssi"; | |
172 | status = "disabled"; | |
173 | reg = <0x54006000 0x100>; | |
174 | interrupts = <0 39 4>; | |
175 | pinctrl-names = "default"; | |
176 | pinctrl-0 = <&pinctrl_spi0>; | |
177 | clocks = <&peri_clk 11>; | |
178 | resets = <&peri_rst 11>; | |
179 | }; | |
180 | ||
181 | spi1: spi@54006100 { | |
182 | compatible = "socionext,uniphier-scssi"; | |
183 | status = "disabled"; | |
184 | reg = <0x54006100 0x100>; | |
185 | interrupts = <0 216 4>; | |
186 | pinctrl-names = "default"; | |
187 | pinctrl-0 = <&pinctrl_spi1>; | |
188 | clocks = <&peri_clk 11>; | |
189 | resets = <&peri_rst 11>; | |
190 | }; | |
191 | ||
2752bcaa MY |
192 | serial0: serial@54006800 { |
193 | compatible = "socionext,uniphier-uart"; | |
194 | status = "disabled"; | |
195 | reg = <0x54006800 0x40>; | |
196 | interrupts = <0 33 4>; | |
197 | pinctrl-names = "default"; | |
198 | pinctrl-0 = <&pinctrl_uart0>; | |
199 | clocks = <&peri_clk 0>; | |
a1763a82 | 200 | resets = <&peri_rst 0>; |
2752bcaa | 201 | }; |
a5e921b4 | 202 | |
2752bcaa MY |
203 | serial1: serial@54006900 { |
204 | compatible = "socionext,uniphier-uart"; | |
205 | status = "disabled"; | |
206 | reg = <0x54006900 0x40>; | |
207 | interrupts = <0 35 4>; | |
208 | pinctrl-names = "default"; | |
209 | pinctrl-0 = <&pinctrl_uart1>; | |
210 | clocks = <&peri_clk 1>; | |
a1763a82 | 211 | resets = <&peri_rst 1>; |
2752bcaa | 212 | }; |
a5e921b4 | 213 | |
2752bcaa MY |
214 | serial2: serial@54006a00 { |
215 | compatible = "socionext,uniphier-uart"; | |
216 | status = "disabled"; | |
217 | reg = <0x54006a00 0x40>; | |
218 | interrupts = <0 37 4>; | |
219 | pinctrl-names = "default"; | |
220 | pinctrl-0 = <&pinctrl_uart2>; | |
221 | clocks = <&peri_clk 2>; | |
a1763a82 | 222 | resets = <&peri_rst 2>; |
2752bcaa | 223 | }; |
a5e921b4 | 224 | |
2752bcaa MY |
225 | serial3: serial@54006b00 { |
226 | compatible = "socionext,uniphier-uart"; | |
227 | status = "disabled"; | |
228 | reg = <0x54006b00 0x40>; | |
229 | interrupts = <0 177 4>; | |
230 | pinctrl-names = "default"; | |
231 | pinctrl-0 = <&pinctrl_uart3>; | |
232 | clocks = <&peri_clk 3>; | |
a1763a82 | 233 | resets = <&peri_rst 3>; |
2752bcaa | 234 | }; |
a5e921b4 | 235 | |
5d4bc4bd MY |
236 | gpio: gpio@55000000 { |
237 | compatible = "socionext,uniphier-gpio"; | |
238 | reg = <0x55000000 0x200>; | |
239 | interrupt-parent = <&aidet>; | |
240 | interrupt-controller; | |
241 | #interrupt-cells = <2>; | |
242 | gpio-controller; | |
243 | #gpio-cells = <2>; | |
244 | gpio-ranges = <&pinctrl 0 0 0>, | |
245 | <&pinctrl 96 0 0>; | |
246 | gpio-ranges-group-names = "gpio_range0", | |
247 | "gpio_range1"; | |
248 | ngpios = <232>; | |
249 | socionext,interrupt-ranges = <0 48 16>, <16 154 5>, | |
250 | <21 217 3>; | |
251 | }; | |
252 | ||
7f9f76b1 KS |
253 | audio@56000000 { |
254 | compatible = "socionext,uniphier-pxs2-aio"; | |
255 | reg = <0x56000000 0x80000>; | |
256 | interrupts = <0 144 4>; | |
257 | pinctrl-names = "default"; | |
258 | pinctrl-0 = <&pinctrl_ain1>, | |
259 | <&pinctrl_ain2>, | |
260 | <&pinctrl_ainiec1>, | |
261 | <&pinctrl_aout2>, | |
262 | <&pinctrl_aout3>, | |
263 | <&pinctrl_aoutiec1>, | |
264 | <&pinctrl_aoutiec2>; | |
265 | clock-names = "aio"; | |
266 | clocks = <&sys_clk 40>; | |
267 | reset-names = "aio"; | |
268 | resets = <&sys_rst 40>; | |
269 | #sound-dai-cells = <1>; | |
6f36ee0b | 270 | socionext,syscon = <&soc_glue>; |
7f9f76b1 KS |
271 | |
272 | i2s_port0: port@0 { | |
273 | i2s_hdmi: endpoint { | |
274 | }; | |
275 | }; | |
276 | ||
277 | i2s_port1: port@1 { | |
278 | i2s_line: endpoint { | |
279 | }; | |
280 | }; | |
281 | ||
282 | i2s_port2: port@2 { | |
283 | i2s_aux: endpoint { | |
284 | }; | |
285 | }; | |
286 | ||
287 | spdif_port0: port@3 { | |
288 | spdif_hiecout1: endpoint { | |
289 | }; | |
290 | }; | |
291 | ||
292 | spdif_port1: port@4 { | |
293 | spdif_iecout1: endpoint { | |
294 | }; | |
295 | }; | |
296 | ||
297 | comp_spdif_port0: port@5 { | |
298 | comp_spdif_hiecout1: endpoint { | |
299 | }; | |
300 | }; | |
301 | ||
302 | comp_spdif_port1: port@6 { | |
303 | comp_spdif_iecout1: endpoint { | |
304 | }; | |
305 | }; | |
306 | }; | |
307 | ||
2752bcaa MY |
308 | i2c0: i2c@58780000 { |
309 | compatible = "socionext,uniphier-fi2c"; | |
310 | status = "disabled"; | |
311 | reg = <0x58780000 0x80>; | |
312 | #address-cells = <1>; | |
313 | #size-cells = <0>; | |
314 | interrupts = <0 41 4>; | |
315 | pinctrl-names = "default"; | |
316 | pinctrl-0 = <&pinctrl_i2c0>; | |
317 | clocks = <&peri_clk 4>; | |
a1763a82 | 318 | resets = <&peri_rst 4>; |
2752bcaa MY |
319 | clock-frequency = <100000>; |
320 | }; | |
a5e921b4 | 321 | |
2752bcaa MY |
322 | i2c1: i2c@58781000 { |
323 | compatible = "socionext,uniphier-fi2c"; | |
324 | status = "disabled"; | |
325 | reg = <0x58781000 0x80>; | |
326 | #address-cells = <1>; | |
327 | #size-cells = <0>; | |
328 | interrupts = <0 42 4>; | |
329 | pinctrl-names = "default"; | |
330 | pinctrl-0 = <&pinctrl_i2c1>; | |
331 | clocks = <&peri_clk 5>; | |
a1763a82 | 332 | resets = <&peri_rst 5>; |
2752bcaa MY |
333 | clock-frequency = <100000>; |
334 | }; | |
61f838c7 | 335 | |
2752bcaa MY |
336 | i2c2: i2c@58782000 { |
337 | compatible = "socionext,uniphier-fi2c"; | |
338 | status = "disabled"; | |
339 | reg = <0x58782000 0x80>; | |
340 | #address-cells = <1>; | |
341 | #size-cells = <0>; | |
342 | interrupts = <0 43 4>; | |
343 | pinctrl-names = "default"; | |
344 | pinctrl-0 = <&pinctrl_i2c2>; | |
345 | clocks = <&peri_clk 6>; | |
a1763a82 | 346 | resets = <&peri_rst 6>; |
2752bcaa MY |
347 | clock-frequency = <100000>; |
348 | }; | |
ad0561d4 | 349 | |
2752bcaa MY |
350 | i2c3: i2c@58783000 { |
351 | compatible = "socionext,uniphier-fi2c"; | |
352 | status = "disabled"; | |
353 | reg = <0x58783000 0x80>; | |
354 | #address-cells = <1>; | |
355 | #size-cells = <0>; | |
356 | interrupts = <0 44 4>; | |
357 | pinctrl-names = "default"; | |
358 | pinctrl-0 = <&pinctrl_i2c3>; | |
359 | clocks = <&peri_clk 7>; | |
a1763a82 | 360 | resets = <&peri_rst 7>; |
2752bcaa MY |
361 | clock-frequency = <100000>; |
362 | }; | |
ad0561d4 | 363 | |
2752bcaa MY |
364 | /* chip-internal connection for DMD */ |
365 | i2c4: i2c@58784000 { | |
366 | compatible = "socionext,uniphier-fi2c"; | |
367 | reg = <0x58784000 0x80>; | |
368 | #address-cells = <1>; | |
369 | #size-cells = <0>; | |
370 | interrupts = <0 45 4>; | |
371 | clocks = <&peri_clk 8>; | |
a1763a82 | 372 | resets = <&peri_rst 8>; |
2752bcaa MY |
373 | clock-frequency = <400000>; |
374 | }; | |
ad0561d4 | 375 | |
2752bcaa MY |
376 | /* chip-internal connection for STM */ |
377 | i2c5: i2c@58785000 { | |
378 | compatible = "socionext,uniphier-fi2c"; | |
379 | reg = <0x58785000 0x80>; | |
380 | #address-cells = <1>; | |
381 | #size-cells = <0>; | |
382 | interrupts = <0 25 4>; | |
383 | clocks = <&peri_clk 9>; | |
a1763a82 | 384 | resets = <&peri_rst 9>; |
2752bcaa MY |
385 | clock-frequency = <400000>; |
386 | }; | |
ad0561d4 | 387 | |
2752bcaa MY |
388 | /* chip-internal connection for HDMI */ |
389 | i2c6: i2c@58786000 { | |
390 | compatible = "socionext,uniphier-fi2c"; | |
391 | reg = <0x58786000 0x80>; | |
392 | #address-cells = <1>; | |
393 | #size-cells = <0>; | |
394 | interrupts = <0 26 4>; | |
395 | clocks = <&peri_clk 10>; | |
a1763a82 | 396 | resets = <&peri_rst 10>; |
2752bcaa MY |
397 | clock-frequency = <400000>; |
398 | }; | |
ad0561d4 | 399 | |
2752bcaa MY |
400 | system_bus: system-bus@58c00000 { |
401 | compatible = "socionext,uniphier-system-bus"; | |
402 | status = "disabled"; | |
403 | reg = <0x58c00000 0x400>; | |
404 | #address-cells = <2>; | |
405 | #size-cells = <1>; | |
406 | pinctrl-names = "default"; | |
407 | pinctrl-0 = <&pinctrl_system_bus>; | |
408 | }; | |
409 | ||
18088678 | 410 | smpctrl@59801000 { |
2752bcaa MY |
411 | compatible = "socionext,uniphier-smpctrl"; |
412 | reg = <0x59801000 0x400>; | |
413 | }; | |
414 | ||
415 | sdctrl@59810000 { | |
416 | compatible = "socionext,uniphier-pxs2-sdctrl", | |
417 | "simple-mfd", "syscon"; | |
7b8330d2 | 418 | reg = <0x59810000 0x400>; |
2752bcaa MY |
419 | |
420 | sd_clk: clock { | |
421 | compatible = "socionext,uniphier-pxs2-sd-clock"; | |
422 | #clock-cells = <1>; | |
423 | }; | |
424 | ||
425 | sd_rst: reset { | |
426 | compatible = "socionext,uniphier-pxs2-sd-reset"; | |
427 | #reset-cells = <1>; | |
428 | }; | |
429 | }; | |
ad0561d4 | 430 | |
2752bcaa MY |
431 | perictrl@59820000 { |
432 | compatible = "socionext,uniphier-pxs2-perictrl", | |
433 | "simple-mfd", "syscon"; | |
434 | reg = <0x59820000 0x200>; | |
435 | ||
436 | peri_clk: clock { | |
437 | compatible = "socionext,uniphier-pxs2-peri-clock"; | |
438 | #clock-cells = <1>; | |
439 | }; | |
440 | ||
441 | peri_rst: reset { | |
442 | compatible = "socionext,uniphier-pxs2-peri-reset"; | |
443 | #reset-cells = <1>; | |
444 | }; | |
445 | }; | |
446 | ||
6f36ee0b | 447 | soc_glue: soc-glue@5f800000 { |
2752bcaa MY |
448 | compatible = "socionext,uniphier-pxs2-soc-glue", |
449 | "simple-mfd", "syscon"; | |
450 | reg = <0x5f800000 0x2000>; | |
451 | ||
452 | pinctrl: pinctrl { | |
453 | compatible = "socionext,uniphier-pxs2-pinctrl"; | |
454 | }; | |
455 | }; | |
456 | ||
6b968186 KH |
457 | soc-glue@5f900000 { |
458 | compatible = "socionext,uniphier-pxs2-soc-glue-debug", | |
459 | "simple-mfd"; | |
460 | #address-cells = <1>; | |
461 | #size-cells = <1>; | |
462 | ranges = <0 0x5f900000 0x2000>; | |
463 | ||
464 | efuse@100 { | |
465 | compatible = "socionext,uniphier-efuse"; | |
466 | reg = <0x100 0x28>; | |
467 | }; | |
468 | ||
469 | efuse@200 { | |
470 | compatible = "socionext,uniphier-efuse"; | |
471 | reg = <0x200 0x58>; | |
472 | }; | |
473 | }; | |
474 | ||
80a68704 MY |
475 | aidet: aidet@5fc20000 { |
476 | compatible = "socionext,uniphier-pxs2-aidet"; | |
477 | reg = <0x5fc20000 0x200>; | |
478 | interrupt-controller; | |
479 | #interrupt-cells = <2>; | |
480 | }; | |
481 | ||
2752bcaa MY |
482 | timer@60000200 { |
483 | compatible = "arm,cortex-a9-global-timer"; | |
484 | reg = <0x60000200 0x20>; | |
485 | interrupts = <1 11 0xf04>; | |
486 | clocks = <&arm_timer_clk>; | |
487 | }; | |
488 | ||
489 | timer@60000600 { | |
490 | compatible = "arm,cortex-a9-twd-timer"; | |
491 | reg = <0x60000600 0x20>; | |
492 | interrupts = <1 13 0xf04>; | |
493 | clocks = <&arm_timer_clk>; | |
494 | }; | |
495 | ||
496 | intc: interrupt-controller@60001000 { | |
497 | compatible = "arm,cortex-a9-gic"; | |
498 | reg = <0x60001000 0x1000>, | |
499 | <0x60000100 0x100>; | |
500 | #interrupt-cells = <3>; | |
501 | interrupt-controller; | |
502 | }; | |
503 | ||
504 | sysctrl@61840000 { | |
505 | compatible = "socionext,uniphier-pxs2-sysctrl", | |
506 | "simple-mfd", "syscon"; | |
507 | reg = <0x61840000 0x10000>; | |
508 | ||
509 | sys_clk: clock { | |
510 | compatible = "socionext,uniphier-pxs2-clock"; | |
511 | #clock-cells = <1>; | |
512 | }; | |
513 | ||
514 | sys_rst: reset { | |
515 | compatible = "socionext,uniphier-pxs2-reset"; | |
516 | #reset-cells = <1>; | |
517 | }; | |
fbd8d583 KH |
518 | |
519 | pvtctl: pvtctl { | |
520 | compatible = "socionext,uniphier-pxs2-thermal"; | |
521 | interrupts = <0 3 4>; | |
522 | #thermal-sensor-cells = <0>; | |
523 | socionext,tmod-calibration = <0x0f86 0x6844>; | |
524 | }; | |
2752bcaa | 525 | }; |
69f9cdc6 | 526 | |
e3cc9319 KH |
527 | eth: ethernet@65000000 { |
528 | compatible = "socionext,uniphier-pxs2-ave4"; | |
529 | status = "disabled"; | |
530 | reg = <0x65000000 0x8500>; | |
531 | interrupts = <0 66 4>; | |
532 | pinctrl-names = "default"; | |
533 | pinctrl-0 = <&pinctrl_ether_rgmii>; | |
92724c03 | 534 | clock-names = "ether"; |
e3cc9319 | 535 | clocks = <&sys_clk 6>; |
92724c03 | 536 | reset-names = "ether"; |
e3cc9319 KH |
537 | resets = <&sys_rst 6>; |
538 | phy-mode = "rgmii"; | |
539 | local-mac-address = [00 00 00 00 00 00]; | |
526f872b | 540 | socionext,syscon-phy-mode = <&soc_glue 0>; |
e3cc9319 KH |
541 | |
542 | mdio: mdio { | |
543 | #address-cells = <1>; | |
544 | #size-cells = <0>; | |
545 | }; | |
546 | }; | |
547 | ||
69f9cdc6 MY |
548 | nand: nand@68000000 { |
549 | compatible = "socionext,uniphier-denali-nand-v5b"; | |
550 | status = "disabled"; | |
551 | reg-names = "nand_data", "denali_reg"; | |
552 | reg = <0x68000000 0x20>, <0x68100000 0x1000>; | |
553 | interrupts = <0 65 4>; | |
554 | pinctrl-names = "default"; | |
555 | pinctrl-0 = <&pinctrl_nand2cs>; | |
007a9389 MY |
556 | clock-names = "nand", "nand_x", "ecc"; |
557 | clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; | |
a1763a82 | 558 | resets = <&sys_rst 2>; |
69f9cdc6 | 559 | }; |
2752bcaa | 560 | }; |
ad0561d4 | 561 | }; |
2752bcaa | 562 | |
ed8bc76b | 563 | #include "uniphier-pinctrl.dtsi" |