Commit | Line | Data |
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a5e921b4 | 1 | /* |
77896e4d | 2 | * Device Tree Source for UniPhier PXs2 SoC |
a5e921b4 | 3 | * |
77896e4d MY |
4 | * Copyright (C) 2015-2016 Socionext Inc. |
5 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
a5e921b4 MY |
6 | * |
7 | * This file is dual-licensed: you can use it either under the terms | |
8 | * of the GPL or the X11 license, at your option. Note that this dual | |
9 | * licensing only applies to this file, and not this project as a | |
10 | * whole. | |
11 | * | |
12 | * a) This file is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of the | |
15 | * License, or (at your option) any later version. | |
16 | * | |
17 | * This file is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * Or, alternatively, | |
23 | * | |
24 | * b) Permission is hereby granted, free of charge, to any person | |
25 | * obtaining a copy of this software and associated documentation | |
26 | * files (the "Software"), to deal in the Software without | |
27 | * restriction, including without limitation the rights to use, | |
28 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
29 | * sell copies of the Software, and to permit persons to whom the | |
30 | * Software is furnished to do so, subject to the following | |
31 | * conditions: | |
32 | * | |
33 | * The above copyright notice and this permission notice shall be | |
34 | * included in all copies or substantial portions of the Software. | |
35 | * | |
36 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
37 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
38 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
39 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
40 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
41 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
42 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
43 | * OTHER DEALINGS IN THE SOFTWARE. | |
44 | */ | |
45 | ||
629b557a | 46 | /include/ "uniphier-common32.dtsi" |
a5e921b4 MY |
47 | |
48 | / { | |
77896e4d | 49 | compatible = "socionext,uniphier-pxs2"; |
a5e921b4 MY |
50 | |
51 | cpus { | |
52 | #address-cells = <1>; | |
53 | #size-cells = <0>; | |
54 | enable-method = "socionext,uniphier-smp"; | |
55 | ||
56 | cpu@0 { | |
57 | device_type = "cpu"; | |
58 | compatible = "arm,cortex-a9"; | |
59 | reg = <0>; | |
7c62f299 | 60 | next-level-cache = <&l2>; |
a5e921b4 MY |
61 | }; |
62 | ||
63 | cpu@1 { | |
64 | device_type = "cpu"; | |
65 | compatible = "arm,cortex-a9"; | |
66 | reg = <1>; | |
7c62f299 | 67 | next-level-cache = <&l2>; |
a5e921b4 MY |
68 | }; |
69 | ||
70 | cpu@2 { | |
71 | device_type = "cpu"; | |
72 | compatible = "arm,cortex-a9"; | |
73 | reg = <2>; | |
7c62f299 | 74 | next-level-cache = <&l2>; |
a5e921b4 MY |
75 | }; |
76 | ||
77 | cpu@3 { | |
78 | device_type = "cpu"; | |
79 | compatible = "arm,cortex-a9"; | |
80 | reg = <3>; | |
7c62f299 | 81 | next-level-cache = <&l2>; |
a5e921b4 MY |
82 | }; |
83 | }; | |
84 | ||
85 | clocks { | |
86 | arm_timer_clk: arm_timer_clk { | |
87 | #clock-cells = <0>; | |
88 | compatible = "fixed-clock"; | |
89 | clock-frequency = <50000000>; | |
90 | }; | |
91 | ||
92 | uart_clk: uart_clk { | |
93 | #clock-cells = <0>; | |
94 | compatible = "fixed-clock"; | |
95 | clock-frequency = <88900000>; | |
96 | }; | |
97 | ||
98 | i2c_clk: i2c_clk { | |
99 | #clock-cells = <0>; | |
100 | compatible = "fixed-clock"; | |
101 | clock-frequency = <50000000>; | |
102 | }; | |
103 | }; | |
629b557a | 104 | }; |
a5e921b4 | 105 | |
629b557a MY |
106 | &soc { |
107 | l2: l2-cache@500c0000 { | |
108 | compatible = "socionext,uniphier-system-cache"; | |
109 | reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; | |
110 | interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; | |
111 | cache-unified; | |
112 | cache-size = <(1280 * 1024)>; | |
113 | cache-sets = <512>; | |
114 | cache-line-size = <128>; | |
115 | cache-level = <2>; | |
116 | }; | |
a5e921b4 | 117 | |
629b557a MY |
118 | i2c0: i2c@58780000 { |
119 | compatible = "socionext,uniphier-fi2c"; | |
120 | status = "disabled"; | |
121 | reg = <0x58780000 0x80>; | |
122 | #address-cells = <1>; | |
123 | #size-cells = <0>; | |
124 | interrupts = <0 41 4>; | |
125 | pinctrl-names = "default"; | |
126 | pinctrl-0 = <&pinctrl_i2c0>; | |
127 | clocks = <&i2c_clk>; | |
128 | clock-frequency = <100000>; | |
129 | }; | |
a5e921b4 | 130 | |
629b557a MY |
131 | i2c1: i2c@58781000 { |
132 | compatible = "socionext,uniphier-fi2c"; | |
133 | status = "disabled"; | |
134 | reg = <0x58781000 0x80>; | |
135 | #address-cells = <1>; | |
136 | #size-cells = <0>; | |
137 | interrupts = <0 42 4>; | |
138 | pinctrl-names = "default"; | |
139 | pinctrl-0 = <&pinctrl_i2c1>; | |
140 | clocks = <&i2c_clk>; | |
141 | clock-frequency = <100000>; | |
142 | }; | |
a5e921b4 | 143 | |
629b557a MY |
144 | i2c2: i2c@58782000 { |
145 | compatible = "socionext,uniphier-fi2c"; | |
146 | status = "disabled"; | |
147 | reg = <0x58782000 0x80>; | |
148 | #address-cells = <1>; | |
149 | #size-cells = <0>; | |
150 | pinctrl-names = "default"; | |
151 | pinctrl-0 = <&pinctrl_i2c2>; | |
152 | interrupts = <0 43 4>; | |
153 | clocks = <&i2c_clk>; | |
154 | clock-frequency = <100000>; | |
155 | }; | |
a5e921b4 | 156 | |
629b557a MY |
157 | i2c3: i2c@58783000 { |
158 | compatible = "socionext,uniphier-fi2c"; | |
159 | status = "disabled"; | |
160 | reg = <0x58783000 0x80>; | |
161 | #address-cells = <1>; | |
162 | #size-cells = <0>; | |
163 | interrupts = <0 44 4>; | |
164 | pinctrl-names = "default"; | |
165 | pinctrl-0 = <&pinctrl_i2c3>; | |
166 | clocks = <&i2c_clk>; | |
167 | clock-frequency = <100000>; | |
168 | }; | |
a5e921b4 | 169 | |
629b557a MY |
170 | /* chip-internal connection for DMD */ |
171 | i2c4: i2c@58784000 { | |
172 | compatible = "socionext,uniphier-fi2c"; | |
173 | reg = <0x58784000 0x80>; | |
174 | #address-cells = <1>; | |
175 | #size-cells = <0>; | |
176 | interrupts = <0 45 4>; | |
177 | clocks = <&i2c_clk>; | |
178 | clock-frequency = <400000>; | |
179 | }; | |
a5e921b4 | 180 | |
629b557a MY |
181 | /* chip-internal connection for STM */ |
182 | i2c5: i2c@58785000 { | |
183 | compatible = "socionext,uniphier-fi2c"; | |
184 | reg = <0x58785000 0x80>; | |
185 | #address-cells = <1>; | |
186 | #size-cells = <0>; | |
187 | interrupts = <0 25 4>; | |
188 | clocks = <&i2c_clk>; | |
189 | clock-frequency = <400000>; | |
190 | }; | |
a5e921b4 | 191 | |
629b557a MY |
192 | /* chip-internal connection for HDMI */ |
193 | i2c6: i2c@58786000 { | |
194 | compatible = "socionext,uniphier-fi2c"; | |
195 | reg = <0x58786000 0x80>; | |
196 | #address-cells = <1>; | |
197 | #size-cells = <0>; | |
198 | interrupts = <0 26 4>; | |
199 | clocks = <&i2c_clk>; | |
200 | clock-frequency = <400000>; | |
a5e921b4 MY |
201 | }; |
202 | }; | |
203 | ||
61f838c7 MY |
204 | &refclk { |
205 | clock-frequency = <25000000>; | |
206 | }; | |
207 | ||
629b557a | 208 | &pinctrl { |
ebe161d3 | 209 | compatible = "socionext,uniphier-pxs2-pinctrl"; |
629b557a | 210 | }; |