[linux-2.6-block.git] / arch / arm / boot / dts / uniphier-pxs2.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR MIT
//
// Device Tree Source for UniPhier PXs2 SoC
//
// Copyright (C) 2015-2016 Socionext Inc.
//   Author: Masahiro Yamada <yamada.masahiro@socionext.com>

#include <dt-bindings/gpio/uniphier-gpio.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "socionext,uniphier-pxs2";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			operating-points-v2 = <&cpu_opp>;
			#cooling-cells = <2>;
		};
	};

	cpu_opp: opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			clock-latency-ns = <300>;
		};
		opp-150000000 {
			opp-hz = /bits/ 64 <150000000>;
			clock-latency-ns = <300>;
		};
		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
			clock-latency-ns = <300>;
		};
		opp-300000000 {
			opp-hz = /bits/ 64 <300000000>;
			clock-latency-ns = <300>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
			clock-latency-ns = <300>;
		};
		opp-600000000 {
			opp-hz = /bits/ 64 <600000000>;
			clock-latency-ns = <300>;
		};
		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			clock-latency-ns = <300>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			clock-latency-ns = <300>;
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};

		arm_timer_clk: arm-timer {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;	/* 250ms */
			polling-delay = <1000>;		/* 1000ms */
			thermal-sensors = <&pvtctl>;

			trips {
				cpu_crit: cpu-crit {
					temperature = <95000>;	/* 95C */
					hysteresis = <2000>;
					type = "critical";
				};
				cpu_alert: cpu-alert {
					temperature = <85000>;	/* 85C */
					hysteresis = <2000>;
					type = "passive";
				};
			};

			cooling-maps {
				map {
					trip = <&cpu_alert>;
					cooling-device = <&cpu0
					    THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		l2: l2-cache@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
			      <0x506c0000 0x400>;
			interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
			cache-unified;
			cache-size = <(1280 * 1024)>;
			cache-sets = <512>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
			resets = <&peri_rst 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
			resets = <&peri_rst 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
			resets = <&peri_rst 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
			resets = <&peri_rst 3>;
		};

		gpio: gpio@55000000 {
			compatible = "socionext,uniphier-gpio";
			reg = <0x55000000 0x200>;
			interrupt-parent = <&aidet>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 0>,
				      <&pinctrl 96 0 0>;
			gpio-ranges-group-names = "gpio_range0",
						  "gpio_range1";
			ngpios = <232>;
			socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
						     <21 217 3>;
		};

		audio@56000000 {
			compatible = "socionext,uniphier-pxs2-aio";
			reg = <0x56000000 0x80000>;
			interrupts = <0 144 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_ain1>,
				    <&pinctrl_ain2>,
				    <&pinctrl_ainiec1>,
				    <&pinctrl_aout2>,
				    <&pinctrl_aout3>,
				    <&pinctrl_aoutiec1>,
				    <&pinctrl_aoutiec2>;
			clock-names = "aio";
			clocks = <&sys_clk 40>;
			reset-names = "aio";
			resets = <&sys_rst 40>;
			#sound-dai-cells = <1>;
			socionext,syscon = <&soc_glue>;

			i2s_port0: port@0 {
				i2s_hdmi: endpoint {
				};
			};

			i2s_port1: port@1 {
				i2s_line: endpoint {
				};
			};

			i2s_port2: port@2 {
				i2s_aux: endpoint {
				};
			};

			spdif_port0: port@3 {
				spdif_hiecout1: endpoint {
				};
			};

			spdif_port1: port@4 {
				spdif_iecout1: endpoint {
				};
			};

			comp_spdif_port0: port@5 {
				comp_spdif_hiecout1: endpoint {
				};
			};

			comp_spdif_port1: port@6 {
				comp_spdif_iecout1: endpoint {
				};
			};
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			resets = <&peri_rst 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			resets = <&peri_rst 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c2>;
			clocks = <&peri_clk 6>;
			resets = <&peri_rst 6>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			resets = <&peri_rst 7>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c4: i2c@58784000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58784000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 4>;
			clocks = <&peri_clk 8>;
			resets = <&peri_rst 8>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for STM */
		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 25 4>;
			clocks = <&peri_clk 9>;
			resets = <&peri_rst 9>;
			clock-frequency = <400000>;
		};

		/* chip-internal connection for HDMI */
		i2c6: i2c@58786000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58786000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 26 4>;
			clocks = <&peri_clk 10>;
			resets = <&peri_rst 10>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		sdctrl@59810000 {
			compatible = "socionext,uniphier-pxs2-sdctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x400>;

			sd_clk: clock {
				compatible = "socionext,uniphier-pxs2-sd-clock";
				#clock-cells = <1>;
			};

			sd_rst: reset {
				compatible = "socionext,uniphier-pxs2-sd-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-pxs2-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-pxs2-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-pxs2-peri-reset";
				#reset-cells = <1>;
			};
		};

		soc_glue: soc-glue@5f800000 {
			compatible = "socionext,uniphier-pxs2-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-pxs2-pinctrl";
			};
		};

		soc-glue@5f900000 {
			compatible = "socionext,uniphier-pxs2-soc-glue-debug",
				     "simple-mfd";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x5f900000 0x2000>;

			efuse@100 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x100 0x28>;
			};

			efuse@200 {
				compatible = "socionext,uniphier-efuse";
				reg = <0x200 0x58>;
			};
		};

		aidet: aidet@5fc20000 {
			compatible = "socionext,uniphier-pxs2-aidet";
			reg = <0x5fc20000 0x200>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		timer@60000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x60000200 0x20>;
			interrupts = <1 11 0xf04>;
			clocks = <&arm_timer_clk>;
		};

		timer@60000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x60000600 0x20>;
			interrupts = <1 13 0xf04>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@60001000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0x60001000 0x1000>,
			      <0x60000100 0x100>;
			#interrupt-cells = <3>;
			interrupt-controller;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-pxs2-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-pxs2-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-pxs2-reset";
				#reset-cells = <1>;
			};

			pvtctl: pvtctl {
				compatible = "socionext,uniphier-pxs2-thermal";
				interrupts = <0 3 4>;
				#thermal-sensor-cells = <0>;
				socionext,tmod-calibration = <0x0f86 0x6844>;
			};
		};

		eth: ethernet@65000000 {
			compatible = "socionext,uniphier-pxs2-ave4";
			status = "disabled";
			reg = <0x65000000 0x8500>;
			interrupts = <0 66 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_ether_rgmii>;
			clock-names = "ether";
			clocks = <&sys_clk 6>;
			reset-names = "ether";
			resets = <&sys_rst 6>;
			phy-mode = "rgmii";
			local-mac-address = [00 00 00 00 00 00];
			socionext,syscon-phy-mode = <&soc_glue 0>;

			mdio: mdio {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		nand: nand@68000000 {
			compatible = "socionext,uniphier-denali-nand-v5b";
			status = "disabled";
			reg-names = "nand_data", "denali_reg";
			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
			interrupts = <0 65 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand2cs>;
			clocks = <&sys_clk 2>;
			resets = <&sys_rst 2>;
		};
	};
};

#include "uniphier-pinctrl.dtsi"
Commit	Line	Data
ea566a4b MY	1	// SPDX-License-Identifier: GPL-2.0+ OR MIT
	2	//
	3	// Device Tree Source for UniPhier PXs2 SoC
	4	//
	5	// Copyright (C) 2015-2016 Socionext Inc.
	6	// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
a5e921b4	7
d1194d49	8	#include <dt-bindings/gpio/uniphier-gpio.h>
fbd8d583 KH	9	#include <dt-bindings/thermal/thermal.h>
fbd8d583 KH	10
a5e921b4	11	/ {
77896e4d	12	compatible = "socionext,uniphier-pxs2";
8e2b908b MY	13	#address-cells = <1>;
8e2b908b MY	14	#size-cells = <1>;
a5e921b4 MY	15
	16	cpus {
	17	#address-cells = <1>;
	18	#size-cells = <0>;
a5e921b4	19
fbd8d583	20	cpu0: cpu@0 {
a5e921b4 MY	21	device_type = "cpu";
	22	compatible = "arm,cortex-a9";
	23	reg = <0>;
7a8a6588	24	clocks = <&sys_clk 32>;
3bdba5ac	25	enable-method = "psci";
7c62f299	26	next-level-cache = <&l2>;
7a8a6588	27	operating-points-v2 = <&cpu_opp>;
fbd8d583	28	#cooling-cells = <2>;
a5e921b4 MY	29	};
a5e921b4 MY	30
fbd8d583	31	cpu1: cpu@1 {
a5e921b4 MY	32	device_type = "cpu";
	33	compatible = "arm,cortex-a9";
	34	reg = <1>;
7a8a6588	35	clocks = <&sys_clk 32>;
3bdba5ac	36	enable-method = "psci";
7c62f299	37	next-level-cache = <&l2>;
7a8a6588	38	operating-points-v2 = <&cpu_opp>;
38dc27c8	39	#cooling-cells = <2>;
a5e921b4 MY	40	};
a5e921b4 MY	41
fbd8d583	42	cpu2: cpu@2 {
a5e921b4 MY	43	device_type = "cpu";
	44	compatible = "arm,cortex-a9";
	45	reg = <2>;
7a8a6588	46	clocks = <&sys_clk 32>;
3bdba5ac	47	enable-method = "psci";
7c62f299	48	next-level-cache = <&l2>;
7a8a6588	49	operating-points-v2 = <&cpu_opp>;
38dc27c8	50	#cooling-cells = <2>;
a5e921b4 MY	51	};
a5e921b4 MY	52
fbd8d583	53	cpu3: cpu@3 {
a5e921b4 MY	54	device_type = "cpu";
	55	compatible = "arm,cortex-a9";
	56	reg = <3>;
7a8a6588	57	clocks = <&sys_clk 32>;
3bdba5ac	58	enable-method = "psci";
7c62f299	59	next-level-cache = <&l2>;
7a8a6588	60	operating-points-v2 = <&cpu_opp>;
38dc27c8	61	#cooling-cells = <2>;
7a8a6588 MY	62	};
	63	};
	64
1658b84d	65	cpu_opp: opp-table {
7a8a6588 MY	66	compatible = "operating-points-v2";
	67	opp-shared;
	68
f21683ae	69	opp-100000000 {
7a8a6588 MY	70	opp-hz = /bits/ 64 <100000000>;
	71	clock-latency-ns = <300>;
	72	};
f21683ae	73	opp-150000000 {
7a8a6588 MY	74	opp-hz = /bits/ 64 <150000000>;
	75	clock-latency-ns = <300>;
	76	};
f21683ae	77	opp-200000000 {
7a8a6588 MY	78	opp-hz = /bits/ 64 <200000000>;
	79	clock-latency-ns = <300>;
	80	};
f21683ae	81	opp-300000000 {
7a8a6588 MY	82	opp-hz = /bits/ 64 <300000000>;
	83	clock-latency-ns = <300>;
	84	};
f21683ae	85	opp-400000000 {
7a8a6588 MY	86	opp-hz = /bits/ 64 <400000000>;
	87	clock-latency-ns = <300>;
	88	};
f21683ae	89	opp-600000000 {
7a8a6588 MY	90	opp-hz = /bits/ 64 <600000000>;
	91	clock-latency-ns = <300>;
	92	};
f21683ae	93	opp-800000000 {
7a8a6588 MY	94	opp-hz = /bits/ 64 <800000000>;
	95	clock-latency-ns = <300>;
	96	};
f21683ae	97	opp-1200000000 {
7a8a6588 MY	98	opp-hz = /bits/ 64 <1200000000>;
7a8a6588 MY	99	clock-latency-ns = <300>;
a5e921b4 MY	100	};
	101	};
	102
2752bcaa MY	103	psci {
	104	compatible = "arm,psci-0.2";
	105	method = "smc";
	106	};
	107
a5e921b4	108	clocks {
2752bcaa MY	109	refclk: ref {
	110	compatible = "fixed-clock";
	111	#clock-cells = <0>;
	112	clock-frequency = <25000000>;
	113	};
	114
1658b84d	115	arm_timer_clk: arm-timer {
a5e921b4 MY	116	#clock-cells = <0>;
	117	compatible = "fixed-clock";
	118	clock-frequency = <50000000>;
	119	};
a5e921b4 MY	120	};
a5e921b4 MY	121
fbd8d583 KH	122	thermal-zones {
	123	cpu-thermal {
	124	polling-delay-passive = <250>; /* 250ms */
	125	polling-delay = <1000>; /* 1000ms */
	126	thermal-sensors = <&pvtctl>;
	127
	128	trips {
	129	cpu_crit: cpu-crit {
	130	temperature = <95000>; /* 95C */
	131	hysteresis = <2000>;
	132	type = "critical";
	133	};
	134	cpu_alert: cpu-alert {
	135	temperature = <85000>; /* 85C */
	136	hysteresis = <2000>;
	137	type = "passive";
	138	};
	139	};
	140
	141	cooling-maps {
	142	map {
	143	trip = <&cpu_alert>;
	144	cooling-device = <&cpu0
	145	THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	146	};
	147	};
	148	};
	149	};
	150
2752bcaa MY	151	soc {
2752bcaa MY	152	compatible = "simple-bus";
629b557a	153	#address-cells = <1>;
2752bcaa MY	154	#size-cells = <1>;
	155	ranges;
	156	interrupt-parent = <&intc>;
a5e921b4	157
2752bcaa MY	158	l2: l2-cache@500c0000 {
	159	compatible = "socionext,uniphier-system-cache";
	160	reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
	161	<0x506c0000 0x400>;
	162	interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
	163	cache-unified;
	164	cache-size = <(1280 * 1024)>;
	165	cache-sets = <512>;
	166	cache-line-size = <128>;
	167	cache-level = <2>;
	168	};
a5e921b4	169
2752bcaa MY	170	serial0: serial@54006800 {
	171	compatible = "socionext,uniphier-uart";
	172	status = "disabled";
	173	reg = <0x54006800 0x40>;
	174	interrupts = <0 33 4>;
	175	pinctrl-names = "default";
	176	pinctrl-0 = <&pinctrl_uart0>;
	177	clocks = <&peri_clk 0>;
a1763a82	178	resets = <&peri_rst 0>;
2752bcaa	179	};
a5e921b4	180
2752bcaa MY	181	serial1: serial@54006900 {
	182	compatible = "socionext,uniphier-uart";
	183	status = "disabled";
	184	reg = <0x54006900 0x40>;
	185	interrupts = <0 35 4>;
	186	pinctrl-names = "default";
	187	pinctrl-0 = <&pinctrl_uart1>;
	188	clocks = <&peri_clk 1>;
a1763a82	189	resets = <&peri_rst 1>;
2752bcaa	190	};
a5e921b4	191
2752bcaa MY	192	serial2: serial@54006a00 {
	193	compatible = "socionext,uniphier-uart";
	194	status = "disabled";
	195	reg = <0x54006a00 0x40>;
	196	interrupts = <0 37 4>;
	197	pinctrl-names = "default";
	198	pinctrl-0 = <&pinctrl_uart2>;
	199	clocks = <&peri_clk 2>;
a1763a82	200	resets = <&peri_rst 2>;
2752bcaa	201	};
a5e921b4	202
2752bcaa MY	203	serial3: serial@54006b00 {
	204	compatible = "socionext,uniphier-uart";
	205	status = "disabled";
	206	reg = <0x54006b00 0x40>;
	207	interrupts = <0 177 4>;
	208	pinctrl-names = "default";
	209	pinctrl-0 = <&pinctrl_uart3>;
	210	clocks = <&peri_clk 3>;
a1763a82	211	resets = <&peri_rst 3>;
2752bcaa	212	};
a5e921b4	213
5d4bc4bd MY	214	gpio: gpio@55000000 {
	215	compatible = "socionext,uniphier-gpio";
	216	reg = <0x55000000 0x200>;
	217	interrupt-parent = <&aidet>;
	218	interrupt-controller;
	219	#interrupt-cells = <2>;
	220	gpio-controller;
	221	#gpio-cells = <2>;
	222	gpio-ranges = <&pinctrl 0 0 0>,
	223	<&pinctrl 96 0 0>;
	224	gpio-ranges-group-names = "gpio_range0",
	225	"gpio_range1";
	226	ngpios = <232>;
	227	socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
	228	<21 217 3>;
	229	};
	230
7f9f76b1 KS	231	audio@56000000 {
	232	compatible = "socionext,uniphier-pxs2-aio";
	233	reg = <0x56000000 0x80000>;
	234	interrupts = <0 144 4>;
	235	pinctrl-names = "default";
	236	pinctrl-0 = <&pinctrl_ain1>,
	237	<&pinctrl_ain2>,
	238	<&pinctrl_ainiec1>,
	239	<&pinctrl_aout2>,
	240	<&pinctrl_aout3>,
	241	<&pinctrl_aoutiec1>,
	242	<&pinctrl_aoutiec2>;
	243	clock-names = "aio";
	244	clocks = <&sys_clk 40>;
	245	reset-names = "aio";
	246	resets = <&sys_rst 40>;
	247	#sound-dai-cells = <1>;
6f36ee0b	248	socionext,syscon = <&soc_glue>;
7f9f76b1 KS	249
	250	i2s_port0: port@0 {
	251	i2s_hdmi: endpoint {
	252	};
	253	};
	254
	255	i2s_port1: port@1 {
	256	i2s_line: endpoint {
	257	};
	258	};
	259
	260	i2s_port2: port@2 {
	261	i2s_aux: endpoint {
	262	};
	263	};
	264
	265	spdif_port0: port@3 {
	266	spdif_hiecout1: endpoint {
	267	};
	268	};
	269
	270	spdif_port1: port@4 {
	271	spdif_iecout1: endpoint {
	272	};
	273	};
	274
	275	comp_spdif_port0: port@5 {
	276	comp_spdif_hiecout1: endpoint {
	277	};
	278	};
	279
	280	comp_spdif_port1: port@6 {
	281	comp_spdif_iecout1: endpoint {
	282	};
	283	};
	284	};
	285
2752bcaa MY	286	i2c0: i2c@58780000 {
	287	compatible = "socionext,uniphier-fi2c";
	288	status = "disabled";
	289	reg = <0x58780000 0x80>;
	290	#address-cells = <1>;
	291	#size-cells = <0>;
	292	interrupts = <0 41 4>;
	293	pinctrl-names = "default";
	294	pinctrl-0 = <&pinctrl_i2c0>;
	295	clocks = <&peri_clk 4>;
a1763a82	296	resets = <&peri_rst 4>;
2752bcaa MY	297	clock-frequency = <100000>;
2752bcaa MY	298	};
a5e921b4	299
2752bcaa MY	300	i2c1: i2c@58781000 {
	301	compatible = "socionext,uniphier-fi2c";
	302	status = "disabled";
	303	reg = <0x58781000 0x80>;
	304	#address-cells = <1>;
	305	#size-cells = <0>;
	306	interrupts = <0 42 4>;
	307	pinctrl-names = "default";
	308	pinctrl-0 = <&pinctrl_i2c1>;
	309	clocks = <&peri_clk 5>;
a1763a82	310	resets = <&peri_rst 5>;
2752bcaa MY	311	clock-frequency = <100000>;
2752bcaa MY	312	};
61f838c7	313
2752bcaa MY	314	i2c2: i2c@58782000 {
	315	compatible = "socionext,uniphier-fi2c";
	316	status = "disabled";
	317	reg = <0x58782000 0x80>;
	318	#address-cells = <1>;
	319	#size-cells = <0>;
	320	interrupts = <0 43 4>;
	321	pinctrl-names = "default";
	322	pinctrl-0 = <&pinctrl_i2c2>;
	323	clocks = <&peri_clk 6>;
a1763a82	324	resets = <&peri_rst 6>;
2752bcaa MY	325	clock-frequency = <100000>;
2752bcaa MY	326	};
ad0561d4	327
2752bcaa MY	328	i2c3: i2c@58783000 {
	329	compatible = "socionext,uniphier-fi2c";
	330	status = "disabled";
	331	reg = <0x58783000 0x80>;
	332	#address-cells = <1>;
	333	#size-cells = <0>;
	334	interrupts = <0 44 4>;
	335	pinctrl-names = "default";
	336	pinctrl-0 = <&pinctrl_i2c3>;
	337	clocks = <&peri_clk 7>;
a1763a82	338	resets = <&peri_rst 7>;
2752bcaa MY	339	clock-frequency = <100000>;
2752bcaa MY	340	};
ad0561d4	341
2752bcaa MY	342	/* chip-internal connection for DMD */
	343	i2c4: i2c@58784000 {
	344	compatible = "socionext,uniphier-fi2c";
	345	reg = <0x58784000 0x80>;
	346	#address-cells = <1>;
	347	#size-cells = <0>;
	348	interrupts = <0 45 4>;
	349	clocks = <&peri_clk 8>;
a1763a82	350	resets = <&peri_rst 8>;
2752bcaa MY	351	clock-frequency = <400000>;
2752bcaa MY	352	};
ad0561d4	353
2752bcaa MY	354	/* chip-internal connection for STM */
	355	i2c5: i2c@58785000 {
	356	compatible = "socionext,uniphier-fi2c";
	357	reg = <0x58785000 0x80>;
	358	#address-cells = <1>;
	359	#size-cells = <0>;
	360	interrupts = <0 25 4>;
	361	clocks = <&peri_clk 9>;
a1763a82	362	resets = <&peri_rst 9>;
2752bcaa MY	363	clock-frequency = <400000>;
2752bcaa MY	364	};
ad0561d4	365
2752bcaa MY	366	/* chip-internal connection for HDMI */
	367	i2c6: i2c@58786000 {
	368	compatible = "socionext,uniphier-fi2c";
	369	reg = <0x58786000 0x80>;
	370	#address-cells = <1>;
	371	#size-cells = <0>;
	372	interrupts = <0 26 4>;
	373	clocks = <&peri_clk 10>;
a1763a82	374	resets = <&peri_rst 10>;
2752bcaa MY	375	clock-frequency = <400000>;
2752bcaa MY	376	};
ad0561d4	377
2752bcaa MY	378	system_bus: system-bus@58c00000 {
	379	compatible = "socionext,uniphier-system-bus";
	380	status = "disabled";
	381	reg = <0x58c00000 0x400>;
	382	#address-cells = <2>;
	383	#size-cells = <1>;
	384	pinctrl-names = "default";
	385	pinctrl-0 = <&pinctrl_system_bus>;
	386	};
	387
18088678	388	smpctrl@59801000 {
2752bcaa MY	389	compatible = "socionext,uniphier-smpctrl";
	390	reg = <0x59801000 0x400>;
	391	};
	392
	393	sdctrl@59810000 {
	394	compatible = "socionext,uniphier-pxs2-sdctrl",
	395	"simple-mfd", "syscon";
7b8330d2	396	reg = <0x59810000 0x400>;
2752bcaa MY	397
	398	sd_clk: clock {
	399	compatible = "socionext,uniphier-pxs2-sd-clock";
	400	#clock-cells = <1>;
	401	};
	402
	403	sd_rst: reset {
	404	compatible = "socionext,uniphier-pxs2-sd-reset";
	405	#reset-cells = <1>;
	406	};
	407	};
ad0561d4	408
2752bcaa MY	409	perictrl@59820000 {
	410	compatible = "socionext,uniphier-pxs2-perictrl",
	411	"simple-mfd", "syscon";
	412	reg = <0x59820000 0x200>;
	413
	414	peri_clk: clock {
	415	compatible = "socionext,uniphier-pxs2-peri-clock";
	416	#clock-cells = <1>;
	417	};
	418
	419	peri_rst: reset {
	420	compatible = "socionext,uniphier-pxs2-peri-reset";
	421	#reset-cells = <1>;
	422	};
	423	};
	424
6f36ee0b	425	soc_glue: soc-glue@5f800000 {
2752bcaa MY	426	compatible = "socionext,uniphier-pxs2-soc-glue",
	427	"simple-mfd", "syscon";
	428	reg = <0x5f800000 0x2000>;
	429
	430	pinctrl: pinctrl {
	431	compatible = "socionext,uniphier-pxs2-pinctrl";
	432	};
	433	};
	434
6b968186 KH	435	soc-glue@5f900000 {
	436	compatible = "socionext,uniphier-pxs2-soc-glue-debug",
	437	"simple-mfd";
	438	#address-cells = <1>;
	439	#size-cells = <1>;
	440	ranges = <0 0x5f900000 0x2000>;
	441
	442	efuse@100 {
	443	compatible = "socionext,uniphier-efuse";
	444	reg = <0x100 0x28>;
	445	};
	446
	447	efuse@200 {
	448	compatible = "socionext,uniphier-efuse";
	449	reg = <0x200 0x58>;
	450	};
	451	};
	452
80a68704 MY	453	aidet: aidet@5fc20000 {
	454	compatible = "socionext,uniphier-pxs2-aidet";
	455	reg = <0x5fc20000 0x200>;
	456	interrupt-controller;
	457	#interrupt-cells = <2>;
	458	};
	459
2752bcaa MY	460	timer@60000200 {
	461	compatible = "arm,cortex-a9-global-timer";
	462	reg = <0x60000200 0x20>;
	463	interrupts = <1 11 0xf04>;
	464	clocks = <&arm_timer_clk>;
	465	};
	466
	467	timer@60000600 {
	468	compatible = "arm,cortex-a9-twd-timer";
	469	reg = <0x60000600 0x20>;
	470	interrupts = <1 13 0xf04>;
	471	clocks = <&arm_timer_clk>;
	472	};
	473
	474	intc: interrupt-controller@60001000 {
	475	compatible = "arm,cortex-a9-gic";
	476	reg = <0x60001000 0x1000>,
	477	<0x60000100 0x100>;
	478	#interrupt-cells = <3>;
	479	interrupt-controller;
	480	};
	481
	482	sysctrl@61840000 {
	483	compatible = "socionext,uniphier-pxs2-sysctrl",
	484	"simple-mfd", "syscon";
	485	reg = <0x61840000 0x10000>;
	486
	487	sys_clk: clock {
	488	compatible = "socionext,uniphier-pxs2-clock";
	489	#clock-cells = <1>;
	490	};
	491
	492	sys_rst: reset {
	493	compatible = "socionext,uniphier-pxs2-reset";
	494	#reset-cells = <1>;
	495	};
fbd8d583 KH	496
	497	pvtctl: pvtctl {
	498	compatible = "socionext,uniphier-pxs2-thermal";
	499	interrupts = <0 3 4>;
	500	#thermal-sensor-cells = <0>;
	501	socionext,tmod-calibration = <0x0f86 0x6844>;
	502	};
2752bcaa	503	};
69f9cdc6	504
e3cc9319 KH	505	eth: ethernet@65000000 {
	506	compatible = "socionext,uniphier-pxs2-ave4";
	507	status = "disabled";
	508	reg = <0x65000000 0x8500>;
	509	interrupts = <0 66 4>;
	510	pinctrl-names = "default";
	511	pinctrl-0 = <&pinctrl_ether_rgmii>;
92724c03	512	clock-names = "ether";
e3cc9319	513	clocks = <&sys_clk 6>;
92724c03	514	reset-names = "ether";
e3cc9319 KH	515	resets = <&sys_rst 6>;
	516	phy-mode = "rgmii";
	517	local-mac-address = [00 00 00 00 00 00];
526f872b	518	socionext,syscon-phy-mode = <&soc_glue 0>;
e3cc9319 KH	519
	520	mdio: mdio {
	521	#address-cells = <1>;
	522	#size-cells = <0>;
	523	};
	524	};
	525
69f9cdc6 MY	526	nand: nand@68000000 {
	527	compatible = "socionext,uniphier-denali-nand-v5b";
	528	status = "disabled";
	529	reg-names = "nand_data", "denali_reg";
	530	reg = <0x68000000 0x20>, <0x68100000 0x1000>;
	531	interrupts = <0 65 4>;
	532	pinctrl-names = "default";
	533	pinctrl-0 = <&pinctrl_nand2cs>;
	534	clocks = <&sys_clk 2>;
a1763a82	535	resets = <&sys_rst 2>;
69f9cdc6	536	};
2752bcaa	537	};
ad0561d4	538	};
2752bcaa	539
ed8bc76b	540	#include "uniphier-pinctrl.dtsi"