projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| a5e921b4 | 1 | /* |
| 77896e4d | 2 | * Device Tree Source for UniPhier PXs2 SoC |
| a5e921b4 | 3 | * |
| 77896e4d MY |
4 | * Copyright (C) 2015-2016 Socionext Inc. |
| 5 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
| a5e921b4 | 6 | * |
| fa53757b | 7 | * SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| a5e921b4 MY |
8 | */ |
| 9 | ||
| fbd8d583 KH |
10 | #include <dt-bindings/thermal/thermal.h> |
| 11 | ||
| a5e921b4 | 12 | / { |
| 77896e4d | 13 | compatible = "socionext,uniphier-pxs2"; |
| 8e2b908b MY |
14 | #address-cells = <1>; |
| 15 | #size-cells = <1>; | |
| a5e921b4 MY |
16 | |
| 17 | cpus { | |
| 18 | #address-cells = <1>; | |
| 19 | #size-cells = <0>; | |
| a5e921b4 | 20 | |
| fbd8d583 | 21 | cpu0: cpu@0 { |
| a5e921b4 MY |
22 | device_type = "cpu"; |
| 23 | compatible = "arm,cortex-a9"; | |
| 24 | reg = <0>; | |
| 7a8a6588 | 25 | clocks = <&sys_clk 32>; |
| 3bdba5ac | 26 | enable-method = "psci"; |
| 7c62f299 | 27 | next-level-cache = <&l2>; |
| 7a8a6588 | 28 | operating-points-v2 = <&cpu_opp>; |
| fbd8d583 | 29 | #cooling-cells = <2>; |
| a5e921b4 MY |
30 | }; |
| 31 | ||
| fbd8d583 | 32 | cpu1: cpu@1 { |
| a5e921b4 MY |
33 | device_type = "cpu"; |
| 34 | compatible = "arm,cortex-a9"; | |
| 35 | reg = <1>; | |
| 7a8a6588 | 36 | clocks = <&sys_clk 32>; |
| 3bdba5ac | 37 | enable-method = "psci"; |
| 7c62f299 | 38 | next-level-cache = <&l2>; |
| 7a8a6588 | 39 | operating-points-v2 = <&cpu_opp>; |
| a5e921b4 MY |
40 | }; |
| 41 | ||
| fbd8d583 | 42 | cpu2: cpu@2 { |
| a5e921b4 MY |
43 | device_type = "cpu"; |
| 44 | compatible = "arm,cortex-a9"; | |
| 45 | reg = <2>; | |
| 7a8a6588 | 46 | clocks = <&sys_clk 32>; |
| 3bdba5ac | 47 | enable-method = "psci"; |
| 7c62f299 | 48 | next-level-cache = <&l2>; |
| 7a8a6588 | 49 | operating-points-v2 = <&cpu_opp>; |
| a5e921b4 MY |
50 | }; |
| 51 | ||
| fbd8d583 | 52 | cpu3: cpu@3 { |
| a5e921b4 MY |
53 | device_type = "cpu"; |
| 54 | compatible = "arm,cortex-a9"; | |
| 55 | reg = <3>; | |
| 7a8a6588 | 56 | clocks = <&sys_clk 32>; |
| 3bdba5ac | 57 | enable-method = "psci"; |
| 7c62f299 | 58 | next-level-cache = <&l2>; |
| 7a8a6588 MY |
59 | operating-points-v2 = <&cpu_opp>; |
| 60 | }; | |
| 61 | }; | |
| 62 | ||
| 1658b84d | 63 | cpu_opp: opp-table { |
| 7a8a6588 MY |
64 | compatible = "operating-points-v2"; |
| 65 | opp-shared; | |
| 66 | ||
| f21683ae | 67 | opp-100000000 { |
| 7a8a6588 MY |
68 | opp-hz = /bits/ 64 <100000000>; |
| 69 | clock-latency-ns = <300>; | |
| 70 | }; | |
| f21683ae | 71 | opp-150000000 { |
| 7a8a6588 MY |
72 | opp-hz = /bits/ 64 <150000000>; |
| 73 | clock-latency-ns = <300>; | |
| 74 | }; | |
| f21683ae | 75 | opp-200000000 { |
| 7a8a6588 MY |
76 | opp-hz = /bits/ 64 <200000000>; |
| 77 | clock-latency-ns = <300>; | |
| 78 | }; | |
| f21683ae | 79 | opp-300000000 { |
| 7a8a6588 MY |
80 | opp-hz = /bits/ 64 <300000000>; |
| 81 | clock-latency-ns = <300>; | |
| 82 | }; | |
| f21683ae | 83 | opp-400000000 { |
| 7a8a6588 MY |
84 | opp-hz = /bits/ 64 <400000000>; |
| 85 | clock-latency-ns = <300>; | |
| 86 | }; | |
| f21683ae | 87 | opp-600000000 { |
| 7a8a6588 MY |
88 | opp-hz = /bits/ 64 <600000000>; |
| 89 | clock-latency-ns = <300>; | |
| 90 | }; | |
| f21683ae | 91 | opp-800000000 { |
| 7a8a6588 MY |
92 | opp-hz = /bits/ 64 <800000000>; |
| 93 | clock-latency-ns = <300>; | |
| 94 | }; | |
| f21683ae | 95 | opp-1200000000 { |
| 7a8a6588 MY |
96 | opp-hz = /bits/ 64 <1200000000>; |
| 97 | clock-latency-ns = <300>; | |
| a5e921b4 MY |
98 | }; |
| 99 | }; | |
| 100 | ||
| 2752bcaa MY |
101 | psci { |
| 102 | compatible = "arm,psci-0.2"; | |
| 103 | method = "smc"; | |
| 104 | }; | |
| 105 | ||
| a5e921b4 | 106 | clocks { |
| 2752bcaa MY |
107 | refclk: ref { |
| 108 | compatible = "fixed-clock"; | |
| 109 | #clock-cells = <0>; | |
| 110 | clock-frequency = <25000000>; | |
| 111 | }; | |
| 112 | ||
| 1658b84d | 113 | arm_timer_clk: arm-timer { |
| a5e921b4 MY |
114 | #clock-cells = <0>; |
| 115 | compatible = "fixed-clock"; | |
| 116 | clock-frequency = <50000000>; | |
| 117 | }; | |
| a5e921b4 MY |
118 | }; |
| 119 | ||
| fbd8d583 KH |
120 | thermal-zones { |
| 121 | cpu-thermal { | |
| 122 | polling-delay-passive = <250>; /* 250ms */ | |
| 123 | polling-delay = <1000>; /* 1000ms */ | |
| 124 | thermal-sensors = <&pvtctl>; | |
| 125 | ||
| 126 | trips { | |
| 127 | cpu_crit: cpu-crit { | |
| 128 | temperature = <95000>; /* 95C */ | |
| 129 | hysteresis = <2000>; | |
| 130 | type = "critical"; | |
| 131 | }; | |
| 132 | cpu_alert: cpu-alert { | |
| 133 | temperature = <85000>; /* 85C */ | |
| 134 | hysteresis = <2000>; | |
| 135 | type = "passive"; | |
| 136 | }; | |
| 137 | }; | |
| 138 | ||
| 139 | cooling-maps { | |
| 140 | map { | |
| 141 | trip = <&cpu_alert>; | |
| 142 | cooling-device = <&cpu0 | |
| 143 | THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
| 144 | }; | |
| 145 | }; | |
| 146 | }; | |
| 147 | }; | |
| 148 | ||
| 2752bcaa MY |
149 | soc { |
| 150 | compatible = "simple-bus"; | |
| 629b557a | 151 | #address-cells = <1>; |
| 2752bcaa MY |
152 | #size-cells = <1>; |
| 153 | ranges; | |
| 154 | interrupt-parent = <&intc>; | |
| a5e921b4 | 155 | |
| 2752bcaa MY |
156 | l2: l2-cache@500c0000 { |
| 157 | compatible = "socionext,uniphier-system-cache"; | |
| 158 | reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, | |
| 159 | <0x506c0000 0x400>; | |
| 160 | interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; | |
| 161 | cache-unified; | |
| 162 | cache-size = <(1280 * 1024)>; | |
| 163 | cache-sets = <512>; | |
| 164 | cache-line-size = <128>; | |
| 165 | cache-level = <2>; | |
| 166 | }; | |
| a5e921b4 | 167 | |
| 2752bcaa MY |
168 | serial0: serial@54006800 { |
| 169 | compatible = "socionext,uniphier-uart"; | |
| 170 | status = "disabled"; | |
| 171 | reg = <0x54006800 0x40>; | |
| 172 | interrupts = <0 33 4>; | |
| 173 | pinctrl-names = "default"; | |
| 174 | pinctrl-0 = <&pinctrl_uart0>; | |
| 175 | clocks = <&peri_clk 0>; | |
| a1763a82 | 176 | resets = <&peri_rst 0>; |
| 2752bcaa | 177 | }; |
| a5e921b4 | 178 | |
| 2752bcaa MY |
179 | serial1: serial@54006900 { |
| 180 | compatible = "socionext,uniphier-uart"; | |
| 181 | status = "disabled"; | |
| 182 | reg = <0x54006900 0x40>; | |
| 183 | interrupts = <0 35 4>; | |
| 184 | pinctrl-names = "default"; | |
| 185 | pinctrl-0 = <&pinctrl_uart1>; | |
| 186 | clocks = <&peri_clk 1>; | |
| a1763a82 | 187 | resets = <&peri_rst 1>; |
| 2752bcaa | 188 | }; |
| a5e921b4 | 189 | |
| 2752bcaa MY |
190 | serial2: serial@54006a00 { |
| 191 | compatible = "socionext,uniphier-uart"; | |
| 192 | status = "disabled"; | |
| 193 | reg = <0x54006a00 0x40>; | |
| 194 | interrupts = <0 37 4>; | |
| 195 | pinctrl-names = "default"; | |
| 196 | pinctrl-0 = <&pinctrl_uart2>; | |
| 197 | clocks = <&peri_clk 2>; | |
| a1763a82 | 198 | resets = <&peri_rst 2>; |
| 2752bcaa | 199 | }; |
| a5e921b4 | 200 | |
| 2752bcaa MY |
201 | serial3: serial@54006b00 { |
| 202 | compatible = "socionext,uniphier-uart"; | |
| 203 | status = "disabled"; | |
| 204 | reg = <0x54006b00 0x40>; | |
| 205 | interrupts = <0 177 4>; | |
| 206 | pinctrl-names = "default"; | |
| 207 | pinctrl-0 = <&pinctrl_uart3>; | |
| 208 | clocks = <&peri_clk 3>; | |
| a1763a82 | 209 | resets = <&peri_rst 3>; |
| 2752bcaa | 210 | }; |
| a5e921b4 | 211 | |
| 5d4bc4bd MY |
212 | gpio: gpio@55000000 { |
| 213 | compatible = "socionext,uniphier-gpio"; | |
| 214 | reg = <0x55000000 0x200>; | |
| 215 | interrupt-parent = <&aidet>; | |
| 216 | interrupt-controller; | |
| 217 | #interrupt-cells = <2>; | |
| 218 | gpio-controller; | |
| 219 | #gpio-cells = <2>; | |
| 220 | gpio-ranges = <&pinctrl 0 0 0>, | |
| 221 | <&pinctrl 96 0 0>; | |
| 222 | gpio-ranges-group-names = "gpio_range0", | |
| 223 | "gpio_range1"; | |
| 224 | ngpios = <232>; | |
| 225 | socionext,interrupt-ranges = <0 48 16>, <16 154 5>, | |
| 226 | <21 217 3>; | |
| 227 | }; | |
| 228 | ||
| 2752bcaa MY |
229 | i2c0: i2c@58780000 { |
| 230 | compatible = "socionext,uniphier-fi2c"; | |
| 231 | status = "disabled"; | |
| 232 | reg = <0x58780000 0x80>; | |
| 233 | #address-cells = <1>; | |
| 234 | #size-cells = <0>; | |
| 235 | interrupts = <0 41 4>; | |
| 236 | pinctrl-names = "default"; | |
| 237 | pinctrl-0 = <&pinctrl_i2c0>; | |
| 238 | clocks = <&peri_clk 4>; | |
| a1763a82 | 239 | resets = <&peri_rst 4>; |
| 2752bcaa MY |
240 | clock-frequency = <100000>; |
| 241 | }; | |
| a5e921b4 | 242 | |
| 2752bcaa MY |
243 | i2c1: i2c@58781000 { |
| 244 | compatible = "socionext,uniphier-fi2c"; | |
| 245 | status = "disabled"; | |
| 246 | reg = <0x58781000 0x80>; | |
| 247 | #address-cells = <1>; | |
| 248 | #size-cells = <0>; | |
| 249 | interrupts = <0 42 4>; | |
| 250 | pinctrl-names = "default"; | |
| 251 | pinctrl-0 = <&pinctrl_i2c1>; | |
| 252 | clocks = <&peri_clk 5>; | |
| a1763a82 | 253 | resets = <&peri_rst 5>; |
| 2752bcaa MY |
254 | clock-frequency = <100000>; |
| 255 | }; | |
| 61f838c7 | 256 | |
| 2752bcaa MY |
257 | i2c2: i2c@58782000 { |
| 258 | compatible = "socionext,uniphier-fi2c"; | |
| 259 | status = "disabled"; | |
| 260 | reg = <0x58782000 0x80>; | |
| 261 | #address-cells = <1>; | |
| 262 | #size-cells = <0>; | |
| 263 | interrupts = <0 43 4>; | |
| 264 | pinctrl-names = "default"; | |
| 265 | pinctrl-0 = <&pinctrl_i2c2>; | |
| 266 | clocks = <&peri_clk 6>; | |
| a1763a82 | 267 | resets = <&peri_rst 6>; |
| 2752bcaa MY |
268 | clock-frequency = <100000>; |
| 269 | }; | |
| ad0561d4 | 270 | |
| 2752bcaa MY |
271 | i2c3: i2c@58783000 { |
| 272 | compatible = "socionext,uniphier-fi2c"; | |
| 273 | status = "disabled"; | |
| 274 | reg = <0x58783000 0x80>; | |
| 275 | #address-cells = <1>; | |
| 276 | #size-cells = <0>; | |
| 277 | interrupts = <0 44 4>; | |
| 278 | pinctrl-names = "default"; | |
| 279 | pinctrl-0 = <&pinctrl_i2c3>; | |
| 280 | clocks = <&peri_clk 7>; | |
| a1763a82 | 281 | resets = <&peri_rst 7>; |
| 2752bcaa MY |
282 | clock-frequency = <100000>; |
| 283 | }; | |
| ad0561d4 | 284 | |
| 2752bcaa MY |
285 | /* chip-internal connection for DMD */ |
| 286 | i2c4: i2c@58784000 { | |
| 287 | compatible = "socionext,uniphier-fi2c"; | |
| 288 | reg = <0x58784000 0x80>; | |
| 289 | #address-cells = <1>; | |
| 290 | #size-cells = <0>; | |
| 291 | interrupts = <0 45 4>; | |
| 292 | clocks = <&peri_clk 8>; | |
| a1763a82 | 293 | resets = <&peri_rst 8>; |
| 2752bcaa MY |
294 | clock-frequency = <400000>; |
| 295 | }; | |
| ad0561d4 | 296 | |
| 2752bcaa MY |
297 | /* chip-internal connection for STM */ |
| 298 | i2c5: i2c@58785000 { | |
| 299 | compatible = "socionext,uniphier-fi2c"; | |
| 300 | reg = <0x58785000 0x80>; | |
| 301 | #address-cells = <1>; | |
| 302 | #size-cells = <0>; | |
| 303 | interrupts = <0 25 4>; | |
| 304 | clocks = <&peri_clk 9>; | |
| a1763a82 | 305 | resets = <&peri_rst 9>; |
| 2752bcaa MY |
306 | clock-frequency = <400000>; |
| 307 | }; | |
| ad0561d4 | 308 | |
| 2752bcaa MY |
309 | /* chip-internal connection for HDMI */ |
| 310 | i2c6: i2c@58786000 { | |
| 311 | compatible = "socionext,uniphier-fi2c"; | |
| 312 | reg = <0x58786000 0x80>; | |
| 313 | #address-cells = <1>; | |
| 314 | #size-cells = <0>; | |
| 315 | interrupts = <0 26 4>; | |
| 316 | clocks = <&peri_clk 10>; | |
| a1763a82 | 317 | resets = <&peri_rst 10>; |
| 2752bcaa MY |
318 | clock-frequency = <400000>; |
| 319 | }; | |
| ad0561d4 | 320 | |
| 2752bcaa MY |
321 | system_bus: system-bus@58c00000 { |
| 322 | compatible = "socionext,uniphier-system-bus"; | |
| 323 | status = "disabled"; | |
| 324 | reg = <0x58c00000 0x400>; | |
| 325 | #address-cells = <2>; | |
| 326 | #size-cells = <1>; | |
| 327 | pinctrl-names = "default"; | |
| 328 | pinctrl-0 = <&pinctrl_system_bus>; | |
| 329 | }; | |
| 330 | ||
| 18088678 | 331 | smpctrl@59801000 { |
| 2752bcaa MY |
332 | compatible = "socionext,uniphier-smpctrl"; |
| 333 | reg = <0x59801000 0x400>; | |
| 334 | }; | |
| 335 | ||
| 336 | sdctrl@59810000 { | |
| 337 | compatible = "socionext,uniphier-pxs2-sdctrl", | |
| 338 | "simple-mfd", "syscon"; | |
| 7b8330d2 | 339 | reg = <0x59810000 0x400>; |
| 2752bcaa MY |
340 | |
| 341 | sd_clk: clock { | |
| 342 | compatible = "socionext,uniphier-pxs2-sd-clock"; | |
| 343 | #clock-cells = <1>; | |
| 344 | }; | |
| 345 | ||
| 346 | sd_rst: reset { | |
| 347 | compatible = "socionext,uniphier-pxs2-sd-reset"; | |
| 348 | #reset-cells = <1>; | |
| 349 | }; | |
| 350 | }; | |
| ad0561d4 | 351 | |
| 2752bcaa MY |
352 | perictrl@59820000 { |
| 353 | compatible = "socionext,uniphier-pxs2-perictrl", | |
| 354 | "simple-mfd", "syscon"; | |
| 355 | reg = <0x59820000 0x200>; | |
| 356 | ||
| 357 | peri_clk: clock { | |
| 358 | compatible = "socionext,uniphier-pxs2-peri-clock"; | |
| 359 | #clock-cells = <1>; | |
| 360 | }; | |
| 361 | ||
| 362 | peri_rst: reset { | |
| 363 | compatible = "socionext,uniphier-pxs2-peri-reset"; | |
| 364 | #reset-cells = <1>; | |
| 365 | }; | |
| 366 | }; | |
| 367 | ||
| 368 | soc-glue@5f800000 { | |
| 369 | compatible = "socionext,uniphier-pxs2-soc-glue", | |
| 370 | "simple-mfd", "syscon"; | |
| 371 | reg = <0x5f800000 0x2000>; | |
| 372 | ||
| 373 | pinctrl: pinctrl { | |
| 374 | compatible = "socionext,uniphier-pxs2-pinctrl"; | |
| 375 | }; | |
| 376 | }; | |
| 377 | ||
| 80a68704 MY |
378 | aidet: aidet@5fc20000 { |
| 379 | compatible = "socionext,uniphier-pxs2-aidet"; | |
| 380 | reg = <0x5fc20000 0x200>; | |
| 381 | interrupt-controller; | |
| 382 | #interrupt-cells = <2>; | |
| 383 | }; | |
| 384 | ||
| 2752bcaa MY |
385 | timer@60000200 { |
| 386 | compatible = "arm,cortex-a9-global-timer"; | |
| 387 | reg = <0x60000200 0x20>; | |
| 388 | interrupts = <1 11 0xf04>; | |
| 389 | clocks = <&arm_timer_clk>; | |
| 390 | }; | |
| 391 | ||
| 392 | timer@60000600 { | |
| 393 | compatible = "arm,cortex-a9-twd-timer"; | |
| 394 | reg = <0x60000600 0x20>; | |
| 395 | interrupts = <1 13 0xf04>; | |
| 396 | clocks = <&arm_timer_clk>; | |
| 397 | }; | |
| 398 | ||
| 399 | intc: interrupt-controller@60001000 { | |
| 400 | compatible = "arm,cortex-a9-gic"; | |
| 401 | reg = <0x60001000 0x1000>, | |
| 402 | <0x60000100 0x100>; | |
| 403 | #interrupt-cells = <3>; | |
| 404 | interrupt-controller; | |
| 405 | }; | |
| 406 | ||
| 407 | sysctrl@61840000 { | |
| 408 | compatible = "socionext,uniphier-pxs2-sysctrl", | |
| 409 | "simple-mfd", "syscon"; | |
| 410 | reg = <0x61840000 0x10000>; | |
| 411 | ||
| 412 | sys_clk: clock { | |
| 413 | compatible = "socionext,uniphier-pxs2-clock"; | |
| 414 | #clock-cells = <1>; | |
| 415 | }; | |
| 416 | ||
| 417 | sys_rst: reset { | |
| 418 | compatible = "socionext,uniphier-pxs2-reset"; | |
| 419 | #reset-cells = <1>; | |
| 420 | }; | |
| fbd8d583 KH |
421 | |
| 422 | pvtctl: pvtctl { | |
| 423 | compatible = "socionext,uniphier-pxs2-thermal"; | |
| 424 | interrupts = <0 3 4>; | |
| 425 | #thermal-sensor-cells = <0>; | |
| 426 | socionext,tmod-calibration = <0x0f86 0x6844>; | |
| 427 | }; | |
| 2752bcaa | 428 | }; |
| 69f9cdc6 MY |
429 | |
| 430 | nand: nand@68000000 { | |
| 431 | compatible = "socionext,uniphier-denali-nand-v5b"; | |
| 432 | status = "disabled"; | |
| 433 | reg-names = "nand_data", "denali_reg"; | |
| 434 | reg = <0x68000000 0x20>, <0x68100000 0x1000>; | |
| 435 | interrupts = <0 65 4>; | |
| 436 | pinctrl-names = "default"; | |
| 437 | pinctrl-0 = <&pinctrl_nand2cs>; | |
| 438 | clocks = <&sys_clk 2>; | |
| a1763a82 | 439 | resets = <&sys_rst 2>; |
| 69f9cdc6 | 440 | }; |
| 2752bcaa | 441 | }; |
| ad0561d4 | 442 | }; |
| 2752bcaa | 443 | |
| ed8bc76b | 444 | #include "uniphier-pinctrl.dtsi" |