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ARM: dts: armada388-clearfog: enable spi flash
[linux-2.6-block.git] / arch / arm / boot / dts / tegra20.dtsi
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
885a8cfa 2#include <dt-bindings/clock/tegra20-car.h>
3325f1bc 3#include <dt-bindings/gpio/tegra-gpio.h>
ba4104e7 4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 5#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 6
1bd0bd49 7#include "skeleton.dtsi"
8e267f3d
GL		 8
9/ {
10 compatible = "nvidia,tegra20";
870c81a4 11 interrupt-parent = <&lic>;
8e267f3d 12
f143bf34
VZ		 13 iram@40000000 {
14 compatible = "mmio-sram";
15 reg = <0x40000000 0x40000>;
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges = <0 0x40000000 0x40000>;
bb768f28 19
0275e4aa 20 vde_pool: vde@400 {
bb768f28
DO		 21 reg = <0x400 0x3fc00>;
22 pool;
23 };
f143bf34
VZ		 24 };
25
58ecb23f 26 host1x@50000000 {
ed821f07
TR		 27 compatible = "nvidia,tegra20-host1x", "simple-bus";
28 reg = <0x50000000 0x00024000>;
6cecf916
SW		 29 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
30 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
885a8cfa 31 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
3393d422
SW		 32 resets = <&tegra_car 28>;
33 reset-names = "host1x";
ed821f07
TR		 34
35 #address-cells = <1>;
36 #size-cells = <1>;
37
38 ranges = <0x54000000 0x54000000 0x04000000>;
39
58ecb23f 40 mpe@54040000 {
ed821f07
TR		 41 compatible = "nvidia,tegra20-mpe";
42 reg = <0x54040000 0x00040000>;
6cecf916 43 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 44 clocks = <&tegra_car TEGRA20_CLK_MPE>;
3393d422
SW		 45 resets = <&tegra_car 60>;
46 reset-names = "mpe";
ed821f07
TR		 47 };
48
58ecb23f 49 vi@54080000 {
ed821f07
TR		 50 compatible = "nvidia,tegra20-vi";
51 reg = <0x54080000 0x00040000>;
6cecf916 52 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 53 clocks = <&tegra_car TEGRA20_CLK_VI>;
3393d422
SW		 54 resets = <&tegra_car 20>;
55 reset-names = "vi";
ed821f07
TR		 56 };
57
58ecb23f 58 epp@540c0000 {
ed821f07
TR		 59 compatible = "nvidia,tegra20-epp";
60 reg = <0x540c0000 0x00040000>;
6cecf916 61 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 62 clocks = <&tegra_car TEGRA20_CLK_EPP>;
3393d422
SW		 63 resets = <&tegra_car 19>;
64 reset-names = "epp";
ed821f07
TR		 65 };
66
58ecb23f 67 isp@54100000 {
ed821f07
TR		 68 compatible = "nvidia,tegra20-isp";
69 reg = <0x54100000 0x00040000>;
6cecf916 70 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 71 clocks = <&tegra_car TEGRA20_CLK_ISP>;
3393d422
SW		 72 resets = <&tegra_car 23>;
73 reset-names = "isp";
ed821f07
TR		 74 };
75
58ecb23f 76 gr2d@54140000 {
ed821f07
TR		 77 compatible = "nvidia,tegra20-gr2d";
78 reg = <0x54140000 0x00040000>;
6cecf916 79 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 80 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
3393d422
SW		 81 resets = <&tegra_car 21>;
82 reset-names = "2d";
ed821f07
TR		 83 };
84
de47699d 85 gr3d@54180000 {
ed821f07 86 compatible = "nvidia,tegra20-gr3d";
de47699d 87 reg = <0x54180000 0x00040000>;
885a8cfa 88 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
3393d422
SW		 89 resets = <&tegra_car 24>;
90 reset-names = "3d";
ed821f07
TR		 91 };
92
93 dc@54200000 {
94 compatible = "nvidia,tegra20-dc";
95 reg = <0x54200000 0x00040000>;
6cecf916 96 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 97 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
98 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 99 clock-names = "dc", "parent";
3393d422
SW		 100 resets = <&tegra_car 27>;
101 reset-names = "dc";
ed821f07 102
688b56b4
TR		 103 nvidia,head = <0>;
104
ed821f07
TR		 105 rgb {
106 status = "disabled";
107 };
108 };
109
110 dc@54240000 {
111 compatible = "nvidia,tegra20-dc";
112 reg = <0x54240000 0x00040000>;
6cecf916 113 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 114 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
115 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 116 clock-names = "dc", "parent";
3393d422
SW		 117 resets = <&tegra_car 26>;
118 reset-names = "dc";
ed821f07 119
688b56b4
TR		 120 nvidia,head = <1>;
121
ed821f07
TR		 122 rgb {
123 status = "disabled";
124 };
125 };
126
58ecb23f 127 hdmi@54280000 {
ed821f07
TR		 128 compatible = "nvidia,tegra20-hdmi";
129 reg = <0x54280000 0x00040000>;
6cecf916 130 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 131 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
132 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
8d8b43da 133 clock-names = "hdmi", "parent";
3393d422
SW		 134 resets = <&tegra_car 51>;
135 reset-names = "hdmi";
ed821f07
TR		 136 status = "disabled";
137 };
138
58ecb23f 139 tvo@542c0000 {
ed821f07
TR		 140 compatible = "nvidia,tegra20-tvo";
141 reg = <0x542c0000 0x00040000>;
6cecf916 142 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 143 clocks = <&tegra_car TEGRA20_CLK_TVO>;
ed821f07
TR		 144 status = "disabled";
145 };
146
de47699d 147 dsi@54300000 {
ed821f07 148 compatible = "nvidia,tegra20-dsi";
de47699d 149 reg = <0x54300000 0x00040000>;
885a8cfa 150 clocks = <&tegra_car TEGRA20_CLK_DSI>;
3393d422
SW		 151 resets = <&tegra_car 48>;
152 reset-names = "dsi";
ed821f07
TR		 153 status = "disabled";
154 };
155 };
156
2cda1880 157 timer@50040600 {
73368ba0 158 compatible = "arm,cortex-a9-twd-timer";
870c81a4 159 interrupt-parent = <&intc>;
73368ba0 160 reg = <0x50040600 0x20>;
6cecf916 161 interrupts = <GIC_PPI 13
e7d9b270 162 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
885a8cfa 163 clocks = <&tegra_car TEGRA20_CLK_TWD>;
73368ba0
SW		 164 };
165
58ecb23f 166 intc: interrupt-controller@50041000 {
0d4f7479 167 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 168 reg = <0x50041000 0x1000
169 0x50040100 0x0100>;
2eaab06e
SW		 170 interrupt-controller;
171 #interrupt-cells = <3>;
870c81a4 172 interrupt-parent = <&intc>;
8e267f3d
GL		 173 };
174
58ecb23f 175 cache-controller@50043000 {
bb2c1de9
SW		 176 compatible = "arm,pl310-cache";
177 reg = <0x50043000 0x1000>;
178 arm,data-latency = <5 5 2>;
179 arm,tag-latency = <4 4 2>;
180 cache-unified;
181 cache-level = <2>;
182 };
183
870c81a4
MZ		 184 lic: interrupt-controller@60004000 {
185 compatible = "nvidia,tegra20-ictlr";
186 reg = <0x60004000 0x100>,
187 <0x60004100 0x50>,
188 <0x60004200 0x50>,
189 <0x60004300 0x50>;
190 interrupt-controller;
191 #interrupt-cells = <3>;
192 interrupt-parent = <&intc>;
193 };
194
2f2b7fb2
SW		 195 timer@60005000 {
196 compatible = "nvidia,tegra20-timer";
197 reg = <0x60005000 0x60>;
6cecf916
SW		 198 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 202 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
2f2b7fb2
SW		 203 };
204
58ecb23f 205 tegra_car: clock@60006000 {
270f8ce3
SW		 206 compatible = "nvidia,tegra20-car";
207 reg = <0x60006000 0x1000>;
208 #clock-cells = <1>;
3393d422 209 #reset-cells = <1>;
270f8ce3
SW		 210 };
211
b1023134
TR		 212 flow-controller@60007000 {
213 compatible = "nvidia,tegra20-flowctrl";
214 reg = <0x60007000 0x1000>;
215 };
216
58ecb23f 217 apbdma: dma@6000a000 {
8051b75a
SW		 218 compatible = "nvidia,tegra20-apbdma";
219 reg = <0x6000a000 0x1200>;
6cecf916
SW		 220 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 236 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
3393d422
SW		 237 resets = <&tegra_car 34>;
238 reset-names = "dma";
034d023f 239 #dma-cells = <1>;
8051b75a
SW		 240 };
241
0d5ccb38 242 ahb@6000c000 {
c04abb3a 243 compatible = "nvidia,tegra20-ahb";
0d5ccb38 244 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
8e267f3d
GL		 245 };
246
58ecb23f 247 gpio: gpio@6000d000 {
8e267f3d 248 compatible = "nvidia,tegra20-gpio";
95decf84 249 reg = <0x6000d000 0x1000>;
6cecf916
SW		 250 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
255 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
8e267f3d
GL		 257 #gpio-cells = <2>;
258 gpio-controller;
6f74dc9b
SW		 259 #interrupt-cells = <2>;
260 interrupt-controller;
4f1d8414 261 /*
17cdddf0 262 gpio-ranges = <&pinmux 0 0 224>;
4f1d8414 263 */
8e267f3d
GL		 264 };
265
bb768f28
DO		 266 vde@6001a000 {
267 compatible = "nvidia,tegra20-vde";
268 reg = <0x6001a000 0x1000 /* Syntax Engine */
269 0x6001b000 0x1000 /* Video Bitstream Engine */
270 0x6001c000 0x100 /* Macroblock Engine */
271 0x6001c200 0x100 /* Post-processing Engine */
272 0x6001c400 0x100 /* Motion Compensation Engine */
273 0x6001c600 0x100 /* Transform Engine */
274 0x6001c800 0x100 /* Pixel prediction block */
275 0x6001ca00 0x100 /* Video DMA */
276 0x6001d800 0x300>; /* Video frame controls */
277 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
278 "tfe", "ppb", "vdma", "frameid";
279 iram = <&vde_pool>; /* IRAM region */
280 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
281 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
282 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
283 interrupt-names = "sync-token", "bsev", "sxe";
284 clocks = <&tegra_car TEGRA20_CLK_VDE>;
285 resets = <&tegra_car 61>;
286 };
287
155dfc7b
PDS		 288 apbmisc@70000800 {
289 compatible = "nvidia,tegra20-apbmisc";
290 reg = <0x70000800 0x64 /* Chip revision */
291 0x70000008 0x04>; /* Strapping options */
292 };
293
58ecb23f 294 pinmux: pinmux@70000014 {
f62f548c 295 compatible = "nvidia,tegra20-pinmux";
95decf84
SW		 296 reg = <0x70000014 0x10 /* Tri-state registers */
297 0x70000080 0x20 /* Mux registers */
298 0x700000a0 0x14 /* Pull-up/down registers */
299 0x70000868 0xa8>; /* Pad control registers */
f62f548c
SW		 300 };
301
58ecb23f 302 das@70000c00 {
c04abb3a
SW		 303 compatible = "nvidia,tegra20-das";
304 reg = <0x70000c00 0x80>;
305 };
fc5c306b 306
58ecb23f 307 tegra_ac97: ac97@70002000 {
0698ed19
LS		 308 compatible = "nvidia,tegra20-ac97";
309 reg = <0x70002000 0x200>;
6cecf916 310 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 311 clocks = <&tegra_car TEGRA20_CLK_AC97>;
3393d422
SW		 312 resets = <&tegra_car 3>;
313 reset-names = "ac97";
034d023f
SW		 314 dmas = <&apbdma 12>, <&apbdma 12>;
315 dma-names = "rx", "tx";
0698ed19
LS		 316 status = "disabled";
317 };
c04abb3a
SW		 318
319 tegra_i2s1: i2s@70002800 {
320 compatible = "nvidia,tegra20-i2s";
321 reg = <0x70002800 0x200>;
6cecf916 322 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 323 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
3393d422
SW		 324 resets = <&tegra_car 11>;
325 reset-names = "i2s";
034d023f
SW		 326 dmas = <&apbdma 2>, <&apbdma 2>;
327 dma-names = "rx", "tx";
223ef78d 328 status = "disabled";
c04abb3a
SW		 329 };
330
331 tegra_i2s2: i2s@70002a00 {
332 compatible = "nvidia,tegra20-i2s";
333 reg = <0x70002a00 0x200>;
6cecf916 334 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 335 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
3393d422
SW		 336 resets = <&tegra_car 18>;
337 reset-names = "i2s";
034d023f
SW		 338 dmas = <&apbdma 1>, <&apbdma 1>;
339 dma-names = "rx", "tx";
223ef78d 340 status = "disabled";
c04abb3a
SW		 341 };
342
b6551bb9
LD		 343 /*
344 * There are two serial driver i.e. 8250 based simple serial
345 * driver and APB DMA based serial driver for higher baudrate
346 * and performace. To enable the 8250 based driver, the compatible
347 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
e1098248 348 * driver, the compatible is "nvidia,tegra20-hsuart".
b6551bb9
LD		 349 */
350 uarta: serial@70006000 {
8e267f3d
GL		 351 compatible = "nvidia,tegra20-uart";
352 reg = <0x70006000 0x40>;
353 reg-shift = <2>;
6cecf916 354 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 355 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
3393d422
SW		 356 resets = <&tegra_car 6>;
357 reset-names = "serial";
034d023f
SW		 358 dmas = <&apbdma 8>, <&apbdma 8>;
359 dma-names = "rx", "tx";
223ef78d 360 status = "disabled";
8e267f3d
GL		 361 };
362
b6551bb9 363 uartb: serial@70006040 {
8e267f3d
GL		 364 compatible = "nvidia,tegra20-uart";
365 reg = <0x70006040 0x40>;
366 reg-shift = <2>;
6cecf916 367 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 368 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
3393d422
SW		 369 resets = <&tegra_car 7>;
370 reset-names = "serial";
034d023f
SW		 371 dmas = <&apbdma 9>, <&apbdma 9>;
372 dma-names = "rx", "tx";
223ef78d 373 status = "disabled";
8e267f3d
GL		 374 };
375
b6551bb9 376 uartc: serial@70006200 {
8e267f3d
GL		 377 compatible = "nvidia,tegra20-uart";
378 reg = <0x70006200 0x100>;
379 reg-shift = <2>;
6cecf916 380 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 381 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
3393d422
SW		 382 resets = <&tegra_car 55>;
383 reset-names = "serial";
034d023f
SW		 384 dmas = <&apbdma 10>, <&apbdma 10>;
385 dma-names = "rx", "tx";
223ef78d 386 status = "disabled";
8e267f3d
GL		 387 };
388
b6551bb9 389 uartd: serial@70006300 {
8e267f3d
GL		 390 compatible = "nvidia,tegra20-uart";
391 reg = <0x70006300 0x100>;
392 reg-shift = <2>;
6cecf916 393 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 394 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
3393d422
SW		 395 resets = <&tegra_car 65>;
396 reset-names = "serial";
034d023f
SW		 397 dmas = <&apbdma 19>, <&apbdma 19>;
398 dma-names = "rx", "tx";
223ef78d 399 status = "disabled";
8e267f3d
GL		 400 };
401
b6551bb9 402 uarte: serial@70006400 {
8e267f3d
GL		 403 compatible = "nvidia,tegra20-uart";
404 reg = <0x70006400 0x100>;
405 reg-shift = <2>;
6cecf916 406 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 407 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
3393d422
SW		 408 resets = <&tegra_car 66>;
409 reset-names = "serial";
034d023f
SW		 410 dmas = <&apbdma 20>, <&apbdma 20>;
411 dma-names = "rx", "tx";
223ef78d 412 status = "disabled";
8e267f3d
GL		 413 };
414
c1700644
MK		 415 gmi@70009000 {
416 compatible = "nvidia,tegra20-gmi";
417 reg = <0x70009000 0x1000>;
418 #address-cells = <2>;
419 #size-cells = <1>;
420 ranges = <0 0 0xd0000000 0xfffffff>;
421 clocks = <&tegra_car TEGRA20_CLK_NOR>;
422 clock-names = "gmi";
423 resets = <&tegra_car 42>;
424 reset-names = "gmi";
425 status = "disabled";
426 };
427
58ecb23f 428 pwm: pwm@7000a000 {
140fd977
TR		 429 compatible = "nvidia,tegra20-pwm";
430 reg = <0x7000a000 0x100>;
431 #pwm-cells = <2>;
885a8cfa 432 clocks = <&tegra_car TEGRA20_CLK_PWM>;
3393d422
SW		 433 resets = <&tegra_car 17>;
434 reset-names = "pwm";
b69cd984 435 status = "disabled";
140fd977
TR		 436 };
437
58ecb23f 438 rtc@7000e000 {
380e04ac
SW		 439 compatible = "nvidia,tegra20-rtc";
440 reg = <0x7000e000 0x100>;
6cecf916 441 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 442 clocks = <&tegra_car TEGRA20_CLK_RTC>;
380e04ac
SW		 443 };
444
c04abb3a 445 i2c@7000c000 {
c04abb3a
SW		 446 compatible = "nvidia,tegra20-i2c";
447 reg = <0x7000c000 0x100>;
6cecf916 448 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 449 #address-cells = <1>;
450 #size-cells = <0>;
885a8cfa
HD		 451 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
452 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 453 clock-names = "div-clk", "fast-clk";
3393d422
SW		 454 resets = <&tegra_car 12>;
455 reset-names = "i2c";
034d023f
SW		 456 dmas = <&apbdma 21>, <&apbdma 21>;
457 dma-names = "rx", "tx";
223ef78d 458 status = "disabled";
0c6700ab
OJ		 459 };
460
fa98a114
LD		 461 spi@7000c380 {
462 compatible = "nvidia,tegra20-sflash";
463 reg = <0x7000c380 0x80>;
6cecf916 464 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
fa98a114
LD		 465 #address-cells = <1>;
466 #size-cells = <0>;
885a8cfa 467 clocks = <&tegra_car TEGRA20_CLK_SPI>;
3393d422
SW		 468 resets = <&tegra_car 43>;
469 reset-names = "spi";
034d023f
SW		 470 dmas = <&apbdma 11>, <&apbdma 11>;
471 dma-names = "rx", "tx";
fa98a114
LD		 472 status = "disabled";
473 };
474
c04abb3a 475 i2c@7000c400 {
c04abb3a
SW		 476 compatible = "nvidia,tegra20-i2c";
477 reg = <0x7000c400 0x100>;
6cecf916 478 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 479 #address-cells = <1>;
480 #size-cells = <0>;
885a8cfa
HD		 481 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
482 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 483 clock-names = "div-clk", "fast-clk";
3393d422
SW		 484 resets = <&tegra_car 54>;
485 reset-names = "i2c";
034d023f
SW		 486 dmas = <&apbdma 22>, <&apbdma 22>;
487 dma-names = "rx", "tx";
223ef78d 488 status = "disabled";
8e267f3d
GL		 489 };
490
c04abb3a 491 i2c@7000c500 {
c04abb3a
SW		 492 compatible = "nvidia,tegra20-i2c";
493 reg = <0x7000c500 0x100>;
6cecf916 494 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 495 #address-cells = <1>;
496 #size-cells = <0>;
885a8cfa
HD		 497 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
498 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 499 clock-names = "div-clk", "fast-clk";
3393d422
SW		 500 resets = <&tegra_car 67>;
501 reset-names = "i2c";
034d023f
SW		 502 dmas = <&apbdma 23>, <&apbdma 23>;
503 dma-names = "rx", "tx";
223ef78d 504 status = "disabled";
8e267f3d
GL		 505 };
506
c04abb3a 507 i2c@7000d000 {
c04abb3a
SW		 508 compatible = "nvidia,tegra20-i2c-dvc";
509 reg = <0x7000d000 0x200>;
6cecf916 510 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 511 #address-cells = <1>;
512 #size-cells = <0>;
885a8cfa
HD		 513 clocks = <&tegra_car TEGRA20_CLK_DVC>,
514 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 515 clock-names = "div-clk", "fast-clk";
3393d422
SW		 516 resets = <&tegra_car 47>;
517 reset-names = "i2c";
034d023f
SW		 518 dmas = <&apbdma 24>, <&apbdma 24>;
519 dma-names = "rx", "tx";
223ef78d 520 status = "disabled";
8e267f3d
GL		 521 };
522
a86b0db3
LD		 523 spi@7000d400 {
524 compatible = "nvidia,tegra20-slink";
525 reg = <0x7000d400 0x200>;
6cecf916 526 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 527 #address-cells = <1>;
528 #size-cells = <0>;
885a8cfa 529 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
3393d422
SW		 530 resets = <&tegra_car 41>;
531 reset-names = "spi";
034d023f
SW		 532 dmas = <&apbdma 15>, <&apbdma 15>;
533 dma-names = "rx", "tx";
a86b0db3
LD		 534 status = "disabled";
535 };
536
537 spi@7000d600 {
538 compatible = "nvidia,tegra20-slink";
539 reg = <0x7000d600 0x200>;
6cecf916 540 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 541 #address-cells = <1>;
542 #size-cells = <0>;
885a8cfa 543 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
3393d422
SW		 544 resets = <&tegra_car 44>;
545 reset-names = "spi";
034d023f
SW		 546 dmas = <&apbdma 16>, <&apbdma 16>;
547 dma-names = "rx", "tx";
a86b0db3
LD		 548 status = "disabled";
549 };
550
551 spi@7000d800 {
552 compatible = "nvidia,tegra20-slink";
57471c8d 553 reg = <0x7000d800 0x200>;
6cecf916 554 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 555 #address-cells = <1>;
556 #size-cells = <0>;
885a8cfa 557 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
3393d422
SW		 558 resets = <&tegra_car 46>;
559 reset-names = "spi";
034d023f
SW		 560 dmas = <&apbdma 17>, <&apbdma 17>;
561 dma-names = "rx", "tx";
a86b0db3
LD		 562 status = "disabled";
563 };
564
565 spi@7000da00 {
566 compatible = "nvidia,tegra20-slink";
567 reg = <0x7000da00 0x200>;
6cecf916 568 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 569 #address-cells = <1>;
570 #size-cells = <0>;
885a8cfa 571 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
3393d422
SW		 572 resets = <&tegra_car 68>;
573 reset-names = "spi";
034d023f
SW		 574 dmas = <&apbdma 18>, <&apbdma 18>;
575 dma-names = "rx", "tx";
a86b0db3
LD		 576 status = "disabled";
577 };
578
58ecb23f 579 kbc@7000e200 {
699ed4b9
LD		 580 compatible = "nvidia,tegra20-kbc";
581 reg = <0x7000e200 0x100>;
6cecf916 582 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 583 clocks = <&tegra_car TEGRA20_CLK_KBC>;
3393d422
SW		 584 resets = <&tegra_car 36>;
585 reset-names = "kbc";
699ed4b9
LD		 586 status = "disabled";
587 };
588
58ecb23f 589 pmc@7000e400 {
c04abb3a
SW		 590 compatible = "nvidia,tegra20-pmc";
591 reg = <0x7000e400 0x400>;
885a8cfa 592 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
7021d122 593 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 594 };
595
bbfc33bd 596 memory-controller@7000f000 {
c04abb3a
SW		 597 compatible = "nvidia,tegra20-mc";
598 reg = <0x7000f000 0x024
599 0x7000f03c 0x3c4>;
6cecf916 600 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a
SW		 601 };
602
58ecb23f 603 iommu@7000f024 {
c04abb3a
SW		 604 compatible = "nvidia,tegra20-gart";
605 reg = <0x7000f024 0x00000018 /* controller registers */
606 0x58000000 0x02000000>; /* GART aperture */
607 };
608
bbfc33bd 609 memory-controller@7000f400 {
c04abb3a
SW		 610 compatible = "nvidia,tegra20-emc";
611 reg = <0x7000f400 0x200>;
2eaab06e
SW		 612 #address-cells = <1>;
613 #size-cells = <0>;
8e267f3d 614 };
c27317c0 615
155dfc7b
PDS		 616 fuse@7000f800 {
617 compatible = "nvidia,tegra20-efuse";
5431b0fd 618 reg = <0x7000f800 0x400>;
155dfc7b
PDS		 619 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
620 clock-names = "fuse";
621 resets = <&tegra_car 39>;
622 reset-names = "fuse";
623 };
624
508d690e 625 pcie@80003000 {
1b62b611
TR		 626 compatible = "nvidia,tegra20-pcie";
627 device_type = "pci";
628 reg = <0x80003000 0x00000800 /* PADS registers */
629 0x80003800 0x00000200 /* AFI registers */
630 0x90000000 0x10000000>; /* configuration space */
631 reg-names = "pads", "afi", "cs";
632 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
633 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
634 interrupt-names = "intr", "msi";
635
97070bd4
LS		 636 #interrupt-cells = <1>;
637 interrupt-map-mask = <0 0 0 0>;
638 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
639
1b62b611
TR		 640 bus-range = <0x00 0xff>;
641 #address-cells = <3>;
642 #size-cells = <2>;
643
644 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
645 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
646 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 647 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
648 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
1b62b611
TR		 649
650 clocks = <&tegra_car TEGRA20_CLK_PEX>,
651 <&tegra_car TEGRA20_CLK_AFI>,
1b62b611 652 <&tegra_car TEGRA20_CLK_PLL_E>;
2bd541ff 653 clock-names = "pex", "afi", "pll_e";
3393d422 654 resets = <&tegra_car 70>,
d8b316b2
MZ		 655 <&tegra_car 72>,
656 <&tegra_car 74>;
3393d422 657 reset-names = "pex", "afi", "pcie_x";
1b62b611
TR		 658 status = "disabled";
659
660 pci@1,0 {
661 device_type = "pci";
662 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
663 reg = <0x000800 0 0 0 0>;
508d690e 664 bus-range = <0x00 0xff>;
1b62b611
TR		 665 status = "disabled";
666
667 #address-cells = <3>;
668 #size-cells = <2>;
669 ranges;
670
671 nvidia,num-lanes = <2>;
672 };
673
674 pci@2,0 {
675 device_type = "pci";
676 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
677 reg = <0x001000 0 0 0 0>;
508d690e 678 bus-range = <0x00 0xff>;
1b62b611
TR		 679 status = "disabled";
680
681 #address-cells = <3>;
682 #size-cells = <2>;
683 ranges;
684
685 nvidia,num-lanes = <2>;
686 };
687 };
688
c27317c0
OJ		 689 usb@c5000000 {
690 compatible = "nvidia,tegra20-ehci", "usb-ehci";
691 reg = <0xc5000000 0x4000>;
6cecf916 692 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 693 phy_type = "utmi";
ba202f15 694 nvidia,has-legacy-mode;
885a8cfa 695 clocks = <&tegra_car TEGRA20_CLK_USBD>;
3393d422
SW		 696 resets = <&tegra_car 22>;
697 reset-names = "usb";
b4e07478 698 nvidia,needs-double-reset;
e374b65c 699 nvidia,phy = <&phy1>;
223ef78d 700 status = "disabled";
c27317c0
OJ		 701 };
702
4c94c8b5 703 phy1: usb-phy@c5000000 {
5d324410 704 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 705 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
5d324410 706 phy_type = "utmi";
885a8cfa
HD		 707 clocks = <&tegra_car TEGRA20_CLK_USBD>,
708 <&tegra_car TEGRA20_CLK_PLL_U>,
709 <&tegra_car TEGRA20_CLK_CLK_M>,
710 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 711 clock-names = "reg", "pll_u", "timer", "utmi-pads";
308efde2
TT		 712 resets = <&tegra_car 22>, <&tegra_car 22>;
713 reset-names = "usb", "utmi-pads";
5d324410 714 nvidia,has-legacy-mode;
c49667e5
MP		 715 nvidia,hssync-start-delay = <9>;
716 nvidia,idle-wait-delay = <17>;
717 nvidia,elastic-limit = <16>;
718 nvidia,term-range-adj = <6>;
719 nvidia,xcvr-setup = <9>;
720 nvidia,xcvr-lsfslew = <1>;
721 nvidia,xcvr-lsrslew = <1>;
308efde2 722 nvidia,has-utmi-pad-registers;
4c94c8b5 723 status = "disabled";
5d324410
SW		 724 };
725
c27317c0
OJ		 726 usb@c5004000 {
727 compatible = "nvidia,tegra20-ehci", "usb-ehci";
728 reg = <0xc5004000 0x4000>;
6cecf916 729 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 730 phy_type = "ulpi";
885a8cfa 731 clocks = <&tegra_car TEGRA20_CLK_USB2>;
3393d422
SW		 732 resets = <&tegra_car 58>;
733 reset-names = "usb";
e374b65c 734 nvidia,phy = <&phy2>;
223ef78d 735 status = "disabled";
c27317c0
OJ		 736 };
737
4c94c8b5 738 phy2: usb-phy@c5004000 {
5d324410 739 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 740 reg = <0xc5004000 0x4000>;
5d324410 741 phy_type = "ulpi";
885a8cfa
HD		 742 clocks = <&tegra_car TEGRA20_CLK_USB2>,
743 <&tegra_car TEGRA20_CLK_PLL_U>,
9bf4e370 744 <&tegra_car TEGRA20_CLK_CDEV2>;
4c94c8b5 745 clock-names = "reg", "pll_u", "ulpi-link";
308efde2
TT		 746 resets = <&tegra_car 58>, <&tegra_car 22>;
747 reset-names = "usb", "utmi-pads";
4c94c8b5 748 status = "disabled";
5d324410
SW		 749 };
750
c27317c0
OJ		 751 usb@c5008000 {
752 compatible = "nvidia,tegra20-ehci", "usb-ehci";
753 reg = <0xc5008000 0x4000>;
6cecf916 754 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 755 phy_type = "utmi";
885a8cfa 756 clocks = <&tegra_car TEGRA20_CLK_USB3>;
3393d422
SW		 757 resets = <&tegra_car 59>;
758 reset-names = "usb";
e374b65c 759 nvidia,phy = <&phy3>;
223ef78d 760 status = "disabled";
c27317c0 761 };
7868a9bc 762
4c94c8b5 763 phy3: usb-phy@c5008000 {
5d324410 764 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 765 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
5d324410 766 phy_type = "utmi";
885a8cfa
HD		 767 clocks = <&tegra_car TEGRA20_CLK_USB3>,
768 <&tegra_car TEGRA20_CLK_PLL_U>,
769 <&tegra_car TEGRA20_CLK_CLK_M>,
770 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 771 clock-names = "reg", "pll_u", "timer", "utmi-pads";
308efde2
TT		 772 resets = <&tegra_car 59>, <&tegra_car 22>;
773 reset-names = "usb", "utmi-pads";
c49667e5
MP		 774 nvidia,hssync-start-delay = <9>;
775 nvidia,idle-wait-delay = <17>;
776 nvidia,elastic-limit = <16>;
777 nvidia,term-range-adj = <6>;
778 nvidia,xcvr-setup = <9>;
779 nvidia,xcvr-lsfslew = <2>;
780 nvidia,xcvr-lsrslew = <2>;
4c94c8b5 781 status = "disabled";
5d324410
SW		 782 };
783
c04abb3a
SW		 784 sdhci@c8000000 {
785 compatible = "nvidia,tegra20-sdhci";
786 reg = <0xc8000000 0x200>;
6cecf916 787 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 788 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
3393d422
SW		 789 resets = <&tegra_car 14>;
790 reset-names = "sdhci";
223ef78d 791 status = "disabled";
7868a9bc 792 };
4a82f2b3 793
c04abb3a
SW		 794 sdhci@c8000200 {
795 compatible = "nvidia,tegra20-sdhci";
796 reg = <0xc8000200 0x200>;
6cecf916 797 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 798 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
3393d422
SW		 799 resets = <&tegra_car 9>;
800 reset-names = "sdhci";
223ef78d 801 status = "disabled";
4a82f2b3 802 };
6a943e0e 803
c04abb3a
SW		 804 sdhci@c8000400 {
805 compatible = "nvidia,tegra20-sdhci";
806 reg = <0xc8000400 0x200>;
6cecf916 807 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 808 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
3393d422
SW		 809 resets = <&tegra_car 69>;
810 reset-names = "sdhci";
223ef78d 811 status = "disabled";
c04abb3a
SW		 812 };
813
814 sdhci@c8000600 {
815 compatible = "nvidia,tegra20-sdhci";
816 reg = <0xc8000600 0x200>;
6cecf916 817 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 818 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
3393d422
SW		 819 resets = <&tegra_car 15>;
820 reset-names = "sdhci";
223ef78d 821 status = "disabled";
c04abb3a
SW		 822 };
823
4dd2bd37
HD		 824 cpus {
825 #address-cells = <1>;
826 #size-cells = <0>;
827
828 cpu@0 {
829 device_type = "cpu";
830 compatible = "arm,cortex-a9";
831 reg = <0>;
832 };
833
834 cpu@1 {
835 device_type = "cpu";
836 compatible = "arm,cortex-a9";
837 reg = <1>;
838 };
839 };
840
c04abb3a
SW		 841 pmu {
842 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 843 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
844 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6a943e0e 845 };
8e267f3d 846};
Linux 6.x block layer and io_uring tree(s)