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License cleanup: add SPDX GPL-2.0 license identifier to files with no license
[linux-2.6-block.git] / arch / arm / boot / dts / tegra20-harmony.dts
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
8e267f3d
GL		 2/dts-v1/;
3
6bccbd5e 4#include <dt-bindings/input/input.h>
1bd0bd49 5#include "tegra20.dtsi"
8e267f3d
GL		 6
7/ {
8fef5dff 8 model = "NVIDIA Tegra20 Harmony evaluation board";
8e267f3d
GL		 9 compatible = "nvidia,harmony", "nvidia,tegra20";
10
553c0a20
SW		 11 aliases {
12 rtc0 = "/i2c@7000d000/tps6586x@34";
13 rtc1 = "/rtc@7000e000";
c4574aa0 14 serial0 = &uartd;
553c0a20
SW		 15 };
16
f5bbb327
JH		 17 chosen {
18 stdout-path = "serial0:115200n8";
19 };
20
f9eb26a4 21 memory {
95decf84 22 reg = <0x00000000 0x40000000>;
8e267f3d
GL		 23 };
24
58ecb23f 25 host1x@50000000 {
1d4e0689
TR		 26 dc@54200000 {
27 rgb {
28 status = "okay";
29
30 nvidia,panel = <&panel>;
31 };
32 };
33
58ecb23f 34 hdmi@54280000 {
20ffbd7d
SW		 35 status = "okay";
36
ad0acf78 37 hdmi-supply = <&vdd_5v0_hdmi>;
20ffbd7d
SW		 38 vdd-supply = <&hdmi_vdd_reg>;
39 pll-supply = <&hdmi_pll_reg>;
40
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
3325f1bc
SW		 42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
43 GPIO_ACTIVE_HIGH>;
20ffbd7d
SW		 44 };
45 };
46
58ecb23f 47 pinmux@70000014 {
ecc295bb
SW		 48 pinctrl-names = "default";
49 pinctrl-0 = <&state_default>;
50
51 state_default: pinmux {
52 ata {
53 nvidia,pins = "ata";
54 nvidia,function = "ide";
55 };
56 atb {
57 nvidia,pins = "atb", "gma", "gme";
58 nvidia,function = "sdio4";
59 };
60 atc {
61 nvidia,pins = "atc";
62 nvidia,function = "nand";
63 };
64 atd {
65 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
66 "spia", "spib", "spic";
67 nvidia,function = "gmi";
68 };
69 cdev1 {
70 nvidia,pins = "cdev1";
71 nvidia,function = "plla_out";
72 };
73 cdev2 {
74 nvidia,pins = "cdev2";
75 nvidia,function = "pllp_out4";
76 };
77 crtp {
78 nvidia,pins = "crtp";
79 nvidia,function = "crt";
80 };
81 csus {
82 nvidia,pins = "csus";
83 nvidia,function = "vi_sensor_clk";
84 };
85 dap1 {
86 nvidia,pins = "dap1";
87 nvidia,function = "dap1";
88 };
89 dap2 {
90 nvidia,pins = "dap2";
91 nvidia,function = "dap2";
92 };
93 dap3 {
94 nvidia,pins = "dap3";
95 nvidia,function = "dap3";
96 };
97 dap4 {
98 nvidia,pins = "dap4";
99 nvidia,function = "dap4";
100 };
101 ddc {
102 nvidia,pins = "ddc";
103 nvidia,function = "i2c2";
104 };
105 dta {
106 nvidia,pins = "dta", "dtd";
107 nvidia,function = "sdio2";
108 };
109 dtb {
110 nvidia,pins = "dtb", "dtc", "dte";
111 nvidia,function = "rsvd1";
112 };
113 dtf {
114 nvidia,pins = "dtf";
115 nvidia,function = "i2c3";
116 };
117 gmc {
118 nvidia,pins = "gmc";
119 nvidia,function = "uartd";
120 };
121 gpu7 {
122 nvidia,pins = "gpu7";
123 nvidia,function = "rtck";
124 };
125 gpv {
126 nvidia,pins = "gpv", "slxa", "slxk";
127 nvidia,function = "pcie";
128 };
129 hdint {
130 nvidia,pins = "hdint", "pta";
131 nvidia,function = "hdmi";
132 };
133 i2cp {
134 nvidia,pins = "i2cp";
135 nvidia,function = "i2cp";
136 };
137 irrx {
138 nvidia,pins = "irrx", "irtx";
139 nvidia,function = "uarta";
140 };
141 kbca {
142 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
143 "kbce", "kbcf";
144 nvidia,function = "kbc";
145 };
146 lcsn {
147 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
148 "ld3", "ld4", "ld5", "ld6", "ld7",
149 "ld8", "ld9", "ld10", "ld11", "ld12",
150 "ld13", "ld14", "ld15", "ld16", "ld17",
151 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
152 "lhs", "lm0", "lm1", "lpp", "lpw0",
153 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
154 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
155 "lvs";
156 nvidia,function = "displaya";
157 };
158 owc {
159 nvidia,pins = "owc", "spdi", "spdo", "uac";
160 nvidia,function = "rsvd2";
161 };
162 pmc {
163 nvidia,pins = "pmc";
164 nvidia,function = "pwr_on";
165 };
166 rm {
167 nvidia,pins = "rm";
168 nvidia,function = "i2c1";
169 };
170 sdb {
171 nvidia,pins = "sdb", "sdc", "sdd";
172 nvidia,function = "pwm";
173 };
174 sdio1 {
175 nvidia,pins = "sdio1";
176 nvidia,function = "sdio1";
177 };
178 slxc {
179 nvidia,pins = "slxc", "slxd";
180 nvidia,function = "spdif";
181 };
182 spid {
183 nvidia,pins = "spid", "spie", "spif";
184 nvidia,function = "spi1";
185 };
186 spig {
187 nvidia,pins = "spig", "spih";
188 nvidia,function = "spi2_alt";
189 };
190 uaa {
191 nvidia,pins = "uaa", "uab", "uda";
192 nvidia,function = "ulpi";
193 };
194 uad {
195 nvidia,pins = "uad";
196 nvidia,function = "irda";
197 };
198 uca {
199 nvidia,pins = "uca", "ucb";
200 nvidia,function = "uartc";
201 };
202 conf_ata {
203 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
563da21b
SW		 204 "cdev1", "cdev2", "dap1", "dtb", "gma",
205 "gmb", "gmc", "gmd", "gme", "gpu7",
206 "gpv", "i2cp", "pta", "rm", "slxa",
207 "slxk", "spia", "spib", "uac";
ba4104e7
LD		 208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
209 nvidia,tristate = <TEGRA_PIN_DISABLE>;
ecc295bb 210 };
ecc295bb
SW		 211 conf_ck32 {
212 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
213 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
ba4104e7 214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ecc295bb 215 };
563da21b
SW		 216 conf_csus {
217 nvidia,pins = "csus", "spid", "spif";
ba4104e7
LD		 218 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
219 nvidia,tristate = <TEGRA_PIN_ENABLE>;
563da21b 220 };
ecc295bb
SW		 221 conf_crtp {
222 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
223 "dtc", "dte", "dtf", "gpu", "sdio1",
224 "slxc", "slxd", "spdi", "spdo", "spig",
563da21b 225 "uda";
ba4104e7
LD		 226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227 nvidia,tristate = <TEGRA_PIN_ENABLE>;
ecc295bb
SW		 228 };
229 conf_ddc {
230 nvidia,pins = "ddc", "dta", "dtd", "kbca",
231 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
232 "sdc";
ba4104e7
LD		 233 nvidia,pull = <TEGRA_PIN_PULL_UP>;
234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
ecc295bb
SW		 235 };
236 conf_hdint {
237 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
238 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
239 "lvp0", "owc", "sdb";
ba4104e7 240 nvidia,tristate = <TEGRA_PIN_ENABLE>;
ecc295bb
SW		 241 };
242 conf_irrx {
243 nvidia,pins = "irrx", "irtx", "sdd", "spic",
244 "spie", "spih", "uaa", "uab", "uad",
245 "uca", "ucb";
ba4104e7
LD		 246 nvidia,pull = <TEGRA_PIN_PULL_UP>;
247 nvidia,tristate = <TEGRA_PIN_ENABLE>;
ecc295bb
SW		 248 };
249 conf_lc {
250 nvidia,pins = "lc", "ls";
ba4104e7 251 nvidia,pull = <TEGRA_PIN_PULL_UP>;
ecc295bb
SW		 252 };
253 conf_ld0 {
254 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
255 "ld5", "ld6", "ld7", "ld8", "ld9",
256 "ld10", "ld11", "ld12", "ld13", "ld14",
257 "ld15", "ld16", "ld17", "ldi", "lhp0",
258 "lhp1", "lhp2", "lhs", "lm0", "lpp",
259 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
260 "lvs", "pmc";
ba4104e7 261 nvidia,tristate = <TEGRA_PIN_DISABLE>;
ecc295bb
SW		 262 };
263 conf_ld17_0 {
264 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
265 "ld23_22";
ba4104e7 266 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
ecc295bb
SW		 267 };
268 };
269 };
270
2a5fdc9a
SW		 271 i2s@70002800 {
272 status = "okay";
c04abb3a
SW		 273 };
274
275 serial@70006300 {
2a5fdc9a 276 status = "okay";
c04abb3a
SW		 277 };
278
1d4e0689
TR		 279 pwm: pwm@7000a000 {
280 status = "okay";
281 };
282
8e267f3d 283 i2c@7000c000 {
2a5fdc9a 284 status = "okay";
8e267f3d
GL		 285 clock-frequency = <400000>;
286
797acf70 287 wm8903: wm8903@1a {
8e267f3d
GL		 288 compatible = "wlf,wm8903";
289 reg = <0x1a>;
797acf70 290 interrupt-parent = <&gpio>;
6cecf916 291 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
8e267f3d
GL		 292
293 gpio-controller;
294 #gpio-cells = <2>;
295
797acf70
SW		 296 micdet-cfg = <0>;
297 micdet-delay = <100>;
95decf84 298 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
8e267f3d
GL		 299 };
300 };
301
20ffbd7d 302 hdmi_ddc: i2c@7000c400 {
2a5fdc9a 303 status = "okay";
20ffbd7d 304 clock-frequency = <100000>;
8e267f3d
GL		 305 };
306
307 i2c@7000c500 {
2a5fdc9a 308 status = "okay";
8e267f3d
GL		 309 clock-frequency = <400000>;
310 };
311
312 i2c@7000d000 {
2a5fdc9a 313 status = "okay";
8e267f3d 314 clock-frequency = <400000>;
3cc404de
LD		 315
316 pmic: tps6586x@34 {
317 compatible = "ti,tps6586x";
318 reg = <0x34>;
6cecf916 319 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
3cc404de 320
be972c32
SW		 321 ti,system-power-controller;
322
3cc404de
LD		 323 #gpio-cells = <2>;
324 gpio-controller;
325
326 sys-supply = <&vdd_5v0_reg>;
327 vin-sm0-supply = <&sys_reg>;
328 vin-sm1-supply = <&sys_reg>;
329 vin-sm2-supply = <&sys_reg>;
330 vinldo01-supply = <&sm2_reg>;
331 vinldo23-supply = <&sm2_reg>;
332 vinldo4-supply = <&sm2_reg>;
333 vinldo678-supply = <&sm2_reg>;
334 vinldo9-supply = <&sm2_reg>;
335
336 regulators {
b9c665d7 337 sys_reg: sys {
3cc404de
LD		 338 regulator-name = "vdd_sys";
339 regulator-always-on;
340 };
341
b9c665d7 342 sm0 {
3cc404de
LD		 343 regulator-name = "vdd_sm0,vdd_core";
344 regulator-min-microvolt = <1200000>;
345 regulator-max-microvolt = <1200000>;
346 regulator-always-on;
347 };
348
b9c665d7 349 sm1 {
3cc404de
LD		 350 regulator-name = "vdd_sm1,vdd_cpu";
351 regulator-min-microvolt = <1000000>;
352 regulator-max-microvolt = <1000000>;
353 regulator-always-on;
354 };
355
b9c665d7 356 sm2_reg: sm2 {
3cc404de
LD		 357 regulator-name = "vdd_sm2,vin_ldo*";
358 regulator-min-microvolt = <3700000>;
359 regulator-max-microvolt = <3700000>;
360 regulator-always-on;
361 };
362
722afc17 363 pci_clk_reg: ldo0 {
3cc404de
LD		 364 regulator-name = "vdd_ldo0,vddio_pex_clk";
365 regulator-min-microvolt = <3300000>;
366 regulator-max-microvolt = <3300000>;
367 };
368
b9c665d7 369 ldo1 {
3cc404de
LD		 370 regulator-name = "vdd_ldo1,avdd_pll*";
371 regulator-min-microvolt = <1100000>;
372 regulator-max-microvolt = <1100000>;
373 regulator-always-on;
374 };
375
b9c665d7 376 ldo2 {
3cc404de
LD		 377 regulator-name = "vdd_ldo2,vdd_rtc";
378 regulator-min-microvolt = <1200000>;
379 regulator-max-microvolt = <1200000>;
380 };
381
b9c665d7 382 ldo3 {
3cc404de
LD		 383 regulator-name = "vdd_ldo3,avdd_usb*";
384 regulator-min-microvolt = <3300000>;
385 regulator-max-microvolt = <3300000>;
386 regulator-always-on;
387 };
388
b9c665d7 389 ldo4 {
3cc404de
LD		 390 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
391 regulator-min-microvolt = <1800000>;
392 regulator-max-microvolt = <1800000>;
393 regulator-always-on;
394 };
395
b9c665d7 396 ldo5 {
3cc404de
LD		 397 regulator-name = "vdd_ldo5,vcore_mmc";
398 regulator-min-microvolt = <2850000>;
399 regulator-max-microvolt = <2850000>;
400 regulator-always-on;
401 };
402
b9c665d7 403 ldo6 {
3cc404de
LD		 404 regulator-name = "vdd_ldo6,avdd_vdac";
405 regulator-min-microvolt = <1800000>;
406 regulator-max-microvolt = <1800000>;
407 };
408
20ffbd7d 409 hdmi_vdd_reg: ldo7 {
740418ef 410 regulator-name = "vdd_ldo7,avdd_hdmi";
3cc404de
LD		 411 regulator-min-microvolt = <3300000>;
412 regulator-max-microvolt = <3300000>;
413 };
414
20ffbd7d 415 hdmi_pll_reg: ldo8 {
3cc404de
LD		 416 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
417 regulator-min-microvolt = <1800000>;
418 regulator-max-microvolt = <1800000>;
419 };
420
b9c665d7 421 ldo9 {
3cc404de
LD		 422 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
423 regulator-min-microvolt = <2850000>;
424 regulator-max-microvolt = <2850000>;
425 regulator-always-on;
426 };
427
b9c665d7 428 ldo_rtc {
3cc404de
LD		 429 regulator-name = "vdd_rtc_out,vdd_cell";
430 regulator-min-microvolt = <3300000>;
431 regulator-max-microvolt = <3300000>;
432 regulator-always-on;
433 };
434 };
435 };
42d2534a
TR		 436
437 temperature-sensor@4c {
438 compatible = "adi,adt7461";
439 reg = <0x4c>;
440 };
8e267f3d
GL		 441 };
442
58ecb23f 443 kbc@7000e200 {
c0967ce0
LD		 444 status = "okay";
445 nvidia,debounce-delay-ms = <2>;
446 nvidia,repeat-delay-ms = <160>;
447 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
448 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
6bccbd5e
LD		 449 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
450 MATRIX_KEY(0x00, 0x03, KEY_S)
451 MATRIX_KEY(0x00, 0x04, KEY_A)
452 MATRIX_KEY(0x00, 0x05, KEY_Z)
453 MATRIX_KEY(0x00, 0x07, KEY_FN)
454 MATRIX_KEY(0x01, 0x07, KEY_MENU)
455 MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
456 MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
457 MATRIX_KEY(0x03, 0x00, KEY_5)
458 MATRIX_KEY(0x03, 0x01, KEY_4)
459 MATRIX_KEY(0x03, 0x02, KEY_R)
460 MATRIX_KEY(0x03, 0x03, KEY_E)
461 MATRIX_KEY(0x03, 0x04, KEY_F)
462 MATRIX_KEY(0x03, 0x05, KEY_D)
463 MATRIX_KEY(0x03, 0x06, KEY_X)
464 MATRIX_KEY(0x04, 0x00, KEY_7)
465 MATRIX_KEY(0x04, 0x01, KEY_6)
466 MATRIX_KEY(0x04, 0x02, KEY_T)
467 MATRIX_KEY(0x04, 0x03, KEY_H)
468 MATRIX_KEY(0x04, 0x04, KEY_G)
469 MATRIX_KEY(0x04, 0x05, KEY_V)
470 MATRIX_KEY(0x04, 0x06, KEY_C)
471 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
472 MATRIX_KEY(0x05, 0x00, KEY_9)
473 MATRIX_KEY(0x05, 0x01, KEY_8)
474 MATRIX_KEY(0x05, 0x02, KEY_U)
475 MATRIX_KEY(0x05, 0x03, KEY_Y)
476 MATRIX_KEY(0x05, 0x04, KEY_J)
477 MATRIX_KEY(0x05, 0x05, KEY_N)
478 MATRIX_KEY(0x05, 0x06, KEY_B)
479 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
480 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
481 MATRIX_KEY(0x06, 0x01, KEY_0)
482 MATRIX_KEY(0x06, 0x02, KEY_O)
483 MATRIX_KEY(0x06, 0x03, KEY_I)
484 MATRIX_KEY(0x06, 0x04, KEY_L)
485 MATRIX_KEY(0x06, 0x05, KEY_K)
486 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
487 MATRIX_KEY(0x06, 0x07, KEY_M)
488 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
489 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
490 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
491 MATRIX_KEY(0x07, 0x07, KEY_MENU)
492 MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
493 MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
494 MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
495 MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
496 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
497 MATRIX_KEY(0x0B, 0x01, KEY_P)
498 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
499 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
500 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
501 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
502 MATRIX_KEY(0x0C, 0x00, KEY_F10)
503 MATRIX_KEY(0x0C, 0x01, KEY_F9)
504 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
505 MATRIX_KEY(0x0C, 0x03, KEY_3)
506 MATRIX_KEY(0x0C, 0x04, KEY_2)
507 MATRIX_KEY(0x0C, 0x05, KEY_UP)
508 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
509 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
510 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
511 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
512 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
513 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
514 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
515 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
516 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
517 MATRIX_KEY(0x0E, 0x00, KEY_F11)
518 MATRIX_KEY(0x0E, 0x01, KEY_F12)
519 MATRIX_KEY(0x0E, 0x02, KEY_F8)
520 MATRIX_KEY(0x0E, 0x03, KEY_Q)
521 MATRIX_KEY(0x0E, 0x04, KEY_F4)
522 MATRIX_KEY(0x0E, 0x05, KEY_F3)
523 MATRIX_KEY(0x0E, 0x06, KEY_1)
524 MATRIX_KEY(0x0E, 0x07, KEY_F7)
525 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
526 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
527 MATRIX_KEY(0x0F, 0x02, KEY_F5)
528 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
529 MATRIX_KEY(0x0F, 0x04, KEY_F1)
530 MATRIX_KEY(0x0F, 0x05, KEY_F2)
531 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
532 MATRIX_KEY(0x0F, 0x07, KEY_F6)
533 MATRIX_KEY(0x14, 0x00, KEY_KP7)
534 MATRIX_KEY(0x15, 0x00, KEY_KP9)
535 MATRIX_KEY(0x15, 0x01, KEY_KP8)
536 MATRIX_KEY(0x15, 0x02, KEY_KP4)
537 MATRIX_KEY(0x15, 0x04, KEY_KP1)
538 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
539 MATRIX_KEY(0x16, 0x02, KEY_KP6)
540 MATRIX_KEY(0x16, 0x03, KEY_KP5)
541 MATRIX_KEY(0x16, 0x04, KEY_KP3)
542 MATRIX_KEY(0x16, 0x05, KEY_KP2)
543 MATRIX_KEY(0x16, 0x07, KEY_KP0)
544 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
545 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
546 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
547 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
548 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
549 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
550 MATRIX_KEY(0x1D, 0x04, KEY_END)
551 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
552 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
553 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
554 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
555 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
556 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
557 MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
c0967ce0
LD		 558 };
559
57899053
SW		 560 pmc@7000e400 {
561 nvidia,invert-interrupt;
562 nvidia,suspend-mode = <1>;
563 nvidia,cpu-pwr-good-time = <5000>;
564 nvidia,cpu-pwr-off-time = <5000>;
565 nvidia,core-pwr-good-time = <3845 3845>;
566 nvidia,core-pwr-off-time = <3875>;
567 nvidia,sys-clock-req-active-high;
568 };
569
508d690e 570 pcie@80003000 {
cca8614d
TR		 571 status = "okay";
572
573 avdd-pex-supply = <&pci_vdd_reg>;
574 vdd-pex-supply = <&pci_vdd_reg>;
575 avdd-pex-pll-supply = <&pci_vdd_reg>;
576 avdd-plle-supply = <&pci_vdd_reg>;
577 vddio-pex-clk-supply = <&pci_clk_reg>;
578
57899053
SW		 579 pci@1,0 {
580 status = "okay";
581 };
582
583 pci@2,0 {
584 status = "okay";
585 };
586 };
587
588 usb@c5000000 {
589 status = "okay";
590 };
591
592 usb-phy@c5000000 {
593 status = "okay";
594 };
595
596 usb@c5004000 {
597 status = "okay";
598 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
599 GPIO_ACTIVE_LOW>;
600 };
601
602 usb-phy@c5004000 {
603 status = "okay";
604 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
605 GPIO_ACTIVE_LOW>;
606 };
607
608 usb@c5008000 {
609 status = "okay";
610 };
611
612 usb-phy@c5008000 {
613 status = "okay";
614 };
615
616 sdhci@c8000200 {
617 status = "okay";
618 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
619 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
620 power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
621 bus-width = <4>;
622 };
623
624 sdhci@c8000600 {
625 status = "okay";
626 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
627 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
628 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
629 bus-width = <8>;
630 };
631
1d4e0689
TR		 632 backlight: backlight {
633 compatible = "pwm-backlight";
634
635 enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
636 power-supply = <&vdd_bl_reg>;
637 pwms = <&pwm 0 5000000>;
638
639 brightness-levels = <0 4 8 16 32 64 128 255>;
640 default-brightness-level = <6>;
641 };
642
57899053
SW		 643 clocks {
644 compatible = "simple-bus";
645 #address-cells = <1>;
646 #size-cells = <0>;
647
648 clk32k_in: clock@0 {
649 compatible = "fixed-clock";
4ec2e601 650 reg = <0>;
57899053
SW		 651 #clock-cells = <0>;
652 clock-frequency = <32768>;
653 };
654 };
655
656 gpio-keys {
657 compatible = "gpio-keys";
658
659 power {
660 label = "Power";
661 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
6bccbd5e 662 linux,code = <KEY_POWER>;
d1c04d30 663 wakeup-source;
57899053
SW		 664 };
665 };
666
1d4e0689
TR		 667 panel: panel {
668 compatible = "auo,b101aw03", "simple-panel";
669
670 power-supply = <&vdd_pnl_reg>;
671 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
672
673 backlight = <&backlight>;
674 };
675
3cc404de
LD		 676 regulators {
677 compatible = "simple-bus";
678 #address-cells = <1>;
679 #size-cells = <0>;
680
681 vdd_5v0_reg: regulator@0 {
682 compatible = "regulator-fixed";
683 reg = <0>;
684 regulator-name = "vdd_5v0";
685 regulator-min-microvolt = <5000000>;
686 regulator-max-microvolt = <5000000>;
687 regulator-always-on;
688 };
689
690 regulator@1 {
691 compatible = "regulator-fixed";
692 reg = <1>;
693 regulator-name = "vdd_1v5";
694 regulator-min-microvolt = <1500000>;
695 regulator-max-microvolt = <1500000>;
3325f1bc 696 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
3cc404de
LD		 697 };
698
699 regulator@2 {
700 compatible = "regulator-fixed";
701 reg = <2>;
702 regulator-name = "vdd_1v2";
703 regulator-min-microvolt = <1200000>;
704 regulator-max-microvolt = <1200000>;
3325f1bc 705 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
3cc404de
LD		 706 enable-active-high;
707 };
708
722afc17 709 pci_vdd_reg: regulator@3 {
3cc404de
LD		 710 compatible = "regulator-fixed";
711 reg = <3>;
712 regulator-name = "vdd_1v05";
713 regulator-min-microvolt = <1050000>;
714 regulator-max-microvolt = <1050000>;
3325f1bc 715 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
3cc404de 716 enable-active-high;
3cc404de
LD		 717 };
718
1d4e0689 719 vdd_pnl_reg: regulator@4 {
3cc404de
LD		 720 compatible = "regulator-fixed";
721 reg = <4>;
722 regulator-name = "vdd_pnl";
723 regulator-min-microvolt = <2800000>;
724 regulator-max-microvolt = <2800000>;
3325f1bc 725 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
3cc404de
LD		 726 enable-active-high;
727 };
728
1d4e0689 729 vdd_bl_reg: regulator@5 {
3cc404de
LD		 730 compatible = "regulator-fixed";
731 reg = <5>;
732 regulator-name = "vdd_bl";
733 regulator-min-microvolt = <2800000>;
734 regulator-max-microvolt = <2800000>;
3325f1bc 735 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
3cc404de
LD		 736 enable-active-high;
737 };
ad0acf78
TR		 738
739 vdd_5v0_hdmi: regulator@6 {
740 compatible = "regulator-fixed";
741 reg = <6>;
742 regulator-name = "VDDIO_HDMI";
743 regulator-min-microvolt = <5000000>;
744 regulator-max-microvolt = <5000000>;
745 gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>;
746 enable-active-high;
747 vin-supply = <&vdd_5v0_reg>;
748 };
3cc404de
LD		 749 };
750
c04abb3a
SW		 751 sound {
752 compatible = "nvidia,tegra-audio-wm8903-harmony",
753 "nvidia,tegra-audio-wm8903";
754 nvidia,model = "NVIDIA Tegra Harmony";
755
756 nvidia,audio-routing =
757 "Headphone Jack", "HPOUTR",
758 "Headphone Jack", "HPOUTL",
759 "Int Spk", "ROP",
760 "Int Spk", "RON",
761 "Int Spk", "LOP",
762 "Int Spk", "LON",
763 "Mic Jack", "MICBIAS",
764 "IN1L", "Mic Jack";
765
766 nvidia,i2s-controller = <&tegra_i2s1>;
767 nvidia,audio-codec = <&wm8903>;
768
3325f1bc
SW		 769 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
770 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
771 GPIO_ACTIVE_HIGH>;
772 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
773 GPIO_ACTIVE_HIGH>;
774 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
775 GPIO_ACTIVE_HIGH>;
f9cd2b3b 776
885a8cfa
HD		 777 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
778 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
779 <&tegra_car TEGRA20_CLK_CDEV1>;
f9cd2b3b 780 clock-names = "pll_a", "pll_a_out0", "mclk";
aa607ebf 781 };
8e267f3d 782};
Linux 6.x block layer and io_uring tree(s)