projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'pm-cpufreq'
[linux-2.6-block.git] / arch / arm / boot / dts / tegra114.dtsi
CommitLineData
a1c85860 1#include <dt-bindings/clock/tegra114-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
32215e71 3#include <dt-bindings/memory/tegra114-mc.h>
5fc6b0dd 4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 5#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 6
1bd0bd49 7#include "skeleton.dtsi"
18a4df70
HD		 8
9/ {
10 compatible = "nvidia,tegra114";
870c81a4 11 interrupt-parent = <&lic>;
18a4df70 12
65344b93
MP		 13 host1x@50000000 {
14 compatible = "nvidia,tegra114-host1x", "simple-bus";
15 reg = <0x50000000 0x00028000>;
16 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
17 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
18 clocks = <&tegra_car TEGRA114_CLK_HOST1X>;
19 resets = <&tegra_car 28>;
20 reset-names = "host1x";
21
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 ranges = <0x54000000 0x54000000 0x01000000>;
26
5648b260
TR		 27 gr2d@54140000 {
28 compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d";
29 reg = <0x54140000 0x00040000>;
30 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
31 clocks = <&tegra_car TEGRA114_CLK_GR2D>;
32 resets = <&tegra_car 21>;
33 reset-names = "2d";
34 };
35
032f11f3
TR		 36 gr3d@54180000 {
37 compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d";
38 reg = <0x54180000 0x00040000>;
39 clocks = <&tegra_car TEGRA114_CLK_GR3D>;
40 resets = <&tegra_car 24>;
41 reset-names = "3d";
42 };
43
65344b93
MP		 44 dc@54200000 {
45 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
46 reg = <0x54200000 0x00040000>;
47 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
48 clocks = <&tegra_car TEGRA114_CLK_DISP1>,
49 <&tegra_car TEGRA114_CLK_PLL_P>;
50 clock-names = "dc", "parent";
51 resets = <&tegra_car 27>;
52 reset-names = "dc";
53
32215e71
TR		 54 iommus = <&mc TEGRA_SWGROUP_DC>;
55
688b56b4
TR		 56 nvidia,head = <0>;
57
65344b93
MP		 58 rgb {
59 status = "disabled";
60 };
61 };
62
63 dc@54240000 {
64 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc";
65 reg = <0x54240000 0x00040000>;
66 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
67 clocks = <&tegra_car TEGRA114_CLK_DISP2>,
68 <&tegra_car TEGRA114_CLK_PLL_P>;
69 clock-names = "dc", "parent";
70 resets = <&tegra_car 26>;
71 reset-names = "dc";
72
32215e71
TR		 73 iommus = <&mc TEGRA_SWGROUP_DCB>;
74
688b56b4
TR		 75 nvidia,head = <1>;
76
65344b93
MP		 77 rgb {
78 status = "disabled";
79 };
80 };
81
82 hdmi@54280000 {
83 compatible = "nvidia,tegra114-hdmi";
84 reg = <0x54280000 0x00040000>;
85 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&tegra_car TEGRA114_CLK_HDMI>,
87 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
88 clock-names = "hdmi", "parent";
89 resets = <&tegra_car 51>;
90 reset-names = "hdmi";
91 status = "disabled";
92 };
7e4ba90f
TR		 93
94 dsi@54300000 {
95 compatible = "nvidia,tegra114-dsi";
96 reg = <0x54300000 0x00040000>;
97 clocks = <&tegra_car TEGRA114_CLK_DSIA>,
98 <&tegra_car TEGRA114_CLK_DSIALP>,
99 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>;
100 clock-names = "dsi", "lp", "parent";
101 resets = <&tegra_car 48>;
102 reset-names = "dsi";
103 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */
104 status = "disabled";
105
106 #address-cells = <1>;
107 #size-cells = <0>;
108 };
109
110 dsi@54400000 {
111 compatible = "nvidia,tegra114-dsi";
112 reg = <0x54400000 0x00040000>;
113 clocks = <&tegra_car TEGRA114_CLK_DSIB>,
114 <&tegra_car TEGRA114_CLK_DSIBLP>,
115 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>;
116 clock-names = "dsi", "lp", "parent";
117 resets = <&tegra_car 82>;
118 reset-names = "dsi";
119 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */
120 status = "disabled";
121
122 #address-cells = <1>;
123 #size-cells = <0>;
124 };
65344b93
MP		 125 };
126
58ecb23f 127 gic: interrupt-controller@50041000 {
18a4df70
HD		 128 compatible = "arm,cortex-a15-gic";
129 #interrupt-cells = <3>;
130 interrupt-controller;
131 reg = <0x50041000 0x1000>,
132 <0x50042000 0x1000>,
133 <0x50044000 0x2000>,
134 <0x50046000 0x2000>;
6cecf916
SW		 135 interrupts = <GIC_PPI 9
136 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
870c81a4
MZ		 137 interrupt-parent = <&gic>;
138 };
139
140 lic: interrupt-controller@60004000 {
141 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr";
142 reg = <0x60004000 0x100>,
143 <0x60004100 0x50>,
144 <0x60004200 0x50>,
145 <0x60004300 0x50>,
146 <0x60004400 0x50>;
147 interrupt-controller;
148 #interrupt-cells = <3>;
149 interrupt-parent = <&gic>;
18a4df70
HD		 150 };
151
152 timer@60005000 {
153 compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer";
154 reg = <0x60005000 0x400>;
6cecf916
SW		 155 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 161 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
18a4df70
HD		 162 };
163
58ecb23f 164 tegra_car: clock@60006000 {
672d889c 165 compatible = "nvidia,tegra114-car";
18a4df70
HD		 166 reg = <0x60006000 0x1000>;
167 #clock-cells = <1>;
3393d422 168 #reset-cells = <1>;
18a4df70
HD		 169 };
170
b1023134
TR		 171 flow-controller@60007000 {
172 compatible = "nvidia,tegra114-flowctrl";
173 reg = <0x60007000 0x1000>;
174 };
175
58ecb23f 176 apbdma: dma@6000a000 {
c5d9da4a
LD		 177 compatible = "nvidia,tegra114-apbdma";
178 reg = <0x6000a000 0x1400>;
6cecf916
SW		 179 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
180 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
181 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
182 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
190 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 211 clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
3393d422
SW		 212 resets = <&tegra_car 34>;
213 reset-names = "dma";
034d023f 214 #dma-cells = <1>;
c5d9da4a
LD		 215 };
216
0d5ccb38 217 ahb: ahb@6000c000 {
0dfe42ed 218 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
0d5ccb38 219 reg = <0x6000c000 0x150>;
0dfe42ed
HD		 220 };
221
58ecb23f 222 gpio: gpio@6000d000 {
b16f9183
LD		 223 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
224 reg = <0x6000d000 0x1000>;
6cecf916
SW		 225 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
b16f9183
LD		 233 #gpio-cells = <2>;
234 gpio-controller;
235 #interrupt-cells = <2>;
236 interrupt-controller;
17cdddf0 237 gpio-ranges = <&pinmux 0 0 246>;
b16f9183
LD		 238 };
239
155dfc7b
PDS		 240 apbmisc@70000800 {
241 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";
242 reg = <0x70000800 0x64 /* Chip revision */
243 0x70000008 0x04>; /* Strapping options */
244 };
245
58ecb23f 246 pinmux: pinmux@70000868 {
031b77af
LD		 247 compatible = "nvidia,tegra114-pinmux";
248 reg = <0x70000868 0x148 /* Pad control registers */
249 0x70003000 0x40c>; /* Mux registers */
250 };
251
0fb22096
LD		 252 /*
253 * There are two serial driver i.e. 8250 based simple serial
254 * driver and APB DMA based serial driver for higher baudrate
255 * and performace. To enable the 8250 based driver, the compatible
256 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
257 * the APB DMA based serial driver, the comptible is
258 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
259 */
260 uarta: serial@70006000 {
18a4df70
HD		 261 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
262 reg = <0x70006000 0x40>;
263 reg-shift = <2>;
6cecf916 264 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 265 clocks = <&tegra_car TEGRA114_CLK_UARTA>;
3393d422
SW		 266 resets = <&tegra_car 6>;
267 reset-names = "serial";
034d023f
SW		 268 dmas = <&apbdma 8>, <&apbdma 8>;
269 dma-names = "rx", "tx";
3393d422 270 status = "disabled";
18a4df70
HD		 271 };
272
0fb22096 273 uartb: serial@70006040 {
18a4df70
HD		 274 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
275 reg = <0x70006040 0x40>;
276 reg-shift = <2>;
6cecf916 277 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 278 clocks = <&tegra_car TEGRA114_CLK_UARTB>;
3393d422
SW		 279 resets = <&tegra_car 7>;
280 reset-names = "serial";
034d023f
SW		 281 dmas = <&apbdma 9>, <&apbdma 9>;
282 dma-names = "rx", "tx";
3393d422 283 status = "disabled";
18a4df70
HD		 284 };
285
0fb22096 286 uartc: serial@70006200 {
18a4df70
HD		 287 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
288 reg = <0x70006200 0x100>;
289 reg-shift = <2>;
6cecf916 290 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 291 clocks = <&tegra_car TEGRA114_CLK_UARTC>;
3393d422
SW		 292 resets = <&tegra_car 55>;
293 reset-names = "serial";
034d023f
SW		 294 dmas = <&apbdma 10>, <&apbdma 10>;
295 dma-names = "rx", "tx";
3393d422 296 status = "disabled";
18a4df70
HD		 297 };
298
0fb22096 299 uartd: serial@70006300 {
18a4df70
HD		 300 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
301 reg = <0x70006300 0x100>;
302 reg-shift = <2>;
6cecf916 303 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 304 clocks = <&tegra_car TEGRA114_CLK_UARTD>;
3393d422
SW		 305 resets = <&tegra_car 65>;
306 reset-names = "serial";
034d023f
SW		 307 dmas = <&apbdma 19>, <&apbdma 19>;
308 dma-names = "rx", "tx";
3393d422 309 status = "disabled";
18a4df70
HD		 310 };
311
58ecb23f 312 pwm: pwm@7000a000 {
6c716db5
AC		 313 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
314 reg = <0x7000a000 0x100>;
315 #pwm-cells = <2>;
a1c85860 316 clocks = <&tegra_car TEGRA114_CLK_PWM>;
3393d422
SW		 317 resets = <&tegra_car 17>;
318 reset-names = "pwm";
6c716db5
AC		 319 status = "disabled";
320 };
321
3fc2f94e
LD		 322 i2c@7000c000 {
323 compatible = "nvidia,tegra114-i2c";
324 reg = <0x7000c000 0x100>;
6cecf916 325 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 326 #address-cells = <1>;
327 #size-cells = <0>;
a1c85860 328 clocks = <&tegra_car TEGRA114_CLK_I2C1>;
3fc2f94e 329 clock-names = "div-clk";
3393d422
SW		 330 resets = <&tegra_car 12>;
331 reset-names = "i2c";
034d023f
SW		 332 dmas = <&apbdma 21>, <&apbdma 21>;
333 dma-names = "rx", "tx";
3fc2f94e
LD		 334 status = "disabled";
335 };
336
337 i2c@7000c400 {
338 compatible = "nvidia,tegra114-i2c";
339 reg = <0x7000c400 0x100>;
6cecf916 340 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 341 #address-cells = <1>;
342 #size-cells = <0>;
a1c85860 343 clocks = <&tegra_car TEGRA114_CLK_I2C2>;
3fc2f94e 344 clock-names = "div-clk";
3393d422
SW		 345 resets = <&tegra_car 54>;
346 reset-names = "i2c";
034d023f
SW		 347 dmas = <&apbdma 22>, <&apbdma 22>;
348 dma-names = "rx", "tx";
3fc2f94e
LD		 349 status = "disabled";
350 };
351
352 i2c@7000c500 {
353 compatible = "nvidia,tegra114-i2c";
354 reg = <0x7000c500 0x100>;
6cecf916 355 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 356 #address-cells = <1>;
357 #size-cells = <0>;
a1c85860 358 clocks = <&tegra_car TEGRA114_CLK_I2C3>;
3fc2f94e 359 clock-names = "div-clk";
3393d422
SW		 360 resets = <&tegra_car 67>;
361 reset-names = "i2c";
034d023f
SW		 362 dmas = <&apbdma 23>, <&apbdma 23>;
363 dma-names = "rx", "tx";
3fc2f94e
LD		 364 status = "disabled";
365 };
366
367 i2c@7000c700 {
368 compatible = "nvidia,tegra114-i2c";
369 reg = <0x7000c700 0x100>;
6cecf916 370 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 371 #address-cells = <1>;
372 #size-cells = <0>;
a1c85860 373 clocks = <&tegra_car TEGRA114_CLK_I2C4>;
3fc2f94e 374 clock-names = "div-clk";
3393d422
SW		 375 resets = <&tegra_car 103>;
376 reset-names = "i2c";
034d023f
SW		 377 dmas = <&apbdma 26>, <&apbdma 26>;
378 dma-names = "rx", "tx";
3fc2f94e
LD		 379 status = "disabled";
380 };
381
382 i2c@7000d000 {
383 compatible = "nvidia,tegra114-i2c";
384 reg = <0x7000d000 0x100>;
6cecf916 385 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
3fc2f94e
LD		 386 #address-cells = <1>;
387 #size-cells = <0>;
a1c85860 388 clocks = <&tegra_car TEGRA114_CLK_I2C5>;
3fc2f94e 389 clock-names = "div-clk";
3393d422
SW		 390 resets = <&tegra_car 47>;
391 reset-names = "i2c";
034d023f
SW		 392 dmas = <&apbdma 24>, <&apbdma 24>;
393 dma-names = "rx", "tx";
3fc2f94e
LD		 394 status = "disabled";
395 };
396
6ea0297e
LD		 397 spi@7000d400 {
398 compatible = "nvidia,tegra114-spi";
399 reg = <0x7000d400 0x200>;
6cecf916 400 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 401 #address-cells = <1>;
402 #size-cells = <0>;
a1c85860 403 clocks = <&tegra_car TEGRA114_CLK_SBC1>;
6ea0297e 404 clock-names = "spi";
3393d422
SW		 405 resets = <&tegra_car 41>;
406 reset-names = "spi";
034d023f
SW		 407 dmas = <&apbdma 15>, <&apbdma 15>;
408 dma-names = "rx", "tx";
6ea0297e
LD		 409 status = "disabled";
410 };
411
412 spi@7000d600 {
413 compatible = "nvidia,tegra114-spi";
414 reg = <0x7000d600 0x200>;
6cecf916 415 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 416 #address-cells = <1>;
417 #size-cells = <0>;
a1c85860 418 clocks = <&tegra_car TEGRA114_CLK_SBC2>;
6ea0297e 419 clock-names = "spi";
3393d422
SW		 420 resets = <&tegra_car 44>;
421 reset-names = "spi";
034d023f
SW		 422 dmas = <&apbdma 16>, <&apbdma 16>;
423 dma-names = "rx", "tx";
6ea0297e
LD		 424 status = "disabled";
425 };
426
427 spi@7000d800 {
428 compatible = "nvidia,tegra114-spi";
429 reg = <0x7000d800 0x200>;
6cecf916 430 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 431 #address-cells = <1>;
432 #size-cells = <0>;
a1c85860 433 clocks = <&tegra_car TEGRA114_CLK_SBC3>;
6ea0297e 434 clock-names = "spi";
3393d422
SW		 435 resets = <&tegra_car 46>;
436 reset-names = "spi";
034d023f
SW		 437 dmas = <&apbdma 17>, <&apbdma 17>;
438 dma-names = "rx", "tx";
6ea0297e
LD		 439 status = "disabled";
440 };
441
442 spi@7000da00 {
443 compatible = "nvidia,tegra114-spi";
444 reg = <0x7000da00 0x200>;
6cecf916 445 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 446 #address-cells = <1>;
447 #size-cells = <0>;
a1c85860 448 clocks = <&tegra_car TEGRA114_CLK_SBC4>;
6ea0297e 449 clock-names = "spi";
3393d422
SW		 450 resets = <&tegra_car 68>;
451 reset-names = "spi";
034d023f
SW		 452 dmas = <&apbdma 18>, <&apbdma 18>;
453 dma-names = "rx", "tx";
6ea0297e
LD		 454 status = "disabled";
455 };
456
457 spi@7000dc00 {
458 compatible = "nvidia,tegra114-spi";
459 reg = <0x7000dc00 0x200>;
6cecf916 460 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 461 #address-cells = <1>;
462 #size-cells = <0>;
a1c85860 463 clocks = <&tegra_car TEGRA114_CLK_SBC5>;
6ea0297e 464 clock-names = "spi";
3393d422
SW		 465 resets = <&tegra_car 104>;
466 reset-names = "spi";
034d023f
SW		 467 dmas = <&apbdma 27>, <&apbdma 27>;
468 dma-names = "rx", "tx";
6ea0297e
LD		 469 status = "disabled";
470 };
471
472 spi@7000de00 {
473 compatible = "nvidia,tegra114-spi";
474 reg = <0x7000de00 0x200>;
6cecf916 475 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
6ea0297e
LD		 476 #address-cells = <1>;
477 #size-cells = <0>;
a1c85860 478 clocks = <&tegra_car TEGRA114_CLK_SBC6>;
6ea0297e 479 clock-names = "spi";
3393d422
SW		 480 resets = <&tegra_car 105>;
481 reset-names = "spi";
034d023f
SW		 482 dmas = <&apbdma 28>, <&apbdma 28>;
483 dma-names = "rx", "tx";
6ea0297e
LD		 484 status = "disabled";
485 };
486
58ecb23f 487 rtc@7000e000 {
18a4df70
HD		 488 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
489 reg = <0x7000e000 0x100>;
6cecf916 490 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 491 clocks = <&tegra_car TEGRA114_CLK_RTC>;
18a4df70
HD		 492 };
493
58ecb23f 494 kbc@7000e200 {
cd467b7d
LD		 495 compatible = "nvidia,tegra114-kbc";
496 reg = <0x7000e200 0x100>;
6cecf916 497 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 498 clocks = <&tegra_car TEGRA114_CLK_KBC>;
3393d422
SW		 499 resets = <&tegra_car 36>;
500 reset-names = "kbc";
cd467b7d
LD		 501 status = "disabled";
502 };
503
58ecb23f 504 pmc@7000e400 {
2b84e53b 505 compatible = "nvidia,tegra114-pmc";
18a4df70 506 reg = <0x7000e400 0x400>;
a1c85860 507 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
7021d122 508 clock-names = "pclk", "clk32k_in";
18a4df70
HD		 509 };
510
155dfc7b
PDS		 511 fuse@7000f800 {
512 compatible = "nvidia,tegra114-efuse";
513 reg = <0x7000f800 0x400>;
514 clocks = <&tegra_car TEGRA114_CLK_FUSE>;
515 clock-names = "fuse";
516 resets = <&tegra_car 39>;
517 reset-names = "fuse";
518 };
519
c6f70a4d
TR		 520 mc: memory-controller@70019000 {
521 compatible = "nvidia,tegra114-mc";
522 reg = <0x70019000 0x1000>;
523 clocks = <&tegra_car TEGRA114_CLK_MC>;
524 clock-names = "mc";
525
526 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
527
528 #iommu-cells = <1>;
2da13965
HD		 529 };
530
58ecb23f 531 ahub@70080000 {
15e5c647
SW		 532 compatible = "nvidia,tegra114-ahub";
533 reg = <0x70080000 0x200>,
534 <0x70080200 0x100>,
535 <0x70081000 0x200>;
536 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
15e5c647 537 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>,
2bd541ff
SW		 538 <&tegra_car TEGRA114_CLK_APBIF>;
539 clock-names = "d_audio", "apbif";
3393d422
SW		 540 resets = <&tegra_car 106>, /* d_audio */
541 <&tegra_car 107>, /* apbif */
542 <&tegra_car 30>, /* i2s0 */
543 <&tegra_car 11>, /* i2s1 */
544 <&tegra_car 18>, /* i2s2 */
545 <&tegra_car 101>, /* i2s3 */
546 <&tegra_car 102>, /* i2s4 */
547 <&tegra_car 108>, /* dam0 */
548 <&tegra_car 109>, /* dam1 */
549 <&tegra_car 110>, /* dam2 */
550 <&tegra_car 10>, /* spdif */
551 <&tegra_car 153>, /* amx */
552 <&tegra_car 154>; /* adx */
553 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
554 "i2s3", "i2s4", "dam0", "dam1", "dam2",
555 "spdif", "amx", "adx";
034d023f
SW		 556 dmas = <&apbdma 1>, <&apbdma 1>,
557 <&apbdma 2>, <&apbdma 2>,
558 <&apbdma 3>, <&apbdma 3>,
559 <&apbdma 4>, <&apbdma 4>,
560 <&apbdma 6>, <&apbdma 6>,
561 <&apbdma 7>, <&apbdma 7>,
562 <&apbdma 12>, <&apbdma 12>,
563 <&apbdma 13>, <&apbdma 13>,
564 <&apbdma 14>, <&apbdma 14>,
565 <&apbdma 29>, <&apbdma 29>;
566 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
567 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5",
568 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8",
569 "rx9", "tx9";
15e5c647
SW		 570 ranges;
571 #address-cells = <1>;
572 #size-cells = <1>;
573
574 tegra_i2s0: i2s@70080300 {
575 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
576 reg = <0x70080300 0x100>;
577 nvidia,ahub-cif-ids = <4 4>;
578 clocks = <&tegra_car TEGRA114_CLK_I2S0>;
3393d422
SW		 579 resets = <&tegra_car 30>;
580 reset-names = "i2s";
15e5c647
SW		 581 status = "disabled";
582 };
583
584 tegra_i2s1: i2s@70080400 {
585 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
586 reg = <0x70080400 0x100>;
587 nvidia,ahub-cif-ids = <5 5>;
588 clocks = <&tegra_car TEGRA114_CLK_I2S1>;
3393d422
SW		 589 resets = <&tegra_car 11>;
590 reset-names = "i2s";
15e5c647
SW		 591 status = "disabled";
592 };
593
594 tegra_i2s2: i2s@70080500 {
595 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
596 reg = <0x70080500 0x100>;
597 nvidia,ahub-cif-ids = <6 6>;
598 clocks = <&tegra_car TEGRA114_CLK_I2S2>;
3393d422
SW		 599 resets = <&tegra_car 18>;
600 reset-names = "i2s";
15e5c647
SW		 601 status = "disabled";
602 };
603
604 tegra_i2s3: i2s@70080600 {
605 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
606 reg = <0x70080600 0x100>;
607 nvidia,ahub-cif-ids = <7 7>;
608 clocks = <&tegra_car TEGRA114_CLK_I2S3>;
3393d422
SW		 609 resets = <&tegra_car 101>;
610 reset-names = "i2s";
15e5c647
SW		 611 status = "disabled";
612 };
613
614 tegra_i2s4: i2s@70080700 {
615 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s";
616 reg = <0x70080700 0x100>;
617 nvidia,ahub-cif-ids = <8 8>;
618 clocks = <&tegra_car TEGRA114_CLK_I2S4>;
3393d422
SW		 619 resets = <&tegra_car 102>;
620 reset-names = "i2s";
15e5c647
SW		 621 status = "disabled";
622 };
623 };
624
e3d04d17
TR		 625 mipi: mipi@700e3000 {
626 compatible = "nvidia,tegra114-mipi";
627 reg = <0x700e3000 0x100>;
628 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>;
629 #nvidia,mipi-calibrate-cells = <1>;
630 };
631
933d87a5
PR		 632 sdhci@78000000 {
633 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
634 reg = <0x78000000 0x200>;
6cecf916 635 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 636 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
3393d422
SW		 637 resets = <&tegra_car 14>;
638 reset-names = "sdhci";
e2b6d77e 639 status = "disabled";
933d87a5
PR		 640 };
641
642 sdhci@78000200 {
643 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
644 reg = <0x78000200 0x200>;
6cecf916 645 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 646 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
3393d422
SW		 647 resets = <&tegra_car 9>;
648 reset-names = "sdhci";
e2b6d77e 649 status = "disabled";
933d87a5
PR		 650 };
651
652 sdhci@78000400 {
653 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
654 reg = <0x78000400 0x200>;
6cecf916 655 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 656 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
3393d422
SW		 657 resets = <&tegra_car 69>;
658 reset-names = "sdhci";
e2b6d77e 659 status = "disabled";
933d87a5
PR		 660 };
661
662 sdhci@78000600 {
663 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
664 reg = <0x78000600 0x200>;
6cecf916 665 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
a1c85860 666 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
3393d422
SW		 667 resets = <&tegra_car 15>;
668 reset-names = "sdhci";
e2b6d77e 669 status = "disabled";
933d87a5
PR		 670 };
671
328dc0ec
MP		 672 usb@7d000000 {
673 compatible = "nvidia,tegra30-ehci", "usb-ehci";
674 reg = <0x7d000000 0x4000>;
675 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
676 phy_type = "utmi";
677 clocks = <&tegra_car TEGRA114_CLK_USBD>;
3393d422
SW		 678 resets = <&tegra_car 22>;
679 reset-names = "usb";
328dc0ec
MP		 680 nvidia,phy = <&phy1>;
681 status = "disabled";
682 };
683
684 phy1: usb-phy@7d000000 {
685 compatible = "nvidia,tegra30-usb-phy";
686 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
687 phy_type = "utmi";
688 clocks = <&tegra_car TEGRA114_CLK_USBD>,
689 <&tegra_car TEGRA114_CLK_PLL_U>,
690 <&tegra_car TEGRA114_CLK_USBD>;
691 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 692 resets = <&tegra_car 22>, <&tegra_car 22>;
693 reset-names = "usb", "utmi-pads";
328dc0ec
MP		 694 nvidia,hssync-start-delay = <0>;
695 nvidia,idle-wait-delay = <17>;
696 nvidia,elastic-limit = <16>;
697 nvidia,term-range-adj = <6>;
698 nvidia,xcvr-setup = <9>;
699 nvidia,xcvr-lsfslew = <0>;
700 nvidia,xcvr-lsrslew = <3>;
701 nvidia,hssquelch-level = <2>;
702 nvidia,hsdiscon-level = <5>;
703 nvidia,xcvr-hsslew = <12>;
308efde2 704 nvidia,has-utmi-pad-registers;
328dc0ec
MP		 705 status = "disabled";
706 };
707
708 usb@7d008000 {
709 compatible = "nvidia,tegra30-ehci", "usb-ehci";
710 reg = <0x7d008000 0x4000>;
711 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
712 phy_type = "utmi";
713 clocks = <&tegra_car TEGRA114_CLK_USB3>;
3393d422
SW		 714 resets = <&tegra_car 59>;
715 reset-names = "usb";
328dc0ec
MP		 716 nvidia,phy = <&phy3>;
717 status = "disabled";
718 };
719
720 phy3: usb-phy@7d008000 {
721 compatible = "nvidia,tegra30-usb-phy";
722 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
723 phy_type = "utmi";
724 clocks = <&tegra_car TEGRA114_CLK_USB3>,
725 <&tegra_car TEGRA114_CLK_PLL_U>,
726 <&tegra_car TEGRA114_CLK_USBD>;
727 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 728 resets = <&tegra_car 59>, <&tegra_car 22>;
729 reset-names = "usb", "utmi-pads";
328dc0ec
MP		 730 nvidia,hssync-start-delay = <0>;
731 nvidia,idle-wait-delay = <17>;
732 nvidia,elastic-limit = <16>;
733 nvidia,term-range-adj = <6>;
734 nvidia,xcvr-setup = <9>;
735 nvidia,xcvr-lsfslew = <0>;
736 nvidia,xcvr-lsrslew = <3>;
737 nvidia,hssquelch-level = <2>;
738 nvidia,hsdiscon-level = <5>;
739 nvidia,xcvr-hsslew = <12>;
740 status = "disabled";
741 };
742
18a4df70
HD		 743 cpus {
744 #address-cells = <1>;
745 #size-cells = <0>;
746
747 cpu@0 {
748 device_type = "cpu";
749 compatible = "arm,cortex-a15";
750 reg = <0>;
751 };
752
753 cpu@1 {
754 device_type = "cpu";
755 compatible = "arm,cortex-a15";
756 reg = <1>;
757 };
758
759 cpu@2 {
760 device_type = "cpu";
761 compatible = "arm,cortex-a15";
762 reg = <2>;
763 };
764
765 cpu@3 {
766 device_type = "cpu";
767 compatible = "arm,cortex-a15";
768 reg = <3>;
769 };
770 };
771
772 timer {
773 compatible = "arm,armv7-timer";
6cecf916
SW		 774 interrupts =
775 <GIC_PPI 13
776 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
777 <GIC_PPI 14
778 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
779 <GIC_PPI 11
780 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
781 <GIC_PPI 10
782 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
870c81a4 783 interrupt-parent = <&gic>;
18a4df70
HD		 784 };
785};
Linux 6.x block layer and io_uring tree(s)