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ARM: dts: sunxi: Use new sun7i-a20-mmc compatible on sun7i and newer
[linux-2.6-block.git] / arch / arm / boot / dts / sun6i-a31.dtsi
CommitLineData
8aed3b31
MR		 1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6c3ba724
MR		 6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
8aed3b31 10 *
5186d83a 11 * a) This file is free software; you can redistribute it and/or
6c3ba724
MR		 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
5186d83a 16 * This file is distributed in the hope that it will be useful,
6c3ba724
MR		 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
6c3ba724
MR		 21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
8aed3b31
MR		 43 */
44
71455701 45#include "skeleton.dtsi"
8aed3b31 46
19882b84 47#include <dt-bindings/interrupt-controller/arm-gic.h>
eb58b40f 48#include <dt-bindings/thermal/thermal.h>
19882b84 49
092a0c3b 50#include <dt-bindings/pinctrl/sun4i-a10.h>
8aed3b31
MR		 51
52/ {
53 interrupt-parent = <&gic>;
54
54428d40 55 aliases {
e5073fde 56 ethernet0 = &gmac;
54428d40
MR		 57 };
58
e53a8b22
HG		 59 chosen {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 ranges;
63
c0949308 64 simplefb_hdmi: framebuffer@0 {
d8cacaa3
MR		 65 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer";
a9f8cda3 67 allwinner,pipeline = "de_be0-lcd0-hdmi";
678e75d3 68 clocks = <&pll6 0>;
e53a8b22
HG		 69 status = "disabled";
70 };
fd18c7ea 71
c0949308 72 simplefb_lcd: framebuffer@1 {
fd18c7ea
HG		 73 compatible = "allwinner,simple-framebuffer",
74 "simple-framebuffer";
75 allwinner,pipeline = "de_be0-lcd0";
76 clocks = <&pll6 0>;
77 status = "disabled";
78 };
e53a8b22 79 };
54428d40 80
121b96cd
MR		 81 timer {
82 compatible = "arm,armv7-timer";
83 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
84 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
85 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
86 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
87 clock-frequency = <24000000>;
88 arm,cpu-registers-not-fw-configured;
e53a8b22 89 };
54428d40 90
8aed3b31 91 cpus {
ce78e353 92 enable-method = "allwinner,sun6i-a31";
8aed3b31
MR		 93 #address-cells = <1>;
94 #size-cells = <0>;
95
3a2bc642 96 cpu0: cpu@0 {
8aed3b31
MR		 97 compatible = "arm,cortex-a7";
98 device_type = "cpu";
99 reg = <0>;
3a2bc642
CYT		 100 clocks = <&cpu>;
101 clock-latency = <244144>; /* 8 32k periods */
102 operating-points = <
8358aada 103 /* kHz uV */
3a2bc642 104 1008000 1200000
8358aada
MR		 105 864000 1200000
106 720000 1100000
107 480000 1000000
3a2bc642
CYT		 108 >;
109 #cooling-cells = <2>;
110 cooling-min-level = <0>;
111 cooling-max-level = <3>;
8aed3b31
MR		 112 };
113
114 cpu@1 {
115 compatible = "arm,cortex-a7";
116 device_type = "cpu";
117 reg = <1>;
118 };
119
120 cpu@2 {
121 compatible = "arm,cortex-a7";
122 device_type = "cpu";
123 reg = <2>;
124 };
125
126 cpu@3 {
127 compatible = "arm,cortex-a7";
128 device_type = "cpu";
129 reg = <3>;
130 };
131 };
132
eb58b40f
CYT		 133 thermal-zones {
134 cpu_thermal {
135 /* milliseconds */
136 polling-delay-passive = <250>;
137 polling-delay = <1000>;
138 thermal-sensors = <&rtp>;
139
140 cooling-maps {
141 map0 {
142 trip = <&cpu_alert0>;
143 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
144 };
145 };
146
147 trips {
148 cpu_alert0: cpu_alert0 {
149 /* milliCelsius */
150 temperature = <70000>;
151 hysteresis = <2000>;
152 type = "passive";
153 };
154
155 cpu_crit: cpu_crit {
156 /* milliCelsius */
157 temperature = <100000>;
158 hysteresis = <2000>;
159 type = "critical";
160 };
161 };
162 };
163 };
164
8aed3b31
MR		 165 memory {
166 reg = <0x40000000 0x80000000>;
167 };
168
b5a10b76
MR		 169 pmu {
170 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
19882b84
MR		 171 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
b5a10b76
MR		 175 };
176
8aed3b31
MR		 177 clocks {
178 #address-cells = <1>;
98096560
MR		 179 #size-cells = <1>;
180 ranges;
8aed3b31 181
98096560 182 osc24M: osc24M {
8aed3b31
MR		 183 #clock-cells = <0>;
184 compatible = "fixed-clock";
185 clock-frequency = <24000000>;
186 };
98096560 187
7b5b2909 188 osc32k: clk@0 {
98096560
MR		 189 #clock-cells = <0>;
190 compatible = "fixed-clock";
191 clock-frequency = <32768>;
7b5b2909 192 clock-output-names = "osc32k";
98096560
MR		 193 };
194
7b5b2909 195 pll1: clk@01c20000 {
98096560
MR		 196 #clock-cells = <0>;
197 compatible = "allwinner,sun6i-a31-pll1-clk";
198 reg = <0x01c20000 0x4>;
199 clocks = <&osc24M>;
7b5b2909 200 clock-output-names = "pll1";
98096560
MR		 201 };
202
b0a09c75 203 pll6: clk@01c20028 {
f6c3b046 204 #clock-cells = <1>;
b0a09c75
MR		 205 compatible = "allwinner,sun6i-a31-pll6-clk";
206 reg = <0x01c20028 0x4>;
207 clocks = <&osc24M>;
f6c3b046 208 clock-output-names = "pll6", "pll6x2";
98096560
MR		 209 };
210
211 cpu: cpu@01c20050 {
212 #clock-cells = <0>;
bf6534a1 213 compatible = "allwinner,sun4i-a10-cpu-clk";
98096560
MR		 214 reg = <0x01c20050 0x4>;
215
216 /*
217 * PLL1 is listed twice here.
218 * While it looks suspicious, it's actually documented
219 * that way both in the datasheet and in the code from
220 * Allwinner.
221 */
222 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
7b5b2909 223 clock-output-names = "cpu";
98096560
MR		 224 };
225
226 axi: axi@01c20050 {
227 #clock-cells = <0>;
bf6534a1 228 compatible = "allwinner,sun4i-a10-axi-clk";
98096560
MR		 229 reg = <0x01c20050 0x4>;
230 clocks = <&cpu>;
7b5b2909 231 clock-output-names = "axi";
98096560
MR		 232 };
233
98096560
MR		 234 ahb1: ahb1@01c20054 {
235 #clock-cells = <0>;
42cc7136 236 compatible = "allwinner,sun6i-a31-ahb1-clk";
98096560 237 reg = <0x01c20054 0x4>;
42cc7136 238 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
7b5b2909 239 clock-output-names = "ahb1";
f22fe1c5
CYT		 240
241 /*
242 * Clock AHB1 from PLL6, instead of CPU/AXI which
243 * has rate changes due to cpufreq. Also the DMA
244 * controller requires AHB1 clocked from PLL6.
245 */
246 assigned-clocks = <&ahb1>;
247 assigned-clock-parents = <&pll6 0>;
98096560
MR		 248 };
249
7b5b2909 250 ahb1_gates: clk@01c20060 {
98096560
MR		 251 #clock-cells = <1>;
252 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
253 reg = <0x01c20060 0x8>;
254 clocks = <&ahb1>;
dbbb6922
MR		 255 clock-indices = <1>, <5>,
256 <6>, <8>, <9>,
257 <10>, <11>, <12>,
258 <13>, <14>,
259 <17>, <18>, <19>,
260 <20>, <21>, <22>,
261 <23>, <24>, <26>,
262 <27>, <29>,
263 <30>, <31>, <32>,
264 <36>, <37>, <40>,
265 <43>, <44>, <45>,
266 <46>, <47>, <50>,
267 <52>, <55>, <56>,
268 <57>, <58>;
98096560
MR		 269 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
270 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
271 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
272 "ahb1_nand0", "ahb1_sdram",
273 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
274 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
275 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
276 "ahb1_ehci1", "ahb1_ohci0",
277 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
278 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
279 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
280 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
281 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
282 "ahb1_drc0", "ahb1_drc1";
283 };
284
285 apb1: apb1@01c20054 {
286 #clock-cells = <0>;
bf6534a1 287 compatible = "allwinner,sun4i-a10-apb0-clk";
98096560
MR		 288 reg = <0x01c20054 0x4>;
289 clocks = <&ahb1>;
7b5b2909 290 clock-output-names = "apb1";
98096560
MR		 291 };
292
7b5b2909 293 apb1_gates: clk@01c20068 {
98096560
MR		 294 #clock-cells = <1>;
295 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
296 reg = <0x01c20068 0x4>;
297 clocks = <&apb1>;
dbbb6922
MR		 298 clock-indices = <0>, <4>,
299 <5>, <12>,
300 <13>;
98096560
MR		 301 clock-output-names = "apb1_codec", "apb1_digital_mic",
302 "apb1_pio", "apb1_daudio0",
303 "apb1_daudio1";
304 };
305
74c947ab 306 apb2: clk@01c20058 {
98096560 307 #clock-cells = <0>;
74c947ab 308 compatible = "allwinner,sun4i-a10-apb1-clk";
98096560 309 reg = <0x01c20058 0x4>;
f6c3b046 310 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
7b5b2909 311 clock-output-names = "apb2";
98096560
MR		 312 };
313
7b5b2909 314 apb2_gates: clk@01c2006c {
98096560
MR		 315 #clock-cells = <1>;
316 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
439d9f58 317 reg = <0x01c2006c 0x4>;
98096560 318 clocks = <&apb2>;
dbbb6922
MR		 319 clock-indices = <0>, <1>,
320 <2>, <3>, <16>,
321 <17>, <18>, <19>,
322 <20>, <21>;
98096560 323 clock-output-names = "apb2_i2c0", "apb2_i2c1",
d8cacaa3
MR		 324 "apb2_i2c2", "apb2_i2c3",
325 "apb2_uart0", "apb2_uart1",
326 "apb2_uart2", "apb2_uart3",
327 "apb2_uart4", "apb2_uart5";
98096560 328 };
b0a09c75 329
adc54c85 330 mmc0_clk: clk@01c20088 {
d8c3a392
MR		 331 #clock-cells = <1>;
332 compatible = "allwinner,sun4i-a10-mmc-clk";
adc54c85 333 reg = <0x01c20088 0x4>;
f6c3b046 334 clocks = <&osc24M>, <&pll6 0>;
d8c3a392
MR		 335 clock-output-names = "mmc0",
336 "mmc0_output",
337 "mmc0_sample";
adc54c85
HG		 338 };
339
340 mmc1_clk: clk@01c2008c {
d8c3a392
MR		 341 #clock-cells = <1>;
342 compatible = "allwinner,sun4i-a10-mmc-clk";
adc54c85 343 reg = <0x01c2008c 0x4>;
f6c3b046 344 clocks = <&osc24M>, <&pll6 0>;
d8c3a392
MR		 345 clock-output-names = "mmc1",
346 "mmc1_output",
347 "mmc1_sample";
adc54c85
HG		 348 };
349
350 mmc2_clk: clk@01c20090 {
d8c3a392
MR		 351 #clock-cells = <1>;
352 compatible = "allwinner,sun4i-a10-mmc-clk";
adc54c85 353 reg = <0x01c20090 0x4>;
f6c3b046 354 clocks = <&osc24M>, <&pll6 0>;
d8c3a392
MR		 355 clock-output-names = "mmc2",
356 "mmc2_output",
357 "mmc2_sample";
adc54c85
HG		 358 };
359
360 mmc3_clk: clk@01c20094 {
d8c3a392
MR		 361 #clock-cells = <1>;
362 compatible = "allwinner,sun4i-a10-mmc-clk";
adc54c85 363 reg = <0x01c20094 0x4>;
f6c3b046 364 clocks = <&osc24M>, <&pll6 0>;
d8c3a392
MR		 365 clock-output-names = "mmc3",
366 "mmc3_output",
367 "mmc3_sample";
adc54c85
HG		 368 };
369
14fee74c
CYT		 370 ss_clk: clk@01c2009c {
371 #clock-cells = <0>;
372 compatible = "allwinner,sun4i-a10-mod0-clk";
373 reg = <0x01c2009c 0x4>;
374 clocks = <&osc24M>, <&pll6 0>;
375 clock-output-names = "ss";
376 };
377
b0a09c75
MR		 378 spi0_clk: clk@01c200a0 {
379 #clock-cells = <0>;
225b0216 380 compatible = "allwinner,sun4i-a10-mod0-clk";
b0a09c75 381 reg = <0x01c200a0 0x4>;
f6c3b046 382 clocks = <&osc24M>, <&pll6 0>;
b0a09c75
MR		 383 clock-output-names = "spi0";
384 };
385
386 spi1_clk: clk@01c200a4 {
387 #clock-cells = <0>;
225b0216 388 compatible = "allwinner,sun4i-a10-mod0-clk";
b0a09c75 389 reg = <0x01c200a4 0x4>;
f6c3b046 390 clocks = <&osc24M>, <&pll6 0>;
b0a09c75
MR		 391 clock-output-names = "spi1";
392 };
393
394 spi2_clk: clk@01c200a8 {
395 #clock-cells = <0>;
225b0216 396 compatible = "allwinner,sun4i-a10-mod0-clk";
b0a09c75 397 reg = <0x01c200a8 0x4>;
f6c3b046 398 clocks = <&osc24M>, <&pll6 0>;
b0a09c75
MR		 399 clock-output-names = "spi2";
400 };
401
402 spi3_clk: clk@01c200ac {
403 #clock-cells = <0>;
225b0216 404 compatible = "allwinner,sun4i-a10-mod0-clk";
b0a09c75 405 reg = <0x01c200ac 0x4>;
f6c3b046 406 clocks = <&osc24M>, <&pll6 0>;
b0a09c75
MR		 407 clock-output-names = "spi3";
408 };
94a1cd14
MR		 409
410 usb_clk: clk@01c200cc {
411 #clock-cells = <1>;
8358aada 412 #reset-cells = <1>;
94a1cd14
MR		 413 compatible = "allwinner,sun6i-a31-usb-clk";
414 reg = <0x01c200cc 0x4>;
415 clocks = <&osc24M>;
dbbb6922
MR		 416 clock-indices = <8>, <9>, <10>,
417 <16>, <17>,
418 <18>;
94a1cd14
MR		 419 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
420 "usb_ohci0", "usb_ohci1",
421 "usb_ohci2";
422 };
ed29861a
CYT		 423
424 /*
d8cacaa3
MR		 425 * The following two are dummy clocks, placeholders
426 * used in the gmac_tx clock. The gmac driver will
427 * choose one parent depending on the PHY interface
428 * mode, using clk_set_rate auto-reparenting.
429 *
430 * The actual TX clock rate is not controlled by the
431 * gmac_tx clock.
ed29861a
CYT		 432 */
433 mii_phy_tx_clk: clk@1 {
434 #clock-cells = <0>;
435 compatible = "fixed-clock";
436 clock-frequency = <25000000>;
437 clock-output-names = "mii_phy_tx";
438 };
439
440 gmac_int_tx_clk: clk@2 {
441 #clock-cells = <0>;
442 compatible = "fixed-clock";
443 clock-frequency = <125000000>;
444 clock-output-names = "gmac_int_tx";
445 };
446
447 gmac_tx_clk: clk@01c200d0 {
448 #clock-cells = <0>;
449 compatible = "allwinner,sun7i-a20-gmac-clk";
450 reg = <0x01c200d0 0x4>;
451 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
452 clock-output-names = "gmac_tx";
453 };
8aed3b31
MR		 454 };
455
456 soc@01c00000 {
457 compatible = "simple-bus";
458 #address-cells = <1>;
459 #size-cells = <1>;
460 ranges;
461
d2d878c4
MR		 462 dma: dma-controller@01c02000 {
463 compatible = "allwinner,sun6i-a31-dma";
464 reg = <0x01c02000 0x1000>;
19882b84 465 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
d2d878c4
MR		 466 clocks = <&ahb1_gates 6>;
467 resets = <&ahb1_rst 6>;
468 #dma-cells = <1>;
469 };
470
5b753f0e 471 mmc0: mmc@01c0f000 {
57af711d 472 compatible = "allwinner,sun7i-a20-mmc";
5b753f0e 473 reg = <0x01c0f000 0x1000>;
d8c3a392
MR		 474 clocks = <&ahb1_gates 8>,
475 <&mmc0_clk 0>,
476 <&mmc0_clk 1>,
477 <&mmc0_clk 2>;
478 clock-names = "ahb",
479 "mmc",
480 "output",
481 "sample";
5b753f0e
HG		 482 resets = <&ahb1_rst 8>;
483 reset-names = "ahb";
19882b84 484 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
5b753f0e 485 status = "disabled";
4c1bb9c3
HG		 486 #address-cells = <1>;
487 #size-cells = <0>;
5b753f0e
HG		 488 };
489
490 mmc1: mmc@01c10000 {
57af711d 491 compatible = "allwinner,sun7i-a20-mmc";
5b753f0e 492 reg = <0x01c10000 0x1000>;
d8c3a392
MR		 493 clocks = <&ahb1_gates 9>,
494 <&mmc1_clk 0>,
495 <&mmc1_clk 1>,
496 <&mmc1_clk 2>;
497 clock-names = "ahb",
498 "mmc",
499 "output",
500 "sample";
5b753f0e
HG		 501 resets = <&ahb1_rst 9>;
502 reset-names = "ahb";
19882b84 503 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
5b753f0e 504 status = "disabled";
4c1bb9c3
HG		 505 #address-cells = <1>;
506 #size-cells = <0>;
5b753f0e
HG		 507 };
508
509 mmc2: mmc@01c11000 {
57af711d 510 compatible = "allwinner,sun7i-a20-mmc";
5b753f0e 511 reg = <0x01c11000 0x1000>;
d8c3a392
MR		 512 clocks = <&ahb1_gates 10>,
513 <&mmc2_clk 0>,
514 <&mmc2_clk 1>,
515 <&mmc2_clk 2>;
516 clock-names = "ahb",
517 "mmc",
518 "output",
519 "sample";
5b753f0e
HG		 520 resets = <&ahb1_rst 10>;
521 reset-names = "ahb";
19882b84 522 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
5b753f0e 523 status = "disabled";
4c1bb9c3
HG		 524 #address-cells = <1>;
525 #size-cells = <0>;
5b753f0e
HG		 526 };
527
528 mmc3: mmc@01c12000 {
57af711d 529 compatible = "allwinner,sun7i-a20-mmc";
5b753f0e 530 reg = <0x01c12000 0x1000>;
d8c3a392
MR		 531 clocks = <&ahb1_gates 11>,
532 <&mmc3_clk 0>,
533 <&mmc3_clk 1>,
534 <&mmc3_clk 2>;
535 clock-names = "ahb",
536 "mmc",
537 "output",
538 "sample";
5b753f0e
HG		 539 resets = <&ahb1_rst 11>;
540 reset-names = "ahb";
19882b84 541 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
5b753f0e 542 status = "disabled";
4c1bb9c3
HG		 543 #address-cells = <1>;
544 #size-cells = <0>;
5b753f0e
HG		 545 };
546
d208eaf2
HG		 547 usb_otg: usb@01c19000 {
548 compatible = "allwinner,sun6i-a31-musb";
549 reg = <0x01c19000 0x0400>;
550 clocks = <&ahb1_gates 24>;
551 resets = <&ahb1_rst 24>;
552 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
553 interrupt-names = "mc";
554 phys = <&usbphy 0>;
555 phy-names = "usb";
556 extcon = <&usbphy 0>;
557 status = "disabled";
558 };
559
ef964085
MR		 560 usbphy: phy@01c19400 {
561 compatible = "allwinner,sun6i-a31-usb-phy";
562 reg = <0x01c19400 0x10>,
563 <0x01c1a800 0x4>,
564 <0x01c1b800 0x4>;
565 reg-names = "phy_ctrl",
566 "pmu1",
567 "pmu2";
568 clocks = <&usb_clk 8>,
569 <&usb_clk 9>,
570 <&usb_clk 10>;
571 clock-names = "usb0_phy",
572 "usb1_phy",
573 "usb2_phy";
574 resets = <&usb_clk 0>,
575 <&usb_clk 1>,
576 <&usb_clk 2>;
577 reset-names = "usb0_reset",
578 "usb1_reset",
579 "usb2_reset";
580 status = "disabled";
581 #phy-cells = <1>;
582 };
583
584 ehci0: usb@01c1a000 {
585 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
586 reg = <0x01c1a000 0x100>;
19882b84 587 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
ef964085
MR		 588 clocks = <&ahb1_gates 26>;
589 resets = <&ahb1_rst 26>;
590 phys = <&usbphy 1>;
591 phy-names = "usb";
592 status = "disabled";
593 };
594
595 ohci0: usb@01c1a400 {
596 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
597 reg = <0x01c1a400 0x100>;
19882b84 598 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
ef964085
MR		 599 clocks = <&ahb1_gates 29>, <&usb_clk 16>;
600 resets = <&ahb1_rst 29>;
601 phys = <&usbphy 1>;
602 phy-names = "usb";
603 status = "disabled";
604 };
605
606 ehci1: usb@01c1b000 {
607 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
608 reg = <0x01c1b000 0x100>;
19882b84 609 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
ef964085
MR		 610 clocks = <&ahb1_gates 27>;
611 resets = <&ahb1_rst 27>;
612 phys = <&usbphy 2>;
613 phy-names = "usb";
614 status = "disabled";
615 };
616
617 ohci1: usb@01c1b400 {
618 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
619 reg = <0x01c1b400 0x100>;
19882b84 620 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
ef964085
MR		 621 clocks = <&ahb1_gates 30>, <&usb_clk 17>;
622 resets = <&ahb1_rst 30>;
623 phys = <&usbphy 2>;
624 phy-names = "usb";
625 status = "disabled";
626 };
627
b294ebbc 628 ohci2: usb@01c1c400 {
ef964085
MR		 629 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
630 reg = <0x01c1c400 0x100>;
19882b84 631 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
ef964085
MR		 632 clocks = <&ahb1_gates 31>, <&usb_clk 18>;
633 resets = <&ahb1_rst 31>;
634 status = "disabled";
635 };
636
140e1721
MR		 637 pio: pinctrl@01c20800 {
638 compatible = "allwinner,sun6i-a31-pinctrl";
639 reg = <0x01c20800 0x400>;
19882b84
MR		 640 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
98096560 644 clocks = <&apb1_gates 5>;
140e1721
MR		 645 gpio-controller;
646 interrupt-controller;
b03e0816 647 #interrupt-cells = <3>;
140e1721 648 #gpio-cells = <3>;
ab4238cd
MR		 649
650 uart0_pins_a: uart0@0 {
651 allwinner,pins = "PH20", "PH21";
652 allwinner,function = "uart0";
092a0c3b
MR		 653 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
654 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
ab4238cd 655 };
8be188b8
MR		 656
657 i2c0_pins_a: i2c0@0 {
658 allwinner,pins = "PH14", "PH15";
659 allwinner,function = "i2c0";
092a0c3b
MR		 660 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
661 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
8be188b8
MR		 662 };
663
664 i2c1_pins_a: i2c1@0 {
665 allwinner,pins = "PH16", "PH17";
666 allwinner,function = "i2c1";
092a0c3b
MR		 667 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
668 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
8be188b8
MR		 669 };
670
671 i2c2_pins_a: i2c2@0 {
672 allwinner,pins = "PH18", "PH19";
673 allwinner,function = "i2c2";
092a0c3b
MR		 674 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
675 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
8be188b8 676 };
9797eb83
HG		 677
678 mmc0_pins_a: mmc0@0 {
d8cacaa3
MR		 679 allwinner,pins = "PF0", "PF1", "PF2",
680 "PF3", "PF4", "PF5";
9797eb83 681 allwinner,function = "mmc0";
092a0c3b
MR		 682 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
683 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
9797eb83 684 };
ee39a3e3 685
878c4ded
CYT		 686 mmc1_pins_a: mmc1@0 {
687 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
688 "PG4", "PG5";
689 allwinner,function = "mmc1";
690 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
691 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
692 };
693
5edab366
HG		 694 mmc2_pins_a: mmc2@0 {
695 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
696 "PC10", "PC11";
697 allwinner,function = "mmc2";
698 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
699 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
700 };
701
702 mmc2_8bit_emmc_pins: mmc2@1 {
4917c46c
CYT		 703 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
704 "PC10", "PC11", "PC12",
705 "PC13", "PC14", "PC15",
706 "PC24";
707 allwinner,function = "mmc2";
708 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
709 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
710 };
711
a22f8b22
CYT		 712 mmc3_8bit_emmc_pins: mmc3@1 {
713 allwinner,pins = "PC6", "PC7", "PC8", "PC9",
714 "PC10", "PC11", "PC12",
715 "PC13", "PC14", "PC15",
716 "PC24";
717 allwinner,function = "mmc3";
718 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
719 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
720 };
721
ee39a3e3
CYT		 722 gmac_pins_mii_a: gmac_mii@0 {
723 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
724 "PA8", "PA9", "PA11",
725 "PA12", "PA13", "PA14", "PA19",
726 "PA20", "PA21", "PA22", "PA23",
727 "PA24", "PA26", "PA27";
728 allwinner,function = "gmac";
092a0c3b
MR		 729 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
730 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
ee39a3e3
CYT		 731 };
732
733 gmac_pins_gmii_a: gmac_gmii@0 {
734 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
735 "PA4", "PA5", "PA6", "PA7",
736 "PA8", "PA9", "PA10", "PA11",
737 "PA12", "PA13", "PA14", "PA15",
738 "PA16", "PA17", "PA18", "PA19",
739 "PA20", "PA21", "PA22", "PA23",
740 "PA24", "PA25", "PA26", "PA27";
741 allwinner,function = "gmac";
742 /*
743 * data lines in GMII mode run at 125MHz and
744 * might need a higher signal drive strength
745 */
092a0c3b
MR		 746 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
747 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
ee39a3e3
CYT		 748 };
749
750 gmac_pins_rgmii_a: gmac_rgmii@0 {
751 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
752 "PA9", "PA10", "PA11",
753 "PA12", "PA13", "PA14", "PA19",
754 "PA20", "PA25", "PA26", "PA27";
755 allwinner,function = "gmac";
756 /*
757 * data lines in RGMII mode use DDR mode
758 * and need a higher signal drive strength
759 */
092a0c3b
MR		 760 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
761 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
ee39a3e3 762 };
140e1721
MR		 763 };
764
24a661e9
MR		 765 ahb1_rst: reset@01c202c0 {
766 #reset-cells = <1>;
767 compatible = "allwinner,sun6i-a31-ahb1-reset";
768 reg = <0x01c202c0 0xc>;
769 };
770
771 apb1_rst: reset@01c202d0 {
772 #reset-cells = <1>;
773 compatible = "allwinner,sun6i-a31-clock-reset";
774 reg = <0x01c202d0 0x4>;
775 };
776
777 apb2_rst: reset@01c202d8 {
778 #reset-cells = <1>;
779 compatible = "allwinner,sun6i-a31-clock-reset";
780 reg = <0x01c202d8 0x4>;
781 };
782
8aed3b31 783 timer@01c20c00 {
b4f26440 784 compatible = "allwinner,sun4i-a10-timer";
8aed3b31 785 reg = <0x01c20c00 0xa0>;
19882b84
MR		 786 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
98096560 791 clocks = <&osc24M>;
8aed3b31
MR		 792 };
793
794 wdt1: watchdog@01c20ca0 {
ca5d04d9 795 compatible = "allwinner,sun6i-a31-wdt";
8aed3b31
MR		 796 reg = <0x01c20ca0 0x20>;
797 };
61d2595c
CYT		 798
799 lradc: lradc@01c22800 {
800 compatible = "allwinner,sun4i-a10-lradc-keys";
801 reg = <0x01c22800 0x100>;
802 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
803 status = "disabled";
804 };
8aed3b31 805
4ec45cd3
CYT		 806 rtp: rtp@01c25000 {
807 compatible = "allwinner,sun6i-a31-ts";
808 reg = <0x01c25000 0x100>;
809 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
810 #thermal-sensor-cells = <0>;
811 };
812
8aed3b31
MR		 813 uart0: serial@01c28000 {
814 compatible = "snps,dw-apb-uart";
815 reg = <0x01c28000 0x400>;
19882b84 816 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
8aed3b31
MR		 817 reg-shift = <2>;
818 reg-io-width = <4>;
98096560 819 clocks = <&apb2_gates 16>;
24a661e9 820 resets = <&apb2_rst 16>;
d2d878c4
MR		 821 dmas = <&dma 6>, <&dma 6>;
822 dma-names = "rx", "tx";
8aed3b31
MR		 823 status = "disabled";
824 };
825
826 uart1: serial@01c28400 {
827 compatible = "snps,dw-apb-uart";
828 reg = <0x01c28400 0x400>;
19882b84 829 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
8aed3b31
MR		 830 reg-shift = <2>;
831 reg-io-width = <4>;
98096560 832 clocks = <&apb2_gates 17>;
24a661e9 833 resets = <&apb2_rst 17>;
d2d878c4
MR		 834 dmas = <&dma 7>, <&dma 7>;
835 dma-names = "rx", "tx";
8aed3b31
MR		 836 status = "disabled";
837 };
838
839 uart2: serial@01c28800 {
840 compatible = "snps,dw-apb-uart";
841 reg = <0x01c28800 0x400>;
19882b84 842 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
8aed3b31
MR		 843 reg-shift = <2>;
844 reg-io-width = <4>;
98096560 845 clocks = <&apb2_gates 18>;
24a661e9 846 resets = <&apb2_rst 18>;
d2d878c4
MR		 847 dmas = <&dma 8>, <&dma 8>;
848 dma-names = "rx", "tx";
8aed3b31
MR		 849 status = "disabled";
850 };
851
852 uart3: serial@01c28c00 {
853 compatible = "snps,dw-apb-uart";
854 reg = <0x01c28c00 0x400>;
19882b84 855 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
8aed3b31
MR		 856 reg-shift = <2>;
857 reg-io-width = <4>;
98096560 858 clocks = <&apb2_gates 19>;
24a661e9 859 resets = <&apb2_rst 19>;
d2d878c4
MR		 860 dmas = <&dma 9>, <&dma 9>;
861 dma-names = "rx", "tx";
8aed3b31
MR		 862 status = "disabled";
863 };
864
865 uart4: serial@01c29000 {
866 compatible = "snps,dw-apb-uart";
867 reg = <0x01c29000 0x400>;
19882b84 868 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
8aed3b31
MR		 869 reg-shift = <2>;
870 reg-io-width = <4>;
98096560 871 clocks = <&apb2_gates 20>;
24a661e9 872 resets = <&apb2_rst 20>;
d2d878c4
MR		 873 dmas = <&dma 10>, <&dma 10>;
874 dma-names = "rx", "tx";
8aed3b31
MR		 875 status = "disabled";
876 };
877
878 uart5: serial@01c29400 {
879 compatible = "snps,dw-apb-uart";
880 reg = <0x01c29400 0x400>;
19882b84 881 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
8aed3b31
MR		 882 reg-shift = <2>;
883 reg-io-width = <4>;
98096560 884 clocks = <&apb2_gates 21>;
24a661e9 885 resets = <&apb2_rst 21>;
d2d878c4
MR		 886 dmas = <&dma 22>, <&dma 22>;
887 dma-names = "rx", "tx";
8aed3b31
MR		 888 status = "disabled";
889 };
890
96c7cc9b
MR		 891 i2c0: i2c@01c2ac00 {
892 compatible = "allwinner,sun6i-a31-i2c";
893 reg = <0x01c2ac00 0x400>;
19882b84 894 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
96c7cc9b 895 clocks = <&apb2_gates 0>;
96c7cc9b
MR		 896 resets = <&apb2_rst 0>;
897 status = "disabled";
495bccf3
CYT		 898 #address-cells = <1>;
899 #size-cells = <0>;
96c7cc9b
MR		 900 };
901
902 i2c1: i2c@01c2b000 {
903 compatible = "allwinner,sun6i-a31-i2c";
904 reg = <0x01c2b000 0x400>;
19882b84 905 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
96c7cc9b 906 clocks = <&apb2_gates 1>;
96c7cc9b
MR		 907 resets = <&apb2_rst 1>;
908 status = "disabled";
495bccf3
CYT		 909 #address-cells = <1>;
910 #size-cells = <0>;
96c7cc9b
MR		 911 };
912
913 i2c2: i2c@01c2b400 {
914 compatible = "allwinner,sun6i-a31-i2c";
915 reg = <0x01c2b400 0x400>;
19882b84 916 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
96c7cc9b 917 clocks = <&apb2_gates 2>;
96c7cc9b
MR		 918 resets = <&apb2_rst 2>;
919 status = "disabled";
495bccf3
CYT		 920 #address-cells = <1>;
921 #size-cells = <0>;
96c7cc9b
MR		 922 };
923
924 i2c3: i2c@01c2b800 {
925 compatible = "allwinner,sun6i-a31-i2c";
926 reg = <0x01c2b800 0x400>;
19882b84 927 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
96c7cc9b 928 clocks = <&apb2_gates 3>;
96c7cc9b
MR		 929 resets = <&apb2_rst 3>;
930 status = "disabled";
495bccf3
CYT		 931 #address-cells = <1>;
932 #size-cells = <0>;
96c7cc9b
MR		 933 };
934
3dca65f8
CYT		 935 gmac: ethernet@01c30000 {
936 compatible = "allwinner,sun7i-a20-gmac";
937 reg = <0x01c30000 0x1054>;
19882b84 938 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3dca65f8
CYT		 939 interrupt-names = "macirq";
940 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
941 clock-names = "stmmaceth", "allwinner_gmac_tx";
942 resets = <&ahb1_rst 17>;
943 reset-names = "stmmaceth";
944 snps,pbl = <2>;
945 snps,fixed-burst;
946 snps,force_sf_dma_mode;
947 status = "disabled";
948 #address-cells = <1>;
949 #size-cells = <0>;
950 };
951
14fee74c
CYT		 952 crypto: crypto-engine@01c15000 {
953 compatible = "allwinner,sun4i-a10-crypto";
954 reg = <0x01c15000 0x1000>;
955 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&ahb1_gates 5>, <&ss_clk>;
957 clock-names = "ahb", "mod";
958 resets = <&ahb1_rst 5>;
959 reset-names = "ahb";
960 };
961
8cffcb0c 962 timer@01c60000 {
d8cacaa3
MR		 963 compatible = "allwinner,sun6i-a31-hstimer",
964 "allwinner,sun7i-a20-hstimer";
8cffcb0c 965 reg = <0x01c60000 0x1000>;
19882b84
MR		 966 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
8cffcb0c
MR		 970 clocks = <&ahb1_gates 19>;
971 resets = <&ahb1_rst 19>;
972 };
973
0d6efe33
MR		 974 spi0: spi@01c68000 {
975 compatible = "allwinner,sun6i-a31-spi";
976 reg = <0x01c68000 0x1000>;
19882b84 977 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0d6efe33
MR		 978 clocks = <&ahb1_gates 20>, <&spi0_clk>;
979 clock-names = "ahb", "mod";
d2d878c4
MR		 980 dmas = <&dma 23>, <&dma 23>;
981 dma-names = "rx", "tx";
0d6efe33
MR		 982 resets = <&ahb1_rst 20>;
983 status = "disabled";
984 };
985
986 spi1: spi@01c69000 {
987 compatible = "allwinner,sun6i-a31-spi";
988 reg = <0x01c69000 0x1000>;
19882b84 989 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0d6efe33
MR		 990 clocks = <&ahb1_gates 21>, <&spi1_clk>;
991 clock-names = "ahb", "mod";
d2d878c4
MR		 992 dmas = <&dma 24>, <&dma 24>;
993 dma-names = "rx", "tx";
0d6efe33
MR		 994 resets = <&ahb1_rst 21>;
995 status = "disabled";
996 };
997
998 spi2: spi@01c6a000 {
999 compatible = "allwinner,sun6i-a31-spi";
1000 reg = <0x01c6a000 0x1000>;
19882b84 1001 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
0d6efe33
MR		 1002 clocks = <&ahb1_gates 22>, <&spi2_clk>;
1003 clock-names = "ahb", "mod";
d2d878c4
MR		 1004 dmas = <&dma 25>, <&dma 25>;
1005 dma-names = "rx", "tx";
0d6efe33
MR		 1006 resets = <&ahb1_rst 22>;
1007 status = "disabled";
1008 };
1009
1010 spi3: spi@01c6b000 {
1011 compatible = "allwinner,sun6i-a31-spi";
1012 reg = <0x01c6b000 0x1000>;
19882b84 1013 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
0d6efe33
MR		 1014 clocks = <&ahb1_gates 23>, <&spi3_clk>;
1015 clock-names = "ahb", "mod";
d2d878c4
MR		 1016 dmas = <&dma 26>, <&dma 26>;
1017 dma-names = "rx", "tx";
0d6efe33
MR		 1018 resets = <&ahb1_rst 23>;
1019 status = "disabled";
1020 };
1021
8aed3b31
MR		 1022 gic: interrupt-controller@01c81000 {
1023 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1024 reg = <0x01c81000 0x1000>,
1025 <0x01c82000 0x1000>,
1026 <0x01c84000 0x2000>,
1027 <0x01c86000 0x2000>;
1028 interrupt-controller;
1029 #interrupt-cells = <3>;
19882b84 1030 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
8aed3b31 1031 };
81ee429f 1032
5e700435
CYT		 1033 rtc: rtc@01f00000 {
1034 compatible = "allwinner,sun6i-a31-rtc";
1035 reg = <0x01f00000 0x54>;
19882b84
MR		 1036 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1037 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
5e700435
CYT		 1038 };
1039
28240d27
MR		 1040 nmi_intc: interrupt-controller@01f00c0c {
1041 compatible = "allwinner,sun6i-a31-sc-nmi";
1042 interrupt-controller;
1043 #interrupt-cells = <2>;
1044 reg = <0x01f00c0c 0x38>;
19882b84 1045 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
28240d27
MR		 1046 };
1047
a42ea603
HG		 1048 prcm@01f01400 {
1049 compatible = "allwinner,sun6i-a31-prcm";
1050 reg = <0x01f01400 0x200>;
cc08f5e9
BB		 1051
1052 ar100: ar100_clk {
1053 compatible = "allwinner,sun6i-a31-ar100-clk";
1054 #clock-cells = <0>;
d8cacaa3
MR		 1055 clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
1056 <&pll6 0>;
cc08f5e9
BB		 1057 clock-output-names = "ar100";
1058 };
1059
1060 ahb0: ahb0_clk {
1061 compatible = "fixed-factor-clock";
1062 #clock-cells = <0>;
1063 clock-div = <1>;
1064 clock-mult = <1>;
1065 clocks = <&ar100>;
1066 clock-output-names = "ahb0";
1067 };
1068
1069 apb0: apb0_clk {
1070 compatible = "allwinner,sun6i-a31-apb0-clk";
1071 #clock-cells = <0>;
1072 clocks = <&ahb0>;
1073 clock-output-names = "apb0";
1074 };
1075
1076 apb0_gates: apb0_gates_clk {
1077 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
1078 #clock-cells = <1>;
1079 clocks = <&apb0>;
1080 clock-output-names = "apb0_pio", "apb0_ir",
1081 "apb0_timer", "apb0_p2wi",
1082 "apb0_uart", "apb0_1wire",
1083 "apb0_i2c";
1084 };
1085
9b5c6e06
HG		 1086 ir_clk: ir_clk {
1087 #clock-cells = <0>;
1088 compatible = "allwinner,sun4i-a10-mod0-clk";
1089 clocks = <&osc32k>, <&osc24M>;
1090 clock-output-names = "ir";
1091 };
1092
cc08f5e9
BB		 1093 apb0_rst: apb0_rst {
1094 compatible = "allwinner,sun6i-a31-clock-reset";
1095 #reset-cells = <1>;
1096 };
a42ea603
HG		 1097 };
1098
81ee429f
MR		 1099 cpucfg@01f01c00 {
1100 compatible = "allwinner,sun6i-a31-cpuconfig";
1101 reg = <0x01f01c00 0x300>;
1102 };
209394ae 1103
4ac367b4
HG		 1104 ir: ir@01f02000 {
1105 compatible = "allwinner,sun5i-a13-ir";
1106 clocks = <&apb0_gates 1>, <&ir_clk>;
1107 clock-names = "apb", "ir";
1108 resets = <&apb0_rst 1>;
19882b84 1109 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
4ac367b4
HG		 1110 reg = <0x01f02000 0x40>;
1111 status = "disabled";
1112 };
1113
209394ae
BB		 1114 r_pio: pinctrl@01f02c00 {
1115 compatible = "allwinner,sun6i-a31-r-pinctrl";
1116 reg = <0x01f02c00 0x400>;
19882b84
MR		 1117 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1118 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
209394ae
BB		 1119 clocks = <&apb0_gates 0>;
1120 resets = <&apb0_rst 0>;
1121 gpio-controller;
1122 interrupt-controller;
6d55d339 1123 #interrupt-cells = <3>;
209394ae
BB		 1124 #size-cells = <0>;
1125 #gpio-cells = <3>;
dbbcd881
HG		 1126
1127 ir_pins_a: ir@0 {
1128 allwinner,pins = "PL4";
1129 allwinner,function = "s_ir";
092a0c3b
MR		 1130 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1131 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
dbbcd881 1132 };
fcd60138
BB		 1133
1134 p2wi_pins: p2wi {
1135 allwinner,pins = "PL0", "PL1";
1136 allwinner,function = "s_p2wi";
1137 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1138 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1139 };
1140 };
1141
1142 p2wi: i2c@01f03400 {
1143 compatible = "allwinner,sun6i-a31-p2wi";
1144 reg = <0x01f03400 0x400>;
1145 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1146 clocks = <&apb0_gates 3>;
1147 clock-frequency = <100000>;
1148 resets = <&apb0_rst 3>;
1149 pinctrl-names = "default";
1150 pinctrl-0 = <&p2wi_pins>;
1151 status = "disabled";
1152 #address-cells = <1>;
1153 #size-cells = <0>;
209394ae 1154 };
8aed3b31
MR		 1155 };
1156};
Linux 6.x block layer and io_uring tree(s)