[linux-2.6-block.git] / arch / arm / boot / dts / stm32mp157-pinctrl.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
 */
#include <dt-bindings/pinctrl/stm32-pinfunc.h>

/ {
	soc {
		pinctrl: pin-controller@50002000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp157-pinctrl";
			ranges = <0 0x50002000 0xa400>;
			interrupt-parent = <&exti>;
			st,syscfg = <&exti 0x60 0xff>;
			pins-are-numbered;

			gpioa: gpio@50002000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x0 0x400>;
				clocks = <&rcc GPIOA>;
				st,bank-name = "GPIOA";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 0 16>;
			};

			gpiob: gpio@50003000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1000 0x400>;
				clocks = <&rcc GPIOB>;
				st,bank-name = "GPIOB";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 16 16>;
			};

			gpioc: gpio@50004000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2000 0x400>;
				clocks = <&rcc GPIOC>;
				st,bank-name = "GPIOC";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 32 16>;
			};

			gpiod: gpio@50005000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x3000 0x400>;
				clocks = <&rcc GPIOD>;
				st,bank-name = "GPIOD";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 48 16>;
			};

			gpioe: gpio@50006000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x4000 0x400>;
				clocks = <&rcc GPIOE>;
				st,bank-name = "GPIOE";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 64 16>;
			};

			gpiof: gpio@50007000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x5000 0x400>;
				clocks = <&rcc GPIOF>;
				st,bank-name = "GPIOF";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 80 16>;
			};

			gpiog: gpio@50008000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x6000 0x400>;
				clocks = <&rcc GPIOG>;
				st,bank-name = "GPIOG";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 96 16>;
			};

			gpioh: gpio@50009000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x7000 0x400>;
				clocks = <&rcc GPIOH>;
				st,bank-name = "GPIOH";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 112 16>;
			};

			gpioi: gpio@5000a000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x8000 0x400>;
				clocks = <&rcc GPIOI>;
				st,bank-name = "GPIOI";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 128 16>;
			};

			gpioj: gpio@5000b000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x9000 0x400>;
				clocks = <&rcc GPIOJ>;
				st,bank-name = "GPIOJ";
				ngpios = <16>;
				gpio-ranges = <&pinctrl 0 144 16>;
			};

			gpiok: gpio@5000c000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0xa000 0x400>;
				clocks = <&rcc GPIOK>;
				st,bank-name = "GPIOK";
				ngpios = <8>;
				gpio-ranges = <&pinctrl 0 160 8>;
			};

			cec_pins_a: cec-0 {
				pins {
					pinmux = <STM32_PINMUX('A', 15, AF4)>;
					bias-disable;
					drive-open-drain;
					slew-rate = <0>;
				};
			};

			i2c1_pins_a: i2c1-0 {
				pins {
					pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
						 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
					bias-disable;
					drive-open-drain;
					slew-rate = <0>;
				};
			};

			i2c2_pins_a: i2c2-0 {
				pins {
					pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
						 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
					bias-disable;
					drive-open-drain;
					slew-rate = <0>;
				};
			};

			i2c5_pins_a: i2c5-0 {
				pins {
					pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
						 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
					bias-disable;
					drive-open-drain;
					slew-rate = <0>;
				};
			};

			pwm2_pins_a: pwm2-0 {
				pins {
					pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
					bias-pull-down;
					drive-push-pull;
					slew-rate = <0>;
				};
			};

			pwm8_pins_a: pwm8-0 {
				pins {
					pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
					bias-pull-down;
					drive-push-pull;
					slew-rate = <0>;
				};
			};

			pwm12_pins_a: pwm12-0 {
				pins {
					pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
					bias-pull-down;
					drive-push-pull;
					slew-rate = <0>;
				};
			};

			qspi_clk_pins_a: qspi-clk-0 {
				pins {
					pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
					bias-disable;
					drive-push-pull;
					slew-rate = <3>;
				};
			};

			qspi_bk1_pins_a: qspi-bk1-0 {
				pins1 {
					pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
						 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
						 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
						 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
					bias-disable;
					drive-push-pull;
					slew-rate = <3>;
				};
				pins2 {
					pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
					bias-pull-up;
					drive-push-pull;
					slew-rate = <3>;
				};
			};

			qspi_bk2_pins_a: qspi-bk2-0 {
				pins1 {
					pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
						 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
						 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
						 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
					bias-disable;
					drive-push-pull;
					slew-rate = <3>;
				};
				pins2 {
					pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
					bias-pull-up;
					drive-push-pull;
					slew-rate = <3>;
				};
			};

			uart4_pins_a: uart4-0 {
				pins1 {
					pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
					bias-disable;
					drive-push-pull;
					slew-rate = <0>;
				};
				pins2 {
					pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
					bias-disable;
				};
			};
		};

		pinctrl_z: pin-controller-z@54004000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp157-z-pinctrl";
			ranges = <0 0x54004000 0x400>;
			pins-are-numbered;
			interrupt-parent = <&exti>;
			st,syscfg = <&exti 0x60 0xff>;
			status = "disabled";

			gpioz: gpio@54004000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0 0x400>;
				clocks = <&rcc GPIOZ>;
				st,bank-name = "GPIOZ";
				st,bank-ioport = <11>;
				ngpios = <8>;
				gpio-ranges = <&pinctrl_z 0 400 8>;
			};

			i2c4_pins_a: i2c4-0 {
				pins {
					pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
						 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
					bias-disable;
					drive-open-drain;
					slew-rate = <0>;
				};
			};
		};
	};
};
Commit	Line	Data
8471a202 LB	1	// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
	2	/*
	3	* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
	4	* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
	5	*/
	6	#include <dt-bindings/pinctrl/stm32-pinfunc.h>
	7
	8	/ {
	9	soc {
20ab2d88	10	pinctrl: pin-controller@50002000 {
8471a202 LB	11	#address-cells = <1>;
	12	#size-cells = <1>;
	13	compatible = "st,stm32mp157-pinctrl";
	14	ranges = <0 0x50002000 0xa400>;
6a88c221 LB	15	interrupt-parent = <&exti>;
6a88c221 LB	16	st,syscfg = <&exti 0x60 0xff>;
8471a202 LB	17	pins-are-numbered;
	18
	19	gpioa: gpio@50002000 {
	20	gpio-controller;
	21	#gpio-cells = <2>;
	22	interrupt-controller;
	23	#interrupt-cells = <2>;
	24	reg = <0x0 0x400>;
3599a8af	25	clocks = <&rcc GPIOA>;
8471a202 LB	26	st,bank-name = "GPIOA";
	27	ngpios = <16>;
	28	gpio-ranges = <&pinctrl 0 0 16>;
	29	};
	30
	31	gpiob: gpio@50003000 {
	32	gpio-controller;
	33	#gpio-cells = <2>;
	34	interrupt-controller;
	35	#interrupt-cells = <2>;
	36	reg = <0x1000 0x400>;
3599a8af	37	clocks = <&rcc GPIOB>;
8471a202 LB	38	st,bank-name = "GPIOB";
	39	ngpios = <16>;
	40	gpio-ranges = <&pinctrl 0 16 16>;
	41	};
	42
	43	gpioc: gpio@50004000 {
	44	gpio-controller;
	45	#gpio-cells = <2>;
	46	interrupt-controller;
	47	#interrupt-cells = <2>;
	48	reg = <0x2000 0x400>;
3599a8af	49	clocks = <&rcc GPIOC>;
8471a202 LB	50	st,bank-name = "GPIOC";
	51	ngpios = <16>;
	52	gpio-ranges = <&pinctrl 0 32 16>;
	53	};
	54
	55	gpiod: gpio@50005000 {
	56	gpio-controller;
	57	#gpio-cells = <2>;
	58	interrupt-controller;
	59	#interrupt-cells = <2>;
	60	reg = <0x3000 0x400>;
3599a8af	61	clocks = <&rcc GPIOD>;
8471a202 LB	62	st,bank-name = "GPIOD";
	63	ngpios = <16>;
	64	gpio-ranges = <&pinctrl 0 48 16>;
	65	};
	66
	67	gpioe: gpio@50006000 {
	68	gpio-controller;
	69	#gpio-cells = <2>;
	70	interrupt-controller;
	71	#interrupt-cells = <2>;
	72	reg = <0x4000 0x400>;
3599a8af	73	clocks = <&rcc GPIOE>;
8471a202 LB	74	st,bank-name = "GPIOE";
	75	ngpios = <16>;
	76	gpio-ranges = <&pinctrl 0 64 16>;
	77	};
	78
	79	gpiof: gpio@50007000 {
	80	gpio-controller;
	81	#gpio-cells = <2>;
	82	interrupt-controller;
	83	#interrupt-cells = <2>;
	84	reg = <0x5000 0x400>;
3599a8af	85	clocks = <&rcc GPIOF>;
8471a202 LB	86	st,bank-name = "GPIOF";
	87	ngpios = <16>;
	88	gpio-ranges = <&pinctrl 0 80 16>;
	89	};
	90
	91	gpiog: gpio@50008000 {
	92	gpio-controller;
	93	#gpio-cells = <2>;
	94	interrupt-controller;
	95	#interrupt-cells = <2>;
	96	reg = <0x6000 0x400>;
3599a8af	97	clocks = <&rcc GPIOG>;
8471a202 LB	98	st,bank-name = "GPIOG";
	99	ngpios = <16>;
	100	gpio-ranges = <&pinctrl 0 96 16>;
	101	};
	102
	103	gpioh: gpio@50009000 {
	104	gpio-controller;
	105	#gpio-cells = <2>;
	106	interrupt-controller;
	107	#interrupt-cells = <2>;
	108	reg = <0x7000 0x400>;
3599a8af	109	clocks = <&rcc GPIOH>;
8471a202 LB	110	st,bank-name = "GPIOH";
	111	ngpios = <16>;
	112	gpio-ranges = <&pinctrl 0 112 16>;
	113	};
	114
	115	gpioi: gpio@5000a000 {
	116	gpio-controller;
	117	#gpio-cells = <2>;
	118	interrupt-controller;
	119	#interrupt-cells = <2>;
	120	reg = <0x8000 0x400>;
3599a8af	121	clocks = <&rcc GPIOI>;
8471a202 LB	122	st,bank-name = "GPIOI";
	123	ngpios = <16>;
	124	gpio-ranges = <&pinctrl 0 128 16>;
	125	};
	126
	127	gpioj: gpio@5000b000 {
	128	gpio-controller;
	129	#gpio-cells = <2>;
	130	interrupt-controller;
	131	#interrupt-cells = <2>;
	132	reg = <0x9000 0x400>;
3599a8af	133	clocks = <&rcc GPIOJ>;
8471a202 LB	134	st,bank-name = "GPIOJ";
	135	ngpios = <16>;
	136	gpio-ranges = <&pinctrl 0 144 16>;
	137	};
	138
	139	gpiok: gpio@5000c000 {
	140	gpio-controller;
	141	#gpio-cells = <2>;
	142	interrupt-controller;
	143	#interrupt-cells = <2>;
	144	reg = <0xa000 0x400>;
3599a8af	145	clocks = <&rcc GPIOK>;
8471a202 LB	146	st,bank-name = "GPIOK";
	147	ngpios = <8>;
	148	gpio-ranges = <&pinctrl 0 160 8>;
	149	};
bcc4f4e1	150
7123be3b	151	cec_pins_a: cec-0 {
	152	pins {
	153	pinmux = <STM32_PINMUX('A', 15, AF4)>;
	154	bias-disable;
	155	drive-open-drain;
	156	slew-rate = <0>;
	157	};
	158	};
	159
4d58a474 PYM	160	i2c1_pins_a: i2c1-0 {
	161	pins {
	162	pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
	163	<STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
	164	bias-disable;
	165	drive-open-drain;
	166	slew-rate = <0>;
	167	};
	168	};
	169
	170	i2c2_pins_a: i2c2-0 {
	171	pins {
	172	pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
	173	<STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
	174	bias-disable;
	175	drive-open-drain;
	176	slew-rate = <0>;
	177	};
	178	};
	179
	180	i2c5_pins_a: i2c5-0 {
	181	pins {
	182	pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
	183	<STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
	184	bias-disable;
	185	drive-open-drain;
	186	slew-rate = <0>;
	187	};
	188	};
	189
52545823 FG	190	pwm2_pins_a: pwm2-0 {
	191	pins {
	192	pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
	193	bias-pull-down;
	194	drive-push-pull;
	195	slew-rate = <0>;
	196	};
	197	};
	198
	199	pwm8_pins_a: pwm8-0 {
	200	pins {
	201	pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
	202	bias-pull-down;
	203	drive-push-pull;
	204	slew-rate = <0>;
	205	};
	206	};
	207
	208	pwm12_pins_a: pwm12-0 {
	209	pins {
	210	pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
	211	bias-pull-down;
	212	drive-push-pull;
	213	slew-rate = <0>;
	214	};
	215	};
	216
84403005 LB	217	qspi_clk_pins_a: qspi-clk-0 {
	218	pins {
	219	pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
	220	bias-disable;
	221	drive-push-pull;
	222	slew-rate = <3>;
	223	};
	224	};
	225
	226	qspi_bk1_pins_a: qspi-bk1-0 {
	227	pins1 {
	228	pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
	229	<STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
	230	<STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
	231	<STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
	232	bias-disable;
	233	drive-push-pull;
	234	slew-rate = <3>;
	235	};
	236	pins2 {
	237	pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
	238	bias-pull-up;
	239	drive-push-pull;
	240	slew-rate = <3>;
	241	};
	242	};
	243
	244	qspi_bk2_pins_a: qspi-bk2-0 {
	245	pins1 {
	246	pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
	247	<STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
	248	<STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
	249	<STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
	250	bias-disable;
	251	drive-push-pull;
	252	slew-rate = <3>;
	253	};
	254	pins2 {
	255	pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
	256	bias-pull-up;
	257	drive-push-pull;
	258	slew-rate = <3>;
	259	};
	260	};
	261
20ab2d88	262	uart4_pins_a: uart4-0 {
bcc4f4e1 LB	263	pins1 {
	264	pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
	265	bias-disable;
	266	drive-push-pull;
	267	slew-rate = <0>;
	268	};
	269	pins2 {
	270	pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
	271	bias-disable;
	272	};
	273	};
8471a202 LB	274	};
8471a202 LB	275
20ab2d88	276	pinctrl_z: pin-controller-z@54004000 {
8471a202 LB	277	#address-cells = <1>;
	278	#size-cells = <1>;
	279	compatible = "st,stm32mp157-z-pinctrl";
	280	ranges = <0 0x54004000 0x400>;
	281	pins-are-numbered;
6a88c221 LB	282	interrupt-parent = <&exti>;
6a88c221 LB	283	st,syscfg = <&exti 0x60 0xff>;
8471a202 LB	284	status = "disabled";
	285
	286	gpioz: gpio@54004000 {
	287	gpio-controller;
	288	#gpio-cells = <2>;
	289	interrupt-controller;
	290	#interrupt-cells = <2>;
	291	reg = <0 0x400>;
3599a8af	292	clocks = <&rcc GPIOZ>;
8471a202 LB	293	st,bank-name = "GPIOZ";
	294	st,bank-ioport = <11>;
	295	ngpios = <8>;
	296	gpio-ranges = <&pinctrl_z 0 400 8>;
	297	};
4d58a474 PYM	298
	299	i2c4_pins_a: i2c4-0 {
	300	pins {
	301	pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
	302	<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
	303	bias-disable;
	304	drive-open-drain;
	305	slew-rate = <0>;
	306	};
	307	};
8471a202 LB	308	};
	309	};
	310	};