[linux-2.6-block.git] / arch / arm / boot / dts / stih410.dtsi

/*
 * Copyright (C) 2014 STMicroelectronics Limited.
 * Author: Peter Griffin <peter.griffin@linaro.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */
#include "stih410-clock.dtsi"
#include "stih407-family.dtsi"
#include "stih410-pinctrl.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
	aliases {
		bdisp0 = &bdisp0;
	};

	soc {
		usb2_picophy1: phy2@0 {
			compatible = "st,stih407-usb2-phy";
			reg = <0 0>;
			#phy-cells = <0>;
			st,syscfg = <&syscfg_core 0xf8 0xf4>;
			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
				 <&picophyreset STIH407_PICOPHY0_RESET>;
			reset-names = "global", "port";

			status = "disabled";
		};

		usb2_picophy2: phy3@0 {
			compatible = "st,stih407-usb2-phy";
			reg = <0 0>;
			#phy-cells = <0>;
			st,syscfg = <&syscfg_core 0xfc 0xf4>;
			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
				 <&picophyreset STIH407_PICOPHY1_RESET>;
			reset-names = "global", "port";

			status = "disabled";
		};

		ohci0: usb@9a03c00 {
			compatible = "st,st-ohci-300x";
			reg = <0x9a03c00 0x100>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy1>;
			phy-names = "usb";

			status = "disabled";
		};

		ehci0: usb@9a03e00 {
			compatible = "st,st-ehci-300x";
			reg = <0x9a03e00 0x100>;
			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb0>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy1>;
			phy-names = "usb";

			status = "disabled";
		};

		ohci1: usb@9a83c00 {
			compatible = "st,st-ohci-300x";
			reg = <0x9a83c00 0x100>;
			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy2>;
			phy-names = "usb";

			status = "disabled";
		};

		ehci1: usb@9a83e00 {
			compatible = "st,st-ehci-300x";
			reg = <0x9a83e00 0x100>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_usb1>;
			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
				 <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
			reset-names = "power", "softreset";
			phys = <&usb2_picophy2>;
			phy-names = "usb";

			status = "disabled";
		};

		sti-display-subsystem@0 {
			compatible = "st,sti-display-subsystem";
			#address-cells = <1>;
			#size-cells = <1>;

			reg = <0 0>;
			assigned-clocks	= <&clk_s_d2_quadfs 0>,
					  <&clk_s_d2_quadfs 1>,
					  <&clk_s_c0_pll1 0>,
					  <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					  <&clk_s_c0_flexgen CLK_MAIN_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP1>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP2>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP3>,
					  <&clk_s_d2_flexgen CLK_PIX_GDP4>;

			assigned-clock-parents = <0>,
						 <0>,
						 <0>,
						 <&clk_s_c0_pll1 0>,
						 <&clk_s_c0_pll1 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 1>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>,
						 <&clk_s_d2_quadfs 0>;

			assigned-clock-rates = <297000000>,
					       <297000000>,
					       <0>,
					       <400000000>,
					       <400000000>;

			ranges;

			sti-compositor@9d11000 {
				compatible = "st,stih407-compositor";
				reg = <0x9d11000 0x1000>;

				clock-names = "compo_main",
					      "compo_aux",
					      "pix_main",
					      "pix_aux",
					      "pix_gdp1",
					      "pix_gdp2",
					      "pix_gdp3",
					      "pix_gdp4",
					      "main_parent",
					      "aux_parent";

				clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					 <&clk_s_c0_flexgen CLK_COMPO_DVP>,
					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP1>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP2>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP3>,
					 <&clk_s_d2_flexgen CLK_PIX_GDP4>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;

				reset-names = "compo-main", "compo-aux";
				resets = <&softreset STIH407_COMPO_SOFTRESET>,
					 <&softreset STIH407_COMPO_SOFTRESET>;
				st,vtg = <&vtg_main>, <&vtg_aux>;
			};

			sti-tvout@8d08000 {
				compatible = "st,stih407-tvout";
				reg = <0x8d08000 0x1000>;
				reg-names = "tvout-reg";
				reset-names = "tvout";
				resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
				#address-cells = <1>;
				#size-cells = <1>;
				assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
						  <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
						  <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
						  <&clk_s_d0_flexgen CLK_PCM_0>,
						  <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
						  <&clk_s_d2_flexgen CLK_HDDAC>;

				assigned-clock-parents = <&clk_s_d2_quadfs 0>,
							 <&clk_tmdsout_hdmi>,
							 <&clk_s_d2_quadfs 0>,
							 <&clk_s_d0_quadfs 0>,
							 <&clk_s_d2_quadfs 0>,
							 <&clk_s_d2_quadfs 0>;
			};

			sti_hdmi: sti-hdmi@8d04000 {
				compatible = "st,stih407-hdmi";
				reg = <0x8d04000 0x1000>;
				reg-names = "hdmi-reg";
				#sound-dai-cells = <0>;
				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "irq";
				clock-names = "pix",
					      "tmds",
					      "phy",
					      "audio",
					      "main_parent",
					      "aux_parent";

				clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
					 <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
					 <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
					 <&clk_s_d0_flexgen CLK_PCM_0>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;

				hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
				reset-names = "hdmi";
				resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
				ddc = <&hdmiddc>;
			};

			sti-hda@8d02000 {
				compatible = "st,stih407-hda";
				status = "disabled";
				reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
				reg-names = "hda-reg", "video-dacs-ctrl";
				clock-names = "pix",
					      "hddac",
					      "main_parent",
					      "aux_parent";
				clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
					 <&clk_s_d2_flexgen CLK_HDDAC>,
					 <&clk_s_d2_quadfs 0>,
					 <&clk_s_d2_quadfs 1>;
			};

			sti-hqvdp@9c00000 {
				compatible = "st,stih407-hqvdp";
				reg = <0x9C00000 0x100000>;
				clock-names = "hqvdp", "pix_main";
				clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
					 <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
				reset-names = "hqvdp";
				resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
				st,vtg = <&vtg_main>;
			};
		};

		bdisp0:bdisp@9f10000 {
			compatible = "st,stih407-bdisp";
			reg = <0x9f10000 0x1000>;
			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "bdisp";
			clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
		};

		hva@8c85000 {
			compatible = "st,st-hva";
			reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
			reg-names = "hva_registers", "hva_esram";
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "clk_hva";
			clocks = <&clk_s_c0_flexgen CLK_HVA>;
		};

		thermal@91a0000 {
			compatible = "st,stih407-thermal";
			reg = <0x91a0000 0x28>;
			clock-names = "thermal";
			clocks = <&clk_sysin>;
			interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
		};

		delta0@0 {
			compatible = "st,st-delta";
			clock-names = "delta",
				      "delta-st231",
				      "delta-flash-promip";
			clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
				 <&clk_s_c0_flexgen CLK_ST231_DMU>,
				 <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
		};

		sti-cec@94a087c {
			compatible = "st,stih-cec";
			reg = <0x94a087c 0x64>;
			clocks = <&clk_sysin>;
			clock-names = "cec-clk";
			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "cec-irq";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_cec0_default>;
			resets = <&softreset STIH407_LPM_SOFTRESET>;
			hdmi-phandle = <&sti_hdmi>;
		};
	};
};
Commit	Line	Data
b16b77a5 PG	1	/*
	2	* Copyright (C) 2014 STMicroelectronics Limited.
	3	* Author: Peter Griffin <peter.griffin@linaro.org>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* publishhed by the Free Software Foundation.
	8	*/
	9	#include "stih410-clock.dtsi"
	10	#include "stih407-family.dtsi"
	11	#include "stih410-pinctrl.dtsi"
7ac1f59c	12	#include <dt-bindings/gpio/gpio.h>
b16b77a5	13	/ {
79444509 FD	14	aliases {
	15	bdisp0 = &bdisp0;
	16	};
	17
9d9f65fc	18	soc {
1d91958f	19	usb2_picophy1: phy2@0 {
9d9f65fc	20	compatible = "st,stih407-usb2-phy";
1d91958f	21	reg = <0 0>;
9d9f65fc PG	22	#phy-cells = <0>;
	23	st,syscfg = <&syscfg_core 0xf8 0xf4>;
	24	resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
	25	<&picophyreset STIH407_PICOPHY0_RESET>;
	26	reset-names = "global", "port";
b771ae27 MC	27
b771ae27 MC	28	status = "disabled";
9d9f65fc	29	};
b16b77a5	30
1d91958f	31	usb2_picophy2: phy3@0 {
9d9f65fc	32	compatible = "st,stih407-usb2-phy";
1d91958f	33	reg = <0 0>;
9d9f65fc PG	34	#phy-cells = <0>;
	35	st,syscfg = <&syscfg_core 0xfc 0xf4>;
	36	resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
	37	<&picophyreset STIH407_PICOPHY1_RESET>;
	38	reset-names = "global", "port";
b771ae27 MC	39
b771ae27 MC	40	status = "disabled";
9d9f65fc	41	};
a59a4d96 PG	42
	43	ohci0: usb@9a03c00 {
	44	compatible = "st,st-ohci-300x";
	45	reg = <0x9a03c00 0x100>;
fd827d0e	46	interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
7e9d2850 LJ	47	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
7e9d2850 LJ	48	<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
a59a4d96 PG	49	resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
	50	<&softreset STIH407_USB2_PORT0_SOFTRESET>;
	51	reset-names = "power", "softreset";
	52	phys = <&usb2_picophy1>;
	53	phy-names = "usb";
b771ae27 MC	54
b771ae27 MC	55	status = "disabled";
a59a4d96 PG	56	};
	57
	58	ehci0: usb@9a03e00 {
	59	compatible = "st,st-ehci-300x";
	60	reg = <0x9a03e00 0x100>;
fd827d0e	61	interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
a59a4d96 PG	62	pinctrl-names = "default";
a59a4d96 PG	63	pinctrl-0 = <&pinctrl_usb0>;
7e9d2850 LJ	64	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
7e9d2850 LJ	65	<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
a59a4d96 PG	66	resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
	67	<&softreset STIH407_USB2_PORT0_SOFTRESET>;
	68	reset-names = "power", "softreset";
	69	phys = <&usb2_picophy1>;
	70	phy-names = "usb";
b771ae27 MC	71
b771ae27 MC	72	status = "disabled";
a59a4d96 PG	73	};
	74
	75	ohci1: usb@9a83c00 {
	76	compatible = "st,st-ohci-300x";
	77	reg = <0x9a83c00 0x100>;
fd827d0e	78	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
7e9d2850 LJ	79	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
7e9d2850 LJ	80	<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
a59a4d96 PG	81	resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
	82	<&softreset STIH407_USB2_PORT1_SOFTRESET>;
	83	reset-names = "power", "softreset";
	84	phys = <&usb2_picophy2>;
	85	phy-names = "usb";
b771ae27 MC	86
b771ae27 MC	87	status = "disabled";
a59a4d96 PG	88	};
	89
	90	ehci1: usb@9a83e00 {
	91	compatible = "st,st-ehci-300x";
	92	reg = <0x9a83e00 0x100>;
fd827d0e	93	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
a59a4d96 PG	94	pinctrl-names = "default";
a59a4d96 PG	95	pinctrl-0 = <&pinctrl_usb1>;
7e9d2850 LJ	96	clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
7e9d2850 LJ	97	<&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
a59a4d96 PG	98	resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
	99	<&softreset STIH407_USB2_PORT1_SOFTRESET>;
	100	reset-names = "power", "softreset";
	101	phys = <&usb2_picophy2>;
	102	phy-names = "usb";
956b42d1	103
b771ae27	104	status = "disabled";
956b42d1 GF	105	};
956b42d1 GF	106
0b09a91a	107	sti-display-subsystem@0 {
956b42d1 GF	108	compatible = "st,sti-display-subsystem";
	109	#address-cells = <1>;
	110	#size-cells = <1>;
	111
0b09a91a	112	reg = <0 0>;
956b42d1	113	assigned-clocks = <&clk_s_d2_quadfs 0>,
3a74152c GF	114	<&clk_s_d2_quadfs 1>,
	115	<&clk_s_c0_pll1 0>,
	116	<&clk_s_c0_flexgen CLK_COMPO_DVP>,
	117	<&clk_s_c0_flexgen CLK_MAIN_DISP>,
956b42d1 GF	118	<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
	119	<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
	120	<&clk_s_d2_flexgen CLK_PIX_GDP1>,
	121	<&clk_s_d2_flexgen CLK_PIX_GDP2>,
	122	<&clk_s_d2_flexgen CLK_PIX_GDP3>,
	123	<&clk_s_d2_flexgen CLK_PIX_GDP4>;
	124
	125	assigned-clock-parents = <0>,
	126	<0>,
3a74152c GF	127	<0>,
	128	<&clk_s_c0_pll1 0>,
	129	<&clk_s_c0_pll1 0>,
956b42d1	130	<&clk_s_d2_quadfs 0>,
3a74152c	131	<&clk_s_d2_quadfs 1>,
956b42d1 GF	132	<&clk_s_d2_quadfs 0>,
	133	<&clk_s_d2_quadfs 0>,
	134	<&clk_s_d2_quadfs 0>,
	135	<&clk_s_d2_quadfs 0>;
	136
3a74152c	137	assigned-clock-rates = <297000000>,
b9ec866d	138	<297000000>,
3a74152c GF	139	<0>,
	140	<400000000>,
	141	<400000000>;
956b42d1 GF	142
	143	ranges;
	144
	145	sti-compositor@9d11000 {
	146	compatible = "st,stih407-compositor";
	147	reg = <0x9d11000 0x1000>;
	148
	149	clock-names = "compo_main",
	150	"compo_aux",
	151	"pix_main",
	152	"pix_aux",
	153	"pix_gdp1",
	154	"pix_gdp2",
	155	"pix_gdp3",
	156	"pix_gdp4",
	157	"main_parent",
	158	"aux_parent";
	159
	160	clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
	161	<&clk_s_c0_flexgen CLK_COMPO_DVP>,
	162	<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
	163	<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
	164	<&clk_s_d2_flexgen CLK_PIX_GDP1>,
	165	<&clk_s_d2_flexgen CLK_PIX_GDP2>,
	166	<&clk_s_d2_flexgen CLK_PIX_GDP3>,
	167	<&clk_s_d2_flexgen CLK_PIX_GDP4>,
	168	<&clk_s_d2_quadfs 0>,
	169	<&clk_s_d2_quadfs 1>;
	170
	171	reset-names = "compo-main", "compo-aux";
	172	resets = <&softreset STIH407_COMPO_SOFTRESET>,
	173	<&softreset STIH407_COMPO_SOFTRESET>;
	174	st,vtg = <&vtg_main>, <&vtg_aux>;
	175	};
	176
	177	sti-tvout@8d08000 {
	178	compatible = "st,stih407-tvout";
	179	reg = <0x8d08000 0x1000>;
	180	reg-names = "tvout-reg";
	181	reset-names = "tvout";
	182	resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
	183	#address-cells = <1>;
	184	#size-cells = <1>;
	185	assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
	186	<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
	187	<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
	188	<&clk_s_d0_flexgen CLK_PCM_0>,
	189	<&clk_s_d2_flexgen CLK_PIX_HDDAC>,
	190	<&clk_s_d2_flexgen CLK_HDDAC>;
	191
	192	assigned-clock-parents = <&clk_s_d2_quadfs 0>,
	193	<&clk_tmdsout_hdmi>,
	194	<&clk_s_d2_quadfs 0>,
	195	<&clk_s_d0_quadfs 0>,
	196	<&clk_s_d2_quadfs 0>,
	197	<&clk_s_d2_quadfs 0>;
79a313f5 BG	198	};
79a313f5 BG	199
24595472	200	sti_hdmi: sti-hdmi@8d04000 {
79a313f5 BG	201	compatible = "st,stih407-hdmi";
	202	reg = <0x8d04000 0x1000>;
	203	reg-names = "hdmi-reg";
4f21a120	204	#sound-dai-cells = <0>;
fd827d0e	205	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
79a313f5 BG	206	interrupt-names = "irq";
	207	clock-names = "pix",
	208	"tmds",
	209	"phy",
	210	"audio",
	211	"main_parent",
	212	"aux_parent";
	213
	214	clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
	215	<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
	216	<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
	217	<&clk_s_d0_flexgen CLK_PCM_0>,
	218	<&clk_s_d2_quadfs 0>,
	219	<&clk_s_d2_quadfs 1>;
	220
7ac1f59c	221	hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
79a313f5 BG	222	reset-names = "hdmi";
	223	resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
	224	ddc = <&hdmiddc>;
	225	};
	226
	227	sti-hda@8d02000 {
	228	compatible = "st,stih407-hda";
9d65f902	229	status = "disabled";
79a313f5 BG	230	reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
	231	reg-names = "hda-reg", "video-dacs-ctrl";
	232	clock-names = "pix",
	233	"hddac",
	234	"main_parent",
	235	"aux_parent";
	236	clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
	237	<&clk_s_d2_flexgen CLK_HDDAC>,
	238	<&clk_s_d2_quadfs 0>,
	239	<&clk_s_d2_quadfs 1>;
956b42d1	240	};
241a6878	241
d6d854cc	242	sti-hqvdp@9c00000 {
241a6878 PC	243	compatible = "st,stih407-hqvdp";
	244	reg = <0x9C00000 0x100000>;
	245	clock-names = "hqvdp", "pix_main";
	246	clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
	247	<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
	248	reset-names = "hqvdp";
	249	resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
	250	st,vtg = <&vtg_main>;
	251	};
956b42d1	252	};
79444509 FD	253
	254	bdisp0:bdisp@9f10000 {
	255	compatible = "st,stih407-bdisp";
	256	reg = <0x9f10000 0x1000>;
fd827d0e	257	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
79444509 FD	258	clock-names = "bdisp";
	259	clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
	260	};
70bc0f3a	261
390aafe3 JCT	262	hva@8c85000 {
	263	compatible = "st,st-hva";
	264	reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
	265	reg-names = "hva_registers", "hva_esram";
fd827d0e PC	266	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
fd827d0e PC	267	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
390aafe3 JCT	268	clock-names = "clk_hva";
	269	clocks = <&clk_s_c0_flexgen CLK_HVA>;
	270	};
	271
70bc0f3a PC	272	thermal@91a0000 {
	273	compatible = "st,stih407-thermal";
	274	reg = <0x91a0000 0x28>;
	275	clock-names = "thermal";
	276	clocks = <&clk_sysin>;
	277	interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
	278	};
b005ebf9	279
5eccdffb	280	delta0@0 {
b005ebf9 HF	281	compatible = "st,st-delta";
	282	clock-names = "delta",
	283	"delta-st231",
	284	"delta-flash-promip";
	285	clocks = <&clk_s_c0_flexgen CLK_VID_DMU>,
	286	<&clk_s_c0_flexgen CLK_ST231_DMU>,
	287	<&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
	288	};
ed3022de	289
8dccafaa	290	sti-cec@94a087c {
ed3022de BG	291	compatible = "st,stih-cec";
	292	reg = <0x94a087c 0x64>;
	293	clocks = <&clk_sysin>;
	294	clock-names = "cec-clk";
fd827d0e	295	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
ed3022de BG	296	interrupt-names = "cec-irq";
	297	pinctrl-names = "default";
	298	pinctrl-0 = <&pinctrl_cec0_default>;
	299	resets = <&softreset STIH407_LPM_SOFTRESET>;
	300	hdmi-phandle = <&sti_hdmi>;
	301	};
9d9f65fc	302	};
b16b77a5	303	};