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Merge branch 'pm-cpufreq'
[linux-2.6-block.git] / arch / arm / boot / dts / stih407-family.dtsi
CommitLineData
f563a571
MC		 1/*
2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
8 */
f563a571 9#include "stih407-pinctrl.dtsi"
358764f3 10#include <dt-bindings/mfd/st-lpc.h>
b3d37f92 11#include <dt-bindings/phy/phy.h>
efdf5aa8 12#include <dt-bindings/reset/stih407-resets.h>
107dea0c 13#include <dt-bindings/interrupt-controller/irq-st.h>
f563a571
MC		 14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21 cpu@0 {
22 device_type = "cpu";
23 compatible = "arm,cortex-a9";
24 reg = <0>;
c1dc02da
PG		 25 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
26 cpu-release-addr = <0x94100A4>;
f563a571
MC		 27 };
28 cpu@1 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a9";
31 reg = <1>;
c1dc02da
PG		 32 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
33 cpu-release-addr = <0x94100A4>;
f563a571
MC		 34 };
35 };
36
37 intc: interrupt-controller@08761000 {
38 compatible = "arm,cortex-a9-gic";
39 #interrupt-cells = <3>;
40 interrupt-controller;
41 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
42 };
43
44 scu@08760000 {
45 compatible = "arm,cortex-a9-scu";
46 reg = <0x08760000 0x1000>;
47 };
48
49 timer@08760200 {
50 interrupt-parent = <&intc>;
51 compatible = "arm,cortex-a9-global-timer";
52 reg = <0x08760200 0x100>;
53 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
54 clocks = <&arm_periph_clk>;
55 };
56
57 l2: cache-controller {
58 compatible = "arm,pl310-cache";
59 reg = <0x08762000 0x1000>;
60 arm,data-latency = <3 3 3>;
61 arm,tag-latency = <2 2 2>;
62 cache-unified;
63 cache-level = <2>;
64 };
65
00133b91
LJ		 66 arm-pmu {
67 interrupt-parent = <&intc>;
68 compatible = "arm,cortex-a9-pmu";
69 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
70 };
71
23155ffc
LJ		 72 pwm_regulator: pwm-regulator {
73 compatible = "pwm-regulator";
74 pwms = <&pwm1 3 8448>;
75 regulator-name = "CPU_1V0_AVS";
76 regulator-min-microvolt = <784000>;
77 regulator-max-microvolt = <1299000>;
78 regulator-always-on;
79 max-duty-cycle = <255>;
80 status = "okay";
81 };
82
f563a571
MC		 83 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 interrupt-parent = <&intc>;
87 ranges;
88 compatible = "simple-bus";
89
48f3fe6b
LJ		 90 restart {
91 compatible = "st,stih407-restart";
92 st,syscfg = <&syscfg_sbc_reg>;
93 status = "okay";
94 };
95
b864a0b9
PG		 96 powerdown: powerdown-controller {
97 compatible = "st,stih407-powerdown";
98 #reset-cells = <1>;
99 };
100
101 softreset: softreset-controller {
102 compatible = "st,stih407-softreset";
103 #reset-cells = <1>;
104 };
105
106 picophyreset: picophyreset-controller {
107 compatible = "st,stih407-picophyreset";
108 #reset-cells = <1>;
109 };
110
f563a571
MC		 111 syscfg_sbc: sbc-syscfg@9620000 {
112 compatible = "st,stih407-sbc-syscfg", "syscon";
113 reg = <0x9620000 0x1000>;
114 };
115
116 syscfg_front: front-syscfg@9280000 {
117 compatible = "st,stih407-front-syscfg", "syscon";
118 reg = <0x9280000 0x1000>;
119 };
120
121 syscfg_rear: rear-syscfg@9290000 {
122 compatible = "st,stih407-rear-syscfg", "syscon";
123 reg = <0x9290000 0x1000>;
124 };
125
126 syscfg_flash: flash-syscfg@92a0000 {
127 compatible = "st,stih407-flash-syscfg", "syscon";
128 reg = <0x92a0000 0x1000>;
129 };
130
131 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
132 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
133 reg = <0x9600000 0x1000>;
134 };
135
136 syscfg_core: core-syscfg@92b0000 {
137 compatible = "st,stih407-core-syscfg", "syscon";
138 reg = <0x92b0000 0x1000>;
139 };
140
141 syscfg_lpm: lpm-syscfg@94b5100 {
142 compatible = "st,stih407-lpm-syscfg", "syscon";
143 reg = <0x94b5100 0x1000>;
144 };
145
107dea0c
LJ		 146 irq-syscfg {
147 compatible = "st,stih407-irq-syscfg";
148 st,syscfg = <&syscfg_core>;
149 st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
150 <ST_IRQ_SYSCFG_PMU_1>;
151 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
152 <ST_IRQ_SYSCFG_DISABLED>;
153 };
154
f563a571
MC		 155 serial@9830000 {
156 compatible = "st,asc";
157 reg = <0x9830000 0x2c>;
158 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_serial0>;
1befe7e4 161 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571
MC		 162
163 status = "disabled";
164 };
165
166 serial@9831000 {
167 compatible = "st,asc";
168 reg = <0x9831000 0x2c>;
169 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_serial1>;
1befe7e4 172 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571
MC		 173
174 status = "disabled";
175 };
176
177 serial@9832000 {
178 compatible = "st,asc";
179 reg = <0x9832000 0x2c>;
180 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_serial2>;
1befe7e4 183 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571
MC		 184
185 status = "disabled";
186 };
187
188 /* SBC_ASC0 - UART10 */
189 sbc_serial0: serial@9530000 {
190 compatible = "st,asc";
191 reg = <0x9530000 0x2c>;
192 interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_sbc_serial0>;
195 clocks = <&clk_sysin>;
196
197 status = "disabled";
198 };
199
200 serial@9531000 {
201 compatible = "st,asc";
202 reg = <0x9531000 0x2c>;
203 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_sbc_serial1>;
206 clocks = <&clk_sysin>;
207
208 status = "disabled";
209 };
210
211 i2c@9840000 {
212 compatible = "st,comms-ssc4-i2c";
213 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
214 reg = <0x9840000 0x110>;
1befe7e4 215 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571
MC		 216 clock-names = "ssc";
217 clock-frequency = <400000>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_i2c0_default>;
220
221 status = "disabled";
222 };
223
224 i2c@9841000 {
225 compatible = "st,comms-ssc4-i2c";
226 reg = <0x9841000 0x110>;
227 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4 228 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571
MC		 229 clock-names = "ssc";
230 clock-frequency = <400000>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_i2c1_default>;
233
234 status = "disabled";
235 };
236
237 i2c@9842000 {
238 compatible = "st,comms-ssc4-i2c";
239 reg = <0x9842000 0x110>;
240 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4 241 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571
MC		 242 clock-names = "ssc";
243 clock-frequency = <400000>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_i2c2_default>;
246
247 status = "disabled";
248 };
249
250 i2c@9843000 {
251 compatible = "st,comms-ssc4-i2c";
252 reg = <0x9843000 0x110>;
253 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4 254 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571
MC		 255 clock-names = "ssc";
256 clock-frequency = <400000>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_i2c3_default>;
259
260 status = "disabled";
261 };
262
263 i2c@9844000 {
264 compatible = "st,comms-ssc4-i2c";
265 reg = <0x9844000 0x110>;
266 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4 267 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571
MC		 268 clock-names = "ssc";
269 clock-frequency = <400000>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_i2c4_default>;
272
273 status = "disabled";
274 };
275
276 i2c@9845000 {
277 compatible = "st,comms-ssc4-i2c";
278 reg = <0x9845000 0x110>;
279 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1befe7e4 280 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
f563a571
MC		 281 clock-names = "ssc";
282 clock-frequency = <400000>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_i2c5_default>;
285
286 status = "disabled";
287 };
288
289
290 /* SSCs on SBC */
291 i2c@9540000 {
292 compatible = "st,comms-ssc4-i2c";
293 reg = <0x9540000 0x110>;
294 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clk_sysin>;
296 clock-names = "ssc";
297 clock-frequency = <400000>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_i2c10_default>;
300
301 status = "disabled";
302 };
303
304 i2c@9541000 {
305 compatible = "st,comms-ssc4-i2c";
306 reg = <0x9541000 0x110>;
307 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&clk_sysin>;
309 clock-names = "ssc";
310 clock-frequency = <400000>;
311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_i2c11_default>;
313
314 status = "disabled";
315 };
8facce13
PG		 316
317 usb2_picophy0: phy1 {
318 compatible = "st,stih407-usb2-phy";
319 #phy-cells = <0>;
320 st,syscfg = <&syscfg_core 0x100 0xf4>;
321 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
743ac9d2 322 <&picophyreset STIH407_PICOPHY2_RESET>;
8facce13
PG		 323 reset-names = "global", "port";
324 };
b26373c0
GF		 325
326 miphy28lp_phy: miphy28lp@9b22000 {
327 compatible = "st,miphy28lp-phy";
328 st,syscfg = <&syscfg_core>;
329 #address-cells = <1>;
330 #size-cells = <1>;
331 ranges;
332
333 phy_port0: port@9b22000 {
334 reg = <0x9b22000 0xff>,
335 <0x9b09000 0xff>,
336 <0x9b04000 0xff>;
337 reg-names = "sata-up",
338 "pcie-up",
339 "pipew";
340
341 st,syscfg = <0x114 0x818 0xe0 0xec>;
342 #phy-cells = <1>;
343
344 reset-names = "miphy-sw-rst";
345 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
346 };
347
348 phy_port1: port@9b2a000 {
349 reg = <0x9b2a000 0xff>,
350 <0x9b19000 0xff>,
351 <0x9b14000 0xff>;
352 reg-names = "sata-up",
353 "pcie-up",
354 "pipew";
355
356 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
357
358 #phy-cells = <1>;
359
360 reset-names = "miphy-sw-rst";
361 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
362 };
363
364 phy_port2: port@8f95000 {
365 reg = <0x8f95000 0xff>,
366 <0x8f90000 0xff>;
367 reg-names = "pipew",
368 "usb3-up";
369
370 st,syscfg = <0x11c 0x820>;
371
372 #phy-cells = <1>;
373
374 reset-names = "miphy-sw-rst";
375 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
376 };
377 };
2c53c272
LJ		 378
379 spi@9840000 {
380 compatible = "st,comms-ssc4-spi";
381 reg = <0x9840000 0x110>;
382 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
384 clock-names = "ssc";
385 pinctrl-0 = <&pinctrl_spi0_default>;
386 pinctrl-names = "default";
387 #address-cells = <1>;
388 #size-cells = <0>;
389
390 status = "disabled";
391 };
392
393 spi@9841000 {
394 compatible = "st,comms-ssc4-spi";
395 reg = <0x9841000 0x110>;
396 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
398 clock-names = "ssc";
399
400 status = "disabled";
401 };
402
403 spi@9842000 {
404 compatible = "st,comms-ssc4-spi";
405 reg = <0x9842000 0x110>;
406 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
408 clock-names = "ssc";
409
410 status = "disabled";
411 };
412
413 spi@9843000 {
414 compatible = "st,comms-ssc4-spi";
415 reg = <0x9843000 0x110>;
416 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
418 clock-names = "ssc";
419
420 status = "disabled";
421 };
422
423 spi@9844000 {
424 compatible = "st,comms-ssc4-spi";
425 reg = <0x9844000 0x110>;
426 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
428 clock-names = "ssc";
429
430 status = "disabled";
431 };
b0bb2bae
LJ		 432
433 /* SBC SSC */
434 spi@9540000 {
435 compatible = "st,comms-ssc4-spi";
436 reg = <0x9540000 0x110>;
437 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&clk_sysin>;
439 clock-names = "ssc";
440
441 status = "disabled";
442 };
443
444 spi@9541000 {
445 compatible = "st,comms-ssc4-spi";
446 reg = <0x9541000 0x110>;
447 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&clk_sysin>;
449 clock-names = "ssc";
450
451 status = "disabled";
452 };
453
454 spi@9542000 {
455 compatible = "st,comms-ssc4-spi";
456 reg = <0x9542000 0x110>;
457 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&clk_sysin>;
459 clock-names = "ssc";
460
461 status = "disabled";
462 };
9286ac48
PG		 463
464 mmc0: sdhci@09060000 {
465 compatible = "st,sdhci-stih407", "st,sdhci";
466 status = "disabled";
467 reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
468 reg-names = "mmc", "top-mmc-delay";
469 interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
470 interrupt-names = "mmcirq";
471 pinctrl-names = "default";
472 pinctrl-0 = <&pinctrl_mmc0>;
473 clock-names = "mmc";
474 clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
475 bus-width = <8>;
476 non-removable;
477 };
478
479 mmc1: sdhci@09080000 {
480 compatible = "st,sdhci-stih407", "st,sdhci";
481 status = "disabled";
482 reg = <0x09080000 0x7ff>;
483 reg-names = "mmc";
484 interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
485 interrupt-names = "mmcirq";
486 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_sd1>;
488 clock-names = "mmc";
489 clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
490 resets = <&softreset STIH407_MMC1_SOFTRESET>;
491 bus-width = <4>;
492 };
358764f3
LJ		 493
494 /* Watchdog and Real-Time Clock */
495 lpc@8787000 {
496 compatible = "st,stih407-lpc";
497 reg = <0x8787000 0x1000>;
498 interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>;
499 clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
500 timeout-sec = <120>;
501 st,syscfg = <&syscfg_core>;
502 st,lpc-mode = <ST_LPC_MODE_WDT>;
503 };
504
505 lpc@8788000 {
506 compatible = "st,stih407-lpc";
507 reg = <0x8788000 0x1000>;
508 interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>;
509 clocks = <&clk_s_d3_flexgen CLK_LPC_1>;
510 st,lpc-mode = <ST_LPC_MODE_RTC>;
511 };
b3d37f92
PG		 512
513 sata0: sata@9b20000 {
514 compatible = "st,ahci";
515 reg = <0x9b20000 0x1000>;
516
517 interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
518 interrupt-names = "hostc";
519
520 phys = <&phy_port0 PHY_TYPE_SATA>;
521 phy-names = "ahci_phy";
522
523 resets = <&powerdown STIH407_SATA0_POWERDOWN>,
524 <&softreset STIH407_SATA0_SOFTRESET>,
525 <&softreset STIH407_SATA0_PWR_SOFTRESET>;
526 reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
527
528 clock-names = "ahci_clk";
529 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
530
531 status = "disabled";
532 };
533
534 sata1: sata@9b28000 {
535 compatible = "st,ahci";
536 reg = <0x9b28000 0x1000>;
537
538 interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>;
539 interrupt-names = "hostc";
540
541 phys = <&phy_port1 PHY_TYPE_SATA>;
542 phy-names = "ahci_phy";
543
544 resets = <&powerdown STIH407_SATA1_POWERDOWN>,
545 <&softreset STIH407_SATA1_SOFTRESET>,
546 <&softreset STIH407_SATA1_PWR_SOFTRESET>;
547 reset-names = "pwr-dwn",
548 "sw-rst",
549 "pwr-rst";
550
551 clock-names = "ahci_clk";
552 clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
553
554 status = "disabled";
555 };
fd555998 556
cd9f59ca 557
fd555998
PG		 558 st_dwc3: dwc3@8f94000 {
559 compatible = "st,stih407-dwc3";
560 reg = <0x08f94000 0x1000>, <0x110 0x4>;
561 reg-names = "reg-glue", "syscfg-reg";
562 st,syscfg = <&syscfg_core>;
563 resets = <&powerdown STIH407_USB3_POWERDOWN>,
564 <&softreset STIH407_MIPHY2_SOFTRESET>;
565 reset-names = "powerdown", "softreset";
566 #address-cells = <1>;
567 #size-cells = <1>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_usb3>;
570 ranges;
571
572 status = "disabled";
573
574 dwc3: dwc3@9900000 {
575 compatible = "snps,dwc3";
576 reg = <0x09900000 0x100000>;
577 interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
578 dr_mode = "host";
579 phy-names = "usb2-phy", "usb3-phy";
580 phys = <&usb2_picophy0>,
581 <&phy_port2 PHY_TYPE_USB3>;
582 };
583 };
cd9f59ca
LJ		 584
585 /* COMMS PWM Module */
586 pwm0: pwm@9810000 {
587 compatible = "st,sti-pwm";
588 status = "okay";
589 #pwm-cells = <2>;
590 reg = <0x9810000 0x68>;
591 pinctrl-names = "default";
592 pinctrl-0 = <&pinctrl_pwm0_chan0_default>;
593 clock-names = "pwm";
594 clocks = <&clk_sysin>;
595 st,pwm-num-chan = <1>;
596 };
597
598 /* SBC PWM Module */
599 pwm1: pwm@9510000 {
600 compatible = "st,sti-pwm";
601 status = "okay";
602 #pwm-cells = <2>;
603 reg = <0x9510000 0x68>;
604 pinctrl-names = "default";
605 pinctrl-0 = <&pinctrl_pwm1_chan0_default
606 &pinctrl_pwm1_chan1_default
607 &pinctrl_pwm1_chan2_default
608 &pinctrl_pwm1_chan3_default>;
609 clock-names = "pwm";
610 clocks = <&clk_sysin>;
611 st,pwm-num-chan = <4>;
612 };
f563a571
MC		 613 };
614};
Linux 6.x block layer and io_uring tree(s)