projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 475dc86d DN |
1 | /* |
| 2 | * Copyright Altera Corporation (C) 2014. All rights reserved. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify | |
| 5 | * it under the terms and conditions of the GNU General Public License, | |
| 6 | * version 2, as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 11 | * more details. | |
| 12 | * | |
| 13 | * You should have received a copy of the GNU General Public License along with | |
| 14 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
| 15 | */ | |
| 16 | ||
| 475dc86d | 17 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 6855e5b7 | 18 | #include <dt-bindings/reset/altr,rst-mgr-a10.h> |
| 475dc86d DN |
19 | |
| 20 | / { | |
| 21 | #address-cells = <1>; | |
| 22 | #size-cells = <1>; | |
| 23 | ||
| 475dc86d DN |
24 | cpus { |
| 25 | #address-cells = <1>; | |
| 26 | #size-cells = <0>; | |
| ebbce1bb | 27 | enable-method = "altr,socfpga-a10-smp"; |
| 475dc86d DN |
28 | |
| 29 | cpu@0 { | |
| 30 | compatible = "arm,cortex-a9"; | |
| 31 | device_type = "cpu"; | |
| 32 | reg = <0>; | |
| 33 | next-level-cache = <&L2>; | |
| 34 | }; | |
| 35 | cpu@1 { | |
| 36 | compatible = "arm,cortex-a9"; | |
| 37 | device_type = "cpu"; | |
| 38 | reg = <1>; | |
| 39 | next-level-cache = <&L2>; | |
| 40 | }; | |
| 41 | }; | |
| 42 | ||
| 43 | intc: intc@ffffd000 { | |
| 44 | compatible = "arm,cortex-a9-gic"; | |
| 45 | #interrupt-cells = <3>; | |
| 46 | interrupt-controller; | |
| 47 | reg = <0xffffd000 0x1000>, | |
| 48 | <0xffffc100 0x100>; | |
| 49 | }; | |
| 50 | ||
| 51 | soc { | |
| 52 | #address-cells = <1>; | |
| 53 | #size-cells = <1>; | |
| 54 | compatible = "simple-bus"; | |
| 55 | device_type = "soc"; | |
| 56 | interrupt-parent = <&intc>; | |
| 57 | ranges; | |
| 58 | ||
| 59 | amba { | |
| 2ef7d5f3 | 60 | compatible = "simple-bus"; |
| 475dc86d DN |
61 | #address-cells = <1>; |
| 62 | #size-cells = <1>; | |
| 63 | ranges; | |
| 64 | ||
| 65 | pdma: pdma@ffda1000 { | |
| 66 | compatible = "arm,pl330", "arm,primecell"; | |
| 67 | reg = <0xffda1000 0x1000>; | |
| 68 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, | |
| 69 | <0 84 IRQ_TYPE_LEVEL_HIGH>, | |
| 70 | <0 85 IRQ_TYPE_LEVEL_HIGH>, | |
| 71 | <0 86 IRQ_TYPE_LEVEL_HIGH>, | |
| 72 | <0 87 IRQ_TYPE_LEVEL_HIGH>, | |
| 73 | <0 88 IRQ_TYPE_LEVEL_HIGH>, | |
| 74 | <0 89 IRQ_TYPE_LEVEL_HIGH>, | |
| a1e89630 GM |
75 | <0 90 IRQ_TYPE_LEVEL_HIGH>, |
| 76 | <0 91 IRQ_TYPE_LEVEL_HIGH>; | |
| 475dc86d DN |
77 | #dma-cells = <1>; |
| 78 | #dma-channels = <8>; | |
| 79 | #dma-requests = <32>; | |
| a1e89630 GM |
80 | clocks = <&l4_main_clk>; |
| 81 | clock-names = "apb_pclk"; | |
| 475dc86d DN |
82 | }; |
| 83 | }; | |
| 84 | ||
| 984442b7 DN |
85 | base_fpga_region { |
| 86 | #address-cells = <0x1>; | |
| 87 | #size-cells = <0x1>; | |
| 88 | ||
| 89 | compatible = "fpga-region"; | |
| 90 | fpga-mgr = <&fpga_mgr>; | |
| 91 | }; | |
| 92 | ||
| 475dc86d DN |
93 | clkmgr@ffd04000 { |
| 94 | compatible = "altr,clk-mgr"; | |
| 95 | reg = <0xffd04000 0x1000>; | |
| 96 | ||
| 97 | clocks { | |
| 98 | #address-cells = <1>; | |
| 99 | #size-cells = <0>; | |
| 100 | ||
| da29d824 DN |
101 | cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { |
| 102 | #clock-cells = <0>; | |
| 103 | compatible = "fixed-clock"; | |
| 104 | }; | |
| 105 | ||
| 106 | cb_intosc_ls_clk: cb_intosc_ls_clk { | |
| 107 | #clock-cells = <0>; | |
| 108 | compatible = "fixed-clock"; | |
| 109 | }; | |
| 110 | ||
| 111 | f2s_free_clk: f2s_free_clk { | |
| 112 | #clock-cells = <0>; | |
| 113 | compatible = "fixed-clock"; | |
| 114 | }; | |
| 115 | ||
| 475dc86d DN |
116 | osc1: osc1 { |
| 117 | #clock-cells = <0>; | |
| 118 | compatible = "fixed-clock"; | |
| 119 | }; | |
| 120 | ||
| 9f24e816 | 121 | main_pll: main_pll@40 { |
| 475dc86d DN |
122 | #address-cells = <1>; |
| 123 | #size-cells = <0>; | |
| 124 | #clock-cells = <0>; | |
| da29d824 DN |
125 | compatible = "altr,socfpga-a10-pll-clock"; |
| 126 | clocks = <&osc1>, <&cb_intosc_ls_clk>, | |
| 127 | <&f2s_free_clk>; | |
| 128 | reg = <0x40>; | |
| 129 | ||
| 130 | main_mpu_base_clk: main_mpu_base_clk { | |
| 131 | #clock-cells = <0>; | |
| 132 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 133 | clocks = <&main_pll>; | |
| 134 | div-reg = <0x140 0 11>; | |
| 135 | }; | |
| 136 | ||
| 137 | main_noc_base_clk: main_noc_base_clk { | |
| 138 | #clock-cells = <0>; | |
| 139 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 140 | clocks = <&main_pll>; | |
| 141 | div-reg = <0x144 0 11>; | |
| 142 | }; | |
| 143 | ||
| 9f24e816 | 144 | main_emaca_clk: main_emaca_clk@68 { |
| da29d824 DN |
145 | #clock-cells = <0>; |
| 146 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 147 | clocks = <&main_pll>; | |
| 148 | reg = <0x68>; | |
| 149 | }; | |
| 150 | ||
| 9f24e816 | 151 | main_emacb_clk: main_emacb_clk@6c { |
| da29d824 DN |
152 | #clock-cells = <0>; |
| 153 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 154 | clocks = <&main_pll>; | |
| 155 | reg = <0x6C>; | |
| 156 | }; | |
| 157 | ||
| 9f24e816 | 158 | main_emac_ptp_clk: main_emac_ptp_clk@70 { |
| da29d824 DN |
159 | #clock-cells = <0>; |
| 160 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 161 | clocks = <&main_pll>; | |
| 162 | reg = <0x70>; | |
| 163 | }; | |
| 164 | ||
| 9f24e816 | 165 | main_gpio_db_clk: main_gpio_db_clk@74 { |
| da29d824 DN |
166 | #clock-cells = <0>; |
| 167 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 168 | clocks = <&main_pll>; | |
| 169 | reg = <0x74>; | |
| 170 | }; | |
| 171 | ||
| 9f24e816 | 172 | main_sdmmc_clk: main_sdmmc_clk@78 { |
| da29d824 DN |
173 | #clock-cells = <0>; |
| 174 | compatible = "altr,socfpga-a10-perip-clk" | |
| 175 | ; | |
| 176 | clocks = <&main_pll>; | |
| 177 | reg = <0x78>; | |
| 178 | }; | |
| 179 | ||
| 9f24e816 | 180 | main_s2f_usr0_clk: main_s2f_usr0_clk@7c { |
| da29d824 DN |
181 | #clock-cells = <0>; |
| 182 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 183 | clocks = <&main_pll>; | |
| 184 | reg = <0x7C>; | |
| 185 | }; | |
| 186 | ||
| 9f24e816 | 187 | main_s2f_usr1_clk: main_s2f_usr1_clk@80 { |
| da29d824 DN |
188 | #clock-cells = <0>; |
| 189 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 190 | clocks = <&main_pll>; | |
| 191 | reg = <0x80>; | |
| 192 | }; | |
| 193 | ||
| 9f24e816 | 194 | main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 { |
| da29d824 DN |
195 | #clock-cells = <0>; |
| 196 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 197 | clocks = <&main_pll>; | |
| 198 | reg = <0x84>; | |
| 199 | }; | |
| 200 | ||
| 9f24e816 | 201 | main_periph_ref_clk: main_periph_ref_clk@9c { |
| da29d824 DN |
202 | #clock-cells = <0>; |
| 203 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 204 | clocks = <&main_pll>; | |
| 205 | reg = <0x9C>; | |
| 206 | }; | |
| 475dc86d DN |
207 | }; |
| 208 | ||
| 9f24e816 | 209 | periph_pll: periph_pll@c0 { |
| 475dc86d DN |
210 | #address-cells = <1>; |
| 211 | #size-cells = <0>; | |
| 212 | #clock-cells = <0>; | |
| da29d824 DN |
213 | compatible = "altr,socfpga-a10-pll-clock"; |
| 214 | clocks = <&osc1>, <&cb_intosc_ls_clk>, | |
| 215 | <&f2s_free_clk>, <&main_periph_ref_clk>; | |
| 216 | reg = <0xC0>; | |
| 217 | ||
| 218 | peri_mpu_base_clk: peri_mpu_base_clk { | |
| 219 | #clock-cells = <0>; | |
| 220 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 221 | clocks = <&periph_pll>; | |
| 222 | div-reg = <0x140 16 11>; | |
| 223 | }; | |
| 224 | ||
| 225 | peri_noc_base_clk: peri_noc_base_clk { | |
| 226 | #clock-cells = <0>; | |
| 227 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 228 | clocks = <&periph_pll>; | |
| 229 | div-reg = <0x144 16 11>; | |
| 230 | }; | |
| 231 | ||
| 9f24e816 | 232 | peri_emaca_clk: peri_emaca_clk@e8 { |
| da29d824 DN |
233 | #clock-cells = <0>; |
| 234 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 235 | clocks = <&periph_pll>; | |
| 236 | reg = <0xE8>; | |
| 237 | }; | |
| 238 | ||
| 9f24e816 | 239 | peri_emacb_clk: peri_emacb_clk@ec { |
| da29d824 DN |
240 | #clock-cells = <0>; |
| 241 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 242 | clocks = <&periph_pll>; | |
| 243 | reg = <0xEC>; | |
| 244 | }; | |
| 245 | ||
| 9f24e816 | 246 | peri_emac_ptp_clk: peri_emac_ptp_clk@f0 { |
| da29d824 DN |
247 | #clock-cells = <0>; |
| 248 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 249 | clocks = <&periph_pll>; | |
| 250 | reg = <0xF0>; | |
| 251 | }; | |
| 252 | ||
| 9f24e816 | 253 | peri_gpio_db_clk: peri_gpio_db_clk@f4 { |
| da29d824 DN |
254 | #clock-cells = <0>; |
| 255 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 256 | clocks = <&periph_pll>; | |
| 257 | reg = <0xF4>; | |
| 258 | }; | |
| 259 | ||
| 9f24e816 | 260 | peri_sdmmc_clk: peri_sdmmc_clk@f8 { |
| da29d824 DN |
261 | #clock-cells = <0>; |
| 262 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 263 | clocks = <&periph_pll>; | |
| 264 | reg = <0xF8>; | |
| 265 | }; | |
| 266 | ||
| 9f24e816 | 267 | peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc { |
| da29d824 DN |
268 | #clock-cells = <0>; |
| 269 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 270 | clocks = <&periph_pll>; | |
| 271 | reg = <0xFC>; | |
| 272 | }; | |
| 273 | ||
| 9f24e816 | 274 | peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 { |
| da29d824 DN |
275 | #clock-cells = <0>; |
| 276 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 277 | clocks = <&periph_pll>; | |
| 278 | reg = <0x100>; | |
| 279 | }; | |
| 280 | ||
| 9f24e816 | 281 | peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 { |
| da29d824 DN |
282 | #clock-cells = <0>; |
| 283 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 284 | clocks = <&periph_pll>; | |
| 285 | reg = <0x104>; | |
| 286 | }; | |
| 287 | }; | |
| 288 | ||
| 9f24e816 | 289 | mpu_free_clk: mpu_free_clk@60 { |
| da29d824 DN |
290 | #clock-cells = <0>; |
| 291 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 292 | clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, | |
| 293 | <&osc1>, <&cb_intosc_hs_div2_clk>, | |
| 294 | <&f2s_free_clk>; | |
| 295 | reg = <0x60>; | |
| 296 | }; | |
| 297 | ||
| 9f24e816 | 298 | noc_free_clk: noc_free_clk@64 { |
| da29d824 DN |
299 | #clock-cells = <0>; |
| 300 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 301 | clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, | |
| 302 | <&osc1>, <&cb_intosc_hs_div2_clk>, | |
| 303 | <&f2s_free_clk>; | |
| 304 | reg = <0x64>; | |
| 305 | }; | |
| 306 | ||
| 9f24e816 | 307 | s2f_user1_free_clk: s2f_user1_free_clk@104 { |
| da29d824 DN |
308 | #clock-cells = <0>; |
| 309 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 310 | clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, | |
| 311 | <&osc1>, <&cb_intosc_hs_div2_clk>, | |
| 312 | <&f2s_free_clk>; | |
| 313 | reg = <0x104>; | |
| 314 | }; | |
| 315 | ||
| 9f24e816 | 316 | sdmmc_free_clk: sdmmc_free_clk@f8 { |
| da29d824 DN |
317 | #clock-cells = <0>; |
| 318 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 319 | clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, | |
| 320 | <&osc1>, <&cb_intosc_hs_div2_clk>, | |
| 321 | <&f2s_free_clk>; | |
| 322 | fixed-divider = <4>; | |
| 323 | reg = <0xF8>; | |
| 324 | }; | |
| 325 | ||
| 326 | l4_sys_free_clk: l4_sys_free_clk { | |
| 327 | #clock-cells = <0>; | |
| 328 | compatible = "altr,socfpga-a10-perip-clk"; | |
| 329 | clocks = <&noc_free_clk>; | |
| 330 | fixed-divider = <4>; | |
| 331 | }; | |
| 332 | ||
| 333 | l4_main_clk: l4_main_clk { | |
| 334 | #clock-cells = <0>; | |
| 335 | compatible = "altr,socfpga-a10-gate-clk"; | |
| 336 | clocks = <&noc_free_clk>; | |
| 337 | div-reg = <0xA8 0 2>; | |
| 338 | clk-gate = <0x48 1>; | |
| 339 | }; | |
| 340 | ||
| 341 | l4_mp_clk: l4_mp_clk { | |
| 342 | #clock-cells = <0>; | |
| 343 | compatible = "altr,socfpga-a10-gate-clk"; | |
| 344 | clocks = <&noc_free_clk>; | |
| 345 | div-reg = <0xA8 8 2>; | |
| 346 | clk-gate = <0x48 2>; | |
| 347 | }; | |
| 348 | ||
| 349 | l4_sp_clk: l4_sp_clk { | |
| 350 | #clock-cells = <0>; | |
| 351 | compatible = "altr,socfpga-a10-gate-clk"; | |
| 352 | clocks = <&noc_free_clk>; | |
| 353 | div-reg = <0xA8 16 2>; | |
| 354 | clk-gate = <0x48 3>; | |
| 355 | }; | |
| 356 | ||
| 357 | mpu_periph_clk: mpu_periph_clk { | |
| 358 | #clock-cells = <0>; | |
| 359 | compatible = "altr,socfpga-a10-gate-clk"; | |
| 360 | clocks = <&mpu_free_clk>; | |
| 361 | fixed-divider = <4>; | |
| 362 | clk-gate = <0x48 0>; | |
| 363 | }; | |
| 364 | ||
| 365 | sdmmc_clk: sdmmc_clk { | |
| 366 | #clock-cells = <0>; | |
| 367 | compatible = "altr,socfpga-a10-gate-clk"; | |
| 368 | clocks = <&sdmmc_free_clk>; | |
| 369 | clk-gate = <0xC8 5>; | |
| faf68cdf | 370 | clk-phase = <0 135>; |
| da29d824 DN |
371 | }; |
| 372 | ||
| 373 | qspi_clk: qspi_clk { | |
| 374 | #clock-cells = <0>; | |
| 375 | compatible = "altr,socfpga-a10-gate-clk"; | |
| 376 | clocks = <&l4_main_clk>; | |
| 377 | clk-gate = <0xC8 11>; | |
| 378 | }; | |
| 379 | ||
| 380 | nand_clk: nand_clk { | |
| 381 | #clock-cells = <0>; | |
| 382 | compatible = "altr,socfpga-a10-gate-clk"; | |
| 383 | clocks = <&l4_mp_clk>; | |
| 384 | clk-gate = <0xC8 10>; | |
| 385 | }; | |
| 386 | ||
| 387 | spi_m_clk: spi_m_clk { | |
| 388 | #clock-cells = <0>; | |
| 389 | compatible = "altr,socfpga-a10-gate-clk"; | |
| 390 | clocks = <&l4_main_clk>; | |
| 391 | clk-gate = <0xC8 9>; | |
| 392 | }; | |
| 393 | ||
| 394 | usb_clk: usb_clk { | |
| 395 | #clock-cells = <0>; | |
| 396 | compatible = "altr,socfpga-a10-gate-clk"; | |
| 397 | clocks = <&l4_mp_clk>; | |
| 398 | clk-gate = <0xC8 8>; | |
| 399 | }; | |
| 400 | ||
| 401 | s2f_usr1_clk: s2f_usr1_clk { | |
| 402 | #clock-cells = <0>; | |
| 403 | compatible = "altr,socfpga-a10-gate-clk"; | |
| 404 | clocks = <&peri_s2f_usr1_clk>; | |
| 405 | clk-gate = <0xC8 6>; | |
| 475dc86d DN |
406 | }; |
| 407 | }; | |
| 408 | }; | |
| 409 | ||
| cda1ade6 TT |
410 | socfpga_axi_setup: stmmac-axi-config { |
| 411 | snps,wr_osr_lmt = <0xf>; | |
| 412 | snps,rd_osr_lmt = <0xf>; | |
| 413 | snps,blen = <0 0 0 0 16 0 0>; | |
| 414 | }; | |
| 415 | ||
| 475dc86d DN |
416 | gmac0: ethernet@ff800000 { |
| 417 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; | |
| 112cadfd | 418 | altr,sysmgr-syscon = <&sysmgr 0x44 0>; |
| 475dc86d DN |
419 | reg = <0xff800000 0x2000>; |
| 420 | interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; | |
| 421 | interrupt-names = "macirq"; | |
| 422 | /* Filled in by bootloader */ | |
| 423 | mac-address = [00 00 00 00 00 00]; | |
| be9863ca VB |
424 | snps,multicast-filter-bins = <256>; |
| 425 | snps,perfect-filter-entries = <128>; | |
| 112cadfd DN |
426 | tx-fifo-depth = <4096>; |
| 427 | rx-fifo-depth = <16384>; | |
| 428 | clocks = <&l4_mp_clk>; | |
| 429 | clock-names = "stmmaceth"; | |
| 6855e5b7 DN |
430 | resets = <&rst EMAC0_RESET>; |
| 431 | reset-names = "stmmaceth"; | |
| cda1ade6 | 432 | snps,axi-config = <&socfpga_axi_setup>; |
| 475dc86d DN |
433 | status = "disabled"; |
| 434 | }; | |
| 435 | ||
| 436 | gmac1: ethernet@ff802000 { | |
| 437 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; | |
| 112cadfd | 438 | altr,sysmgr-syscon = <&sysmgr 0x48 0>; |
| 475dc86d DN |
439 | reg = <0xff802000 0x2000>; |
| 440 | interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; | |
| 441 | interrupt-names = "macirq"; | |
| 442 | /* Filled in by bootloader */ | |
| 443 | mac-address = [00 00 00 00 00 00]; | |
| be9863ca VB |
444 | snps,multicast-filter-bins = <256>; |
| 445 | snps,perfect-filter-entries = <128>; | |
| c01e8cdb VB |
446 | tx-fifo-depth = <4096>; |
| 447 | rx-fifo-depth = <16384>; | |
| 112cadfd DN |
448 | clocks = <&l4_mp_clk>; |
| 449 | clock-names = "stmmaceth"; | |
| 6855e5b7 DN |
450 | resets = <&rst EMAC1_RESET>; |
| 451 | reset-names = "stmmaceth"; | |
| cda1ade6 | 452 | snps,axi-config = <&socfpga_axi_setup>; |
| 475dc86d DN |
453 | status = "disabled"; |
| 454 | }; | |
| 455 | ||
| 456 | gmac2: ethernet@ff804000 { | |
| 457 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; | |
| 112cadfd | 458 | altr,sysmgr-syscon = <&sysmgr 0x4C 0>; |
| 475dc86d DN |
459 | reg = <0xff804000 0x2000>; |
| 460 | interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; | |
| 461 | interrupt-names = "macirq"; | |
| 462 | /* Filled in by bootloader */ | |
| 463 | mac-address = [00 00 00 00 00 00]; | |
| be9863ca VB |
464 | snps,multicast-filter-bins = <256>; |
| 465 | snps,perfect-filter-entries = <128>; | |
| c01e8cdb VB |
466 | tx-fifo-depth = <4096>; |
| 467 | rx-fifo-depth = <16384>; | |
| 112cadfd DN |
468 | clocks = <&l4_mp_clk>; |
| 469 | clock-names = "stmmaceth"; | |
| cda1ade6 | 470 | snps,axi-config = <&socfpga_axi_setup>; |
| 475dc86d DN |
471 | status = "disabled"; |
| 472 | }; | |
| 473 | ||
| 474 | gpio0: gpio@ffc02900 { | |
| 475 | #address-cells = <1>; | |
| 476 | #size-cells = <0>; | |
| 477 | compatible = "snps,dw-apb-gpio"; | |
| 478 | reg = <0xffc02900 0x100>; | |
| 479 | status = "disabled"; | |
| 480 | ||
| 481 | porta: gpio-controller@0 { | |
| 482 | compatible = "snps,dw-apb-gpio-port"; | |
| 483 | gpio-controller; | |
| 484 | #gpio-cells = <2>; | |
| 485 | snps,nr-gpios = <29>; | |
| 486 | reg = <0>; | |
| 487 | interrupt-controller; | |
| 488 | #interrupt-cells = <2>; | |
| 489 | interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; | |
| 490 | }; | |
| 491 | }; | |
| 492 | ||
| 493 | gpio1: gpio@ffc02a00 { | |
| 494 | #address-cells = <1>; | |
| 495 | #size-cells = <0>; | |
| 496 | compatible = "snps,dw-apb-gpio"; | |
| 497 | reg = <0xffc02a00 0x100>; | |
| 498 | status = "disabled"; | |
| 499 | ||
| 500 | portb: gpio-controller@0 { | |
| 501 | compatible = "snps,dw-apb-gpio-port"; | |
| 502 | gpio-controller; | |
| 503 | #gpio-cells = <2>; | |
| 504 | snps,nr-gpios = <29>; | |
| 505 | reg = <0>; | |
| 506 | interrupt-controller; | |
| 507 | #interrupt-cells = <2>; | |
| 508 | interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; | |
| 509 | }; | |
| 510 | }; | |
| 511 | ||
| 512 | gpio2: gpio@ffc02b00 { | |
| 513 | #address-cells = <1>; | |
| 514 | #size-cells = <0>; | |
| 515 | compatible = "snps,dw-apb-gpio"; | |
| 516 | reg = <0xffc02b00 0x100>; | |
| 517 | status = "disabled"; | |
| 518 | ||
| 519 | portc: gpio-controller@0 { | |
| 520 | compatible = "snps,dw-apb-gpio-port"; | |
| 521 | gpio-controller; | |
| 522 | #gpio-cells = <2>; | |
| 523 | snps,nr-gpios = <27>; | |
| 524 | reg = <0>; | |
| 525 | interrupt-controller; | |
| 526 | #interrupt-cells = <2>; | |
| 527 | interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; | |
| 528 | }; | |
| 529 | }; | |
| 530 | ||
| f8a89281 DN |
531 | fpga_mgr: fpga-mgr@ffd03000 { |
| 532 | compatible = "altr,socfpga-a10-fpga-mgr"; | |
| 533 | reg = <0xffd03000 0x100 | |
| 534 | 0xffcfe400 0x20>; | |
| 535 | clocks = <&l4_mp_clk>; | |
| 536 | resets = <&rst FPGAMGR_RESET>; | |
| 537 | reset-names = "fpgamgr"; | |
| 538 | }; | |
| 539 | ||
| 475dc86d DN |
540 | i2c0: i2c@ffc02200 { |
| 541 | #address-cells = <1>; | |
| 542 | #size-cells = <0>; | |
| 543 | compatible = "snps,designware-i2c"; | |
| 544 | reg = <0xffc02200 0x100>; | |
| 545 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; | |
| e7604ae2 | 546 | clocks = <&l4_sp_clk>; |
| 475dc86d DN |
547 | status = "disabled"; |
| 548 | }; | |
| 549 | ||
| 550 | i2c1: i2c@ffc02300 { | |
| 551 | #address-cells = <1>; | |
| 552 | #size-cells = <0>; | |
| 553 | compatible = "snps,designware-i2c"; | |
| 554 | reg = <0xffc02300 0x100>; | |
| 555 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; | |
| e7604ae2 | 556 | clocks = <&l4_sp_clk>; |
| 475dc86d DN |
557 | status = "disabled"; |
| 558 | }; | |
| 559 | ||
| 560 | i2c2: i2c@ffc02400 { | |
| 561 | #address-cells = <1>; | |
| 562 | #size-cells = <0>; | |
| 563 | compatible = "snps,designware-i2c"; | |
| 564 | reg = <0xffc02400 0x100>; | |
| 565 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | |
| e7604ae2 | 566 | clocks = <&l4_sp_clk>; |
| 475dc86d DN |
567 | status = "disabled"; |
| 568 | }; | |
| 569 | ||
| 570 | i2c3: i2c@ffc02500 { | |
| 571 | #address-cells = <1>; | |
| 572 | #size-cells = <0>; | |
| 573 | compatible = "snps,designware-i2c"; | |
| 574 | reg = <0xffc02500 0x100>; | |
| 575 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | |
| e7604ae2 | 576 | clocks = <&l4_sp_clk>; |
| 475dc86d DN |
577 | status = "disabled"; |
| 578 | }; | |
| 579 | ||
| 580 | i2c4: i2c@ffc02600 { | |
| 581 | #address-cells = <1>; | |
| 582 | #size-cells = <0>; | |
| 583 | compatible = "snps,designware-i2c"; | |
| 584 | reg = <0xffc02600 0x100>; | |
| 585 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; | |
| e7604ae2 | 586 | clocks = <&l4_sp_clk>; |
| 475dc86d DN |
587 | status = "disabled"; |
| 588 | }; | |
| 589 | ||
| f2d6f8f8 TT |
590 | spi1: spi@ffda5000 { |
| 591 | compatible = "snps,dw-apb-ssi"; | |
| 592 | #address-cells = <1>; | |
| 593 | #size-cells = <0>; | |
| 594 | reg = <0xffda5000 0x100>; | |
| 595 | interrupts = <0 102 4>; | |
| 596 | num-chipselect = <4>; | |
| 597 | bus-num = <0>; | |
| 598 | /*32bit_access;*/ | |
| 599 | tx-dma-channel = <&pdma 16>; | |
| 600 | rx-dma-channel = <&pdma 17>; | |
| 601 | clocks = <&spi_m_clk>; | |
| 602 | status = "disabled"; | |
| 603 | }; | |
| 604 | ||
| 54b4a8f5 | 605 | sdr: sdr@ffc25000 { |
| 7f0f5460 | 606 | compatible = "altr,sdr-ctl", "syscon"; |
| 54b4a8f5 TT |
607 | reg = <0xffcfb100 0x80>; |
| 608 | }; | |
| 609 | ||
| 475dc86d DN |
610 | L2: l2-cache@fffff000 { |
| 611 | compatible = "arm,pl310-cache"; | |
| 612 | reg = <0xfffff000 0x1000>; | |
| 613 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; | |
| 614 | cache-unified; | |
| 615 | cache-level = <2>; | |
| ecba2390 DN |
616 | prefetch-data = <1>; |
| 617 | prefetch-instr = <1>; | |
| 618 | arm,shared-override; | |
| 475dc86d DN |
619 | }; |
| 620 | ||
| 621 | mmc: dwmmc0@ff808000 { | |
| 622 | #address-cells = <1>; | |
| 623 | #size-cells = <0>; | |
| 624 | compatible = "altr,socfpga-dw-mshc"; | |
| 625 | reg = <0xff808000 0x1000>; | |
| 626 | interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; | |
| 627 | fifo-depth = <0x400>; | |
| faf68cdf | 628 | clocks = <&l4_mp_clk>, <&sdmmc_clk>; |
| da29d824 | 629 | clock-names = "biu", "ciu"; |
| 1dfb7d2f | 630 | status = "disabled"; |
| 475dc86d DN |
631 | }; |
| 632 | ||
| f549af06 GM |
633 | nand: nand@ffb90000 { |
| 634 | #address-cells = <1>; | |
| 635 | #size-cells = <1>; | |
| 636 | compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand"; | |
| 637 | reg = <0xffb90000 0x72000>, | |
| 638 | <0xffb80000 0x10000>; | |
| 639 | reg-names = "nand_data", "denali_reg"; | |
| 640 | interrupts = <0 99 4>; | |
| 641 | dma-mask = <0xffffffff>; | |
| 642 | clocks = <&nand_clk>; | |
| 643 | status = "disabled"; | |
| 644 | }; | |
| 645 | ||
| 475dc86d DN |
646 | ocram: sram@ffe00000 { |
| 647 | compatible = "mmio-sram"; | |
| 648 | reg = <0xffe00000 0x40000>; | |
| 649 | }; | |
| 650 | ||
| 0c9ff615 | 651 | eccmgr: eccmgr { |
| 64ded09d TT |
652 | compatible = "altr,socfpga-a10-ecc-manager"; |
| 653 | altr,sysmgr-syscon = <&sysmgr>; | |
| 654 | #address-cells = <1>; | |
| 655 | #size-cells = <1>; | |
| 656 | interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
| 657 | <0 0 IRQ_TYPE_LEVEL_HIGH>; | |
| a034a8d9 TT |
658 | interrupt-controller; |
| 659 | #interrupt-cells = <2>; | |
| 64ded09d TT |
660 | ranges; |
| 661 | ||
| 4586e4ea TT |
662 | sdramedac { |
| 663 | compatible = "altr,sdram-edac-a10"; | |
| 664 | altr,sdr-syscon = <&sdr>; | |
| 665 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH>, | |
| 666 | <49 IRQ_TYPE_LEVEL_HIGH>; | |
| 667 | }; | |
| 668 | ||
| 64ded09d TT |
669 | l2-ecc@ffd06010 { |
| 670 | compatible = "altr,socfpga-a10-l2-ecc"; | |
| 671 | reg = <0xffd06010 0x4>; | |
| a034a8d9 TT |
672 | interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, |
| 673 | <32 IRQ_TYPE_LEVEL_HIGH>; | |
| 64ded09d | 674 | }; |
| a44a7711 TT |
675 | |
| 676 | ocram-ecc@ff8c3000 { | |
| 677 | compatible = "altr,socfpga-a10-ocram-ecc"; | |
| 678 | reg = <0xff8c3000 0x400>; | |
| a034a8d9 TT |
679 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, |
| 680 | <33 IRQ_TYPE_LEVEL_HIGH>; | |
| a44a7711 | 681 | }; |
| a67adb32 TT |
682 | |
| 683 | emac0-rx-ecc@ff8c0800 { | |
| 684 | compatible = "altr,socfpga-eth-mac-ecc"; | |
| 685 | reg = <0xff8c0800 0x400>; | |
| 686 | altr,ecc-parent = <&gmac0>; | |
| 687 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, | |
| 688 | <36 IRQ_TYPE_LEVEL_HIGH>; | |
| 689 | }; | |
| 690 | ||
| 691 | emac0-tx-ecc@ff8c0c00 { | |
| 692 | compatible = "altr,socfpga-eth-mac-ecc"; | |
| 693 | reg = <0xff8c0c00 0x400>; | |
| 694 | altr,ecc-parent = <&gmac0>; | |
| 695 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, | |
| 696 | <37 IRQ_TYPE_LEVEL_HIGH>; | |
| 697 | }; | |
| 15ef94f4 TT |
698 | |
| 699 | dma-ecc@ff8c8000 { | |
| 700 | compatible = "altr,socfpga-dma-ecc"; | |
| 701 | reg = <0xff8c8000 0x400>; | |
| 702 | altr,ecc-parent = <&pdma>; | |
| 703 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, | |
| 704 | <42 IRQ_TYPE_LEVEL_HIGH>; | |
| 705 | }; | |
| 7c51d98d TT |
706 | |
| 707 | usb0-ecc@ff8c8800 { | |
| 708 | compatible = "altr,socfpga-usb-ecc"; | |
| 709 | reg = <0xff8c8800 0x400>; | |
| 710 | altr,ecc-parent = <&usb0>; | |
| 711 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, | |
| 712 | <34 IRQ_TYPE_LEVEL_HIGH>; | |
| 713 | }; | |
| 64ded09d TT |
714 | }; |
| 715 | ||
| 5d662bf1 DN |
716 | qspi: spi@ff809000 { |
| 717 | compatible = "cdns,qspi-nor"; | |
| 718 | #address-cells = <1>; | |
| 719 | #size-cells = <0>; | |
| 720 | reg = <0xff809000 0x100>, | |
| 721 | <0xffa00000 0x100000>; | |
| 722 | interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; | |
| 723 | cdns,fifo-depth = <128>; | |
| 724 | cdns,fifo-width = <4>; | |
| 725 | cdns,trigger-address = <0x00000000>; | |
| 726 | clocks = <&qspi_clk>; | |
| 727 | status = "disabled"; | |
| 728 | }; | |
| 729 | ||
| 475dc86d DN |
730 | rst: rstmgr@ffd05000 { |
| 731 | #reset-cells = <1>; | |
| 732 | compatible = "altr,rst-mgr"; | |
| 733 | reg = <0xffd05000 0x100>; | |
| 1a94acf8 | 734 | altr,modrst-offset = <0x20>; |
| 475dc86d DN |
735 | }; |
| 736 | ||
| 479f8df0 DN |
737 | scu: snoop-control-unit@ffffc000 { |
| 738 | compatible = "arm,cortex-a9-scu"; | |
| 739 | reg = <0xffffc000 0x100>; | |
| 740 | }; | |
| 741 | ||
| 475dc86d DN |
742 | sysmgr: sysmgr@ffd06000 { |
| 743 | compatible = "altr,sys-mgr", "syscon"; | |
| 744 | reg = <0xffd06000 0x300>; | |
| 08d6638f | 745 | cpu1-start-addr = <0xffd06230>; |
| 475dc86d DN |
746 | }; |
| 747 | ||
| 748 | /* Local timer */ | |
| 749 | timer@ffffc600 { | |
| 750 | compatible = "arm,cortex-a9-twd-timer"; | |
| 751 | reg = <0xffffc600 0x100>; | |
| 752 | interrupts = <1 13 0xf04>; | |
| da29d824 | 753 | clocks = <&mpu_periph_clk>; |
| 475dc86d DN |
754 | }; |
| 755 | ||
| 756 | timer0: timer0@ffc02700 { | |
| 757 | compatible = "snps,dw-apb-timer"; | |
| 758 | interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; | |
| 759 | reg = <0xffc02700 0x100>; | |
| da29d824 DN |
760 | clocks = <&l4_sp_clk>; |
| 761 | clock-names = "timer"; | |
| 475dc86d DN |
762 | }; |
| 763 | ||
| 764 | timer1: timer1@ffc02800 { | |
| 765 | compatible = "snps,dw-apb-timer"; | |
| 766 | interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; | |
| 767 | reg = <0xffc02800 0x100>; | |
| da29d824 DN |
768 | clocks = <&l4_sp_clk>; |
| 769 | clock-names = "timer"; | |
| 475dc86d DN |
770 | }; |
| 771 | ||
| 772 | timer2: timer2@ffd00000 { | |
| 773 | compatible = "snps,dw-apb-timer"; | |
| 774 | interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; | |
| 775 | reg = <0xffd00000 0x100>; | |
| da29d824 DN |
776 | clocks = <&l4_sys_free_clk>; |
| 777 | clock-names = "timer"; | |
| 475dc86d DN |
778 | }; |
| 779 | ||
| 780 | timer3: timer3@ffd00100 { | |
| 781 | compatible = "snps,dw-apb-timer"; | |
| 782 | interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; | |
| 783 | reg = <0xffd01000 0x100>; | |
| da29d824 DN |
784 | clocks = <&l4_sys_free_clk>; |
| 785 | clock-names = "timer"; | |
| 475dc86d DN |
786 | }; |
| 787 | ||
| 788 | uart0: serial0@ffc02000 { | |
| 789 | compatible = "snps,dw-apb-uart"; | |
| 790 | reg = <0xffc02000 0x100>; | |
| 791 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; | |
| 792 | reg-shift = <2>; | |
| 793 | reg-io-width = <4>; | |
| e7604ae2 | 794 | clocks = <&l4_sp_clk>; |
| 1dfb7d2f | 795 | status = "disabled"; |
| 475dc86d DN |
796 | }; |
| 797 | ||
| 798 | uart1: serial1@ffc02100 { | |
| 799 | compatible = "snps,dw-apb-uart"; | |
| 800 | reg = <0xffc02100 0x100>; | |
| 801 | interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; | |
| 802 | reg-shift = <2>; | |
| 803 | reg-io-width = <4>; | |
| da29d824 | 804 | clocks = <&l4_sp_clk>; |
| 1dfb7d2f | 805 | status = "disabled"; |
| 475dc86d DN |
806 | }; |
| 807 | ||
| 0c9ff615 | 808 | usbphy0: usbphy { |
| 475dc86d DN |
809 | #phy-cells = <0>; |
| 810 | compatible = "usb-nop-xceiv"; | |
| 811 | status = "okay"; | |
| 812 | }; | |
| 813 | ||
| 814 | usb0: usb@ffb00000 { | |
| 815 | compatible = "snps,dwc2"; | |
| 816 | reg = <0xffb00000 0xffff>; | |
| 817 | interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; | |
| da29d824 DN |
818 | clocks = <&usb_clk>; |
| 819 | clock-names = "otg"; | |
| 249ff32e DN |
820 | resets = <&rst USB0_RESET>; |
| 821 | reset-names = "dwc2"; | |
| 475dc86d DN |
822 | phys = <&usbphy0>; |
| 823 | phy-names = "usb2-phy"; | |
| 824 | status = "disabled"; | |
| 825 | }; | |
| 826 | ||
| 827 | usb1: usb@ffb40000 { | |
| 828 | compatible = "snps,dwc2"; | |
| 829 | reg = <0xffb40000 0xffff>; | |
| 830 | interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; | |
| e7604ae2 DN |
831 | clocks = <&usb_clk>; |
| 832 | clock-names = "otg"; | |
| 249ff32e DN |
833 | resets = <&rst USB1_RESET>; |
| 834 | reset-names = "dwc2"; | |
| 475dc86d DN |
835 | phys = <&usbphy0>; |
| 836 | phy-names = "usb2-phy"; | |
| 837 | status = "disabled"; | |
| 838 | }; | |
| 839 | ||
| 840 | watchdog0: watchdog@ffd00200 { | |
| 841 | compatible = "snps,dw-wdt"; | |
| 842 | reg = <0xffd00200 0x100>; | |
| 843 | interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; | |
| da29d824 | 844 | clocks = <&l4_sys_free_clk>; |
| 475dc86d DN |
845 | status = "disabled"; |
| 846 | }; | |
| 847 | ||
| 848 | watchdog1: watchdog@ffd00300 { | |
| 849 | compatible = "snps,dw-wdt"; | |
| 850 | reg = <0xffd00300 0x100>; | |
| 851 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; | |
| da29d824 | 852 | clocks = <&l4_sys_free_clk>; |
| 475dc86d DN |
853 | status = "disabled"; |
| 854 | }; | |
| 855 | }; | |
| 856 | }; |