[linux-2.6-block.git] / arch / arm / boot / dts / rk322x.dtsi

/*
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@f00 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf00>;
			resets = <&cru SRST_CORE0>;
			operating-points = <
				/* KHz    uV */
				 816000 1000000
			>;
			#cooling-cells = <2>; /* min followed by max */
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
		};

		cpu1: cpu@f01 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf01>;
			resets = <&cru SRST_CORE1>;
		};

		cpu2: cpu@f02 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf02>;
			resets = <&cru SRST_CORE2>;
		};

		cpu3: cpu@f03 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0xf03>;
			resets = <&cru SRST_CORE3>;
		};
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		pdma: pdma@110f0000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x110f0000 0x4000>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			clocks = <&cru ACLK_DMAC>;
			clock-names = "apb_pclk";
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	};

	timer {
		compatible = "arm,armv7-timer";
		arm,cpu-registers-not-fw-configured;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clock-frequency = <24000000>;
	};

	xin24m: oscillator {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	i2s1: i2s1@100b0000 {
		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
		reg = <0x100b0000 0x4000>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
		dmas = <&pdma 14>, <&pdma 15>;
		dma-names = "tx", "rx";
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1_bus>;
		status = "disabled";
	};

	i2s0: i2s0@100c0000 {
		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
		reg = <0x100c0000 0x4000>;
		interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
		dmas = <&pdma 11>, <&pdma 12>;
		dma-names = "tx", "rx";
		status = "disabled";
	};

	i2s2: i2s2@100e0000 {
		compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
		reg = <0x100e0000 0x4000>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2s_clk", "i2s_hclk";
		clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
		dmas = <&pdma 0>, <&pdma 1>;
		dma-names = "tx", "rx";
		status = "disabled";
	};

	grf: syscon@11000000 {
		compatible = "syscon";
		reg = <0x11000000 0x1000>;
	};

	uart0: serial@11010000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x11010000 0x100>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	uart1: serial@11020000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x11020000 0x100>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart1_xfer>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	uart2: serial@11030000 {
		compatible = "snps,dw-apb-uart";
		reg = <0x11030000 0x100>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <24000000>;
		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
		clock-names = "baudclk", "apb_pclk";
		pinctrl-names = "default";
		pinctrl-0 = <&uart2_xfer>;
		reg-shift = <2>;
		reg-io-width = <4>;
		status = "disabled";
	};

	i2c0: i2c@11050000 {
		compatible = "rockchip,rk3228-i2c";
		reg = <0x11050000 0x1000>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c0_xfer>;
		status = "disabled";
	};

	i2c1: i2c@11060000 {
		compatible = "rockchip,rk3228-i2c";
		reg = <0x11060000 0x1000>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C1>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c1_xfer>;
		status = "disabled";
	};

	i2c2: i2c@11070000 {
		compatible = "rockchip,rk3228-i2c";
		reg = <0x11070000 0x1000>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C2>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c2_xfer>;
		status = "disabled";
	};

	i2c3: i2c@11080000 {
		compatible = "rockchip,rk3228-i2c";
		reg = <0x11080000 0x1000>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "i2c";
		clocks = <&cru PCLK_I2C3>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2c3_xfer>;
		status = "disabled";
	};

	pwm0: pwm@110b0000 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x110b0000 0x10>;
		#pwm-cells = <3>;
		clocks = <&cru PCLK_PWM>;
		clock-names = "pwm";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm0_pin>;
		status = "disabled";
	};

	pwm1: pwm@110b0010 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x110b0010 0x10>;
		#pwm-cells = <3>;
		clocks = <&cru PCLK_PWM>;
		clock-names = "pwm";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm1_pin>;
		status = "disabled";
	};

	pwm2: pwm@110b0020 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x110b0020 0x10>;
		#pwm-cells = <3>;
		clocks = <&cru PCLK_PWM>;
		clock-names = "pwm";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm2_pin>;
		status = "disabled";
	};

	pwm3: pwm@110b0030 {
		compatible = "rockchip,rk3288-pwm";
		reg = <0x110b0030 0x10>;
		#pwm-cells = <2>;
		clocks = <&cru PCLK_PWM>;
		clock-names = "pwm";
		pinctrl-names = "default";
		pinctrl-0 = <&pwm3_pin>;
		status = "disabled";
	};

	timer: timer@110c0000 {
		compatible = "rockchip,rk3288-timer";
		reg = <0x110c0000 0x20>;
		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&xin24m>, <&cru PCLK_TIMER>;
		clock-names = "timer", "pclk";
	};

	cru: clock-controller@110e0000 {
		compatible = "rockchip,rk3228-cru";
		reg = <0x110e0000 0x1000>;
		rockchip,grf = <&grf>;
		#clock-cells = <1>;
		#reset-cells = <1>;
		assigned-clocks = <&cru PLL_GPLL>;
		assigned-clock-rates = <594000000>;
	};

	thermal-zones {
		cpu_thermal: cpu-thermal {
			polling-delay-passive = <100>; /* milliseconds */
			polling-delay = <5000>; /* milliseconds */

			thermal-sensors = <&tsadc 0>;

			trips {
				cpu_alert0: cpu_alert0 {
					temperature = <70000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "passive";
				};
				cpu_alert1: cpu_alert1 {
					temperature = <75000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "passive";
				};
				cpu_crit: cpu_crit {
					temperature = <90000>; /* millicelsius */
					hysteresis = <2000>; /* millicelsius */
					type = "critical";
				};
			};

			cooling-maps {
				map0 {
					trip = <&cpu_alert0>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT 6>;
				};
				map1 {
					trip = <&cpu_alert1>;
					cooling-device =
						<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	tsadc: tsadc@11150000 {
		compatible = "rockchip,rk3228-tsadc";
		reg = <0x11150000 0x100>;
		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
		clock-names = "tsadc", "apb_pclk";
		resets = <&cru SRST_TSADC>;
		reset-names = "tsadc-apb";
		pinctrl-names = "init", "default", "sleep";
		pinctrl-0 = <&otp_gpio>;
		pinctrl-1 = <&otp_out>;
		pinctrl-2 = <&otp_gpio>;
		#thermal-sensor-cells = <0>;
		rockchip,hw-tshut-temp = <95000>;
		status = "disabled";
	};

	emmc: dwmmc@30020000 {
		compatible = "rockchip,rk3288-dw-mshc";
		reg = <0x30020000 0x4000>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <37500000>;
		max-frequency = <37500000>;
		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
		clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
		bus-width = <8>;
		default-sample-phase = <158>;
		num-slots = <1>;
		fifo-depth = <0x100>;
		pinctrl-names = "default";
		pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
		status = "disabled";
	};

	gmac: ethernet@30200000 {
		compatible = "rockchip,rk3228-gmac";
		reg = <0x30200000 0x10000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "macirq";
		clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
			<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
			<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
			<&cru PCLK_GMAC>;
		clock-names = "stmmaceth", "mac_clk_rx",
			"mac_clk_tx", "clk_mac_ref",
			"clk_mac_refout", "aclk_mac",
			"pclk_mac";
		resets = <&cru SRST_GMAC>;
		reset-names = "stmmaceth";
		rockchip,grf = <&grf>;
		status = "disabled";
	};

	gic: interrupt-controller@32010000 {
		compatible = "arm,gic-400";
		interrupt-controller;
		#interrupt-cells = <3>;
		#address-cells = <0>;

		reg = <0x32011000 0x1000>,
		      <0x32012000 0x2000>,
		      <0x32014000 0x2000>,
		      <0x32016000 0x2000>;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3228-pinctrl";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@11110000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x11110000 0x100>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@11120000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x11120000 0x100>;
			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@11130000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x11130000 0x100>;
			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@11140000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x11140000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_up: pcfg-pull-up {
			bias-pull-up;
		};

		pcfg_pull_down: pcfg-pull-down {
			bias-pull-down;
		};

		pcfg_pull_none: pcfg-pull-none {
			bias-disable;
		};

		pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
			drive-strength = <12>;
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
			};

			emmc_bus8: emmc-bus8 {
				rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
						<1 25 RK_FUNC_2 &pcfg_pull_none>,
						<1 26 RK_FUNC_2 &pcfg_pull_none>,
						<1 27 RK_FUNC_2 &pcfg_pull_none>,
						<1 28 RK_FUNC_2 &pcfg_pull_none>,
						<1 29 RK_FUNC_2 &pcfg_pull_none>,
						<1 30 RK_FUNC_2 &pcfg_pull_none>,
						<1 31 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		gmac {
			rgmii_pins: rgmii-pins {
				rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
						<2 12 RK_FUNC_1 &pcfg_pull_none>,
						<2 25 RK_FUNC_1 &pcfg_pull_none>,
						<2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 17 RK_FUNC_1 &pcfg_pull_none>,
						<2 16 RK_FUNC_1 &pcfg_pull_none>,
						<2 21 RK_FUNC_2 &pcfg_pull_none>,
						<2 20 RK_FUNC_2 &pcfg_pull_none>,
						<2 11 RK_FUNC_1 &pcfg_pull_none>,
						<2 8 RK_FUNC_1 &pcfg_pull_none>;
			};

			rmii_pins: rmii-pins {
				rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
						<2 12 RK_FUNC_1 &pcfg_pull_none>,
						<2 25 RK_FUNC_1 &pcfg_pull_none>,
						<2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
						<2 17 RK_FUNC_1 &pcfg_pull_none>,
						<2 16 RK_FUNC_1 &pcfg_pull_none>,
						<2 8 RK_FUNC_1 &pcfg_pull_none>,
						<2 15 RK_FUNC_1 &pcfg_pull_none>;
			};

			phy_pins: phy-pins {
				rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
						<2 8 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
						<0 1 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
						<0 3 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
						<2 21 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
						<0 7 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2s1 {
			i2s1_bus: i2s1-bus {
				rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
						<0 9 RK_FUNC_1 &pcfg_pull_none>,
						<0 11 RK_FUNC_1 &pcfg_pull_none>,
						<0 12 RK_FUNC_1 &pcfg_pull_none>,
						<0 13 RK_FUNC_1 &pcfg_pull_none>,
						<0 14 RK_FUNC_1 &pcfg_pull_none>,
						<1 2 RK_FUNC_1 &pcfg_pull_none>,
						<1 4 RK_FUNC_1 &pcfg_pull_none>,
						<1 5 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_pin: pwm0-pin {
				rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_pin: pwm1-pin {
				rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_pin: pwm2-pin {
				rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_pin: pwm3-pin {
				rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		tsadc {
			otp_gpio: otp-gpio {
				rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
			};

			otp_out: otp-out {
				rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
						<2 27 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
						<1 10 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
						<1 19 RK_FUNC_2 &pcfg_pull_none>;
			};

			uart2_cts: uart2-cts {
				rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
			};

			uart2_rts: uart2-rts {
				rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
			};
		};
	};
};
Commit	Line	Data
9848ebeb JC	1	/*
	2	* This file is dual-licensed: you can use it either under the terms
	3	* of the GPL or the X11 license, at your option. Note that this dual
	4	* licensing only applies to this file, and not this project as a
	5	* whole.
	6	*
	7	* a) This file is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of the
	10	* License, or (at your option) any later version.
	11	*
	12	* This file is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* Or, alternatively,
	18	*
	19	* b) Permission is hereby granted, free of charge, to any person
	20	* obtaining a copy of this software and associated documentation
	21	* files (the "Software"), to deal in the Software without
	22	* restriction, including without limitation the rights to use,
	23	* copy, modify, merge, publish, distribute, sublicense, and/or
	24	* sell copies of the Software, and to permit persons to whom the
	25	* Software is furnished to do so, subject to the following
	26	* conditions:
	27	*
	28	* The above copyright notice and this permission notice shall be
	29	* included in all copies or substantial portions of the Software.
	30	*
	31	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	32	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	33	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	34	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	35	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	36	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	37	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	38	* OTHER DEALINGS IN THE SOFTWARE.
	39	*/
	40
	41	#include <dt-bindings/gpio/gpio.h>
	42	#include <dt-bindings/interrupt-controller/irq.h>
	43	#include <dt-bindings/interrupt-controller/arm-gic.h>
	44	#include <dt-bindings/pinctrl/rockchip.h>
	45	#include <dt-bindings/clock/rk3228-cru.h>
7796031e	46	#include <dt-bindings/thermal/thermal.h>
9848ebeb JC	47
9848ebeb JC	48	/ {
0193273d JMC	49	#address-cells = <1>;
	50	#size-cells = <1>;
	51
9848ebeb JC	52	interrupt-parent = <&gic>;
	53
	54	aliases {
	55	serial0 = &uart0;
	56	serial1 = &uart1;
	57	serial2 = &uart2;
	58	};
	59
	60	cpus {
	61	#address-cells = <1>;
	62	#size-cells = <0>;
	63
	64	cpu0: cpu@f00 {
	65	device_type = "cpu";
	66	compatible = "arm,cortex-a7";
	67	reg = <0xf00>;
	68	resets = <&cru SRST_CORE0>;
	69	operating-points = <
	70	/* KHz uV */
	71	816000 1000000
	72	>;
7796031e	73	#cooling-cells = <2>; /* min followed by max */
9848ebeb JC	74	clock-latency = <40000>;
	75	clocks = <&cru ARMCLK>;
	76	};
	77
	78	cpu1: cpu@f01 {
	79	device_type = "cpu";
	80	compatible = "arm,cortex-a7";
	81	reg = <0xf01>;
	82	resets = <&cru SRST_CORE1>;
	83	};
	84
	85	cpu2: cpu@f02 {
	86	device_type = "cpu";
	87	compatible = "arm,cortex-a7";
	88	reg = <0xf02>;
	89	resets = <&cru SRST_CORE2>;
	90	};
	91
	92	cpu3: cpu@f03 {
	93	device_type = "cpu";
	94	compatible = "arm,cortex-a7";
	95	reg = <0xf03>;
	96	resets = <&cru SRST_CORE3>;
	97	};
	98	};
	99
	100	amba {
2ef7d5f3	101	compatible = "simple-bus";
9848ebeb JC	102	#address-cells = <1>;
	103	#size-cells = <1>;
	104	ranges;
	105
	106	pdma: pdma@110f0000 {
	107	compatible = "arm,pl330", "arm,primecell";
	108	reg = <0x110f0000 0x4000>;
	109	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	110	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	111	#dma-cells = <1>;
	112	clocks = <&cru ACLK_DMAC>;
	113	clock-names = "apb_pclk";
	114	};
	115	};
	116
	117	arm-pmu {
	118	compatible = "arm,cortex-a7-pmu";
	119	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
	120	<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
	121	<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
	122	<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	123	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
	124	};
	125
	126	timer {
	127	compatible = "arm,armv7-timer";
	128	arm,cpu-registers-not-fw-configured;
	129	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	130	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	131	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	132	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	133	clock-frequency = <24000000>;
	134	};
	135
	136	xin24m: oscillator {
	137	compatible = "fixed-clock";
	138	clock-frequency = <24000000>;
	139	clock-output-names = "xin24m";
	140	#clock-cells = <0>;
	141	};
	142
ccada248 XZ	143	i2s1: i2s1@100b0000 {
	144	compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
	145	reg = <0x100b0000 0x4000>;
	146	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	147	#address-cells = <1>;
	148	#size-cells = <0>;
	149	clock-names = "i2s_clk", "i2s_hclk";
	150	clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
	151	dmas = <&pdma 14>, <&pdma 15>;
	152	dma-names = "tx", "rx";
	153	pinctrl-names = "default";
	154	pinctrl-0 = <&i2s1_bus>;
	155	status = "disabled";
	156	};
	157
	158	i2s0: i2s0@100c0000 {
	159	compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
	160	reg = <0x100c0000 0x4000>;
	161	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	162	#address-cells = <1>;
	163	#size-cells = <0>;
	164	clock-names = "i2s_clk", "i2s_hclk";
	165	clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
	166	dmas = <&pdma 11>, <&pdma 12>;
	167	dma-names = "tx", "rx";
	168	status = "disabled";
	169	};
	170
	171	i2s2: i2s2@100e0000 {
	172	compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
	173	reg = <0x100e0000 0x4000>;
	174	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	175	#address-cells = <1>;
	176	#size-cells = <0>;
	177	clock-names = "i2s_clk", "i2s_hclk";
	178	clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
	179	dmas = <&pdma 0>, <&pdma 1>;
	180	dma-names = "tx", "rx";
	181	status = "disabled";
	182	};
	183
9848ebeb JC	184	grf: syscon@11000000 {
	185	compatible = "syscon";
	186	reg = <0x11000000 0x1000>;
	187	};
	188
	189	uart0: serial@11010000 {
	190	compatible = "snps,dw-apb-uart";
	191	reg = <0x11010000 0x100>;
	192	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	193	clock-frequency = <24000000>;
	194	clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
	195	clock-names = "baudclk", "apb_pclk";
	196	pinctrl-names = "default";
	197	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
	198	reg-shift = <2>;
	199	reg-io-width = <4>;
	200	status = "disabled";
	201	};
	202
	203	uart1: serial@11020000 {
	204	compatible = "snps,dw-apb-uart";
	205	reg = <0x11020000 0x100>;
	206	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	207	clock-frequency = <24000000>;
	208	clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
	209	clock-names = "baudclk", "apb_pclk";
	210	pinctrl-names = "default";
	211	pinctrl-0 = <&uart1_xfer>;
	212	reg-shift = <2>;
	213	reg-io-width = <4>;
	214	status = "disabled";
	215	};
	216
	217	uart2: serial@11030000 {
	218	compatible = "snps,dw-apb-uart";
	219	reg = <0x11030000 0x100>;
	220	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	221	clock-frequency = <24000000>;
	222	clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
	223	clock-names = "baudclk", "apb_pclk";
	224	pinctrl-names = "default";
	225	pinctrl-0 = <&uart2_xfer>;
	226	reg-shift = <2>;
	227	reg-io-width = <4>;
	228	status = "disabled";
	229	};
	230
d549df4b YY	231	i2c0: i2c@11050000 {
	232	compatible = "rockchip,rk3228-i2c";
	233	reg = <0x11050000 0x1000>;
	234	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	235	#address-cells = <1>;
	236	#size-cells = <0>;
	237	clock-names = "i2c";
	238	clocks = <&cru PCLK_I2C0>;
	239	pinctrl-names = "default";
	240	pinctrl-0 = <&i2c0_xfer>;
	241	status = "disabled";
	242	};
	243
	244	i2c1: i2c@11060000 {
	245	compatible = "rockchip,rk3228-i2c";
	246	reg = <0x11060000 0x1000>;
	247	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	248	#address-cells = <1>;
	249	#size-cells = <0>;
	250	clock-names = "i2c";
	251	clocks = <&cru PCLK_I2C1>;
	252	pinctrl-names = "default";
	253	pinctrl-0 = <&i2c1_xfer>;
	254	status = "disabled";
	255	};
	256
	257	i2c2: i2c@11070000 {
	258	compatible = "rockchip,rk3228-i2c";
	259	reg = <0x11070000 0x1000>;
	260	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	261	#address-cells = <1>;
	262	#size-cells = <0>;
	263	clock-names = "i2c";
	264	clocks = <&cru PCLK_I2C2>;
	265	pinctrl-names = "default";
	266	pinctrl-0 = <&i2c2_xfer>;
	267	status = "disabled";
	268	};
	269
	270	i2c3: i2c@11080000 {
	271	compatible = "rockchip,rk3228-i2c";
	272	reg = <0x11080000 0x1000>;
	273	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
	274	#address-cells = <1>;
	275	#size-cells = <0>;
	276	clock-names = "i2c";
	277	clocks = <&cru PCLK_I2C3>;
	278	pinctrl-names = "default";
	279	pinctrl-0 = <&i2c3_xfer>;
	280	status = "disabled";
	281	};
	282
9848ebeb JC	283	pwm0: pwm@110b0000 {
	284	compatible = "rockchip,rk3288-pwm";
	285	reg = <0x110b0000 0x10>;
	286	#pwm-cells = <3>;
	287	clocks = <&cru PCLK_PWM>;
	288	clock-names = "pwm";
	289	pinctrl-names = "default";
	290	pinctrl-0 = <&pwm0_pin>;
	291	status = "disabled";
	292	};
	293
	294	pwm1: pwm@110b0010 {
	295	compatible = "rockchip,rk3288-pwm";
	296	reg = <0x110b0010 0x10>;
	297	#pwm-cells = <3>;
	298	clocks = <&cru PCLK_PWM>;
	299	clock-names = "pwm";
	300	pinctrl-names = "default";
	301	pinctrl-0 = <&pwm1_pin>;
	302	status = "disabled";
	303	};
	304
	305	pwm2: pwm@110b0020 {
	306	compatible = "rockchip,rk3288-pwm";
	307	reg = <0x110b0020 0x10>;
	308	#pwm-cells = <3>;
	309	clocks = <&cru PCLK_PWM>;
	310	clock-names = "pwm";
	311	pinctrl-names = "default";
	312	pinctrl-0 = <&pwm2_pin>;
	313	status = "disabled";
	314	};
	315
	316	pwm3: pwm@110b0030 {
	317	compatible = "rockchip,rk3288-pwm";
	318	reg = <0x110b0030 0x10>;
	319	#pwm-cells = <2>;
	320	clocks = <&cru PCLK_PWM>;
	321	clock-names = "pwm";
	322	pinctrl-names = "default";
	323	pinctrl-0 = <&pwm3_pin>;
	324	status = "disabled";
	325	};
	326
	327	timer: timer@110c0000 {
	328	compatible = "rockchip,rk3288-timer";
	329	reg = <0x110c0000 0x20>;
	330	interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
	331	clocks = <&xin24m>, <&cru PCLK_TIMER>;
	332	clock-names = "timer", "pclk";
	333	};
	334
	335	cru: clock-controller@110e0000 {
	336	compatible = "rockchip,rk3228-cru";
	337	reg = <0x110e0000 0x1000>;
	338	rockchip,grf = <&grf>;
	339	#clock-cells = <1>;
	340	#reset-cells = <1>;
	341	assigned-clocks = <&cru PLL_GPLL>;
	342	assigned-clock-rates = <594000000>;
	343	};
	344
7796031e CW	345	thermal-zones {
	346	cpu_thermal: cpu-thermal {
	347	polling-delay-passive = <100>; /* milliseconds */
	348	polling-delay = <5000>; /* milliseconds */
	349
	350	thermal-sensors = <&tsadc 0>;
	351
	352	trips {
	353	cpu_alert0: cpu_alert0 {
	354	temperature = <70000>; /* millicelsius */
	355	hysteresis = <2000>; /* millicelsius */
	356	type = "passive";
	357	};
	358	cpu_alert1: cpu_alert1 {
	359	temperature = <75000>; /* millicelsius */
	360	hysteresis = <2000>; /* millicelsius */
	361	type = "passive";
	362	};
	363	cpu_crit: cpu_crit {
	364	temperature = <90000>; /* millicelsius */
	365	hysteresis = <2000>; /* millicelsius */
	366	type = "critical";
	367	};
	368	};
	369
	370	cooling-maps {
	371	map0 {
	372	trip = <&cpu_alert0>;
	373	cooling-device =
	374	<&cpu0 THERMAL_NO_LIMIT 6>;
	375	};
	376	map1 {
	377	trip = <&cpu_alert1>;
	378	cooling-device =
	379	<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	380	};
	381	};
	382	};
	383	};
	384
	385	tsadc: tsadc@11150000 {
	386	compatible = "rockchip,rk3228-tsadc";
	387	reg = <0x11150000 0x100>;
	388	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	389	clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
	390	clock-names = "tsadc", "apb_pclk";
	391	resets = <&cru SRST_TSADC>;
	392	reset-names = "tsadc-apb";
	393	pinctrl-names = "init", "default", "sleep";
	394	pinctrl-0 = <&otp_gpio>;
	395	pinctrl-1 = <&otp_out>;
	396	pinctrl-2 = <&otp_gpio>;
	397	#thermal-sensor-cells = <0>;
	398	rockchip,hw-tshut-temp = <95000>;
	399	status = "disabled";
	400	};
	401
9848ebeb JC	402	emmc: dwmmc@30020000 {
	403	compatible = "rockchip,rk3288-dw-mshc";
	404	reg = <0x30020000 0x4000>;
	405	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
	406	clock-frequency = <37500000>;
6a8883d6	407	max-frequency = <37500000>;
9848ebeb JC	408	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
	409	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
	410	clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
	411	bus-width = <8>;
	412	default-sample-phase = <158>;
	413	num-slots = <1>;
	414	fifo-depth = <0x100>;
	415	pinctrl-names = "default";
	416	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
	417	status = "disabled";
	418	};
	419
5d3d7c72 XZ	420	gmac: ethernet@30200000 {
	421	compatible = "rockchip,rk3228-gmac";
	422	reg = <0x30200000 0x10000>;
	423	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	424	interrupt-names = "macirq";
	425	clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
	426	<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
	427	<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
	428	<&cru PCLK_GMAC>;
	429	clock-names = "stmmaceth", "mac_clk_rx",
	430	"mac_clk_tx", "clk_mac_ref",
	431	"clk_mac_refout", "aclk_mac",
	432	"pclk_mac";
	433	resets = <&cru SRST_GMAC>;
	434	reset-names = "stmmaceth";
	435	rockchip,grf = <&grf>;
	436	status = "disabled";
	437	};
	438
9848ebeb JC	439	gic: interrupt-controller@32010000 {
	440	compatible = "arm,gic-400";
	441	interrupt-controller;
	442	#interrupt-cells = <3>;
	443	#address-cells = <0>;
	444
	445	reg = <0x32011000 0x1000>,
387720c9	446	<0x32012000 0x2000>,
9848ebeb JC	447	<0x32014000 0x2000>,
	448	<0x32016000 0x2000>;
	449	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	450	};
	451
	452	pinctrl: pinctrl {
	453	compatible = "rockchip,rk3228-pinctrl";
	454	rockchip,grf = <&grf>;
	455	#address-cells = <1>;
	456	#size-cells = <1>;
	457	ranges;
	458
	459	gpio0: gpio0@11110000 {
	460	compatible = "rockchip,gpio-bank";
	461	reg = <0x11110000 0x100>;
	462	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
	463	clocks = <&cru PCLK_GPIO0>;
	464
	465	gpio-controller;
	466	#gpio-cells = <2>;
	467
	468	interrupt-controller;
	469	#interrupt-cells = <2>;
	470	};
	471
	472	gpio1: gpio1@11120000 {
	473	compatible = "rockchip,gpio-bank";
	474	reg = <0x11120000 0x100>;
	475	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	476	clocks = <&cru PCLK_GPIO1>;
	477
	478	gpio-controller;
	479	#gpio-cells = <2>;
	480
	481	interrupt-controller;
	482	#interrupt-cells = <2>;
	483	};
	484
	485	gpio2: gpio2@11130000 {
	486	compatible = "rockchip,gpio-bank";
	487	reg = <0x11130000 0x100>;
	488	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	489	clocks = <&cru PCLK_GPIO2>;
	490
	491	gpio-controller;
	492	#gpio-cells = <2>;
	493
	494	interrupt-controller;
	495	#interrupt-cells = <2>;
	496	};
	497
	498	gpio3: gpio3@11140000 {
	499	compatible = "rockchip,gpio-bank";
	500	reg = <0x11140000 0x100>;
	501	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	502	clocks = <&cru PCLK_GPIO3>;
	503
	504	gpio-controller;
	505	#gpio-cells = <2>;
	506
	507	interrupt-controller;
	508	#interrupt-cells = <2>;
	509	};
	510
511	pcfg_pull_up: pcfg-pull-up {
512	bias-pull-up;
513	};
514
515	pcfg_pull_down: pcfg-pull-down {
516	bias-pull-down;
517	};
518
519	pcfg_pull_none: pcfg-pull-none {
520	bias-disable;
521	};
522
5d3d7c72 XZ	523	pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
	524	drive-strength = <12>;
	525	};
	526
9848ebeb JC	527	emmc {
	528	emmc_clk: emmc-clk {
	529	rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
	530	};
	531
	532	emmc_cmd: emmc-cmd {
	533	rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
	534	};
	535
	536	emmc_bus8: emmc-bus8 {
	537	rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
	538	<1 25 RK_FUNC_2 &pcfg_pull_none>,
	539	<1 26 RK_FUNC_2 &pcfg_pull_none>,
	540	<1 27 RK_FUNC_2 &pcfg_pull_none>,
	541	<1 28 RK_FUNC_2 &pcfg_pull_none>,
	542	<1 29 RK_FUNC_2 &pcfg_pull_none>,
	543	<1 30 RK_FUNC_2 &pcfg_pull_none>,
	544	<1 31 RK_FUNC_2 &pcfg_pull_none>;
	545	};
	546	};
	547
5d3d7c72 XZ	548	gmac {
	549	rgmii_pins: rgmii-pins {
	550	rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
	551	<2 12 RK_FUNC_1 &pcfg_pull_none>,
	552	<2 25 RK_FUNC_1 &pcfg_pull_none>,
	553	<2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	554	<2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	555	<2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	556	<2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	557	<2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	558	<2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	559	<2 17 RK_FUNC_1 &pcfg_pull_none>,
	560	<2 16 RK_FUNC_1 &pcfg_pull_none>,
	561	<2 21 RK_FUNC_2 &pcfg_pull_none>,
	562	<2 20 RK_FUNC_2 &pcfg_pull_none>,
	563	<2 11 RK_FUNC_1 &pcfg_pull_none>,
	564	<2 8 RK_FUNC_1 &pcfg_pull_none>;
	565	};
	566
	567	rmii_pins: rmii-pins {
	568	rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
	569	<2 12 RK_FUNC_1 &pcfg_pull_none>,
	570	<2 25 RK_FUNC_1 &pcfg_pull_none>,
	571	<2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	572	<2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	573	<2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
	574	<2 17 RK_FUNC_1 &pcfg_pull_none>,
	575	<2 16 RK_FUNC_1 &pcfg_pull_none>,
	576	<2 8 RK_FUNC_1 &pcfg_pull_none>,
	577	<2 15 RK_FUNC_1 &pcfg_pull_none>;
	578	};
	579
	580	phy_pins: phy-pins {
	581	rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
	582	<2 8 RK_FUNC_2 &pcfg_pull_none>;
	583	};
	584	};
	585
d549df4b YY	586	i2c0 {
	587	i2c0_xfer: i2c0-xfer {
	588	rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
	589	<0 1 RK_FUNC_1 &pcfg_pull_none>;
	590	};
	591	};
	592
	593	i2c1 {
	594	i2c1_xfer: i2c1-xfer {
	595	rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
	596	<0 3 RK_FUNC_1 &pcfg_pull_none>;
	597	};
	598	};
	599
	600	i2c2 {
	601	i2c2_xfer: i2c2-xfer {
	602	rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
	603	<2 21 RK_FUNC_1 &pcfg_pull_none>;
	604	};
	605	};
	606
	607	i2c3 {
	608	i2c3_xfer: i2c3-xfer {
	609	rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
	610	<0 7 RK_FUNC_1 &pcfg_pull_none>;
	611	};
	612	};
	613
ccada248 XZ	614	i2s1 {
	615	i2s1_bus: i2s1-bus {
	616	rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
	617	<0 9 RK_FUNC_1 &pcfg_pull_none>,
	618	<0 11 RK_FUNC_1 &pcfg_pull_none>,
	619	<0 12 RK_FUNC_1 &pcfg_pull_none>,
	620	<0 13 RK_FUNC_1 &pcfg_pull_none>,
	621	<0 14 RK_FUNC_1 &pcfg_pull_none>,
	622	<1 2 RK_FUNC_1 &pcfg_pull_none>,
	623	<1 4 RK_FUNC_1 &pcfg_pull_none>,
	624	<1 5 RK_FUNC_1 &pcfg_pull_none>;
	625	};
	626	};
	627
9848ebeb JC	628	pwm0 {
	629	pwm0_pin: pwm0-pin {
	630	rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
	631	};
	632	};
	633
	634	pwm1 {
	635	pwm1_pin: pwm1-pin {
	636	rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
	637	};
	638	};
	639
	640	pwm2 {
	641	pwm2_pin: pwm2-pin {
	642	rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
	643	};
	644	};
	645
	646	pwm3 {
	647	pwm3_pin: pwm3-pin {
	648	rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
	649	};
	650	};
	651
7796031e CW	652	tsadc {
	653	otp_gpio: otp-gpio {
	654	rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
	655	};
	656
	657	otp_out: otp-out {
	658	rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
	659	};
	660	};
	661
9848ebeb JC	662	uart0 {
	663	uart0_xfer: uart0-xfer {
	664	rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
	665	<2 27 RK_FUNC_1 &pcfg_pull_none>;
	666	};
	667
	668	uart0_cts: uart0-cts {
	669	rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
	670	};
	671
	672	uart0_rts: uart0-rts {
	673	rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
	674	};
	675	};
	676
	677	uart1 {
	678	uart1_xfer: uart1-xfer {
	679	rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
	680	<1 10 RK_FUNC_1 &pcfg_pull_none>;
	681	};
	682
	683	uart1_cts: uart1-cts {
	684	rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
	685	};
	686
	687	uart1_rts: uart1-rts {
	688	rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
	689	};
	690	};
	691
	692	uart2 {
	693	uart2_xfer: uart2-xfer {
	694	rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
	695	<1 19 RK_FUNC_2 &pcfg_pull_none>;
	696	};
	697
	698	uart2_cts: uart2-cts {
	699	rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
	700	};
	701
	702	uart2_rts: uart2-rts {
	703	rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
	704	};
	705	};
	706	};
	707	};