[linux-2.6-block.git] / arch / arm / boot / dts / rk3066a.dtsi

/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3066a-cru.h>
#include "rk3xxx.dtsi"

/ {
	compatible = "rockchip,rk3066a";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "rockchip,rk3066-smp";

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
			operating-points = <
				/* kHz    uV */
				1008000 1075000
				 816000 1025000
				 600000 1025000
				 504000 1000000
				 312000  975000
			>;
			clock-latency = <40000>;
			clocks = <&cru ARMCLK>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
	};

	sram: sram@10080000 {
		compatible = "mmio-sram";
		reg = <0x10080000 0x10000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0x10080000 0x10000>;

		smp-sram@0 {
			compatible = "rockchip,rk3066-smp-sram";
			reg = <0x0 0x50>;
		};
	};

	i2s0: i2s@10118000 {
		compatible = "rockchip,rk3066-i2s";
		reg = <0x10118000 0x2000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s0_bus>;
		dmas = <&dmac1_s 4>, <&dmac1_s 5>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
		status = "disabled";
	};

	i2s1: i2s@1011a000 {
		compatible = "rockchip,rk3066-i2s";
		reg = <0x1011a000 0x2000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s1_bus>;
		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
		status = "disabled";
	};

	i2s2: i2s@1011c000 {
		compatible = "rockchip,rk3066-i2s";
		reg = <0x1011c000 0x2000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&i2s2_bus>;
		dmas = <&dmac1_s 9>, <&dmac1_s 10>;
		dma-names = "tx", "rx";
		clock-names = "i2s_hclk", "i2s_clk";
		clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
		status = "disabled";
	};

	cru: clock-controller@20000000 {
		compatible = "rockchip,rk3066a-cru";
		reg = <0x20000000 0x1000>;
		rockchip,grf = <&grf>;

		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	timer@2000e000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2000e000 0x100>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
		clock-names = "timer", "pclk";
	};

	timer@20038000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x20038000 0x100>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
		clock-names = "timer", "pclk";
	};

	timer@2003a000 {
		compatible = "snps,dw-apb-timer-osc";
		reg = <0x2003a000 0x100>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
		clock-names = "timer", "pclk";
	};

	usbphy: phy {
		compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		usbphy0: usb-phy0 {
			#phy-cells = <0>;
			reg = <0x17c>;
			clocks = <&cru SCLK_OTGPHY0>;
			clock-names = "phyclk";
		};

		usbphy1: usb-phy1 {
			#phy-cells = <0>;
			reg = <0x188>;
			clocks = <&cru SCLK_OTGPHY1>;
			clock-names = "phyclk";
		};
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3066a-pinctrl";
		rockchip,grf = <&grf>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		gpio0: gpio0@20034000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20034000 0x100>;
			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO0>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio1@2003c000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003c000 0x100>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO1>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio2@2003e000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2003e000 0x100>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO2>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio3@20080000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20080000 0x100>;
			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO3>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio4@20084000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x20084000 0x100>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO4>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio6@2000a000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x2000a000 0x100>;
			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cru PCLK_GPIO6>;

			gpio-controller;
			#gpio-cells = <2>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		pcfg_pull_default: pcfg_pull_default {
			bias-pull-pin-default;
		};

		pcfg_pull_none: pcfg_pull_none {
			bias-disable;
		};

		emac {
			emac_xfer: emac-xfer {
				rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
						<RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
						<RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
						<RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
						<RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
						<RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
						<RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
						<RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
			};

			emac_mdio: emac-mdio {
				rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
						<RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
			};
		};

		emmc {
			emmc_clk: emmc-clk {
				rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
			};

			emmc_cmd: emmc-cmd {
				rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
			};

			emmc_rst: emmc-rst {
				rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
			};

			/*
			 * The data pins are shared between nandc and emmc and
			 * not accessible through pinctrl. Also they should've
			 * been already set correctly by firmware, as
			 * flash/emmc is the boot-device.
			 */
		};

		i2c0 {
			i2c0_xfer: i2c0-xfer {
				rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c1 {
			i2c1_xfer: i2c1-xfer {
				rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c2 {
			i2c2_xfer: i2c2-xfer {
				rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		i2c3 {
			i2c3_xfer: i2c3-xfer {
				rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
						<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
			};
		};

		i2c4 {
			i2c4_xfer: i2c4-xfer {
				rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
						<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm0 {
			pwm0_out: pwm0-out {
				rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm1 {
			pwm1_out: pwm1-out {
				rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm2 {
			pwm2_out: pwm2-out {
				rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		pwm3 {
			pwm3_out: pwm3-out {
				rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
			};
		};

		spi0 {
			spi0_clk: spi0-clk {
				rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_cs0: spi0-cs0 {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_tx: spi0-tx {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_rx: spi0-rx {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi0_cs1: spi0-cs1 {
				rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		spi1 {
			spi1_clk: spi1-clk {
				rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_cs0: spi1-cs0 {
				rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_rx: spi1-rx {
				rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_tx: spi1-tx {
				rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
			};
			spi1_cs1: spi1-cs1 {
				rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
			};
		};

		uart0 {
			uart0_xfer: uart0-xfer {
				rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart0_cts: uart0-cts {
				rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart0_rts: uart0-rts {
				rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		uart1 {
			uart1_xfer: uart1-xfer {
				rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart1_cts: uart1-cts {
				rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart1_rts: uart1-rts {
				rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		uart2 {
			uart2_xfer: uart2-xfer {
				rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
			};
			/* no rts / cts for uart2 */
		};

		uart3 {
			uart3_xfer: uart3-xfer {
				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart3_cts: uart3-cts {
				rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
			};

			uart3_rts: uart3-rts {
				rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		sd0 {
			sd0_clk: sd0-clk {
				rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_cmd: sd0-cmd {
				rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_cd: sd0-cd {
				rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_wp: sd0-wp {
				rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_bus1: sd0-bus-width1 {
				rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd0_bus4: sd0-bus-width4 {
				rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		sd1 {
			sd1_clk: sd1-clk {
				rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_cmd: sd1-cmd {
				rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_cd: sd1-cd {
				rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_wp: sd1-wp {
				rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_bus1: sd1-bus-width1 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
			};

			sd1_bus4: sd1-bus-width4 {
				rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		i2s0 {
			i2s0_bus: i2s0-bus {
				rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		i2s1 {
			i2s1_bus: i2s1-bus {
				rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
			};
		};

		i2s2 {
			i2s2_bus: i2s2-bus {
				rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
						<RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
			};
		};
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_xfer>;
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c1_xfer>;
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c2_xfer>;
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c3_xfer>;
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c4_xfer>;
};

&mmc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
};

&mmc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm0_out>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm1_out>;
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm2_out>;
};

&pwm3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pwm3_out>;
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
};

&spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart0_xfer>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_xfer>;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_xfer>;
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart3_xfer>;
};

&wdt {
	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
};

&emac {
	compatible = "rockchip,rk3066-emac";
};
Commit	Line	Data
d63dc051 HS	1	/*
	2	* Copyright (c) 2013 MundoReader S.L.
	3	* Author: Heiko Stuebner <heiko@sntech.de>
	4	*
5218c6bc HS	5	* This file is dual-licensed: you can use it either under the terms
	6	* of the GPL or the X11 license, at your option. Note that this dual
	7	* licensing only applies to this file, and not this project as a
	8	* whole.
d63dc051	9	*
5218c6bc HS	10	* a) This file is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of the
	13	* License, or (at your option) any later version.
	14	*
	15	* This file is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* Or, alternatively,
	21	*
	22	* b) Permission is hereby granted, free of charge, to any person
	23	* obtaining a copy of this software and associated documentation
	24	* files (the "Software"), to deal in the Software without
	25	* restriction, including without limitation the rights to use,
	26	* copy, modify, merge, publish, distribute, sublicense, and/or
	27	* sell copies of the Software, and to permit persons to whom the
	28	* Software is furnished to do so, subject to the following
	29	* conditions:
	30	*
	31	* The above copyright notice and this permission notice shall be
	32	* included in all copies or substantial portions of the Software.
	33	*
	34	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	35	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	36	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	37	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	38	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	39	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	40	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	41	* OTHER DEALINGS IN THE SOFTWARE.
d63dc051 HS	42	*/
	43
	44	#include <dt-bindings/gpio/gpio.h>
d63dc051	45	#include <dt-bindings/pinctrl/rockchip.h>
b13d2a7b	46	#include <dt-bindings/clock/rk3066a-cru.h>
f75efdd7	47	#include "rk3xxx.dtsi"
d63dc051 HS	48
	49	/ {
	50	compatible = "rockchip,rk3066a";
d63dc051 HS	51
	52	cpus {
	53	#address-cells = <1>;
	54	#size-cells = <0>;
26ab69cb	55	enable-method = "rockchip,rk3066-smp";
d63dc051	56
be8a77c5	57	cpu0: cpu@0 {
d63dc051 HS	58	device_type = "cpu";
	59	compatible = "arm,cortex-a9";
	60	next-level-cache = <&L2>;
	61	reg = <0x0>;
be8a77c5 HS	62	operating-points = <
	63	/* kHz uV */
	64	1008000 1075000
	65	816000 1025000
	66	600000 1025000
	67	504000 1000000
	68	312000 975000
	69	>;
	70	clock-latency = <40000>;
	71	clocks = <&cru ARMCLK>;
d63dc051 HS	72	};
	73	cpu@1 {
	74	device_type = "cpu";
	75	compatible = "arm,cortex-a9";
	76	next-level-cache = <&L2>;
	77	reg = <0x1>;
	78	};
	79	};
	80
c3030d30 HS	81	sram: sram@10080000 {
	82	compatible = "mmio-sram";
	83	reg = <0x10080000 0x10000>;
	84	#address-cells = <1>;
	85	#size-cells = <1>;
	86	ranges = <0 0x10080000 0x10000>;
	87
	88	smp-sram@0 {
	89	compatible = "rockchip,rk3066-smp-sram";
	90	reg = <0x0 0x50>;
d63dc051	91	};
c3030d30 HS	92	};
c3030d30 HS	93
5fe62b83 JC	94	i2s0: i2s@10118000 {
	95	compatible = "rockchip,rk3066-i2s";
	96	reg = <0x10118000 0x2000>;
	97	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
	98	#address-cells = <1>;
	99	#size-cells = <0>;
	100	pinctrl-names = "default";
	101	pinctrl-0 = <&i2s0_bus>;
	102	dmas = <&dmac1_s 4>, <&dmac1_s 5>;
	103	dma-names = "tx", "rx";
	104	clock-names = "i2s_hclk", "i2s_clk";
	105	clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
	106	status = "disabled";
	107	};
	108
	109	i2s1: i2s@1011a000 {
	110	compatible = "rockchip,rk3066-i2s";
	111	reg = <0x1011a000 0x2000>;
	112	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
	113	#address-cells = <1>;
	114	#size-cells = <0>;
	115	pinctrl-names = "default";
	116	pinctrl-0 = <&i2s1_bus>;
	117	dmas = <&dmac1_s 6>, <&dmac1_s 7>;
	118	dma-names = "tx", "rx";
	119	clock-names = "i2s_hclk", "i2s_clk";
	120	clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>;
	121	status = "disabled";
	122	};
	123
	124	i2s2: i2s@1011c000 {
	125	compatible = "rockchip,rk3066-i2s";
	126	reg = <0x1011c000 0x2000>;
	127	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	128	#address-cells = <1>;
	129	#size-cells = <0>;
	130	pinctrl-names = "default";
	131	pinctrl-0 = <&i2s2_bus>;
	132	dmas = <&dmac1_s 9>, <&dmac1_s 10>;
	133	dma-names = "tx", "rx";
	134	clock-names = "i2s_hclk", "i2s_clk";
	135	clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>;
	136	status = "disabled";
	137	};
	138
c3030d30 HS	139	cru: clock-controller@20000000 {
	140	compatible = "rockchip,rk3066a-cru";
	141	reg = <0x20000000 0x1000>;
	142	rockchip,grf = <&grf>;
	143
	144	#clock-cells = <1>;
	145	#reset-cells = <1>;
	146	};
	147
ff84b90e HS	148	timer@2000e000 {
	149	compatible = "snps,dw-apb-timer-osc";
	150	reg = <0x2000e000 0x100>;
	151	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	152	clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
	153	clock-names = "timer", "pclk";
	154	};
	155
	156	timer@20038000 {
	157	compatible = "snps,dw-apb-timer-osc";
	158	reg = <0x20038000 0x100>;
	159	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
	160	clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
	161	clock-names = "timer", "pclk";
	162	};
	163
	164	timer@2003a000 {
	165	compatible = "snps,dw-apb-timer-osc";
	166	reg = <0x2003a000 0x100>;
	167	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	168	clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
	169	clock-names = "timer", "pclk";
	170	};
	171
760bb977 HS	172	usbphy: phy {
	173	compatible = "rockchip,rk3066a-usb-phy", "rockchip,rk3288-usb-phy";
	174	rockchip,grf = <&grf>;
	175	#address-cells = <1>;
	176	#size-cells = <0>;
	177	status = "disabled";
	178
	179	usbphy0: usb-phy0 {
	180	#phy-cells = <0>;
	181	reg = <0x17c>;
	182	clocks = <&cru SCLK_OTGPHY0>;
	183	clock-names = "phyclk";
	184	};
	185
	186	usbphy1: usb-phy1 {
	187	#phy-cells = <0>;
	188	reg = <0x188>;
	189	clocks = <&cru SCLK_OTGPHY1>;
	190	clock-names = "phyclk";
	191	};
	192	};
	193
6e4b3b4b	194	pinctrl: pinctrl {
c3030d30 HS	195	compatible = "rockchip,rk3066a-pinctrl";
	196	rockchip,grf = <&grf>;
	197	#address-cells = <1>;
	198	#size-cells = <1>;
	199	ranges;
d63dc051	200
c3030d30 HS	201	gpio0: gpio0@20034000 {
	202	compatible = "rockchip,gpio-bank";
	203	reg = <0x20034000 0x100>;
	204	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
	205	clocks = <&cru PCLK_GPIO0>;
	206
	207	gpio-controller;
	208	#gpio-cells = <2>;
	209
	210	interrupt-controller;
	211	#interrupt-cells = <2>;
d63dc051 HS	212	};
d63dc051 HS	213
c3030d30 HS	214	gpio1: gpio1@2003c000 {
	215	compatible = "rockchip,gpio-bank";
	216	reg = <0x2003c000 0x100>;
	217	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
	218	clocks = <&cru PCLK_GPIO1>;
de18e014	219
c3030d30 HS	220	gpio-controller;
	221	#gpio-cells = <2>;
	222
	223	interrupt-controller;
	224	#interrupt-cells = <2>;
de18e014 HS	225	};
de18e014 HS	226
c3030d30 HS	227	gpio2: gpio2@2003e000 {
	228	compatible = "rockchip,gpio-bank";
	229	reg = <0x2003e000 0x100>;
	230	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	231	clocks = <&cru PCLK_GPIO2>;
	232
	233	gpio-controller;
	234	#gpio-cells = <2>;
b13d2a7b	235
c3030d30 HS	236	interrupt-controller;
c3030d30 HS	237	#interrupt-cells = <2>;
b13d2a7b HS	238	};
b13d2a7b HS	239
c3030d30 HS	240	gpio3: gpio3@20080000 {
	241	compatible = "rockchip,gpio-bank";
	242	reg = <0x20080000 0x100>;
	243	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	244	clocks = <&cru PCLK_GPIO3>;
d63dc051	245
c3030d30 HS	246	gpio-controller;
c3030d30 HS	247	#gpio-cells = <2>;
d63dc051	248
c3030d30 HS	249	interrupt-controller;
	250	#interrupt-cells = <2>;
	251	};
d63dc051	252
c3030d30 HS	253	gpio4: gpio4@20084000 {
	254	compatible = "rockchip,gpio-bank";
	255	reg = <0x20084000 0x100>;
	256	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
	257	clocks = <&cru PCLK_GPIO4>;
d63dc051	258
c3030d30 HS	259	gpio-controller;
c3030d30 HS	260	#gpio-cells = <2>;
d63dc051	261
c3030d30 HS	262	interrupt-controller;
	263	#interrupt-cells = <2>;
	264	};
d63dc051	265
c3030d30 HS	266	gpio6: gpio6@2000a000 {
	267	compatible = "rockchip,gpio-bank";
	268	reg = <0x2000a000 0x100>;
	269	interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	270	clocks = <&cru PCLK_GPIO6>;
d63dc051	271
c3030d30 HS	272	gpio-controller;
c3030d30 HS	273	#gpio-cells = <2>;
d63dc051	274
c3030d30 HS	275	interrupt-controller;
	276	#interrupt-cells = <2>;
	277	};
d63dc051	278
c3030d30 HS	279	pcfg_pull_default: pcfg_pull_default {
	280	bias-pull-pin-default;
	281	};
d63dc051	282
c3030d30 HS	283	pcfg_pull_none: pcfg_pull_none {
	284	bias-disable;
	285	};
d63dc051	286
89f66876 RP	287	emac {
	288	emac_xfer: emac-xfer {
	289	rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */
	290	<RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */
	291	<RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */
	292	<RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */
	293	<RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */
	294	<RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */
	295	<RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */
	296	<RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */
	297	};
	298
	299	emac_mdio: emac-mdio {
	300	rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */
	301	<RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */
	302	};
	303	};
	304
4ff4ae12 HS	305	emmc {
	306	emmc_clk: emmc-clk {
	307	rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>;
	308	};
	309
	310	emmc_cmd: emmc-cmd {
	311	rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>;
	312	};
	313
	314	emmc_rst: emmc-rst {
	315	rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>;
	316	};
	317
	318	/*
	319	* The data pins are shared between nandc and emmc and
	320	* not accessible through pinctrl. Also they should've
	321	* been already set correctly by firmware, as
	322	* flash/emmc is the boot-device.
	323	*/
	324	};
	325
9cdffd8c HS	326	i2c0 {
	327	i2c0_xfer: i2c0-xfer {
	328	rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
	329	<RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
	330	};
	331	};
	332
	333	i2c1 {
	334	i2c1_xfer: i2c1-xfer {
	335	rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
	336	<RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
	337	};
	338	};
	339
	340	i2c2 {
	341	i2c2_xfer: i2c2-xfer {
	342	rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
	343	<RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
	344	};
	345	};
	346
	347	i2c3 {
	348	i2c3_xfer: i2c3-xfer {
	349	rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
	350	<RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
	351	};
	352	};
	353
	354	i2c4 {
	355	i2c4_xfer: i2c4-xfer {
	356	rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
	357	<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
	358	};
	359	};
	360
550c7f4e BG	361	pwm0 {
	362	pwm0_out: pwm0-out {
	363	rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
	364	};
	365	};
	366
	367	pwm1 {
	368	pwm1_out: pwm1-out {
	369	rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
	370	};
	371	};
	372
	373	pwm2 {
	374	pwm2_out: pwm2-out {
	375	rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
	376	};
	377	};
	378
	379	pwm3 {
	380	pwm3_out: pwm3-out {
	381	rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
	382	};
	383	};
	384
39c2bd78 HS	385	spi0 {
	386	spi0_clk: spi0-clk {
	387	rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>;
	388	};
	389	spi0_cs0: spi0-cs0 {
	390	rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>;
	391	};
	392	spi0_tx: spi0-tx {
	393	rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>;
	394	};
	395	spi0_rx: spi0-rx {
	396	rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>;
	397	};
	398	spi0_cs1: spi0-cs1 {
	399	rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>;
	400	};
	401	};
	402
	403	spi1 {
	404	spi1_clk: spi1-clk {
	405	rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>;
	406	};
	407	spi1_cs0: spi1-cs0 {
	408	rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>;
	409	};
	410	spi1_rx: spi1-rx {
	411	rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>;
	412	};
	413	spi1_tx: spi1-tx {
	414	rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>;
	415	};
	416	spi1_cs1: spi1-cs1 {
	417	rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>;
	418	};
	419	};
	420
c3030d30 HS	421	uart0 {
	422	uart0_xfer: uart0-xfer {
	423	rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
	424	<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
	425	};
d63dc051	426
c3030d30 HS	427	uart0_cts: uart0-cts {
c3030d30 HS	428	rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	429	};
d63dc051 HS	430
c3030d30 HS	431	uart0_rts: uart0-rts {
	432	rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
	433	};
	434	};
d63dc051	435
c3030d30 HS	436	uart1 {
	437	uart1_xfer: uart1-xfer {
	438	rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
	439	<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
	440	};
d63dc051	441
c3030d30 HS	442	uart1_cts: uart1-cts {
c3030d30 HS	443	rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	444	};
d63dc051 HS	445
c3030d30 HS	446	uart1_rts: uart1-rts {
	447	rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
	448	};
	449	};
d63dc051	450
c3030d30 HS	451	uart2 {
	452	uart2_xfer: uart2-xfer {
	453	rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
	454	<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
	455	};
	456	/* no rts / cts for uart2 */
	457	};
d63dc051	458
c3030d30 HS	459	uart3 {
	460	uart3_xfer: uart3-xfer {
	461	rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
	462	<RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	463	};
d63dc051 HS	464
c3030d30 HS	465	uart3_cts: uart3-cts {
c3030d30 HS	466	rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	467	};
d63dc051 HS	468
c3030d30 HS	469	uart3_rts: uart3-rts {
c3030d30 HS	470	rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
d63dc051	471	};
c3030d30	472	};
d63dc051	473
c3030d30 HS	474	sd0 {
	475	sd0_clk: sd0-clk {
	476	rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
	477	};
d63dc051	478
c3030d30 HS	479	sd0_cmd: sd0-cmd {
	480	rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
	481	};
d63dc051	482
c3030d30 HS	483	sd0_cd: sd0-cd {
c3030d30 HS	484	rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	485	};
d63dc051 HS	486
c3030d30 HS	487	sd0_wp: sd0-wp {
	488	rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
	489	};
d63dc051	490
c3030d30 HS	491	sd0_bus1: sd0-bus-width1 {
	492	rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
	493	};
d63dc051	494
c3030d30 HS	495	sd0_bus4: sd0-bus-width4 {
	496	rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
	497	<RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
	498	<RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
	499	<RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
d63dc051	500	};
c3030d30	501	};
d63dc051	502
c3030d30 HS	503	sd1 {
	504	sd1_clk: sd1-clk {
	505	rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	506	};
d63dc051 HS	507
c3030d30 HS	508	sd1_cmd: sd1-cmd {
	509	rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
	510	};
d63dc051	511
c3030d30 HS	512	sd1_cd: sd1-cd {
	513	rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
	514	};
d63dc051	515
c3030d30 HS	516	sd1_wp: sd1-wp {
c3030d30 HS	517	rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	518	};
d63dc051 HS	519
c3030d30 HS	520	sd1_bus1: sd1-bus-width1 {
c3030d30 HS	521	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	522	};
d63dc051 HS	523
c3030d30 HS	524	sd1_bus4: sd1-bus-width4 {
	525	rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
	526	<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
	527	<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
	528	<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
d63dc051 HS	529	};
d63dc051 HS	530	};
5fe62b83 JC	531
	532	i2s0 {
	533	i2s0_bus: i2s0-bus {
	534	rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>,
	535	<RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>,
	536	<RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>,
	537	<RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>,
	538	<RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>,
	539	<RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>,
	540	<RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>,
	541	<RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>,
	542	<RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>;
	543	};
	544	};
	545
	546	i2s1 {
	547	i2s1_bus: i2s1-bus {
	548	rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>,
	549	<RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>,
	550	<RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>,
	551	<RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>,
	552	<RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>,
	553	<RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>;
	554	};
	555	};
	556
	557	i2s2 {
	558	i2s2_bus: i2s2-bus {
	559	rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>,
	560	<RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>,
	561	<RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>,
	562	<RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>,
	563	<RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>,
	564	<RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>;
	565	};
	566	};
d63dc051 HS	567	};
d63dc051 HS	568	};
fcbbf965	569
9cdffd8c HS	570	&i2c0 {
	571	pinctrl-names = "default";
	572	pinctrl-0 = <&i2c0_xfer>;
	573	};
	574
	575	&i2c1 {
	576	pinctrl-names = "default";
	577	pinctrl-0 = <&i2c1_xfer>;
	578	};
	579
	580	&i2c2 {
	581	pinctrl-names = "default";
	582	pinctrl-0 = <&i2c2_xfer>;
	583	};
	584
	585	&i2c3 {
	586	pinctrl-names = "default";
	587	pinctrl-0 = <&i2c3_xfer>;
	588	};
	589
	590	&i2c4 {
	591	pinctrl-names = "default";
	592	pinctrl-0 = <&i2c4_xfer>;
	593	};
	594
fcbbf965 HS	595	&mmc0 {
	596	pinctrl-names = "default";
	597	pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
	598	};
	599
	600	&mmc1 {
	601	pinctrl-names = "default";
	602	pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
	603	};
	604
550c7f4e BG	605	&pwm0 {
	606	pinctrl-names = "default";
	607	pinctrl-0 = <&pwm0_out>;
	608	};
	609
	610	&pwm1 {
	611	pinctrl-names = "default";
	612	pinctrl-0 = <&pwm1_out>;
	613	};
	614
	615	&pwm2 {
	616	pinctrl-names = "default";
	617	pinctrl-0 = <&pwm2_out>;
	618	};
	619
	620	&pwm3 {
	621	pinctrl-names = "default";
	622	pinctrl-0 = <&pwm3_out>;
	623	};
	624
39c2bd78 HS	625	&spi0 {
	626	pinctrl-names = "default";
	627	pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
	628	};
	629
	630	&spi1 {
	631	pinctrl-names = "default";
	632	pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
	633	};
	634
fcbbf965 HS	635	&uart0 {
	636	pinctrl-names = "default";
	637	pinctrl-0 = <&uart0_xfer>;
	638	};
	639
	640	&uart1 {
	641	pinctrl-names = "default";
	642	pinctrl-0 = <&uart1_xfer>;
	643	};
	644
	645	&uart2 {
	646	pinctrl-names = "default";
	647	pinctrl-0 = <&uart2_xfer>;
	648	};
	649
	650	&uart3 {
	651	pinctrl-names = "default";
	652	pinctrl-0 = <&uart3_xfer>;
	653	};
eb2b9d47 HS	654
	655	&wdt {
	656	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
	657	};
89f66876 RP	658
	659	&emac {
	660	compatible = "rockchip,rk3066-emac";
	661	};