Commit | Line | Data |
---|---|---|
2aec37c6 RV |
1 | /dts-v1/; |
2 | ||
bf7f6b04 | 3 | #include <dt-bindings/interrupt-controller/irq.h> |
3933d267 | 4 | #include <dt-bindings/clock/qcom,gcc-msm8974.h> |
bf7f6b04 | 5 | #include "skeleton.dtsi" |
3933d267 | 6 | |
2aec37c6 RV |
7 | / { |
8 | model = "Qualcomm MSM8974"; | |
9 | compatible = "qcom,msm8974"; | |
10 | interrupt-parent = <&intc>; | |
11 | ||
6297c4b2 BA |
12 | reserved-memory { |
13 | #address-cells = <1>; | |
14 | #size-cells = <1>; | |
15 | ranges; | |
16 | ||
17 | smem_region: smem@fa00000 { | |
18 | reg = <0xfa00000 0x200000>; | |
19 | no-map; | |
20 | }; | |
21 | }; | |
22 | ||
2ab27991 RV |
23 | cpus { |
24 | #address-cells = <1>; | |
25 | #size-cells = <0>; | |
26 | interrupts = <1 9 0xf04>; | |
2ab27991 RV |
27 | |
28 | cpu@0 { | |
ba08220a KG |
29 | compatible = "qcom,krait"; |
30 | enable-method = "qcom,kpss-acc-v2"; | |
2ab27991 RV |
31 | device_type = "cpu"; |
32 | reg = <0>; | |
33 | next-level-cache = <&L2>; | |
34 | qcom,acc = <&acc0>; | |
8c76a638 | 35 | qcom,saw = <&saw0>; |
d596d620 | 36 | cpu-idle-states = <&CPU_SPC>; |
2ab27991 RV |
37 | }; |
38 | ||
39 | cpu@1 { | |
ba08220a KG |
40 | compatible = "qcom,krait"; |
41 | enable-method = "qcom,kpss-acc-v2"; | |
2ab27991 RV |
42 | device_type = "cpu"; |
43 | reg = <1>; | |
44 | next-level-cache = <&L2>; | |
45 | qcom,acc = <&acc1>; | |
8c76a638 | 46 | qcom,saw = <&saw1>; |
d596d620 | 47 | cpu-idle-states = <&CPU_SPC>; |
2ab27991 RV |
48 | }; |
49 | ||
50 | cpu@2 { | |
ba08220a KG |
51 | compatible = "qcom,krait"; |
52 | enable-method = "qcom,kpss-acc-v2"; | |
2ab27991 RV |
53 | device_type = "cpu"; |
54 | reg = <2>; | |
55 | next-level-cache = <&L2>; | |
56 | qcom,acc = <&acc2>; | |
8c76a638 | 57 | qcom,saw = <&saw2>; |
d596d620 | 58 | cpu-idle-states = <&CPU_SPC>; |
2ab27991 RV |
59 | }; |
60 | ||
61 | cpu@3 { | |
ba08220a KG |
62 | compatible = "qcom,krait"; |
63 | enable-method = "qcom,kpss-acc-v2"; | |
2ab27991 RV |
64 | device_type = "cpu"; |
65 | reg = <3>; | |
66 | next-level-cache = <&L2>; | |
67 | qcom,acc = <&acc3>; | |
8c76a638 | 68 | qcom,saw = <&saw3>; |
d596d620 | 69 | cpu-idle-states = <&CPU_SPC>; |
2ab27991 RV |
70 | }; |
71 | ||
72 | L2: l2-cache { | |
73 | compatible = "cache"; | |
74 | cache-level = <2>; | |
2ab27991 RV |
75 | qcom,saw = <&saw_l2>; |
76 | }; | |
d596d620 LI |
77 | |
78 | idle-states { | |
79 | CPU_SPC: spc { | |
80 | compatible = "qcom,idle-state-spc", | |
81 | "arm,idle-state"; | |
82 | entry-latency-us = <150>; | |
83 | exit-latency-us = <200>; | |
84 | min-residency-us = <2000>; | |
85 | }; | |
86 | }; | |
2ab27991 RV |
87 | }; |
88 | ||
3bff5474 SB |
89 | cpu-pmu { |
90 | compatible = "qcom,krait-pmu"; | |
91 | interrupts = <1 7 0xf04>; | |
92 | }; | |
93 | ||
ba08220a KG |
94 | timer { |
95 | compatible = "arm,armv7-timer"; | |
96 | interrupts = <1 2 0xf08>, | |
97 | <1 3 0xf08>, | |
98 | <1 4 0xf08>, | |
99 | <1 1 0xf08>; | |
100 | clock-frequency = <19200000>; | |
101 | }; | |
102 | ||
2aec37c6 RV |
103 | soc: soc { |
104 | #address-cells = <1>; | |
105 | #size-cells = <1>; | |
106 | ranges; | |
107 | compatible = "simple-bus"; | |
108 | ||
109 | intc: interrupt-controller@f9000000 { | |
110 | compatible = "qcom,msm-qgic2"; | |
111 | interrupt-controller; | |
112 | #interrupt-cells = <3>; | |
113 | reg = <0xf9000000 0x1000>, | |
114 | <0xf9002000 0x1000>; | |
115 | }; | |
116 | ||
47c5a5d6 SB |
117 | timer@f9020000 { |
118 | #address-cells = <1>; | |
119 | #size-cells = <1>; | |
120 | ranges; | |
121 | compatible = "arm,armv7-timer-mem"; | |
122 | reg = <0xf9020000 0x1000>; | |
123 | clock-frequency = <19200000>; | |
124 | ||
125 | frame@f9021000 { | |
126 | frame-number = <0>; | |
127 | interrupts = <0 8 0x4>, | |
128 | <0 7 0x4>; | |
129 | reg = <0xf9021000 0x1000>, | |
130 | <0xf9022000 0x1000>; | |
131 | }; | |
132 | ||
133 | frame@f9023000 { | |
134 | frame-number = <1>; | |
135 | interrupts = <0 9 0x4>; | |
136 | reg = <0xf9023000 0x1000>; | |
137 | status = "disabled"; | |
138 | }; | |
139 | ||
140 | frame@f9024000 { | |
141 | frame-number = <2>; | |
142 | interrupts = <0 10 0x4>; | |
143 | reg = <0xf9024000 0x1000>; | |
144 | status = "disabled"; | |
145 | }; | |
146 | ||
147 | frame@f9025000 { | |
148 | frame-number = <3>; | |
149 | interrupts = <0 11 0x4>; | |
150 | reg = <0xf9025000 0x1000>; | |
151 | status = "disabled"; | |
152 | }; | |
153 | ||
154 | frame@f9026000 { | |
155 | frame-number = <4>; | |
156 | interrupts = <0 12 0x4>; | |
157 | reg = <0xf9026000 0x1000>; | |
158 | status = "disabled"; | |
159 | }; | |
160 | ||
161 | frame@f9027000 { | |
162 | frame-number = <5>; | |
163 | interrupts = <0 13 0x4>; | |
164 | reg = <0xf9027000 0x1000>; | |
165 | status = "disabled"; | |
166 | }; | |
167 | ||
168 | frame@f9028000 { | |
169 | frame-number = <6>; | |
170 | interrupts = <0 14 0x4>; | |
171 | reg = <0xf9028000 0x1000>; | |
172 | status = "disabled"; | |
173 | }; | |
174 | }; | |
175 | ||
8c76a638 LI |
176 | saw0: power-controller@f9089000 { |
177 | compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; | |
178 | reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; | |
179 | }; | |
180 | ||
181 | saw1: power-controller@f9099000 { | |
182 | compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; | |
183 | reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; | |
184 | }; | |
185 | ||
186 | saw2: power-controller@f90a9000 { | |
187 | compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; | |
188 | reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; | |
189 | }; | |
190 | ||
191 | saw3: power-controller@f90b9000 { | |
192 | compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2"; | |
193 | reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; | |
194 | }; | |
195 | ||
196 | saw_l2: power-controller@f9012000 { | |
2ab27991 RV |
197 | compatible = "qcom,saw2"; |
198 | reg = <0xf9012000 0x1000>; | |
199 | regulator; | |
200 | }; | |
201 | ||
202 | acc0: clock-controller@f9088000 { | |
203 | compatible = "qcom,kpss-acc-v2"; | |
204 | reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; | |
205 | }; | |
206 | ||
207 | acc1: clock-controller@f9098000 { | |
208 | compatible = "qcom,kpss-acc-v2"; | |
209 | reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; | |
210 | }; | |
211 | ||
212 | acc2: clock-controller@f90a8000 { | |
213 | compatible = "qcom,kpss-acc-v2"; | |
214 | reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; | |
215 | }; | |
216 | ||
217 | acc3: clock-controller@f90b8000 { | |
218 | compatible = "qcom,kpss-acc-v2"; | |
219 | reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; | |
220 | }; | |
221 | ||
74e848f6 SB |
222 | restart@fc4ab000 { |
223 | compatible = "qcom,pshold"; | |
224 | reg = <0xfc4ab000 0x4>; | |
225 | }; | |
3933d267 SB |
226 | |
227 | gcc: clock-controller@fc400000 { | |
228 | compatible = "qcom,gcc-msm8974"; | |
229 | #clock-cells = <1>; | |
230 | #reset-cells = <1>; | |
231 | reg = <0xfc400000 0x4000>; | |
232 | }; | |
233 | ||
b4e745e1 BA |
234 | tcsr_mutex_block: syscon@fd484000 { |
235 | compatible = "syscon"; | |
236 | reg = <0xfd484000 0x2000>; | |
237 | }; | |
238 | ||
3933d267 SB |
239 | mmcc: clock-controller@fd8c0000 { |
240 | compatible = "qcom,mmcc-msm8974"; | |
241 | #clock-cells = <1>; | |
242 | #reset-cells = <1>; | |
243 | reg = <0xfd8c0000 0x6000>; | |
244 | }; | |
245 | ||
b4e745e1 BA |
246 | tcsr_mutex: tcsr-mutex { |
247 | compatible = "qcom,tcsr-mutex"; | |
248 | syscon = <&tcsr_mutex_block 0 0x80>; | |
249 | ||
250 | #hwlock-cells = <1>; | |
251 | }; | |
252 | ||
6297c4b2 BA |
253 | smem@fa00000 { |
254 | compatible = "qcom,smem"; | |
255 | ||
256 | memory-region = <&smem_region>; | |
257 | reg = <0xfc428000 0x4000>; | |
258 | ||
259 | hwlocks = <&tcsr_mutex 3>; | |
260 | }; | |
261 | ||
10bfcfea | 262 | blsp1_uart2: serial@f991e000 { |
3933d267 SB |
263 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
264 | reg = <0xf991e000 0x1000>; | |
265 | interrupts = <0 108 0x0>; | |
266 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | |
267 | clock-names = "core", "iface"; | |
ba08220a | 268 | status = "disabled"; |
3933d267 | 269 | }; |
19f4f8c1 | 270 | |
3e944c76 GD |
271 | sdhci@f9824900 { |
272 | compatible = "qcom,sdhci-msm-v4"; | |
273 | reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; | |
274 | reg-names = "hc_mem", "core_mem"; | |
275 | interrupts = <0 123 0>, <0 138 0>; | |
276 | interrupt-names = "hc_irq", "pwr_irq"; | |
277 | clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; | |
278 | clock-names = "core", "iface"; | |
279 | status = "disabled"; | |
280 | }; | |
281 | ||
282 | sdhci@f98a4900 { | |
283 | compatible = "qcom,sdhci-msm-v4"; | |
284 | reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; | |
285 | reg-names = "hc_mem", "core_mem"; | |
286 | interrupts = <0 125 0>, <0 221 0>; | |
287 | interrupt-names = "hc_irq", "pwr_irq"; | |
288 | clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; | |
289 | clock-names = "core", "iface"; | |
290 | status = "disabled"; | |
291 | }; | |
292 | ||
19f4f8c1 SV |
293 | rng@f9bff000 { |
294 | compatible = "qcom,prng"; | |
295 | reg = <0xf9bff000 0x200>; | |
296 | clocks = <&gcc GCC_PRNG_AHB_CLK>; | |
297 | clock-names = "core"; | |
298 | }; | |
7d7db8db II |
299 | |
300 | msmgpio: pinctrl@fd510000 { | |
301 | compatible = "qcom,msm8974-pinctrl"; | |
302 | reg = <0xfd510000 0x4000>; | |
303 | gpio-controller; | |
304 | #gpio-cells = <2>; | |
305 | interrupt-controller; | |
306 | #interrupt-cells = <2>; | |
307 | interrupts = <0 208 0>; | |
7d7db8db | 308 | }; |
bf7f6b04 | 309 | |
310 | blsp_i2c11: i2c@f9967000 { | |
311 | status = "disable"; | |
312 | compatible = "qcom,i2c-qup-v2.1.1"; | |
313 | reg = <0xf9967000 0x1000>; | |
314 | interrupts = <0 105 IRQ_TYPE_NONE>; | |
315 | clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; | |
316 | clock-names = "core", "iface"; | |
317 | #address-cells = <1>; | |
318 | #size-cells = <0>; | |
319 | }; | |
af22e46d II |
320 | |
321 | spmi_bus: spmi@fc4cf000 { | |
322 | compatible = "qcom,spmi-pmic-arb"; | |
323 | reg-names = "core", "intr", "cnfg"; | |
324 | reg = <0xfc4cf000 0x1000>, | |
325 | <0xfc4cb000 0x1000>, | |
326 | <0xfc4ca000 0x1000>; | |
327 | interrupt-names = "periph_irq"; | |
328 | interrupts = <0 190 0>; | |
329 | qcom,ee = <0>; | |
330 | qcom,channel = <0>; | |
331 | #address-cells = <2>; | |
332 | #size-cells = <0>; | |
333 | interrupt-controller; | |
334 | #interrupt-cells = <4>; | |
335 | }; | |
2aec37c6 RV |
336 | }; |
337 | }; |