[linux-2.6-block.git] / arch / arm / boot / dts / qcom-msm8974.dtsi

/dts-v1/;

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include "skeleton.dtsi"

/ {
	model = "Qualcomm MSM8974";
	compatible = "qcom,msm8974";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <1 9 0xf04>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
		};

		cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
		};

		cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			qcom,saw = <&saw_l2>;
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 7 0xf04>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 4 0xf08>,
			     <1 1 0xf08>;
		clock-frequency = <19200000>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
		};

		timer@f9020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;
			clock-frequency = <19200000>;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <0 8 0x4>,
					     <0 7 0x4>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <0 9 0x4>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <0 10 0x4>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <0 11 0x4>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <0 12 0x4>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <0 13 0x4>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <0 14 0x4>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		saw0: power-controller@f9089000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
		};

		saw1: power-controller@f9099000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
		};

		saw2: power-controller@f90a9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw3: power-controller@f90b9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw_l2: power-controller@f9012000 {
			compatible = "qcom,saw2";
			reg = <0xf9012000 0x1000>;
			regulator;
		};

		acc0: clock-controller@f9088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
		};

		acc1: clock-controller@f9098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
		};

		acc2: clock-controller@f90a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
		};

		acc3: clock-controller@f90b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			reg = <0xfc400000 0x4000>;
		};

		mmcc: clock-controller@fd8c0000 {
			compatible = "qcom,mmcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			reg = <0xfd8c0000 0x6000>;
		};

		serial@f991e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991e000 0x1000>;
			interrupts = <0 108 0x0>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f9824900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 123 0>, <0 138 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f98a4900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 125 0>, <0 221 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		rng@f9bff000 {
			compatible = "qcom,prng";
			reg = <0xf9bff000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		msmgpio: pinctrl@fd510000 {
			compatible = "qcom,msm8974-pinctrl";
			reg = <0xfd510000 0x4000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 208 0>;
		};

		blsp_i2c11: i2c@f9967000 {
			status = "disable";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9967000 0x1000>;
			interrupts = <0 105 IRQ_TYPE_NONE>;
			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <0 190 0>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};
	};
};
Commit	Line	Data
2aec37c6 RV	1	/dts-v1/;
2aec37c6 RV	2
bf7f6b04	3	#include <dt-bindings/interrupt-controller/irq.h>
3933d267	4	#include <dt-bindings/clock/qcom,gcc-msm8974.h>
bf7f6b04	5	#include "skeleton.dtsi"
3933d267	6
2aec37c6 RV	7	/ {
	8	model = "Qualcomm MSM8974";
	9	compatible = "qcom,msm8974";
	10	interrupt-parent = <&intc>;
	11
2ab27991 RV	12	cpus {
	13	#address-cells = <1>;
	14	#size-cells = <0>;
	15	interrupts = <1 9 0xf04>;
2ab27991 RV	16
2ab27991 RV	17	cpu@0 {
ba08220a KG	18	compatible = "qcom,krait";
ba08220a KG	19	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	20	device_type = "cpu";
	21	reg = <0>;
	22	next-level-cache = <&L2>;
	23	qcom,acc = <&acc0>;
8c76a638	24	qcom,saw = <&saw0>;
2ab27991 RV	25	};
	26
	27	cpu@1 {
ba08220a KG	28	compatible = "qcom,krait";
ba08220a KG	29	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	30	device_type = "cpu";
	31	reg = <1>;
	32	next-level-cache = <&L2>;
	33	qcom,acc = <&acc1>;
8c76a638	34	qcom,saw = <&saw1>;
2ab27991 RV	35	};
	36
	37	cpu@2 {
ba08220a KG	38	compatible = "qcom,krait";
ba08220a KG	39	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	40	device_type = "cpu";
	41	reg = <2>;
	42	next-level-cache = <&L2>;
	43	qcom,acc = <&acc2>;
8c76a638	44	qcom,saw = <&saw2>;
2ab27991 RV	45	};
	46
	47	cpu@3 {
ba08220a KG	48	compatible = "qcom,krait";
ba08220a KG	49	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	50	device_type = "cpu";
	51	reg = <3>;
	52	next-level-cache = <&L2>;
	53	qcom,acc = <&acc3>;
8c76a638	54	qcom,saw = <&saw3>;
2ab27991 RV	55	};
	56
	57	L2: l2-cache {
	58	compatible = "cache";
	59	cache-level = <2>;
2ab27991 RV	60	qcom,saw = <&saw_l2>;
	61	};
	62	};
	63
3bff5474 SB	64	cpu-pmu {
	65	compatible = "qcom,krait-pmu";
	66	interrupts = <1 7 0xf04>;
	67	};
	68
ba08220a KG	69	timer {
	70	compatible = "arm,armv7-timer";
	71	interrupts = <1 2 0xf08>,
	72	<1 3 0xf08>,
	73	<1 4 0xf08>,
	74	<1 1 0xf08>;
	75	clock-frequency = <19200000>;
	76	};
	77
2aec37c6 RV	78	soc: soc {
	79	#address-cells = <1>;
	80	#size-cells = <1>;
	81	ranges;
	82	compatible = "simple-bus";
	83
	84	intc: interrupt-controller@f9000000 {
	85	compatible = "qcom,msm-qgic2";
	86	interrupt-controller;
	87	#interrupt-cells = <3>;
	88	reg = <0xf9000000 0x1000>,
	89	<0xf9002000 0x1000>;
	90	};
	91
47c5a5d6 SB	92	timer@f9020000 {
	93	#address-cells = <1>;
	94	#size-cells = <1>;
	95	ranges;
	96	compatible = "arm,armv7-timer-mem";
	97	reg = <0xf9020000 0x1000>;
	98	clock-frequency = <19200000>;
	99
	100	frame@f9021000 {
	101	frame-number = <0>;
	102	interrupts = <0 8 0x4>,
	103	<0 7 0x4>;
	104	reg = <0xf9021000 0x1000>,
	105	<0xf9022000 0x1000>;
	106	};
	107
	108	frame@f9023000 {
	109	frame-number = <1>;
	110	interrupts = <0 9 0x4>;
	111	reg = <0xf9023000 0x1000>;
	112	status = "disabled";
	113	};
	114
	115	frame@f9024000 {
	116	frame-number = <2>;
	117	interrupts = <0 10 0x4>;
	118	reg = <0xf9024000 0x1000>;
	119	status = "disabled";
	120	};
	121
	122	frame@f9025000 {
	123	frame-number = <3>;
	124	interrupts = <0 11 0x4>;
	125	reg = <0xf9025000 0x1000>;
	126	status = "disabled";
	127	};
	128
	129	frame@f9026000 {
	130	frame-number = <4>;
	131	interrupts = <0 12 0x4>;
	132	reg = <0xf9026000 0x1000>;
	133	status = "disabled";
	134	};
	135
	136	frame@f9027000 {
	137	frame-number = <5>;
	138	interrupts = <0 13 0x4>;
	139	reg = <0xf9027000 0x1000>;
	140	status = "disabled";
	141	};
	142
	143	frame@f9028000 {
	144	frame-number = <6>;
	145	interrupts = <0 14 0x4>;
	146	reg = <0xf9028000 0x1000>;
	147	status = "disabled";
	148	};
	149	};
	150
8c76a638 LI	151	saw0: power-controller@f9089000 {
	152	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	153	reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
	154	};
	155
	156	saw1: power-controller@f9099000 {
	157	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	158	reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
	159	};
	160
	161	saw2: power-controller@f90a9000 {
	162	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	163	reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
	164	};
	165
	166	saw3: power-controller@f90b9000 {
	167	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	168	reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
	169	};
	170
	171	saw_l2: power-controller@f9012000 {
2ab27991 RV	172	compatible = "qcom,saw2";
	173	reg = <0xf9012000 0x1000>;
	174	regulator;
	175	};
	176
	177	acc0: clock-controller@f9088000 {
	178	compatible = "qcom,kpss-acc-v2";
	179	reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
	180	};
	181
	182	acc1: clock-controller@f9098000 {
	183	compatible = "qcom,kpss-acc-v2";
	184	reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
	185	};
	186
	187	acc2: clock-controller@f90a8000 {
	188	compatible = "qcom,kpss-acc-v2";
	189	reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
	190	};
	191
	192	acc3: clock-controller@f90b8000 {
	193	compatible = "qcom,kpss-acc-v2";
	194	reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
	195	};
	196
74e848f6 SB	197	restart@fc4ab000 {
	198	compatible = "qcom,pshold";
	199	reg = <0xfc4ab000 0x4>;
	200	};
3933d267 SB	201
	202	gcc: clock-controller@fc400000 {
	203	compatible = "qcom,gcc-msm8974";
	204	#clock-cells = <1>;
	205	#reset-cells = <1>;
	206	reg = <0xfc400000 0x4000>;
	207	};
	208
	209	mmcc: clock-controller@fd8c0000 {
	210	compatible = "qcom,mmcc-msm8974";
	211	#clock-cells = <1>;
	212	#reset-cells = <1>;
	213	reg = <0xfd8c0000 0x6000>;
	214	};
	215
	216	serial@f991e000 {
	217	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	218	reg = <0xf991e000 0x1000>;
	219	interrupts = <0 108 0x0>;
	220	clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	221	clock-names = "core", "iface";
ba08220a	222	status = "disabled";
3933d267	223	};
19f4f8c1	224
3e944c76 GD	225	sdhci@f9824900 {
	226	compatible = "qcom,sdhci-msm-v4";
	227	reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
	228	reg-names = "hc_mem", "core_mem";
	229	interrupts = <0 123 0>, <0 138 0>;
	230	interrupt-names = "hc_irq", "pwr_irq";
	231	clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
	232	clock-names = "core", "iface";
	233	status = "disabled";
	234	};
	235
	236	sdhci@f98a4900 {
	237	compatible = "qcom,sdhci-msm-v4";
	238	reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
	239	reg-names = "hc_mem", "core_mem";
	240	interrupts = <0 125 0>, <0 221 0>;
	241	interrupt-names = "hc_irq", "pwr_irq";
	242	clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
	243	clock-names = "core", "iface";
	244	status = "disabled";
	245	};
	246
19f4f8c1 SV	247	rng@f9bff000 {
	248	compatible = "qcom,prng";
	249	reg = <0xf9bff000 0x200>;
	250	clocks = <&gcc GCC_PRNG_AHB_CLK>;
	251	clock-names = "core";
	252	};
7d7db8db II	253
	254	msmgpio: pinctrl@fd510000 {
	255	compatible = "qcom,msm8974-pinctrl";
	256	reg = <0xfd510000 0x4000>;
	257	gpio-controller;
	258	#gpio-cells = <2>;
	259	interrupt-controller;
	260	#interrupt-cells = <2>;
	261	interrupts = <0 208 0>;
7d7db8db	262	};
bf7f6b04	263
	264	blsp_i2c11: i2c@f9967000 {
	265	status = "disable";
	266	compatible = "qcom,i2c-qup-v2.1.1";
	267	reg = <0xf9967000 0x1000>;
	268	interrupts = <0 105 IRQ_TYPE_NONE>;
	269	clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	270	clock-names = "core", "iface";
	271	#address-cells = <1>;
	272	#size-cells = <0>;
	273	};
af22e46d II	274
	275	spmi_bus: spmi@fc4cf000 {
	276	compatible = "qcom,spmi-pmic-arb";
	277	reg-names = "core", "intr", "cnfg";
	278	reg = <0xfc4cf000 0x1000>,
	279	<0xfc4cb000 0x1000>,
	280	<0xfc4ca000 0x1000>;
	281	interrupt-names = "periph_irq";
	282	interrupts = <0 190 0>;
	283	qcom,ee = <0>;
	284	qcom,channel = <0>;
	285	#address-cells = <2>;
	286	#size-cells = <0>;
	287	interrupt-controller;
	288	#interrupt-cells = <4>;
	289	};
2aec37c6 RV	290	};
2aec37c6 RV	291	};