[linux-2.6-block.git] / arch / arm / boot / dts / qcom-msm8974.dtsi

/dts-v1/;

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include "skeleton.dtsi"

/ {
	model = "Qualcomm MSM8974";
	compatible = "qcom,msm8974";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		mpss@08000000 {
			reg = <0x08000000 0x5100000>;
			no-map;
		};

		mba@00d100000 {
			reg = <0x0d100000 0x100000>;
			no-map;
		};

		reserved@0d200000 {
			reg = <0x0d200000 0xa00000>;
			no-map;
		};

		adsp@0dc00000 {
			reg = <0x0dc00000 0x1900000>;
			no-map;
		};

		venus@0f500000 {
			reg = <0x0f500000 0x500000>;
			no-map;
		};

		smem_region: smem@fa00000 {
			reg = <0xfa00000 0x200000>;
			no-map;
		};

		tz@0fc00000 {
			reg = <0x0fc00000 0x160000>;
			no-map;
		};

		efs@0fd600000 {
			reg = <0x0fd60000 0x1a0000>;
			no-map;
		};

		unused@0ff00000 {
			reg = <0x0ff00000 0x10100000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <1 9 0xf04>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			qcom,saw = <&saw_l2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <150>;
				exit-latency-us = <200>;
				min-residency-us = <2000>;
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 7 0xf04>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 4 0xf08>,
			     <1 1 0xf08>;
		clock-frequency = <19200000>;
	};

	smem {
		compatible = "qcom,smem";

		memory-region = <&smem_region>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		hwlocks = <&tcsr_mutex 3>;
	};

	smp2p-wcnss {
		compatible = "qcom,smp2p";
		qcom,smem = <451>, <431>;

		interrupt-parent = <&intc>;
		interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs 8 18>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <4>;

		wcnss_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";

			#qcom,state-cells = <1>;
		};

		wcnss_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smsm {
		compatible = "qcom,smsm";

		#address-cells = <1>;
		#size-cells = <0>;

		qcom,ipc-1 = <&apcs 8 13>;
		qcom,ipc-2 = <&apcs 8 9>;
		qcom,ipc-3 = <&apcs 8 19>;

		apps_smsm: apps@0 {
			reg = <0>;

			#qcom,state-cells = <1>;
		};

		modem_smsm: modem@1 {
			reg = <1>;
			interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		adsp_smsm: adsp@2 {
			reg = <2>;
			interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		wcnss_smsm: wcnss@7 {
			reg = <7>;
			interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
		};

		apcs: syscon@f9011000 {
			compatible = "syscon";
			reg = <0xf9011000 0x1000>;
		};

		timer@f9020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;
			clock-frequency = <19200000>;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <0 8 0x4>,
					     <0 7 0x4>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <0 9 0x4>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <0 10 0x4>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <0 11 0x4>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <0 12 0x4>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <0 13 0x4>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <0 14 0x4>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		saw0: power-controller@f9089000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
		};

		saw1: power-controller@f9099000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
		};

		saw2: power-controller@f90a9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw3: power-controller@f90b9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw_l2: power-controller@f9012000 {
			compatible = "qcom,saw2";
			reg = <0xf9012000 0x1000>;
			regulator;
		};

		acc0: clock-controller@f9088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
		};

		acc1: clock-controller@f9098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
		};

		acc2: clock-controller@f90a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
		};

		acc3: clock-controller@f90b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfc400000 0x4000>;
		};

		tcsr_mutex_block: syscon@fd484000 {
			compatible = "syscon";
			reg = <0xfd484000 0x2000>;
		};

		mmcc: clock-controller@fd8c0000 {
			compatible = "qcom,mmcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfd8c0000 0x6000>;
		};

		tcsr_mutex: tcsr-mutex {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_block 0 0x80>;

			#hwlock-cells = <1>;
		};

		rpm_msg_ram: memory@fc428000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0xfc428000 0x4000>;
		};

		blsp1_uart2: serial@f991e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991e000 0x1000>;
			interrupts = <0 108 0x0>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f9824900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 123 0>, <0 138 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f98a4900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 125 0>, <0 221 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		rng@f9bff000 {
			compatible = "qcom,prng";
			reg = <0xf9bff000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		msmgpio: pinctrl@fd510000 {
			compatible = "qcom,msm8974-pinctrl";
			reg = <0xfd510000 0x4000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 208 0>;
		};

		blsp_i2c8: i2c@f9964000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9964000 0x1000>;
			interrupts = <0 102 IRQ_TYPE_NONE>;
			clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp_i2c11: i2c@f9967000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9967000 0x1000>;
			interrupts = <0 105 IRQ_TYPE_NONE>;
			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <0 190 0>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};
	};

	smd {
		compatible = "qcom,smd";

		rpm {
			interrupts = <0 168 1>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			rpm_requests {
				compatible = "qcom,rpm-msm8974";
				qcom,smd-channels = "rpm_requests";

				pm8841-regulators {
					compatible = "qcom,rpm-pm8841-regulators";

					pm8841_s1: s1 {};
					pm8841_s2: s2 {};
					pm8841_s3: s3 {};
					pm8841_s4: s4 {};
					pm8841_s5: s5 {};
					pm8841_s6: s6 {};
					pm8841_s7: s7 {};
					pm8841_s8: s8 {};
				};

				pm8941-regulators {
					compatible = "qcom,rpm-pm8941-regulators";

					pm8941_s1: s1 {};
					pm8941_s2: s2 {};
					pm8941_s3: s3 {};
					pm8941_5v: s4 {};

					pm8941_l1: l1 {};
					pm8941_l2: l2 {};
					pm8941_l3: l3 {};
					pm8941_l4: l4 {};
					pm8941_l5: l5 {};
					pm8941_l6: l6 {};
					pm8941_l7: l7 {};
					pm8941_l8: l8 {};
					pm8941_l9: l9 {};
					pm8941_l10: l10 {};
					pm8941_l11: l11 {};
					pm8941_l12: l12 {};
					pm8941_l13: l13 {};
					pm8941_l14: l14 {};
					pm8941_l15: l15 {};
					pm8941_l16: l16 {};
					pm8941_l17: l17 {};
					pm8941_l18: l18 {};
					pm8941_l19: l19 {};
					pm8941_l20: l20 {};
					pm8941_l21: l21 {};
					pm8941_l22: l22 {};
					pm8941_l23: l23 {};
					pm8941_l24: l24 {};

					pm8941_lvs1: lvs1 {};
					pm8941_lvs2: lvs2 {};
					pm8941_lvs3: lvs3 {};

					pm8941_5vs1: 5vs1 {};
					pm8941_5vs2: 5vs2 {};
				};
			};
		};
	};
};
Commit	Line	Data
2aec37c6 RV	1	/dts-v1/;
2aec37c6 RV	2
bf7f6b04	3	#include <dt-bindings/interrupt-controller/irq.h>
3933d267	4	#include <dt-bindings/clock/qcom,gcc-msm8974.h>
bf7f6b04	5	#include "skeleton.dtsi"
3933d267	6
2aec37c6 RV	7	/ {
	8	model = "Qualcomm MSM8974";
	9	compatible = "qcom,msm8974";
	10	interrupt-parent = <&intc>;
	11
6297c4b2 BA	12	reserved-memory {
	13	#address-cells = <1>;
	14	#size-cells = <1>;
	15	ranges;
	16
ca3971cf BA	17	mpss@08000000 {
	18	reg = <0x08000000 0x5100000>;
	19	no-map;
	20	};
	21
	22	mba@00d100000 {
	23	reg = <0x0d100000 0x100000>;
	24	no-map;
	25	};
	26
	27	reserved@0d200000 {
	28	reg = <0x0d200000 0xa00000>;
	29	no-map;
	30	};
	31
	32	adsp@0dc00000 {
	33	reg = <0x0dc00000 0x1900000>;
	34	no-map;
	35	};
	36
	37	venus@0f500000 {
	38	reg = <0x0f500000 0x500000>;
	39	no-map;
	40	};
	41
6297c4b2 BA	42	smem_region: smem@fa00000 {
	43	reg = <0xfa00000 0x200000>;
	44	no-map;
	45	};
ca3971cf BA	46
	47	tz@0fc00000 {
	48	reg = <0x0fc00000 0x160000>;
	49	no-map;
	50	};
	51
	52	efs@0fd600000 {
	53	reg = <0x0fd60000 0x1a0000>;
	54	no-map;
	55	};
	56
	57	unused@0ff00000 {
	58	reg = <0x0ff00000 0x10100000>;
	59	no-map;
	60	};
6297c4b2 BA	61	};
6297c4b2 BA	62
2ab27991 RV	63	cpus {
	64	#address-cells = <1>;
	65	#size-cells = <0>;
	66	interrupts = <1 9 0xf04>;
2ab27991 RV	67
2ab27991 RV	68	cpu@0 {
ba08220a KG	69	compatible = "qcom,krait";
ba08220a KG	70	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	71	device_type = "cpu";
	72	reg = <0>;
	73	next-level-cache = <&L2>;
	74	qcom,acc = <&acc0>;
8c76a638	75	qcom,saw = <&saw0>;
d596d620	76	cpu-idle-states = <&CPU_SPC>;
2ab27991 RV	77	};
	78
	79	cpu@1 {
ba08220a KG	80	compatible = "qcom,krait";
ba08220a KG	81	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	82	device_type = "cpu";
	83	reg = <1>;
	84	next-level-cache = <&L2>;
	85	qcom,acc = <&acc1>;
8c76a638	86	qcom,saw = <&saw1>;
d596d620	87	cpu-idle-states = <&CPU_SPC>;
2ab27991 RV	88	};
	89
	90	cpu@2 {
ba08220a KG	91	compatible = "qcom,krait";
ba08220a KG	92	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	93	device_type = "cpu";
	94	reg = <2>;
	95	next-level-cache = <&L2>;
	96	qcom,acc = <&acc2>;
8c76a638	97	qcom,saw = <&saw2>;
d596d620	98	cpu-idle-states = <&CPU_SPC>;
2ab27991 RV	99	};
	100
	101	cpu@3 {
ba08220a KG	102	compatible = "qcom,krait";
ba08220a KG	103	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	104	device_type = "cpu";
	105	reg = <3>;
	106	next-level-cache = <&L2>;
	107	qcom,acc = <&acc3>;
8c76a638	108	qcom,saw = <&saw3>;
d596d620	109	cpu-idle-states = <&CPU_SPC>;
2ab27991 RV	110	};
	111
	112	L2: l2-cache {
	113	compatible = "cache";
	114	cache-level = <2>;
2ab27991 RV	115	qcom,saw = <&saw_l2>;
2ab27991 RV	116	};
d596d620 LI	117
	118	idle-states {
	119	CPU_SPC: spc {
	120	compatible = "qcom,idle-state-spc",
	121	"arm,idle-state";
	122	entry-latency-us = <150>;
	123	exit-latency-us = <200>;
	124	min-residency-us = <2000>;
	125	};
	126	};
2ab27991 RV	127	};
2ab27991 RV	128
3bff5474 SB	129	cpu-pmu {
	130	compatible = "qcom,krait-pmu";
	131	interrupts = <1 7 0xf04>;
	132	};
	133
ba08220a KG	134	timer {
	135	compatible = "arm,armv7-timer";
	136	interrupts = <1 2 0xf08>,
	137	<1 3 0xf08>,
	138	<1 4 0xf08>,
	139	<1 1 0xf08>;
	140	clock-frequency = <19200000>;
	141	};
	142
d0bfd7c9 SB	143	smem {
	144	compatible = "qcom,smem";
	145
	146	memory-region = <&smem_region>;
	147	qcom,rpm-msg-ram = <&rpm_msg_ram>;
	148
	149	hwlocks = <&tcsr_mutex 3>;
	150	};
	151
7ccb11e7 BA	152	smp2p-wcnss {
	153	compatible = "qcom,smp2p";
	154	qcom,smem = <451>, <431>;
	155
	156	interrupt-parent = <&intc>;
	157	interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
	158
	159	qcom,ipc = <&apcs 8 18>;
	160
	161	qcom,local-pid = <0>;
	162	qcom,remote-pid = <4>;
	163
	164	wcnss_smp2p_out: master-kernel {
	165	qcom,entry-name = "master-kernel";
	166
	167	#qcom,state-cells = <1>;
	168	};
	169
	170	wcnss_smp2p_in: slave-kernel {
	171	qcom,entry-name = "slave-kernel";
	172
	173	interrupt-controller;
	174	#interrupt-cells = <2>;
	175	};
	176	};
	177
9af88b2d BA	178	smsm {
	179	compatible = "qcom,smsm";
	180
	181	#address-cells = <1>;
	182	#size-cells = <0>;
	183
	184	qcom,ipc-1 = <&apcs 8 13>;
	185	qcom,ipc-2 = <&apcs 8 9>;
	186	qcom,ipc-3 = <&apcs 8 19>;
	187
	188	apps_smsm: apps@0 {
	189	reg = <0>;
	190
	191	#qcom,state-cells = <1>;
	192	};
	193
	194	modem_smsm: modem@1 {
	195	reg = <1>;
	196	interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
	197
	198	interrupt-controller;
	199	#interrupt-cells = <2>;
	200	};
	201
	202	adsp_smsm: adsp@2 {
	203	reg = <2>;
	204	interrupts = <0 157 IRQ_TYPE_EDGE_RISING>;
	205
	206	interrupt-controller;
	207	#interrupt-cells = <2>;
	208	};
	209
	210	wcnss_smsm: wcnss@7 {
	211	reg = <7>;
	212	interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
	213
	214	interrupt-controller;
	215	#interrupt-cells = <2>;
	216	};
	217	};
	218
2aec37c6 RV	219	soc: soc {
	220	#address-cells = <1>;
	221	#size-cells = <1>;
	222	ranges;
	223	compatible = "simple-bus";
	224
	225	intc: interrupt-controller@f9000000 {
	226	compatible = "qcom,msm-qgic2";
	227	interrupt-controller;
	228	#interrupt-cells = <3>;
	229	reg = <0xf9000000 0x1000>,
	230	<0xf9002000 0x1000>;
	231	};
	232
45b0ef05 BA	233	apcs: syscon@f9011000 {
	234	compatible = "syscon";
	235	reg = <0xf9011000 0x1000>;
	236	};
	237
47c5a5d6 SB	238	timer@f9020000 {
	239	#address-cells = <1>;
	240	#size-cells = <1>;
	241	ranges;
	242	compatible = "arm,armv7-timer-mem";
	243	reg = <0xf9020000 0x1000>;
	244	clock-frequency = <19200000>;
	245
	246	frame@f9021000 {
	247	frame-number = <0>;
	248	interrupts = <0 8 0x4>,
	249	<0 7 0x4>;
	250	reg = <0xf9021000 0x1000>,
	251	<0xf9022000 0x1000>;
	252	};
	253
	254	frame@f9023000 {
	255	frame-number = <1>;
	256	interrupts = <0 9 0x4>;
	257	reg = <0xf9023000 0x1000>;
	258	status = "disabled";
	259	};
	260
	261	frame@f9024000 {
	262	frame-number = <2>;
	263	interrupts = <0 10 0x4>;
	264	reg = <0xf9024000 0x1000>;
	265	status = "disabled";
	266	};
	267
	268	frame@f9025000 {
	269	frame-number = <3>;
	270	interrupts = <0 11 0x4>;
	271	reg = <0xf9025000 0x1000>;
	272	status = "disabled";
	273	};
	274
	275	frame@f9026000 {
	276	frame-number = <4>;
	277	interrupts = <0 12 0x4>;
	278	reg = <0xf9026000 0x1000>;
	279	status = "disabled";
	280	};
	281
	282	frame@f9027000 {
	283	frame-number = <5>;
	284	interrupts = <0 13 0x4>;
	285	reg = <0xf9027000 0x1000>;
	286	status = "disabled";
	287	};
	288
	289	frame@f9028000 {
	290	frame-number = <6>;
	291	interrupts = <0 14 0x4>;
	292	reg = <0xf9028000 0x1000>;
	293	status = "disabled";
	294	};
	295	};
	296
8c76a638 LI	297	saw0: power-controller@f9089000 {
	298	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	299	reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
	300	};
	301
	302	saw1: power-controller@f9099000 {
	303	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	304	reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
	305	};
	306
	307	saw2: power-controller@f90a9000 {
	308	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	309	reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
	310	};
	311
	312	saw3: power-controller@f90b9000 {
	313	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	314	reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
	315	};
	316
	317	saw_l2: power-controller@f9012000 {
2ab27991 RV	318	compatible = "qcom,saw2";
	319	reg = <0xf9012000 0x1000>;
	320	regulator;
	321	};
	322
	323	acc0: clock-controller@f9088000 {
	324	compatible = "qcom,kpss-acc-v2";
	325	reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
	326	};
	327
	328	acc1: clock-controller@f9098000 {
	329	compatible = "qcom,kpss-acc-v2";
	330	reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
	331	};
	332
	333	acc2: clock-controller@f90a8000 {
	334	compatible = "qcom,kpss-acc-v2";
	335	reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
	336	};
	337
	338	acc3: clock-controller@f90b8000 {
	339	compatible = "qcom,kpss-acc-v2";
	340	reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
	341	};
	342
74e848f6 SB	343	restart@fc4ab000 {
	344	compatible = "qcom,pshold";
	345	reg = <0xfc4ab000 0x4>;
	346	};
3933d267 SB	347
	348	gcc: clock-controller@fc400000 {
	349	compatible = "qcom,gcc-msm8974";
	350	#clock-cells = <1>;
	351	#reset-cells = <1>;
89c7e671	352	#power-domain-cells = <1>;
3933d267 SB	353	reg = <0xfc400000 0x4000>;
	354	};
	355
b4e745e1 BA	356	tcsr_mutex_block: syscon@fd484000 {
	357	compatible = "syscon";
	358	reg = <0xfd484000 0x2000>;
	359	};
	360
3933d267 SB	361	mmcc: clock-controller@fd8c0000 {
	362	compatible = "qcom,mmcc-msm8974";
	363	#clock-cells = <1>;
	364	#reset-cells = <1>;
89c7e671	365	#power-domain-cells = <1>;
3933d267 SB	366	reg = <0xfd8c0000 0x6000>;
	367	};
	368
b4e745e1 BA	369	tcsr_mutex: tcsr-mutex {
	370	compatible = "qcom,tcsr-mutex";
	371	syscon = <&tcsr_mutex_block 0 0x80>;
	372
	373	#hwlock-cells = <1>;
	374	};
	375
d0bfd7c9 SB	376	rpm_msg_ram: memory@fc428000 {
d0bfd7c9 SB	377	compatible = "qcom,rpm-msg-ram";
6297c4b2	378	reg = <0xfc428000 0x4000>;
6297c4b2 BA	379	};
6297c4b2 BA	380
10bfcfea	381	blsp1_uart2: serial@f991e000 {
3933d267 SB	382	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	383	reg = <0xf991e000 0x1000>;
	384	interrupts = <0 108 0x0>;
	385	clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	386	clock-names = "core", "iface";
ba08220a	387	status = "disabled";
3933d267	388	};
19f4f8c1	389
3e944c76 GD	390	sdhci@f9824900 {
	391	compatible = "qcom,sdhci-msm-v4";
	392	reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
	393	reg-names = "hc_mem", "core_mem";
	394	interrupts = <0 123 0>, <0 138 0>;
	395	interrupt-names = "hc_irq", "pwr_irq";
	396	clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
	397	clock-names = "core", "iface";
	398	status = "disabled";
	399	};
	400
	401	sdhci@f98a4900 {
	402	compatible = "qcom,sdhci-msm-v4";
	403	reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
	404	reg-names = "hc_mem", "core_mem";
	405	interrupts = <0 125 0>, <0 221 0>;
	406	interrupt-names = "hc_irq", "pwr_irq";
	407	clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
	408	clock-names = "core", "iface";
	409	status = "disabled";
	410	};
	411
19f4f8c1 SV	412	rng@f9bff000 {
	413	compatible = "qcom,prng";
	414	reg = <0xf9bff000 0x200>;
	415	clocks = <&gcc GCC_PRNG_AHB_CLK>;
	416	clock-names = "core";
	417	};
7d7db8db II	418
	419	msmgpio: pinctrl@fd510000 {
	420	compatible = "qcom,msm8974-pinctrl";
	421	reg = <0xfd510000 0x4000>;
	422	gpio-controller;
	423	#gpio-cells = <2>;
	424	interrupt-controller;
	425	#interrupt-cells = <2>;
	426	interrupts = <0 208 0>;
7d7db8db	427	};
bf7f6b04	428
580df59f BA	429	blsp_i2c8: i2c@f9964000 {
	430	status = "disabled";
	431	compatible = "qcom,i2c-qup-v2.1.1";
	432	reg = <0xf9964000 0x1000>;
	433	interrupts = <0 102 IRQ_TYPE_NONE>;
	434	clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	435	clock-names = "core", "iface";
	436	#address-cells = <1>;
	437	#size-cells = <0>;
	438	};
	439
bf7f6b04	440	blsp_i2c11: i2c@f9967000 {
04edde25	441	status = "disabled";
bf7f6b04	442	compatible = "qcom,i2c-qup-v2.1.1";
	443	reg = <0xf9967000 0x1000>;
	444	interrupts = <0 105 IRQ_TYPE_NONE>;
	445	clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	446	clock-names = "core", "iface";
	447	#address-cells = <1>;
	448	#size-cells = <0>;
	449	};
af22e46d II	450
	451	spmi_bus: spmi@fc4cf000 {
	452	compatible = "qcom,spmi-pmic-arb";
	453	reg-names = "core", "intr", "cnfg";
	454	reg = <0xfc4cf000 0x1000>,
	455	<0xfc4cb000 0x1000>,
	456	<0xfc4ca000 0x1000>;
	457	interrupt-names = "periph_irq";
	458	interrupts = <0 190 0>;
	459	qcom,ee = <0>;
	460	qcom,channel = <0>;
	461	#address-cells = <2>;
	462	#size-cells = <0>;
	463	interrupt-controller;
	464	#interrupt-cells = <4>;
	465	};
2aec37c6	466	};
45b0ef05 BA	467
	468	smd {
	469	compatible = "qcom,smd";
	470
	471	rpm {
	472	interrupts = <0 168 1>;
	473	qcom,ipc = <&apcs 8 0>;
	474	qcom,smd-edge = <15>;
	475
	476	rpm_requests {
	477	compatible = "qcom,rpm-msm8974";
	478	qcom,smd-channels = "rpm_requests";
	479
	480	pm8841-regulators {
	481	compatible = "qcom,rpm-pm8841-regulators";
	482
	483	pm8841_s1: s1 {};
	484	pm8841_s2: s2 {};
	485	pm8841_s3: s3 {};
	486	pm8841_s4: s4 {};
	487	pm8841_s5: s5 {};
	488	pm8841_s6: s6 {};
	489	pm8841_s7: s7 {};
	490	pm8841_s8: s8 {};
	491	};
	492
	493	pm8941-regulators {
	494	compatible = "qcom,rpm-pm8941-regulators";
	495
	496	pm8941_s1: s1 {};
	497	pm8941_s2: s2 {};
	498	pm8941_s3: s3 {};
	499	pm8941_5v: s4 {};
	500
	501	pm8941_l1: l1 {};
	502	pm8941_l2: l2 {};
	503	pm8941_l3: l3 {};
	504	pm8941_l4: l4 {};
	505	pm8941_l5: l5 {};
	506	pm8941_l6: l6 {};
	507	pm8941_l7: l7 {};
	508	pm8941_l8: l8 {};
	509	pm8941_l9: l9 {};
	510	pm8941_l10: l10 {};
	511	pm8941_l11: l11 {};
	512	pm8941_l12: l12 {};
	513	pm8941_l13: l13 {};
	514	pm8941_l14: l14 {};
	515	pm8941_l15: l15 {};
	516	pm8941_l16: l16 {};
	517	pm8941_l17: l17 {};
	518	pm8941_l18: l18 {};
	519	pm8941_l19: l19 {};
	520	pm8941_l20: l20 {};
	521	pm8941_l21: l21 {};
	522	pm8941_l22: l22 {};
	523	pm8941_l23: l23 {};
	524	pm8941_l24: l24 {};
	525
	526	pm8941_lvs1: lvs1 {};
	527	pm8941_lvs2: lvs2 {};
	528	pm8941_lvs3: lvs3 {};
	529
	530	pm8941_5vs1: 5vs1 {};
531	pm8941_5vs2: 5vs2 {};
532	};
533	};
534	};
535	};
2aec37c6	536	};