[linux-2.6-block.git] / arch / arm / boot / dts / qcom-msm8974.dtsi

/dts-v1/;

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include "skeleton.dtsi"

/ {
	model = "Qualcomm MSM8974";
	compatible = "qcom,msm8974";
	interrupt-parent = <&intc>;

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		smem_region: smem@fa00000 {
			reg = <0xfa00000 0x200000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <1 9 0xf04>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <2>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v2";
			device_type = "cpu";
			reg = <3>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
			qcom,saw = <&saw_l2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <150>;
				exit-latency-us = <200>;
				min-residency-us = <2000>;
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 7 0xf04>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 4 0xf08>,
			     <1 1 0xf08>;
		clock-frequency = <19200000>;
	};

	smem {
		compatible = "qcom,smem";

		memory-region = <&smem_region>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		hwlocks = <&tcsr_mutex 3>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
		};

		apcs: syscon@f9011000 {
			compatible = "syscon";
			reg = <0xf9011000 0x1000>;
		};

		timer@f9020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;
			clock-frequency = <19200000>;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <0 8 0x4>,
					     <0 7 0x4>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <0 9 0x4>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <0 10 0x4>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <0 11 0x4>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <0 12 0x4>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <0 13 0x4>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <0 14 0x4>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		saw0: power-controller@f9089000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
		};

		saw1: power-controller@f9099000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
		};

		saw2: power-controller@f90a9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw3: power-controller@f90b9000 {
			compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw_l2: power-controller@f9012000 {
			compatible = "qcom,saw2";
			reg = <0xf9012000 0x1000>;
			regulator;
		};

		acc0: clock-controller@f9088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
		};

		acc1: clock-controller@f9098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
		};

		acc2: clock-controller@f90a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
		};

		acc3: clock-controller@f90b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfc400000 0x4000>;
		};

		tcsr_mutex_block: syscon@fd484000 {
			compatible = "syscon";
			reg = <0xfd484000 0x2000>;
		};

		mmcc: clock-controller@fd8c0000 {
			compatible = "qcom,mmcc-msm8974";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0xfd8c0000 0x6000>;
		};

		tcsr_mutex: tcsr-mutex {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_block 0 0x80>;

			#hwlock-cells = <1>;
		};

		rpm_msg_ram: memory@fc428000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0xfc428000 0x4000>;
		};

		blsp1_uart2: serial@f991e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991e000 0x1000>;
			interrupts = <0 108 0x0>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f9824900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 123 0>, <0 138 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f98a4900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 125 0>, <0 221 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		rng@f9bff000 {
			compatible = "qcom,prng";
			reg = <0xf9bff000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		msmgpio: pinctrl@fd510000 {
			compatible = "qcom,msm8974-pinctrl";
			reg = <0xfd510000 0x4000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 208 0>;
		};

		blsp_i2c11: i2c@f9967000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9967000 0x1000>;
			interrupts = <0 105 IRQ_TYPE_NONE>;
			clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <0 190 0>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};
	};

	smd {
		compatible = "qcom,smd";

		rpm {
			interrupts = <0 168 1>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			rpm_requests {
				compatible = "qcom,rpm-msm8974";
				qcom,smd-channels = "rpm_requests";

				pm8841-regulators {
					compatible = "qcom,rpm-pm8841-regulators";

					pm8841_s1: s1 {};
					pm8841_s2: s2 {};
					pm8841_s3: s3 {};
					pm8841_s4: s4 {};
					pm8841_s5: s5 {};
					pm8841_s6: s6 {};
					pm8841_s7: s7 {};
					pm8841_s8: s8 {};
				};

				pm8941-regulators {
					compatible = "qcom,rpm-pm8941-regulators";

					pm8941_s1: s1 {};
					pm8941_s2: s2 {};
					pm8941_s3: s3 {};
					pm8941_5v: s4 {};

					pm8941_l1: l1 {};
					pm8941_l2: l2 {};
					pm8941_l3: l3 {};
					pm8941_l4: l4 {};
					pm8941_l5: l5 {};
					pm8941_l6: l6 {};
					pm8941_l7: l7 {};
					pm8941_l8: l8 {};
					pm8941_l9: l9 {};
					pm8941_l10: l10 {};
					pm8941_l11: l11 {};
					pm8941_l12: l12 {};
					pm8941_l13: l13 {};
					pm8941_l14: l14 {};
					pm8941_l15: l15 {};
					pm8941_l16: l16 {};
					pm8941_l17: l17 {};
					pm8941_l18: l18 {};
					pm8941_l19: l19 {};
					pm8941_l20: l20 {};
					pm8941_l21: l21 {};
					pm8941_l22: l22 {};
					pm8941_l23: l23 {};
					pm8941_l24: l24 {};

					pm8941_lvs1: lvs1 {};
					pm8941_lvs2: lvs2 {};
					pm8941_lvs3: lvs3 {};

					pm8941_5vs1: 5vs1 {};
					pm8941_5vs2: 5vs2 {};
				};
			};
		};
	};
};
Commit	Line	Data
2aec37c6 RV	1	/dts-v1/;
2aec37c6 RV	2
bf7f6b04	3	#include <dt-bindings/interrupt-controller/irq.h>
3933d267	4	#include <dt-bindings/clock/qcom,gcc-msm8974.h>
bf7f6b04	5	#include "skeleton.dtsi"
3933d267	6
2aec37c6 RV	7	/ {
	8	model = "Qualcomm MSM8974";
	9	compatible = "qcom,msm8974";
	10	interrupt-parent = <&intc>;
	11
6297c4b2 BA	12	reserved-memory {
	13	#address-cells = <1>;
	14	#size-cells = <1>;
	15	ranges;
	16
	17	smem_region: smem@fa00000 {
	18	reg = <0xfa00000 0x200000>;
	19	no-map;
	20	};
	21	};
	22
2ab27991 RV	23	cpus {
	24	#address-cells = <1>;
	25	#size-cells = <0>;
	26	interrupts = <1 9 0xf04>;
2ab27991 RV	27
2ab27991 RV	28	cpu@0 {
ba08220a KG	29	compatible = "qcom,krait";
ba08220a KG	30	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	31	device_type = "cpu";
	32	reg = <0>;
	33	next-level-cache = <&L2>;
	34	qcom,acc = <&acc0>;
8c76a638	35	qcom,saw = <&saw0>;
d596d620	36	cpu-idle-states = <&CPU_SPC>;
2ab27991 RV	37	};
	38
	39	cpu@1 {
ba08220a KG	40	compatible = "qcom,krait";
ba08220a KG	41	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	42	device_type = "cpu";
	43	reg = <1>;
	44	next-level-cache = <&L2>;
	45	qcom,acc = <&acc1>;
8c76a638	46	qcom,saw = <&saw1>;
d596d620	47	cpu-idle-states = <&CPU_SPC>;
2ab27991 RV	48	};
	49
	50	cpu@2 {
ba08220a KG	51	compatible = "qcom,krait";
ba08220a KG	52	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	53	device_type = "cpu";
	54	reg = <2>;
	55	next-level-cache = <&L2>;
	56	qcom,acc = <&acc2>;
8c76a638	57	qcom,saw = <&saw2>;
d596d620	58	cpu-idle-states = <&CPU_SPC>;
2ab27991 RV	59	};
	60
	61	cpu@3 {
ba08220a KG	62	compatible = "qcom,krait";
ba08220a KG	63	enable-method = "qcom,kpss-acc-v2";
2ab27991 RV	64	device_type = "cpu";
	65	reg = <3>;
	66	next-level-cache = <&L2>;
	67	qcom,acc = <&acc3>;
8c76a638	68	qcom,saw = <&saw3>;
d596d620	69	cpu-idle-states = <&CPU_SPC>;
2ab27991 RV	70	};
	71
	72	L2: l2-cache {
	73	compatible = "cache";
	74	cache-level = <2>;
2ab27991 RV	75	qcom,saw = <&saw_l2>;
2ab27991 RV	76	};
d596d620 LI	77
	78	idle-states {
	79	CPU_SPC: spc {
	80	compatible = "qcom,idle-state-spc",
	81	"arm,idle-state";
	82	entry-latency-us = <150>;
	83	exit-latency-us = <200>;
	84	min-residency-us = <2000>;
	85	};
	86	};
2ab27991 RV	87	};
2ab27991 RV	88
3bff5474 SB	89	cpu-pmu {
	90	compatible = "qcom,krait-pmu";
	91	interrupts = <1 7 0xf04>;
	92	};
	93
ba08220a KG	94	timer {
	95	compatible = "arm,armv7-timer";
	96	interrupts = <1 2 0xf08>,
	97	<1 3 0xf08>,
	98	<1 4 0xf08>,
	99	<1 1 0xf08>;
	100	clock-frequency = <19200000>;
	101	};
	102
d0bfd7c9 SB	103	smem {
	104	compatible = "qcom,smem";
	105
	106	memory-region = <&smem_region>;
	107	qcom,rpm-msg-ram = <&rpm_msg_ram>;
	108
	109	hwlocks = <&tcsr_mutex 3>;
	110	};
	111
2aec37c6 RV	112	soc: soc {
	113	#address-cells = <1>;
	114	#size-cells = <1>;
	115	ranges;
	116	compatible = "simple-bus";
	117
	118	intc: interrupt-controller@f9000000 {
	119	compatible = "qcom,msm-qgic2";
	120	interrupt-controller;
	121	#interrupt-cells = <3>;
	122	reg = <0xf9000000 0x1000>,
	123	<0xf9002000 0x1000>;
	124	};
	125
45b0ef05 BA	126	apcs: syscon@f9011000 {
	127	compatible = "syscon";
	128	reg = <0xf9011000 0x1000>;
	129	};
	130
47c5a5d6 SB	131	timer@f9020000 {
	132	#address-cells = <1>;
	133	#size-cells = <1>;
	134	ranges;
	135	compatible = "arm,armv7-timer-mem";
	136	reg = <0xf9020000 0x1000>;
	137	clock-frequency = <19200000>;
	138
	139	frame@f9021000 {
	140	frame-number = <0>;
	141	interrupts = <0 8 0x4>,
	142	<0 7 0x4>;
	143	reg = <0xf9021000 0x1000>,
	144	<0xf9022000 0x1000>;
	145	};
	146
	147	frame@f9023000 {
	148	frame-number = <1>;
	149	interrupts = <0 9 0x4>;
	150	reg = <0xf9023000 0x1000>;
	151	status = "disabled";
	152	};
	153
	154	frame@f9024000 {
	155	frame-number = <2>;
	156	interrupts = <0 10 0x4>;
	157	reg = <0xf9024000 0x1000>;
	158	status = "disabled";
	159	};
	160
	161	frame@f9025000 {
	162	frame-number = <3>;
	163	interrupts = <0 11 0x4>;
	164	reg = <0xf9025000 0x1000>;
	165	status = "disabled";
	166	};
	167
	168	frame@f9026000 {
	169	frame-number = <4>;
	170	interrupts = <0 12 0x4>;
	171	reg = <0xf9026000 0x1000>;
	172	status = "disabled";
	173	};
	174
	175	frame@f9027000 {
	176	frame-number = <5>;
	177	interrupts = <0 13 0x4>;
	178	reg = <0xf9027000 0x1000>;
	179	status = "disabled";
	180	};
	181
	182	frame@f9028000 {
	183	frame-number = <6>;
	184	interrupts = <0 14 0x4>;
	185	reg = <0xf9028000 0x1000>;
	186	status = "disabled";
	187	};
	188	};
	189
8c76a638 LI	190	saw0: power-controller@f9089000 {
	191	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	192	reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
	193	};
	194
	195	saw1: power-controller@f9099000 {
	196	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	197	reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
	198	};
	199
	200	saw2: power-controller@f90a9000 {
	201	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	202	reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
	203	};
	204
	205	saw3: power-controller@f90b9000 {
	206	compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
	207	reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
	208	};
	209
	210	saw_l2: power-controller@f9012000 {
2ab27991 RV	211	compatible = "qcom,saw2";
	212	reg = <0xf9012000 0x1000>;
	213	regulator;
	214	};
	215
	216	acc0: clock-controller@f9088000 {
	217	compatible = "qcom,kpss-acc-v2";
	218	reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
	219	};
	220
	221	acc1: clock-controller@f9098000 {
	222	compatible = "qcom,kpss-acc-v2";
	223	reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
	224	};
	225
	226	acc2: clock-controller@f90a8000 {
	227	compatible = "qcom,kpss-acc-v2";
	228	reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
	229	};
	230
	231	acc3: clock-controller@f90b8000 {
	232	compatible = "qcom,kpss-acc-v2";
	233	reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
	234	};
	235
74e848f6 SB	236	restart@fc4ab000 {
	237	compatible = "qcom,pshold";
	238	reg = <0xfc4ab000 0x4>;
	239	};
3933d267 SB	240
	241	gcc: clock-controller@fc400000 {
	242	compatible = "qcom,gcc-msm8974";
	243	#clock-cells = <1>;
	244	#reset-cells = <1>;
89c7e671	245	#power-domain-cells = <1>;
3933d267 SB	246	reg = <0xfc400000 0x4000>;
	247	};
	248
b4e745e1 BA	249	tcsr_mutex_block: syscon@fd484000 {
	250	compatible = "syscon";
	251	reg = <0xfd484000 0x2000>;
	252	};
	253
3933d267 SB	254	mmcc: clock-controller@fd8c0000 {
	255	compatible = "qcom,mmcc-msm8974";
	256	#clock-cells = <1>;
	257	#reset-cells = <1>;
89c7e671	258	#power-domain-cells = <1>;
3933d267 SB	259	reg = <0xfd8c0000 0x6000>;
	260	};
	261
b4e745e1 BA	262	tcsr_mutex: tcsr-mutex {
	263	compatible = "qcom,tcsr-mutex";
	264	syscon = <&tcsr_mutex_block 0 0x80>;
	265
	266	#hwlock-cells = <1>;
	267	};
	268
d0bfd7c9 SB	269	rpm_msg_ram: memory@fc428000 {
d0bfd7c9 SB	270	compatible = "qcom,rpm-msg-ram";
6297c4b2	271	reg = <0xfc428000 0x4000>;
6297c4b2 BA	272	};
6297c4b2 BA	273
10bfcfea	274	blsp1_uart2: serial@f991e000 {
3933d267 SB	275	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	276	reg = <0xf991e000 0x1000>;
	277	interrupts = <0 108 0x0>;
	278	clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
	279	clock-names = "core", "iface";
ba08220a	280	status = "disabled";
3933d267	281	};
19f4f8c1	282
3e944c76 GD	283	sdhci@f9824900 {
	284	compatible = "qcom,sdhci-msm-v4";
	285	reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
	286	reg-names = "hc_mem", "core_mem";
	287	interrupts = <0 123 0>, <0 138 0>;
	288	interrupt-names = "hc_irq", "pwr_irq";
	289	clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
	290	clock-names = "core", "iface";
	291	status = "disabled";
	292	};
	293
	294	sdhci@f98a4900 {
	295	compatible = "qcom,sdhci-msm-v4";
	296	reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
	297	reg-names = "hc_mem", "core_mem";
	298	interrupts = <0 125 0>, <0 221 0>;
	299	interrupt-names = "hc_irq", "pwr_irq";
	300	clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
	301	clock-names = "core", "iface";
	302	status = "disabled";
	303	};
	304
19f4f8c1 SV	305	rng@f9bff000 {
	306	compatible = "qcom,prng";
	307	reg = <0xf9bff000 0x200>;
	308	clocks = <&gcc GCC_PRNG_AHB_CLK>;
	309	clock-names = "core";
	310	};
7d7db8db II	311
	312	msmgpio: pinctrl@fd510000 {
	313	compatible = "qcom,msm8974-pinctrl";
	314	reg = <0xfd510000 0x4000>;
	315	gpio-controller;
	316	#gpio-cells = <2>;
	317	interrupt-controller;
	318	#interrupt-cells = <2>;
	319	interrupts = <0 208 0>;
7d7db8db	320	};
bf7f6b04	321
bf7f6b04	322	blsp_i2c11: i2c@f9967000 {
04edde25	323	status = "disabled";
bf7f6b04	324	compatible = "qcom,i2c-qup-v2.1.1";
	325	reg = <0xf9967000 0x1000>;
	326	interrupts = <0 105 IRQ_TYPE_NONE>;
	327	clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	328	clock-names = "core", "iface";
	329	#address-cells = <1>;
	330	#size-cells = <0>;
	331	};
af22e46d II	332
	333	spmi_bus: spmi@fc4cf000 {
	334	compatible = "qcom,spmi-pmic-arb";
	335	reg-names = "core", "intr", "cnfg";
	336	reg = <0xfc4cf000 0x1000>,
	337	<0xfc4cb000 0x1000>,
	338	<0xfc4ca000 0x1000>;
	339	interrupt-names = "periph_irq";
	340	interrupts = <0 190 0>;
	341	qcom,ee = <0>;
	342	qcom,channel = <0>;
	343	#address-cells = <2>;
	344	#size-cells = <0>;
	345	interrupt-controller;
	346	#interrupt-cells = <4>;
	347	};
2aec37c6	348	};
45b0ef05 BA	349
	350	smd {
	351	compatible = "qcom,smd";
	352
	353	rpm {
	354	interrupts = <0 168 1>;
	355	qcom,ipc = <&apcs 8 0>;
	356	qcom,smd-edge = <15>;
	357
	358	rpm_requests {
	359	compatible = "qcom,rpm-msm8974";
	360	qcom,smd-channels = "rpm_requests";
	361
	362	pm8841-regulators {
	363	compatible = "qcom,rpm-pm8841-regulators";
	364
	365	pm8841_s1: s1 {};
	366	pm8841_s2: s2 {};
	367	pm8841_s3: s3 {};
	368	pm8841_s4: s4 {};
	369	pm8841_s5: s5 {};
	370	pm8841_s6: s6 {};
	371	pm8841_s7: s7 {};
	372	pm8841_s8: s8 {};
	373	};
	374
	375	pm8941-regulators {
	376	compatible = "qcom,rpm-pm8941-regulators";
	377
	378	pm8941_s1: s1 {};
	379	pm8941_s2: s2 {};
	380	pm8941_s3: s3 {};
	381	pm8941_5v: s4 {};
	382
	383	pm8941_l1: l1 {};
	384	pm8941_l2: l2 {};
	385	pm8941_l3: l3 {};
	386	pm8941_l4: l4 {};
	387	pm8941_l5: l5 {};
	388	pm8941_l6: l6 {};
	389	pm8941_l7: l7 {};
	390	pm8941_l8: l8 {};
	391	pm8941_l9: l9 {};
	392	pm8941_l10: l10 {};
	393	pm8941_l11: l11 {};
	394	pm8941_l12: l12 {};
	395	pm8941_l13: l13 {};
	396	pm8941_l14: l14 {};
	397	pm8941_l15: l15 {};
	398	pm8941_l16: l16 {};
	399	pm8941_l17: l17 {};
	400	pm8941_l18: l18 {};
	401	pm8941_l19: l19 {};
	402	pm8941_l20: l20 {};
	403	pm8941_l21: l21 {};
	404	pm8941_l22: l22 {};
	405	pm8941_l23: l23 {};
	406	pm8941_l24: l24 {};
	407
	408	pm8941_lvs1: lvs1 {};
	409	pm8941_lvs2: lvs2 {};
	410	pm8941_lvs3: lvs3 {};
	411
	412	pm8941_5vs1: 5vs1 {};
413	pm8941_5vs2: 5vs2 {};
414	};
415	};
416	};
417	};
2aec37c6	418	};